Semiconductor configuration and method of forming the same

Abstract

This disclosure provides a semiconductor configuration and a method for forming the same. The semiconductor configuration includes a first photodiode, wherein the first photodiode is embedded in a substrate. The semiconductor configuration also includes a lens array, wherein the lens array is located on the substrate. A first group of lenses in the lens array is positioned on the first photodiode. Radiation incident on the first group of lenses is guided by the first group of lenses to the first photodiode.

Description

Technical Field

[0001] This disclosure relates to a semiconductor, and more particularly to a semiconductor configuration and a method of forming the same. Background Technology

[0002] Semiconductor configurations are used in many types of electronic components, such as mobile phones, notebook computers, desktop computers, tablet computers, watches, gaming systems, and various other industrial, commercial, and consumer electronics. A semiconductor configuration generally consists of a semiconductor section and wiring formed within that semiconductor section. Summary of the Invention

[0003] This disclosure provides a semiconductor configuration. This semiconductor configuration may include, but is not limited to, a first photodiode and a lens array, wherein the first photodiode is in a substrate and the lens array is on the substrate. A first group of lenses in the lens array is on the first photodiode, and radiation incident on the first group of lenses may, for example, be guided by the first group of lenses to the first photodiode.

[0004] This disclosure also provides a semiconductor configuration. This semiconductor configuration may include, but is not limited to, a first element, a first dielectric layer, and a lens array, wherein the first element is in a substrate, the first dielectric layer is located on the substrate, and the lens array is on the first dielectric layer. A first portion of the first dielectric layer is located on the first element. The first portion of the first dielectric layer has tapered sidewalls. A first portion of the substrate separates the first portion of the first dielectric layer from the first element. A second portion of the first dielectric layer is located on the first element. The second portion of the first dielectric layer has tapered sidewalls. The second portion of the substrate separates the second portion of the first dielectric layer from the first element. A first lens of the lens array is located on the first portion of the first dielectric layer and the first portion of the substrate. A second lens of the lens array is located on the second portion of the first dielectric layer and the second portion of the substrate.

[0005] This disclosure further provides a method for forming a semiconductor configuration. First, a first recess is formed in a substrate, wherein the first recess is located on a first photodiode, and the first photodiode is located within the substrate. Next, a second recess is formed in the substrate, wherein the second recess is located on the first photodiode, and the first photodiode is located within the substrate. Then, a first dielectric structure is formed in the first recess. Next, a second dielectric structure is formed in the second recess. Next, a first lens is formed in the first dielectric structure. Finally, a second lens is formed in the second dielectric structure. Attached Figure Description

[0006] A better understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are for illustrative purposes only and are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0007] Figures 1 to 5 This is a cross-sectional view illustrating semiconductor configurations at various process stages according to some embodiments of this disclosure;

[0008] Figure 6A This is a top view illustrating a semiconductor configuration at a process stage according to some embodiments;

[0009] Figure 6B This is an illustration based on some embodiments. Figure 6A The semiconductor configuration is shown in a cross-sectional view along line BB;

[0010] Figure 7A This is a top view illustrating a semiconductor configuration at a process stage according to some embodiments;

[0011] Figure 7B This is an illustration based on some embodiments. Figure 7A The semiconductor configuration is shown in a cross-sectional view along line BB;

[0012] Figures 8 to 11 It is a cross-sectional view illustrating semiconductor configurations at various process stages according to some embodiments;

[0013] Figure 12A It is a cross-sectional view illustrating semiconductor configurations at various process stages according to some embodiments;

[0014] Figure 12B These are illustrations based on some embodiments. Figure 12A The semiconductor configuration is shown in the cross-sectional view along line BB.

[0015] [Symbol Explanation]

[0016] 100: Semiconductor Configuration

[0017] 102: Substrate

[0018] 102a, 802a, 1102a: Part 1

[0019] 102b, 1102b, 802b: Part Two

[0020] 802c: Part Three

[0021] 102c, 102d: Partial

[0022] 104: First dielectric layer

[0023] 106, 108, 1004: Thickness

[0024] 202: Components

[0025] 202A: First Component

[0026] 202B: Second Component

[0027] 204: First side

[0028] 206: Second side

[0029] 208, 1208: Direction

[0030] 302: Photomask layer

[0031] 402: Patterned photomask layer

[0032] 502, 502A, 502B, 502C, 502D: Depression

[0033] 602, 608, 708, 710, 812, 1214: Distance

[0034] 604, 606, 704, 706, 712, 804, 806, 808, 810, 814, 816: Sidewall

[0035] 610: Angle

[0036] 702, 702A, 702B, 702C, 702D: Trench

[0037] 802: Second dielectric layer

[0038] 902: Gate structure

[0039] 904,1212: Altitude

[0040] 1002: Third dielectric layer

[0041] 1102: Color Filter Layer

[0042] 1202: Lens Array

[0043] 1202A: First group of lenses

[0044] 1202B: Second group of lenses

[0045] 1202C: Third group of lenses

[0046] 1202D: Fourth Group Lens

[0047] 1204: Diameter

[0048] 1206: Width

[0049] 1210: Lens layer Detailed Implementation

[0050] The following disclosure provides various embodiments or illustrations to achieve different features of this disclosure. Specific examples of elements and configurations described below are for simplification purposes. It is understood that these descriptions are illustrative only and are not intended to limit the scope of this disclosure. For example, in the following description, forming a first feature on or above a second feature may include some embodiments where the first and second features are in direct contact with each other; it may also include some embodiments where other features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, element symbols and / or reference numerals may be reused in multiple embodiments of this disclosure. Such reuse is for simplification and clarity purposes and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0051] Furthermore, spatial correspondence terms, such as "below," "below," "lower than," "above," and similar terms, may be used here to facilitate the explanation of the relationship between one element or feature depicted in the figure and one or more other elements or features. These spatial correspondence terms, in addition to the orientation shown in the figure, also encompass various different orientations in which the device is used or operated. The device may be placed in other orientations (e.g., rotated 90 degrees or in other orientations), and the spatial correspondence descriptions used in this disclosure may be interpreted accordingly.

[0052] A semiconductor configuration includes a first element (e.g., a first photodiode) and a lens array, wherein the first element is in a substrate and the lens array is on the substrate. A first group of lenses in the lens array is located on the first element. Each lens in the first group of lenses performs at least one of the following: refracting radiation, directing radiation to the first element, or focusing and concentrating radiation onto the first element. Compared to a semiconductor configuration with only a single lens on the first element, the aforementioned first group of lenses achieves an increase in the amount of radiation sensed, detected, or converted into electrons by the first element.

[0053] The semiconductor configuration includes a dielectric layer situated between a lens array and a substrate. A first portion of the dielectric layer has tapered sidewalls and is located on a first element. Compared to a dielectric layer without tapered sidewalls, the first portion of the dielectric layer absorbs more radiation, thereby directing more radiation toward the first element. In some embodiments, the first portion of the dielectric layer is a first high absorption (HA) structure. Compared to the first portion of the dielectric layer with tapered sidewalls, a dielectric layer without tapered sidewalls is not a high absorption structure and may scatter or reflect radiation, causing more radiation to be diverted away from the first element. In some embodiments, a first lens of a first group of lenses is located on the first high absorption structure, and a second lens of the first group of lenses is located on a second high absorption structure. The combination of implementing a high absorption structure and a lens array on the first element further increases the amount of radiation sensed, detected, or converted into at least one electron by the first element.

[0054] The second portion of the dielectric layer is located within the substrate and is positioned between or laterally offset from the first and second elements (e.g., a second photodiode). This second portion of the dielectric layer corresponds to a deep trench isolation (DTI) structure. In some embodiments, the semiconductor configuration is formed on the back side of the substrate, such that the second portion of the dielectric layer corresponds to a back deep trench isolation (BDTI) structure. The second portion of the dielectric layer, through at least one of a first group of lenses, a first high absorption (HA) structure, or a second high absorption structure, suppresses radiation from the second element to the first element, thereby achieving at least one of the following: suppressing crosstalk between the first and second elements or increasing the modulation transfer function (MTF). Among other characteristics, a higher MTF improves image resolution, where the image is generated based on light sensed by a photodiode in the substrate.

[0055] Compared to a semiconductor configuration lacking at least one of the first group of lenses, the first high-absorption structure, the second high-absorption structure, or the second portion of the dielectric layer, implementing at least one of the following structures and / or configurations improves quantum efficiency (QE): the first group of lenses is disposed on the first element, the first high-absorption structure is disposed on the first element, the second high-absorption structure is disposed on the first element, or the second portion of the dielectric layer is laterally offset from the first element in the substrate. In some embodiments, the semiconductor configuration serves as a sensing element (e.g., an image sensor, a proximity sensor, or at least one of other different types of sensors). Assuming increased quantum efficiency, the semiconductor configuration operates more efficiently than other sensors, for example, consuming less power and detecting more light in relatively low-light environments.

[0056] Figures 1 to 12B This illustrates a semiconductor configuration 100 at various process stages according to some embodiments. Figures 1 to 5 and Figures 8 to 11 It is a cross-sectional view of semiconductor configuration 100. Figure 6A , Figure 7A and Figure 12A This is a top view illustrating the semiconductor configuration 100, and Figure 6B , Figure 7B and Figure 12B They are drawn separately Figure 6A , Figure 7A and Figure 12A The semiconductor configuration 100 is shown in cross-sectional view along line BB.

[0057] In some embodiments, the sensing element is implemented via semiconductor configuration 100. This sensing element includes at least one of an image sensor, a proximity sensor, a time-of-flight (ToF) sensor, an indirect time-of-flight (iToF) sensor, a backside illumination (BSI) sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, a backside complementary metal-oxide-semiconductor image sensor, or other types of sensors. Other structures and / or configurations of semiconductor configuration 100 and / or the sensing element are within the scope of this disclosure.

[0058] Figure 1This illustration depicts a semiconductor configuration 100 according to some embodiments. The semiconductor configuration 100 includes a substrate 102 and a first dielectric layer 104. The substrate 102 has a first side 204 and a second side 206, wherein the first side 204 corresponds to the rear side of the substrate 102, and the second side 206 corresponds to the front side of the substrate 102. According to some embodiments, the first dielectric layer 104 is formed on the second side 206 of the substrate 102, and the configuration is consistent with... Figure 1 The drawing direction is inverted. For example... Figure 1 As illustrated, the upper surface of the substrate 102 corresponds to the back side or the first side 204, and the lower surface of the substrate 102 corresponds to the front side or the second side 206. The substrate 102 is located on the first dielectric layer 104, and the substrate 102 may be in direct contact with the first dielectric layer 104 or may not be in direct contact with the first dielectric layer 104. At least one of the above structures and / or configurations is present.

[0059] Substrate 102 comprises at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a grain formed from a wafer. Substrate 102 comprises at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. Substrate 102 comprises single-crystal silicon with a crystal orientation of... <100> Crystalline silicon, crystal orientation is <110> Crystalline silicon, crystal orientation is <111> The substrate 102 is at least one of crystalline silicon or other suitable materials. The substrate 102 has at least one doped region. The thickness 106 of the substrate 102 is substantially between about 10,000 angstroms and about 150,000 angstroms (e.g., between about 20,000 angstroms and about 100,000 angstroms). Other structures and / or configurations of the substrate 102 are within the scope of this disclosure.

[0060] The first dielectric layer 104 comprises at least one of Si3N4, SiO2, SiO, MgO, Al2O3, Yb2O3, ZnO, Ta2O5, ZrO2, HfO2, TeO2, TiO2, or other suitable materials. The first dielectric layer 104 is at least one of an interlevel dielectric (ILD) or an intermetallic dielectric (IMD). The first dielectric layer 104 is formed using at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), reduced-pressure chemical vapor deposition (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, growth, or other suitable techniques. The thickness 108 of the first dielectric layer 104 is substantially between about 5,000 angstroms and about 15,000 angstroms (e.g., about 10,000 angstroms). Other structures and / or configurations of the first dielectric layer 104 are within the scope of this disclosure.

[0061] Figure 2 This illustration depicts an element 202 according to some embodiments, wherein the element 202 is formed in a substrate 102. The element 202 is formed using at least one of doping, ion implantation, molecular diffusion, or other suitable techniques. In some embodiments, the element 202 comprises a photodiode, such as a fixed-layer photodiode, a phototransistor, a photogate, or at least one of other suitable techniques. At least some elements 202 may differ from other elements 202 in at least one of height, thickness, width, material composition, etc. The element 202 comprises at least one of a first element 202A or a second element 202B. Any number of elements 202 are contemplated in the substrate 102.

[0062] At least some elements 202 comprise at least one of germanium, indium, phosphorus, boron, BF2, arsenic, antimony, fluorine, InAs, InSb, GaSb, GaAs, InP, silicide, or other suitable materials. Element 202 is configured to sense radiation, such as incident light projected onto substrate 102 along direction 208. At least some elements 202 may comprise materials with relatively high absorption for near-infrared (NIR) wavelengths (e.g., radiation with wavelengths substantially from about 700 nm to about 2500 nm). Other structures and / or configurations of element 202 are within the scope of this disclosure.

[0063] Figure 3 This illustration depicts a photomask layer 302 according to some embodiments, wherein the photomask layer 302 is formed on a substrate 102. The photomask layer 302 is located on the substrate 102, directly contacts the substrate 102, or indirectly contacts the substrate 102, and at least one of the above structures and / or configurations is present. In some embodiments, the photomask layer 302 is a hard mask layer. The photomask layer 302 comprises at least one of oxides, nitrides, metals, or other suitable materials. The photomask layer 302 is formed using at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable methods. Other structures and / or configurations of the photomask layer 302 are within the scope of this disclosure.

[0064] Figure 4This illustration depicts a photomask layer 302 according to some embodiments of the present disclosure, wherein the photomask layer 302 is patterned to form a patterned photomask layer 402, and the patterned photomask layer 402 is on a substrate 102. According to some embodiments, a photoresist (not shown) is used to form the patterned photomask layer 402. The photoresist is formed on the photomask layer 302, and the photoresist is formed using at least one of chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The photoresist comprises a photosensitive material, wherein the properties of the photoresist (e.g., solubility) are affected by light. The photoresist is either positive or negative. In the case of negative photoresist, after being irradiated by a light source, the areas of the negative photoresist become insoluble, such that during a subsequent development stage, the use of a solvent on the negative photoresist removes the unirradiated areas of the negative photoresist. Therefore, the pattern formed in negative photoresist is a negative image of the pattern defined by the opaque area of ​​a template (e.g., a photomask), where the template is between the light source and the negative photoresist. In the case of positive photoresist, the irradiated area of ​​the positive photoresist becomes soluble and can be removed during development by applying a solvent. Therefore, the pattern formed in positive photoresist is a positive image of the opaque area of ​​a template (e.g., a photomask), where the template is between the light source and the positive photoresist. One or more etchants are selective, exhibiting a higher etching or removal rate for one or more layers exposed or not covered by photoresist than for one or more etchants for one or more layers not exposed or covered by photoresist. Therefore, openings in the photoresist allow one or more etchants to form corresponding openings in one or more layers beneath the photoresist, thereby transferring the pattern of the photoresist to one or more layers beneath the photoresist. The photoresist is stripped or cleaned after pattern transfer.

[0065] The etching process used to remove portions of the photomask layer 302 is at least one of a dry etching process, a wet etching process, anisotropic etching process, isotropic etching process, or other suitable etching process to form a patterned photomask layer 402. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable materials. In some embodiments, the etching process is performed to remove portions of the photomask layer 302 and form a patterned photomask layer 402, and this etching process also removes at least some of the substrate 102, such as removing portions of the substrate 102 below openings in the patterned photomask layer 402. Other processes and / or techniques used to form the patterned photomask layer 402 are within the scope of this disclosure.

[0066] Figure 5This illustration depicts an application of forming a recess 502 in a substrate 102 using a patterned photomask layer 402 according to some embodiments. In some embodiments, an etching process is performed to form the recess 502, wherein during the etching process, openings in the patterned photomask layer 402 allow the application of one or more etchants to remove portions of the substrate 102, while the patterned photomask layer 402 protects or shields the portions of the substrate 102 covered by the patterned photomask layer 402. The etching process is at least one of a dry etching process, a wet etching process, anisotropic etching process, isotropic etching process, or other suitable etching process. The etching process uses at least one of HF, diluted HF, a chlorine compound (e.g., HCl2), H2S, or other suitable materials. Other processes and / or techniques for forming the recess 502 are within the scope of this disclosure.

[0067] One or more recesses 502 are located on element 202. Any number of recesses 502 on element 202 is contemplated. A portion of substrate 102 is maintained on element 202 to separate the recesses 502 from element 202. Other structures and / or configurations of the recesses 502 are within the scope of this disclosure.

[0068] Figure 6A and Figure 6B This illustration depicts the removal of a patterned photomask layer 402 according to some embodiments. The patterned photomask layer 402 is removed after the recess 502 is formed. The patterned photomask layer 402 is removed using at least one of chemical mechanical planarization, etching, or other suitable etching processes. The etching process uses at least one of HF, diluted HF, chlorine compounds (e.g., HCl2), H2S, or other suitable materials. Other processes and / or techniques for removing the patterned photomask layer 402 are within the scope of this disclosure.

[0069] The portion of the substrate 102 that defines the recess 502 has a first tapered sidewall 604 (e.g.) Figure 6B (as shown) or the second conical sidewall 606 (as shown) Figure 6B At least one of the following (as shown). The first tapered sidewall 604 has a first slope (e.g., a negative slope), or the second tapered sidewall 606 has a second slope (e.g., a positive slope), and the above structures and / or configurations have at least one of them. In some embodiments, the second slope is opposite in polarity to the first slope. In some embodiments, the recess 502 is triangular. In some embodiments, the cross-sectional area of ​​the recess 502 decreases along direction 208 such that the width of the upper portion of the recess 502 is greater than the width of the lower portion of the recess 502. Other structures and / or configurations of the recess 502 are within the scope of this disclosure. In some embodiments, the angle 610 between the tapered sidewall of the recess 502 and the upper surface of the substrate 102 is defined (e.g., ...). Figure 6B (As shown) is actually between about 30 degrees and about 80 degrees (e.g., about 54.74 degrees).

[0070] In some embodiments, the substrate 102 has a specific crystal orientation (e.g., having a crystal orientation). <100> Crystal orientation <110> or crystal orientation <111> At least one of the crystalline silicon, and the etching process can form sidewalls 604 and 606. In some embodiments, multiple portions of the substrate 102 have different crystal orientations, such as: crystal orientation <100> Crystal orientation <110> Or crystal orientation crystal direction <111> At least one of them. Among them, at least because different crystal orientations have different densities, the etching process has different etching rates for different crystal orientations, thereby forming sidewalls 604 and 606.

[0071] In some embodiments, the first portion of the substrate 102 has a first crystal orientation (e.g., crystal orientation). <111> The second portion of the substrate 102 has a second crystal orientation (e.g., crystal orientation). <100> In this embodiment, a first portion of substrate 102 has a first tapered sidewall 604 and a second tapered sidewall 606, and a second portion of substrate 102 is removed to form a recess 502. In some embodiments, the density of a first crystal orientation (e.g., surface density) is greater than the density of a second crystal orientation (e.g., surface density), such that the etching process removes the second portion of substrate 102, but removes a small amount or none of the first portion of substrate 102, because the etching rate of the second portion of substrate 102 is greater than the etching rate of the first portion of substrate 102. Other processes and / or techniques for forming the sidewalls are also within the scope of this disclosure, wherein such sidewalls define the recess 502.

[0072] The distance 602 between the upper surface of element 202 and the uppermost part of recess 502 or between the upper surface of element 202 and the upper surface of substrate 102 (e.g.) Figure 6B The actual value (as shown) is less than or equal to approximately 20,000 angstroms (e.g., at least less than or equal to approximately 10,000 angstroms). The distance 608 between adjacent depressions 502 (e.g.) Figure 6B (As shown) The actual depth is between about 0 angstroms and about 50,000 angstroms. Other structures and / or configurations of other elements and features of recess 502 are within the scope of this disclosure.

[0073] Depression 502 includes the first group of depressions 502A (e.g.) Figure 6A As shown), the second group of depressions 502B (as shown) Figure 6A As shown), the third group of depressions 502C (as shown) Figure 6A (as shown) or the fourth group of depressions 502D (as shown) Figure 6AAt least one of the following (as shown). A first group of recesses 502A is located on the first element 202A, a second group of recesses 502B is located on the second element 202B, a third group of recesses 502C is located on the third element 202 (not shown), and a fourth group of recesses 502D is located on the fourth element 202 (not shown). Other structures and / or configurations of other elements and features of the recesses 502 are within the scope of this disclosure.

[0074] Figure 7A and Figure 7B This illustration depicts a trench 702 formed on a substrate 102 according to some embodiments. The trench 702 is laterally offset from element 202 or the trench 702 is between two elements 202, and at least one of the above structures and / or configurations is present. The first portion 102a of the substrate 102 (e.g., Figure 7B (As shown) Separating trench 702 and first element 202A, and the second portion 102b of substrate 102 (as shown) Figure 7B (As shown) Separate groove 702 and second element 202B.

[0075] In some embodiments, the trench 702 is formed using photoresist (not shown), wherein the photoresist is formed and patterned on a substrate 102. The photoresist is formed by at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The photoresist comprises a photosensitive material, wherein the properties of the photoresist (e.g., solubility) are affected by light. The photoresist is either negative or positive, and the photoresist is formed using the aforementioned methods.

[0076] One or more etchants are used in conjunction with patterned photoresist to form trenches 702. The etchants are selective, etching or removing one or more exposed or unexposed photoresist-covered layers at a higher rate than etching or removing one or more layers that are not exposed or covered by the photoresist. Openings in the photoresist allow the etchants to form trenches 702 in the substrate 102, thereby transferring the pattern of the photoresist to one or more layers beneath it. After pattern transfer, the photoresist is removed by at least one method, such as stripping or cleaning. The etching process used to form trenches 702 is at least one of dry etching, wet etching, anisotropic etching, isotropic etching, or other suitable etching processes. The etching process uses at least one of HF, diluted HF, chlorine compounds (e.g., HCl2), H2S, or other suitable materials. Other processes and / or techniques used to form trenches 702 are within the scope of this disclosure.

[0077] The portion of the substrate 102 defining the first trench 702A has a first sidewall 704 (e.g. Figure 7B(as shown) and the second sidewall 706 (as shown) Figure 7B (As shown). At least some of the first sidewalls 704 are tapered and / or at least some of the second sidewalls 706 are tapered. The first sidewalls 704 have a first slope (e.g., a negative slope) and / or the second sidewalls 706 have a second slope (e.g., a positive slope). In some embodiments, the second slope and the first slope are opposite in polarity. In some embodiments, the cross-sectional area of ​​the trench 702 decreases along direction 208 such that the width of the upper portion of the trench 702 is greater than the width of the lower portion of the trench 702.

[0078] In some embodiments, the substrate 102 has a specific crystal orientation (e.g., crystalline silicon has a crystal orientation). <100> Crystal orientation <110> or crystal orientation <111> (at least one of) allows the etching process to form sidewalls 704 and 706. In some embodiments, portions of the substrate 102 have different crystal orientations, such as: crystal orientation <100> Crystal orientation <110> or crystal orientation <111> At least one of them. Among them, at least because different crystal orientations have different densities, the etching process has different etching rates for different crystal orientations, thereby forming sidewalls 704 and 706.

[0079] In some embodiments, the first portion of the substrate 102 has a first crystal orientation (e.g., crystal orientation). <111> The second portion of the substrate 102 has a second crystal orientation (e.g., crystal orientation). <100> The substrate 102 has a first portion having a first sidewall 704 and a second sidewall 706, and a second portion of the substrate 102 is removed to form a first trench 702A. In some embodiments, the density of a first crystal orientation (e.g., surface density) is greater than the density of a second crystal orientation (e.g., surface density), such that the etching process removes the second portion of the substrate 102, but removes a small amount or none of the first portion of the substrate 102, because the etching rate of the second portion of the substrate 102 is greater than the etching rate of the first portion of the substrate 102. Other processes and / or techniques for forming the sidewalls are within the scope of this disclosure, wherein the sidewalls are used to define the trench 702.

[0080] According to some embodiments, at least some sidewalls [e.g., at least some first sidewalls 704 and / or second sidewalls 706 extending vertically (e.g., in a direction parallel to direction 208)] define the trench 702. Other structures and / or configurations of the trench 702 are within the scope of this disclosure.

[0081] In some embodiments, the distance 708 between adjacent trenches 702 (e.g.) Figure 7BThe distance 710 between the uppermost portion of the first sidewall 704 of the first trench 702A and the uppermost portion of the sidewall 712 of the adjacent trench 702 is substantially between approximately 10,200 angstroms and approximately 130,000 angstroms (e.g., approximately 95,000 angstroms). In some embodiments, the distance 710 corresponds to a pixel size. In some embodiments, the trench 702 includes the first trench 702A (e.g., approximately 10,200 angstroms to approximately 120,000 angstroms). Figure 7A and Figure 7B As shown), the second trench 702B (as shown) Figure 7A As shown), the third trench 702C (as shown) Figure 7A (as shown) or the fourth trench 702D (as shown) Figure 7A At least one of the following structures and / or configurations is shown: First trench 702A is between first element 202A and second element 202B; second trench 702B is between second element 202B and fourth element 202 (not shown); third trench 702C is between fourth element 202 and third element 202 (not shown); or fourth trench 702D is between third element 202 and first element 202A. The first trench 702A is located between first group of recesses 502A and second group of recesses 502B; second trench 702B is located between second group of recesses 502B and fourth group of recesses 502D; third trench 702C is located between fourth group of recesses 502D and third group of recesses 502C; or fourth trench 702D is located between third group of recesses 502C and first group of recesses 502A. The above structures and / or configurations are at least one of the following. Other features and other structures and / or configurations of the groove 702 are within the scope of this disclosure.

[0082] In some embodiments, the lowermost part of trench 702 is lower than the uppermost part of element 202. In some embodiments, the lowermost part of trench 702 is higher than the lowermost part of element 202. In some embodiments, the lowermost part of trench 702 is lower than the lowermost part of element 202. In some embodiments, the lowermost part of trench 702 and the lowermost part of element 202 are at the same height or coplanar. Other structural and / or configurational features of trench 702 and element 202 are within the scope of this disclosure.

[0083] Figure 8This illustration depicts a second dielectric layer 802 formed on a substrate 102, according to several embodiments. In some embodiments, the second dielectric layer 802 directly contacts the upper surface of the substrate 102 and / or is defined on the sidewalls of the substrate 102 (e.g., the sidewalls defining the recess 502 and the sidewalls defining the trench 702). In some embodiments, the second dielectric layer 802 indirectly contacts the upper surface of the substrate 102 and / or is defined on the sidewalls of the substrate 102. Other structures and / or configurations of the second dielectric layer 802 are within the scope of this disclosure.

[0084] In some embodiments, the semiconductor configuration 100 includes a buffer layer (not shown) between a substrate 102 and a second dielectric layer 802, such that the buffer layer is formed on the substrate 102 before the second dielectric layer 802 is formed. The buffer layer directly contacts the upper surface of the substrate 102 and / or sidewalls defined in the substrate 102 (e.g., sidewalls defining recess 502 and sidewalls defining trench 702), or indirectly contacts the upper surface of the substrate 102 and / or sidewalls defined in the substrate 102.

[0085] The buffer layer contains anti-reflective coating material, SiO2, HfSiON, and HfSiO x HfAlO x The buffer layer is formed by at least one of the following: HfO2, ZrO2, La2O3, Y2O3, or other suitable materials. The buffer layer is formed by at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. In some embodiments, the buffer layer comprises a monolayer, wherein the monolayer is configured to adhere the second dielectric layer 802 and the substrate 102. According to some embodiments, the buffer layer comprises multiple layers, wherein the outermost layer of the multiple layers is configured to adhere the second dielectric layer 802. When the semiconductor configuration 100 includes a buffer layer, the second dielectric layer 802 is located on the buffer layer, the second dielectric layer 802 directly contacts the upper surface of the buffer layer, or the second dielectric layer 802 indirectly contacts the upper surface of the buffer layer, and at least one of the above structures and / or configurations is present. Other structures and / or configurations of the buffer layer are within the scope of this disclosure.

[0086] The second dielectric layer 802 comprises at least one of Si3N4, SiO2, SiO, MgO, Al2O3, Yb2O3, ZnO, Ta2O5, ZrO2, HfO2, TeO2, TiO2, or other suitable materials. The second dielectric layer 802 is formed by at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The second dielectric layer 802 is formed on the upper surface of the recess 502, trench 702, or substrate 102, and the above structure and / or configuration has at least one of the above features. The distance 812 between the upper surface of the second dielectric layer 802 and the upper surface of the substrate 102 is substantially less than or equal to about 10,000 angstroms (e.g., less than or equal to about 5,000 angstroms).

[0087] A first portion 802a of the second dielectric layer 802 is located in a recess 502. The first portion 802a of the second dielectric layer 802 has a third tapered sidewall 804, which aligns with a first tapered sidewall 604 of the substrate 102. When the semiconductor configuration 100 includes a buffer layer, and the buffer layer is on the substrate 102, a portion of the buffer layer separates the third tapered sidewall 804 of the first portion 802a of the second dielectric layer from the first tapered sidewall 604 of the substrate 102.

[0088] The first portion 802a of the second dielectric layer 802 has a fourth tapered sidewall 806, wherein the fourth tapered sidewall 806 is aligned with the second tapered sidewall 606 of the substrate 102. When the semiconductor configuration 100 includes a buffer layer, wherein the buffer layer is on the substrate 102, a portion of the buffer layer separates the fourth tapered sidewall 806 of the first portion 802a of the second dielectric layer 802 from the second tapered sidewall 606 of the substrate 102. The first portion 802a of the second dielectric layer 802 is located on the first element 202A. At least one of a portion of the buffer layer or a portion 102c of the substrate 102 separates the first portion 802a of the second dielectric layer 802 from the first element 202A.

[0089] The first portion 802a of the second dielectric layer 802 in the recess 502 is a high-absorption structure, at least in part because the first portion 802a has at least one of a third conical sidewall 804, a first conical sidewall 604, a fourth conical sidewall 806, or a second conical sidewall 606. Compared to portions of the second dielectric layer 802 and substrate 102 that do not have one or more conical sidewalls, the high-absorption structure will conduct more radiation to the element 202, which is located beneath the first portion 802a of the second dielectric layer 802. One or more additional portions of the second dielectric layer 802 in the recess 502 of the substrate 102 form a similar high-absorption structure on the element 202. Other structures and / or configurations of the high-absorption structure are within the scope of this disclosure.

[0090] A second portion 802b of the second dielectric layer 802 is located in the trench 702. The second portion 802b of the second dielectric layer 802 has a third sidewall 808, wherein the third sidewall 808 is aligned with a first sidewall 704 of the substrate 102. At least some of the third sidewalls 808 and at least some of the first sidewalls 704 are tapered. When the semiconductor configuration 100 includes a buffer layer, and the buffer layer is located on the substrate 102, a portion of the buffer layer separates the third sidewall 808 and the first sidewall 704. The second portion 802b of the second dielectric layer 802 has a fourth sidewall 810, wherein the fourth sidewall 810 is aligned with a second sidewall 706 of the substrate 102. At least some of the fourth sidewalls 810 and at least some of the second sidewalls 706 are tapered. When the semiconductor configuration 100 includes a buffer layer, and the buffer layer is located on the substrate 102, a portion of the buffer layer separates the fourth sidewall 810 and the second sidewall 706.

[0091] The second portion 802b of the second dielectric layer 802 is offset laterally from element 202 or between at least one of the two elements. The second portion 802b of the second dielectric layer 802 and the first element 202A are separated by a portion of the buffer layer and / or the first portion 102a of the substrate 102. The second portion 802b of the second dielectric layer 802 and the second element 202B are separated by a portion of the buffer layer and / or the second portion 102b of the substrate 102. In some embodiments, at least some of the second portions 802b of the second dielectric layer 802 directly contact at least some of the first elements 202A and / or at least some of the second elements 202B.

[0092] In some embodiments, the second portion 802b of the second dielectric layer 802 is a deep trench isolation structure in the substrate 102. The deep trench isolation structure is a back-side deep trench isolation structure or a different type of deep trench isolation structure. When the semiconductor configuration 100 includes a buffer layer, the deep trench isolation structure includes at least some buffer layers. Other structures of the second portion 802b of the second dielectric layer 802 are within the scope of this disclosure. In some embodiments, it is assumed that at least some of the second dielectric layers 802 (e.g., the second portion 802b of the second dielectric layer 802) are in one or more trenches (e.g., the first trench 702A), and the distances 708 and 710 of the one or more trenches (illustrated in...) Figure 7B This applies to at least some of the second dielectric layers 802.

[0093] Figure 9 This illustration depicts a gate structure 902 formed on a second dielectric layer 802 according to some embodiments. A portion of the gate structure 902 is located on the second dielectric layer 802, and the gate structure 902 directly contacts or indirectly contacts the upper surface of the second dielectric layer 802, wherein at least one of the above structures and / or configurations is present. The gate structure 902 is disposed between elements 202 such that the gate structure 902 is generally not located on or laterally offset from the elements 202. The gate structure 902 is disposed between two adjacent elements 202 such that the gate structure 902 is located on the portion of the substrate 102 between the two adjacent elements 202. In some embodiments, at least some of the gate structures 902 have tapered sidewalls.

[0094] Gate structure 902 comprises at least one of copper, polysilicon, doped polysilicon, aluminum, beryllium, chromium, copper, gold, iron, molybdenum, nickel, platinum, silver, tungsten, boron, antimony, or other suitable materials. Gate structure 902 is formed by forming one or more layers of gate structure material on a second dielectric layer 802 and patterning such one or more layers of gate structure material. The one or more layers of gate structure material are formed using at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The one or more layers of gate structure material are patterned using at least one of photoresist, hard mask layer, etching process, or other suitable techniques to form gate structure 902. In some embodiments, two adjacent gate structures 902 radiate guiding elements 202, wherein element 202 is located between two adjacent gate structures 902. The height 904 of the gate structure 902 is less than or equal to 10,000 angstroms (e.g., less than or equal to about 5,000 angstroms, or about 2,000 angstroms). Other structures and / or configurations of the gate structure 902 are within the scope of this disclosure.

[0095] Figure 10 This illustration depicts a third dielectric layer 1002 according to some embodiments, wherein the third dielectric layer 1002 is on the gate structure 902 or the second dielectric layer 802, and at least one of the above structures and / or configurations is present. At least a portion of the third dielectric layer 1002 is located on the second dielectric layer 802, and the third dielectric layer 1002 directly contacts the upper surface of the second dielectric layer 802 and indirectly contacts the upper surface of the second dielectric layer 802, and at least one of the above structures and / or configurations is present. In some embodiments, the third dielectric layer 1002 differs from the second dielectric layer 802, for example, by having a different material composition, such that an interface is defined between the third dielectric layer 1002 and the second dielectric layer 802. The third dielectric layer 1002 is located on the gate structure 902, directly contacts the sidewalls of the gate structure 902, directly contacts the upper surface of the gate structure 902, indirectly contacts the sidewalls of the gate structure 902, or indirectly contacts the upper surface of the gate structure 902, and at least one of the above structures and / or configurations is present.

[0096] The third dielectric layer 1002 comprises at least one of Si3N4, SiO2, SiO, MgO, Al2O3, Yb2O3, ZnO, Ta2O5, ZrO2, HfO2, TeO2, TiO2, or other suitable materials. In some embodiments, the third dielectric layer 1002 comprises a material that is substantially optically transparent to the wavelength (e.g., near-infrared light) of the radiation that the element 202 is attempting to detect. The third dielectric layer 1002 is formed using at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The thickness 1004 of the third dielectric layer 1002 is substantially less than or equal to about 20,000 angstroms (e.g., less than or equal to about 10,000 angstroms, or at least less than or equal to about 5,000 angstroms). Other structures and / or configurations of the third dielectric layer 1002 are within the scope of this disclosure.

[0097] Figure 11This illustration depicts one or more color filter layers 1102 according to some embodiments, wherein the one or more color filter layers 1102 are located on a third dielectric layer 1002. The one or more color filter layers 1102 are located on the third dielectric layer 1002, directly contacting or indirectly contacting the upper surface of the third dielectric layer 1002, and the above structure and / or configuration has at least one of these. The one or more color filter layers 1102 comprise at least one of pigment-dispersed color resist (PDCR) material, photosensitive substance, photoinitiator, multifunctional monomer, one or more additives, leveling agent, adhesion promoter, resin, polymer soluble in alkaline solution, color paste, pigment, dispersant, solvent, or other suitable material. The one or more color filter layers 1102 filter specific wavelengths of radiation. In some embodiments, different portions of the one or more color filter layers 1102 have different material compositions to filter different wavelengths. A first portion 1102a of one or more color filter layers 1102 located on a first element 202A has a first material composition and filters a first wavelength. A second portion 1102b of one or more color filter layers 1102 located on a second element 202B has a second material composition and filters a second wavelength, wherein the first wavelength and the second wavelength are different. In some embodiments, the one or more color filter layers 1102 comprise multiple color filter layers located above each other. In some embodiments, a first color filter layer of the multiple color filter layers corresponds to a red filter layer, wherein the red filter layer is configured to filter radiation with wavelengths other than red light. In some embodiments, a second color filter layer of the multiple color filter layers corresponds to a blue filter layer, wherein the blue filter layer is configured to filter radiation with wavelengths other than blue light. In some embodiments, the second color filter layer is located on top of the first color filter layer. In some embodiments, the first color filter layer is located on top of the second color filter layer. One or more color filter layers 1102 are formed using at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The thickness of at least one of the one or more color filter layers 1102 (e.g., at least one of a first color filter layer or a second color filter layer) is substantially less than or equal to about 10,000 angstroms (e.g., less than or equal to about 5,000 angstroms). Other structures and / or configurations of the one or more color filter layers 1102 are within the scope of this disclosure.

[0098] Figure 12A and Figure 12BThis illustration depicts a lens array 1202 according to some embodiments, wherein the lens array 1202 is formed on one or more color filter layers 1102. The lenses of the lens array 1202 are at least one of microlenses or other suitable lenses. The lens array 1202 includes at least one of a first group of lenses 1202A, a second group of lenses 1202B, a third group of lenses 1202C, or a fourth group of lenses 1202D. The first group of lenses 1202A is located on a first element 202A, the second group of lenses 1202B is located on a second element 202B, the third group of lenses 1202C is located on a third element 202 (not shown), and the fourth group of lenses 1202D is located on a fourth element 202 (not shown).

[0099] In some embodiments, one or more lenses of the lens array 1202 are located on one or more portions of the second dielectric layer 802, wherein these one or more portions have tapered sidewalls, such as one or more high-absorption structures. A first lens of the first group of lenses 1202A is located on a first portion 102a of the second dielectric layer 802 or on one or more other portions of the second dielectric layer 802. The aforementioned structure and / or configuration has at least one of the following: the first portion 802a of the second dielectric layer 802 has a third tapered sidewall 804 and a fourth tapered sidewall 806, and one or more other portions of the second dielectric layer 802 have tapered sidewalls. A first lens of the first group of lenses 1202A is located on a portion 102c of the substrate 102, wherein this portion 102c separates the first portion 802a of the second dielectric layer 802 from the first element 202A. The second lens of the first group of lenses 1202A is located on at least one of the third portion 802c of the second dielectric layer 802 or on one or more other portions of the second dielectric layer 802, wherein the third portion 802c of the second dielectric layer 802 has a fifth conical sidewall 814 and a sixth conical sidewall 816, and one or more other portions of the second dielectric layer 802 have conical sidewalls. The second lens of the first group of lenses 1202A is located on a portion 102d of the substrate 102, wherein this portion 102d separates the third portion 802c of the second dielectric layer 802 and the first element 202A.

[0100] In some embodiments, the first group of lenses 1202A is located on a first plurality of portions of the second dielectric layer 802, wherein these first plurality of portions are formed in a first group of recesses 502A (illustrated in...). Figure 6A In the second group of lenses 1202B, the second group of lenses 1202B is located on a second plurality of portions of the second dielectric layer 802, wherein these second plurality of portions are formed in a second group of recesses 502B (illustrated in...). Figure 6A In the second dielectric layer 802, the third group of lenses 1202C is located on the third plurality of portions of the second dielectric layer 802, wherein these third plurality of portions are formed in the third group of recesses 502C (illustrated in...). Figure 6AIn the second dielectric layer 802, the fourth group of lenses 1202D is located on the fourth plurality of portions of the second dielectric layer 802, wherein these fourth plurality of portions are formed in the fourth group of recesses 502D (illustrated in...). Figure 6A )middle.

[0101] In some embodiments, each lens of the first group of lenses 1202A is located on a portion of the second dielectric layer 802, wherein this portion is located on at least one recess of the first group of recesses 502A, such as at least one high-absorption structure located on the first element 202A. In some embodiments, each lens of the second group of lenses 1202B is located on a portion of the second dielectric layer 802, wherein this portion is located on at least one recess of the second group of recesses 502B, such as on at least one high-absorption structure, wherein this at least one high-absorption structure is located on the second element 202B. In some embodiments, each lens of the third group of lenses 1202C is located on a portion of the second dielectric layer 802, wherein this portion is located on at least one recess of the third group of recesses 502C, such as on at least one high-absorption structure, wherein this at least one high-absorption structure is located on the third element 202 (not shown). In some embodiments, each lens of the fourth group of lenses 1202D is located on a portion of the second dielectric layer 802, wherein this portion is located on at least one recess of the fourth group of recesses 502D, such as: at least one high absorption structure, wherein this at least one high absorption structure is located on the fourth element 202 (not shown).

[0102] The diameter of the lens in lens array 1202 is 1204 (shown in...). Figure 12A The actual value is between approximately 5,000 angstroms and approximately 60,000 angstroms (e.g., approximately 46,200 angstroms). For example, due to the one or more material properties of the lens array 1202, the height 1212 of the lenses of the lens array 1202 (illustrated in...) Figure 12B The actual width is between approximately 2,500 angstroms and approximately 40,000 angstroms (e.g., approximately 23,000 angstroms). The width of the first element 202A is 1206 (shown in...). Figure 12B The depth of the first element 202A is substantially at least 20,000 angstroms (e.g., approximately 95,000 angstroms). In some embodiments, the depth of the first element 202A is approximately equal to the width 1206 of the first element 202A. In some embodiments, the depth of the first element 202A is not equal to the width 1206 of the first element 202A. The depth of the first element 202A corresponds to the length of the first element 202A extending along direction 1208.

[0103] In some embodiments, the lens array 1202 is located on the lens layer 1210, directly contacting or indirectly contacting the upper surface of the lens layer 1210, and the above structure and / or configuration has at least one of these. The lens layer 1210 is at least partially located on one or more color filter layers 1102, directly contacting or indirectly contacting the upper surface of one or more color filter layers 1102, and the above structure and / or configuration has at least one of these. The lens layer 1210 is a lens substrate, wherein the lens substrate comprises at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonyide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. Lens layer 1210 is formed using at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable methods. In one embodiment, the distance 1214 between the uppermost part of the lens of lens array 1202 and at least one of the upper surface of one or more color filter layers 1102 or the lower surface of lens layer 1210 is (e.g., ...). Figure 12B The actual value (as shown) is less than or equal to about 100,000 angstroms (e.g., less than or equal to about 50,000 angstroms). Other structures and / or configurations of the lens layer 1210 are within the scope of this disclosure.

[0104] When the semiconductor configuration 100 does not include the lens layer 1210, the lens array 1202 directly contacts or indirectly contacts the upper surface of one or more color filter layers 1102, and at least one of the above structures and / or configurations is present. In some embodiments, the lens array 1202 is formed by at least one of thermal reflow, microplastic imprinting, microdroplet jetting, photolithography, reactive ion etching, machining, or other suitable methods. Other structures and / or configurations of the lens array 1202 are within the scope of this disclosure.

[0105] In some embodiments, radiation is projected toward the semiconductor configuration 100, such as in direction 208 or at least one of different directions. At least some of the radiation passes through at least one of the lens array 1202, lens layer 1210, one or more color filter layers 1102, third dielectric layer 1002, second dielectric layer 802, or some substrates 102, and this radiation is sensed, detected, or converted into electrons by the first element 202. The lenses of the lens array 1202 are configured to perform at least one of the following: refracting radiation, directing radiation to the element 202 under the lens, or focusing and concentrating radiation onto the element 202. Compared to other semiconductor configurations, the semiconductor configuration 100 increases the radiation on the upper surface of the single element 202. The other semiconductor configurations described above have only a single lens, wherein the single lens is located on the element, and the semiconductor configuration 100 has a lens array 1202, and the lens array 1202 is located on the single element 202. Compared to other semiconductor configurations, semiconductor configuration 100 increases the uniformity of radiation on the upper surface of a single element 202 (reducing the difference in radiation levels between different regions of the upper surface of the single element 202). The other semiconductor configurations described above consist only of a single lens, wherein the single lens is located on the element, and semiconductor configuration 100 has a lens array 1202 located on the single element 202. In some embodiments, increasing the radiation on the upper surface of the single element 202 or increasing the uniformity of radiation on the upper surface of the single element 202 increases the amount of radiation sensed, detected, or converted into at least one electron by the single element 202.

[0106] In some embodiments, radiation that is sensed, detected, or converted into electrons by a single element 202 is incident on a lens array 1202, wherein the lens array 1202 is located on element 202. The radiation incident on the lens array 1202 is guided to element 202 by the lens array 1202, wherein the lens array 1202 is located on element 202. The radiation that is sensed, detected, or converted into electrons by a single element 202 is incident on a first group of lenses 1202A. The radiation incident on the first group of lenses 1202A is guided to the first element 202A by the first group of lenses 1202A.

[0107] Some semiconductor configurations have a single lens located at a photodiode. The size of this single lens is designed to conform to the size of the photodiode, and thus the diameter of the single lens is approximately equal to at least one of the width or depth of the photodiode. When the size of the photodiode exceeds a critical size, the diameter of the single lens exceeds a critical diameter to conform to the photodiode size. The height of the lens (e.g., at least one of a single lens or a lens array 1202) is limited to a maximum height, wherein the limitation to the maximum height may be due to at least one of one or more material properties of the lens or one or more process limitations of the processes used to form the lens. In some embodiments, the maximum height is substantially between about 20,000 angstroms and about 40,000 angstroms (e.g., 30,000 angstroms, or about 23,000 angstroms). Because the height of the single lens is limited to a maximum height, if the diameter of the single lens exceeds a critical diameter, the shape of the single lens is different from a hemispherical shape, such as a semi-spherical or flattened hemisphere. In some embodiments, the critical diameter is about twice the maximum height. Other values ​​for the critical diameter are within the scope of this disclosure.

[0108] By implementing the semiconductor configuration 100, even if the size of a single element 202 exceeds a critical size, the diameter 1204 of the formed lens may not exceed a critical diameter or the shape of the lens may be hemispherical. The above structure and / or configuration has at least one of these features, wherein the semiconductor configuration 100 has a plurality of lenses in a lens array 1202, and the lens array 1202 is on the single element 202. Compared to other elements whose size does not exceed the critical size, the size of the single element 202 exceeding the critical size can increase the full well capacity (FWC) of the single element 202. In some embodiments, at least some elements 202 exceed the critical size. In some embodiments, the critical size corresponds to at least one of a critical width or a critical depth. In some embodiments, the critical width is substantially between about 30,000 angstroms and about 70,000 angstroms (e.g., substantially about 50,000 angstroms). In some embodiments, the critical depth is substantially between about 30,000 angstroms and about 70,000 angstroms (e.g., substantially about 50,000 angstroms). Other structures and / or configurations of element 202 (e.g., element 202 with a size not exceeding the critical size) are within the scope of this disclosure.

[0109] In some embodiments, each lens of the formed lens array 1202 has at least one of the following: hemispherical or a diameter 1204 not exceeding a critical diameter. Compared to semiconductor configurations with only a single lens on other elements, the lens array 1202 has multiple lenses, thereby increasing at least one of the following: radiation refracted by the multiple lenses, radiation directed to a single element 202 by the multiple lenses, radiation focused or concentrated to a single element 202 by the multiple lenses, radiation sensed by the first element 202, radiation detected by the first element 202, or radiation converted into electrons by the multiple lenses. In some embodiments, the increase in radiation is at least partly due to at least one of the multiple lenses having a diameter not exceeding a critical diameter and / or at least some of the lenses being hemispherical.

[0110] Compared to other sensing devices without a high-absorption structure, the high-absorption structure (e.g., the portion of the second dielectric layer 802 located in the recess 502 on element 202) increases the amount of radiation sensed, detected, or converted into electrons by the first element. The substrate 102 causes radiation to be reflected or deflected away from element 202, while the high-absorption structure reduces the reflection or deflection of radiation, allowing radiation to be projected onto element 202. In some embodiments, the radiation includes near-infrared radiation, such as radiation with wavelengths substantially between 700 nm and 2500 nm. Other wavelengths of radiation directed to element 202 by the high-absorption structure are also within the scope of this disclosure.

[0111] In some embodiments, the deep trench isolation structure (e.g., a portion of the second dielectric layer 802 within trench 702, wherein trench 702 is between elements 202) performs at least one of the following: preventing or mitigating crosstalk between elements 202. The deep trench isolation structure performs at least one of the following: preventing or mitigating radiation from element 202 to another adjacent element 202, or, in the case of no adjacent element 202, preventing or mitigating radiation simply away from element 202. Radiation traveling away from element 202 is reflected back to element 202 by the deep trench isolation structure. Generally, when radiation is redirected to element 202, element 202 detects more radiation.

[0112] In some embodiments, compared to other sensors that do not implement at least one of the multiple lenses on a single element 202, a high-absorption structure, or a deep trench isolation structure, the multiple lenses on the single element 202, the high-absorption structure, or the deep trench isolation structure improve at least one of the modulation transfer function or spatial frequency response of the sensor. The improvement in the modulation transfer function or spatial frequency response is at least partly due to light being refracted, focused, concentrated, transmitted, guided, or reflected to the element (e.g., a photodiode). In some embodiments, compared to other sensors that do not implement at least one of the multiple lenses on a single element 202, a high-absorption structure, or a deep trench isolation structure, the multiple lenses on the single element 202, the high-absorption structure, or the deep trench isolation structure improve resolution. The improvement in resolution is at least partly due to light being refracted, focused, concentrated, transmitted, guided, or reflected to the element (e.g., a photodiode). In some embodiments, implementing at least one of the multiple lenses improves the quantum efficiency of the sensor compared to other sensors that do not have at least one of the multiple lenses implemented on a single element 202, a high-absorption structure, or a deep trench isolation structure. The multiple lenses are located on the single element 202, the high-absorption structure, or the deep trench isolation structure, and the multiple lenses are implemented through a semiconductor configuration 100. According to the above, at least one of the multiple lenses located on the single element 202, the high-absorption structure, or the deep trench isolation structure enhances the radiation (e.g., near- and far-infrared radiation) that is sensed, detected, or converted into electrons.

[0113] In some embodiments, a semiconductor configuration is provided. The semiconductor configuration includes a first photodiode, wherein the first photodiode is embedded in a substrate. The semiconductor configuration includes a lens array, wherein the lens array is on the substrate. A first group of lenses of the lens array is on the first photodiode. Radiation incident on the first group of lenses is directed by the first group of lenses to the first photodiode.

[0114] In some embodiments, the semiconductor configuration may further include a first dielectric layer, wherein a first portion of the first dielectric layer is offset laterally from the first photodiode.

[0115] In some embodiments, the semiconductor configuration may further include a second photodiode, wherein the second photodiode is in the substrate. A first portion of the first dielectric layer may be offset laterally from the second photodiode, for example, and the first portion of the first dielectric layer may be, for example, between the first photodiode and the second photodiode.

[0116] In some embodiments, the second group of lenses of the lens array is located on the second photodiode.

[0117] In some embodiments, the semiconductor configuration may further include a first dielectric layer, wherein a first portion of the first dielectric layer is located on the first photodiode, the first portion of the first dielectric layer has tapered sidewalls, and a first portion of the substrate separates the first portion of the first dielectric layer from the first photodiode.

[0118] In some embodiments, the first portion of the substrate has a first tapered sidewall, wherein the first tapered sidewall is aligned with the tapered sidewall of the first portion of the first dielectric layer.

[0119] In some embodiments, the second portion of the first dielectric layer is located on the first photodiode, the second portion of the first dielectric layer has a tapered sidewall, and the first portion of the substrate has a second tapered sidewall, wherein the second tapered sidewall is aligned with the tapered sidewall of the second portion of the first dielectric layer.

[0120] In some embodiments, the first tapered sidewall of the first portion of the substrate has a first slope, the second tapered sidewall of the first portion of the substrate has a second slope, and the second slope is opposite in polarity to the first slope.

[0121] In some embodiments, the second portion of the first dielectric layer is located on the first photodiode, the second portion of the first dielectric layer has a tapered sidewall, the second portion of the substrate separates the second portion of the first dielectric layer and the first photodiode, the first lens of the first group of lenses is located on the first portion of the first dielectric layer and the first portion of the substrate, and the second lens of the first group of lenses is located on the second portion of the first dielectric layer and the second portion of the substrate.

[0122] In some embodiments, a semiconductor configuration is provided. The semiconductor configuration includes a first element, wherein the first element is in a substrate. The semiconductor configuration includes a first dielectric layer, wherein the first dielectric layer is on the substrate. A first portion of the first dielectric layer is located on the first element. The first portion of the first dielectric layer has tapered sidewalls. A first portion of the substrate separates the first element and the first dielectric layer. A second portion of the first dielectric layer is located on the first element. The second portion of the first dielectric layer has tapered sidewalls. The second portion of the substrate separates the second portion of the first dielectric layer and the first element. The semiconductor configuration includes a lens array, wherein the lens array is on the first dielectric layer. A first lens of the lens array is located on the first portion of the first dielectric layer and the first portion of the substrate. A second lens of the lens array is located on the second portion of the first dielectric layer and the second portion of the substrate.

[0123] In some embodiments, a first portion of the substrate has a first tapered sidewall, wherein the first tapered sidewall is aligned with the tapered sidewall of a first portion of the first dielectric layer.

[0124] In some embodiments, a first portion of the substrate has a second tapered sidewall, wherein the second tapered sidewall is aligned with the tapered sidewall of a second portion of the first dielectric layer.

[0125] In some embodiments, the first tapered sidewall of the first portion of the substrate has a first slope, the second tapered sidewall of the first portion of the substrate has a second slope, and the second slope is opposite in polarity to the first slope.

[0126] In some embodiments, the third portion of the first dielectric layer is offset laterally from the first element.

[0127] In some embodiments, the semiconductor configuration may further include a second element, wherein the second element is in a substrate. A third portion of the first dielectric layer is laterally offset from the second element, and the third portion of the first dielectric layer is located between the first element and the second element.

[0128] In some embodiments, the third lens and the fourth lens of the lens array are located on the second element.

[0129] In some embodiments, the first element may be, for example, a photodiode.

[0130] In some embodiments, a method for forming a semiconductor configuration is provided. The method includes forming a first recess in a substrate, wherein the first recess is located on a first photodiode within the substrate. The method includes forming a second recess in the substrate, wherein the second recess is located on the first photodiode within the substrate. The method includes forming a first dielectric structure in the first recess. The method includes forming a second dielectric structure in the second recess. The method includes forming a first lens on the first dielectric structure. The method includes forming a second lens on the second dielectric structure.

[0131] In some embodiments, the above method may further include forming a first trench in a substrate, wherein the first trench is between a first photodiode and a second photodiode, and the first photodiode and the second photodiode are in the substrate, and a third dielectric structure is formed in the first trench.

[0132] In some embodiments, the step of forming the first recess may include forming a first recess having tapered sidewalls, and the step of forming the first dielectric structure includes forming a first dielectric structure having tapered sidewalls, wherein the tapered sidewalls of the first dielectric structure correspond to the tapered sidewalls of the first recess.

[0133] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will recognize that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made thereto without departing from the spirit and scope of this disclosure.

[0134] Although the subject matter of this disclosure has been described using language specific to structural features or methodological actions, it should be understood that the subject matter of the appended claims is not limited to the specific features or actions described above, but is disclosed as an exemplary form for implementing at least some of the claims.

[0135] Various operations are provided in the embodiments herein. The order in which some or all of the operations are described should not be construed as implying that these operations must be performed in that order. It should be understood that alternative orders will also have the beneficial effects of this description. Furthermore, it should be understood that not all operations are required to be present in every embodiment provided herein. Additionally, it should be understood that in some embodiments, not all operations are necessary.

[0136] It should be understood that in some embodiments, for example for the purposes of simplicity and ease of understanding, the layers, features, elements, etc. illustrated herein are illustrated with respect to specific dimensions (e.g., structural dimensions or orientations), and the actual dimensions of the layers, features, elements, etc. are substantially different from the dimensions illustrated herein. Furthermore, various techniques exist, such as at least one of the following, to form the layers, regions, features, elements, etc. mentioned herein, including etching, planarization, implantation, doping, spin coating, sputtering, growth, or deposition techniques (e.g., chemical vapor deposition).

[0137] Furthermore, the term "exemplary" is used herein to refer to something serving as an example, instance, or illustration, and not necessarily to something advantageous. The word "or" as used in this application is intended to refer to an inclusive "or" rather than an exclusive "or." Additionally, the term "a" and "an" as used in this application and the appended claims are generally considered to mean "one or more," unless otherwise specified or clearly indicated from the context to refer to the singular form. Furthermore, expressions such as "at least one of A and B" generally refer to A or B, or both A and B. Moreover, with regard to the use of "includes," "having," "with," or variations thereof, these terms are intended to indicate inclusion in a manner similar to the term "comprising." Additionally, unless otherwise specified, "first," "second," etc., are not intended to imply temporal, spatial, or sequential aspects. Specifically, these terms are used only as identifiers, names, etc., for features, elements, projects, etc. For example, a first element and a second element generally correspond to element A and element B, or two different elements, or two identical elements, or the same element.

[0138] Furthermore, although this disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure encompasses all such modifications and modifications and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned elements (e.g., elements, resources, etc.), the terminology used to describe such elements is intended to correspond to any element performing a specified function (e.g., functionally equivalent) of the element (unless otherwise stated), even if the element is not structurally equivalent to the disclosed structure. Additionally, although a particular feature of this disclosure may be disclosed only with respect to one embodiment of several embodiments, this feature may be combined with one or more other features of other embodiments where it may be desirable and advantageous for any given or particular application.

Claims

1. A semiconductor configuration, characterized by Include: A first photodiode, wherein the first photodiode is embedded in a substrate; and A lens array, wherein the lens array is on the substrate, wherein: The first group of lenses in the lens array is on the first photodiode, and the first group of lenses includes a first lens and a second lens; A plurality of first recesses are defined in an upper surface of a first portion of the substrate, wherein the first portion is located below the first lens and above the first photodiode; A plurality of second recesses are defined in an upper surface of a second portion of the substrate, wherein the second portion is located below the second lens and above the first photodiode; A third portion of the substrate is located between the first recesses and the second recesses and below the junction of the first lens and the second lens, wherein an upper surface of the third portion is flat; and The radiation incident on the first group of lenses is guided by the first group of lenses to the first photodiode.

2. The semiconductor configuration of claim 1, wherein Also includes: A first dielectric layer, wherein a first portion of the first dielectric layer is offset laterally from the first photodiode.

3. The semiconductor configuration of claim 2, wherein, Also includes: A second photodiode, wherein the second photodiode is embedded in the substrate, wherein: The first portion of the first dielectric layer is offset laterally from the second photodiode; and The first portion of the first dielectric layer is located between the first photodiode and the second photodiode.

4. The semiconductor configuration of claim 3, wherein, in: A second group of lenses in the lens array is located on the second photodiode.

5. The semiconductor configuration of claim 1, wherein, Also includes: A first dielectric layer, wherein: A first portion of the first dielectric layer is located on the first photodiode; The first portion of the first dielectric layer has a tapered sidewall; and A first portion of the substrate separates the first portion of the first dielectric layer from the first photodiode.

6. The semiconductor configuration of claim 5, wherein, in: The first portion of the substrate has a first tapered sidewall, wherein the first tapered sidewall is aligned with the tapered sidewall of the first portion of the first dielectric layer.

7. The semiconductor configuration of claim 6, wherein, in: A second portion of the first dielectric layer is located on the first photodiode; The second portion of the first dielectric layer has a tapered sidewall; and The first portion of the substrate has a second tapered sidewall, wherein the second tapered sidewall is aligned with the tapered sidewall of the second portion of the first dielectric layer.

8. The semiconductor configuration according to claim 7, characterized in that, in: The first tapered sidewall of the first portion of the substrate has a first slope; The second tapered sidewall of the first portion of the substrate has a second slope; and The second slope is opposite in polarity to the first slope.

9. The semiconductor configuration according to claim 5, characterized in that, in: The second portion of the first dielectric layer is located on the first photodiode; The second portion of the first dielectric layer has a tapered sidewall; The second portion of the substrate separates the second portion of the first dielectric layer from the first photodiode; A first lens of the first group of lenses is located on the first portion of the first dielectric layer and the first portion of the substrate; and A second lens of the first group of lenses is located on the second portion of the first dielectric layer and the second portion of the substrate.

10. A semiconductor configuration, characterized in that, Include: A first element, wherein the first element is in a substrate; A first dielectric layer, wherein the first dielectric layer is located on the substrate, wherein: A first portion of the first dielectric layer is located on the first element; The first portion of the first dielectric layer has a tapered sidewall; A first portion of the substrate separates the first portion of the first dielectric layer from the first element; A second portion of the first dielectric layer is located on the first element; The second portion of the first dielectric layer has a tapered sidewall; A second portion of the substrate separates the second portion of the first dielectric layer from the first element; and A lens array, wherein the lens array is on the first dielectric layer, wherein: A first lens of the lens array is located on the first portion of the first dielectric layer and the first portion of the substrate; A second lens of the lens array is located on the second portion of the first dielectric layer and the second portion of the substrate; A plurality of first recesses are defined in an upper surface of the first portion of the substrate; A plurality of second recesses are defined in an upper surface of the second portion of the substrate; and A third portion of the substrate is located between the first recesses and the second recesses and below the junction of the first lens and the second lens, wherein an upper surface of the third portion is flat.

11. The semiconductor configuration according to claim 10, characterized in that, in: The first portion of the substrate has a first tapered sidewall, wherein the first tapered sidewall is aligned with the tapered sidewall of the first portion of the first dielectric layer.

12. The semiconductor configuration according to claim 11, characterized in that, in: The first portion of the substrate has a second tapered sidewall, wherein the second tapered sidewall is aligned with the tapered sidewall of the second portion of the first dielectric layer.

13. The semiconductor configuration according to claim 12, characterized in that, in: The first tapered sidewall of the first portion of the substrate has a first slope; The second tapered sidewall of the first portion of the substrate has a second slope; and The second slope is opposite in polarity to the first slope.

14. The semiconductor configuration according to claim 10, characterized in that, in: A third portion of the first dielectric layer is offset laterally from the first element.

15. The semiconductor configuration according to claim 14, characterized in that, Also includes: A second element, wherein the second element is in the substrate, wherein: The third portion of the first dielectric layer is offset laterally from the second element; and The third portion of the first dielectric layer is located between the first element and the second element.

16. The semiconductor configuration according to claim 15, characterized in that, in: A third lens and a fourth lens of the lens array are located on the second element.

17. The semiconductor configuration according to claim 10, characterized in that, in: The first component is a photodiode.

18. A method for forming a semiconductor configuration, characterized in that, Include: A plurality of first recesses are formed in a first portion of a substrate above a first photodiode, wherein the first photodiode is in the substrate; A plurality of second recesses are formed in a second portion of the substrate located above the first photodiode; A third portion of the substrate is retained between the plurality of first recesses and the plurality of second recesses, such that the upper surface of the third portion below the junction of the first lens and the second lens to be formed is flat; Multiple first dielectric structures are formed in these first depressions; Multiple second dielectric structures are formed in these second depressions; A first lens is formed in these first dielectric structures; and A second lens is formed within these second dielectric structures.

19. The method for forming a semiconductor configuration according to claim 18, characterized in that, Also includes: A first trench is formed in the substrate, wherein the first trench is between the first photodiode and the second photodiode, and the first photodiode and the second photodiode are in the substrate; as well as A third dielectric structure is formed in the first trench.

20. The method for forming a semiconductor configuration according to claim 18, characterized in that, in: The step of forming the first recesses includes forming the first recesses having a plurality of tapered sidewalls; and The step of forming the first dielectric structures includes forming the first dielectric structures having a plurality of tapered sidewalls, wherein the tapered sidewalls of the first dielectric structures correspond to the tapered sidewalls of the first recesses.

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