Semiconductor structure

Abstract

A semiconductor structure, a sub-pixel includes at least one second-conductivity-type hinge photodiode layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one second-conductivity-type hinge photodiode layer forms a PN junction with a substrate semiconductor layer. The at least one transfer gate stack structure can at least partially laterally surround the at least one second-conductivity-type hinge photodiode layer around a geometric center of the second-conductivity-type hinge photodiode layer with a total azimuthal extension angle between 240 degrees and 360 degrees. The at least one transfer gate stack structure can include a plurality of edges that cover different sections of a perimeter of the at least one second-conductivity-type hinge photodiode layer, respectively. The floating diffusion region includes a portion between a first edge and a second edge. Further, there can be multiple transfer gate stack structures and multiple floating diffusion regions for a sub-pixel.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a device comprising a metal-oxide-semiconductor (MOS) photodetector such as an image sensor, and a method thereof for forming the same. Background Technology

[0002] Semiconductor image sensors are used to sense electromagnetic radiation, such as visible light, infrared radiation, and / or ultraviolet light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in a variety of applications. For example, such image sensors can be used in digital cameras or embedded cameras in mobile devices. These devices use pixel arrays (which may include photodiodes and transistors) to detect radiation using electron-hole pair photogeneration. A large PN junction area can increase the photosensitivity of a photodetector. However, for such a large PN junction area in a photodetector, the transfer rate of charge to the floating diffusion region can be slow. A faster transfer rate of charge to the floating diffusion region can improve the operating speed of CMOS image sensors. Summary of the Invention

[0003] The purpose of this disclosure is to provide a semiconductor structure including at least one example of a sub-pixel located on a semiconductor substrate, the semiconductor substrate including a substrate semiconductor layer doped with a first conductivity type. Each of the at least one example of a sub-pixel includes: a second conductivity type hinged photodiode layer, at least one floating diffusion region, and at least one transfer gate stack structure. The second conductivity type hinged photodiode layer forms a PN junction with the substrate semiconductor layer. The at least one floating diffusion region is laterally spaced from the periphery of the second conductivity type hinged photodiode layer. The at least one floating diffusion region at least partially laterally surrounds the second conductivity type hinged photodiode layer. The at least one transfer gate stack structure includes a corresponding transfer gate dielectric and a corresponding transfer gate electrode. The at least one transfer gate stack structure is located between the second conductivity type hinged photodiode layer and the at least one floating diffusion region. The at least one transfer gate stack structure at least partially laterally surrounds the second conductivity type hinged photodiode layer with a total azimuth extension angle around the geometric center of the second conductivity type hinged photodiode layer. The total azimuth extension angle ranges from 240 degrees to 360 degrees.

[0004] The purpose of this disclosure is to provide another example of a semiconductor structure including at least one instance of a sub-pixel located on a semiconductor substrate, the semiconductor substrate including a substrate semiconductor layer doped with a first conductivity type. Each of the at least one instance of a sub-pixel includes: at least one second conductivity type hinged photodiode layer, a floating diffusion region, and a transfer gate stack structure. The at least one second conductivity type hinged photodiode layer forms at least one PN junction with the substrate semiconductor layer. The floating diffusion region is laterally spaced from the at least one second conductivity type hinged photodiode layer. The transfer gate stack structure includes a transfer gate dielectric and a transfer gate electrode, and the transfer gate stack structure is located between the floating diffusion region and each of the at least one second conductivity type hinged photodiode layer. The transfer gate stack structure has a first edge and a second edge, the first edge covering a first segment of at least a periphery of the at least one second conductivity type hinged photodiode layer, and the second edge covering a second segment of at least a periphery of the at least one second conductivity type hinged photodiode layer. The floating diffusion region includes a portion located between the first edge and the second edge.

[0005] The purpose of this disclosure is to provide another embodiment of a semiconductor structure including at least one example of a sub-pixel located on a semiconductor substrate, the semiconductor substrate including a substrate semiconductor layer doped with a first conductivity type. Each of the at least one example of a sub-pixel includes: a second conductivity type hinged photodiode layer, a plurality of floating diffusion regions, and at least one transfer gate stack structure. The second conductivity type hinged photodiode layer forms a PN junction with the substrate semiconductor layer. The floating diffusion regions are laterally spaced from the second conductivity type hinged photodiode layer. The at least one transfer gate stack structure includes a corresponding transfer gate dielectric and a corresponding transfer gate electrode. The at least one transfer gate stack structure is located between the second conductivity type hinged photodiode layer and a corresponding one of the plurality of floating diffusion regions. Attached Figure Description

[0006] A better understanding of the features disclosed herein can be obtained from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A This is a plan view of a first configuration of the pixel array of an image sensor according to an embodiment of the present disclosure;

[0008] Figure 1B This is a plan view of a second configuration of the pixel array of an image sensor according to another embodiment of the present disclosure;

[0009] Figure 2A This is a plan view of the front-side sensor element in the region of a sub-pixel in a first configuration of a first exemplary structure according to an embodiment of the present disclosure;

[0010] Figure 2B It is along Figure 2A The first exemplary structure of the hinged vertical plane B-B'-B” is shown in a vertical cross section.

[0011] Figure 2C Is Figure 2A and Figure 2B A scaled-down plan view of the front-side sensor element within a pixel in the first configuration of the first exemplary structure;

[0012] Figure 2D This is a plan view of the front-side sensor element in the region of a sub-pixel in a second configuration of a first exemplary structure according to an embodiment of the present disclosure;

[0013] Figure 2E This is a plan view of the front-side sensor element in the region of a sub-pixel in a third configuration of a first exemplary structure according to an embodiment of the present disclosure;

[0014] Figure 2F This is a plan view of the front-side sensor element in the region of a sub-pixel in a fourth configuration of a first exemplary structure according to an embodiment of the present disclosure;

[0015] Figure 3A This is a plan view of the front sensing element within the region of a sub-pixel in the first configuration of the second exemplary structure according to the embodiments of this disclosure;

[0016] Figure 3B This is a plan view of the front sensing element within the region of a sub-pixel in a second configuration of a second exemplary structure according to an embodiment of the present disclosure;

[0017] Figure 3C This is a plan view of the front sensing element within the region of a sub-pixel in the third configuration of the second exemplary structure according to the embodiments of this disclosure;

[0018] Figure 3D This is a plan view of the front sensing element within the region of a sub-pixel in the fourth configuration of the second exemplary structure according to the embodiments of this disclosure;

[0019] Figure 3E This is a plan view of the front sensing element within the region of a sub-pixel in the fifth configuration of the second exemplary structure according to the embodiments of this disclosure;

[0020] Figure 3F This is a plan view of the front sensing element within the region of a sub-pixel in the sixth configuration of the second exemplary structure according to the embodiments of this disclosure;

[0021] Figure 4AThis is a plan view of the front sensing element within the region of a sub-pixel in the first configuration of the third exemplary structure according to the embodiments of this disclosure;

[0022] Figure 4B This is a plan view of the front sensing element within the region of a sub-pixel in the second configuration of the third exemplary structure according to the embodiments of this disclosure;

[0023] Figure 4C This is a plan view of the front sensing element within the region of a sub-pixel in a third configuration of a third exemplary structure according to an embodiment of the present disclosure;

[0024] Figure 4D This is a plan view of the front sensing element within the region of a sub-pixel in the fourth configuration of the third exemplary structure according to the embodiments of this disclosure;

[0025] Figure 4E This is a plan view of the front sensing element within the region of a sub-pixel in the fifth configuration of the third exemplary structure according to the embodiments of this disclosure;

[0026] Figure 4F This is a plan view of the front sensing element within the region of a sub-pixel in the sixth configuration of the third exemplary structure according to the embodiments of this disclosure;

[0027] Figure 5 This is a vertical cross-sectional view of an exemplary structure after the metal interconnect structure formed in the interconnect level dielectric layer according to an embodiment of the present disclosure has been formed and after attachment to a carrier substrate.

[0028] Figure 6 This is a vertical cross-sectional view of an exemplary structure after thinning of a semiconductor substrate according to an embodiment of the present disclosure;

[0029] Figure 7 This is a vertical cross-sectional view of an exemplary structure after a deep trench has been formed on the back side of a semiconductor substrate according to an embodiment of the present disclosure.

[0030] Figure 8 This is a vertical cross-sectional view of an exemplary structure after removing the hard mask layer and the connecting pad dielectric layer according to an embodiment of the present disclosure.

[0031] Figure 9 This is a vertical cross-sectional view of an exemplary structure after the formation of a dielectric metal oxide pad and a dielectric isolation layer according to an embodiment of the present disclosure;

[0032] Figure 10 This is a vertical cross-sectional view of an exemplary structure after the formation of a deep trench isolation structure according to an embodiment of the present disclosure;

[0033] Figure 11This is a vertical cross-sectional view of an exemplary structure after forming an anti-reflective coating, an optical refractive layer, a dielectric grating material layer, a metallized refractive material layer, and a patterned photoresist layer according to an embodiment of the present disclosure.

[0034] Figure 12A This is a vertical cross-sectional view of an exemplary structure after forming a composite grid structure according to an embodiment of the present disclosure;

[0035] Figure 12B yes Figure 12A The illustrative plan view of the structure, with the hinged vertical plane A-A' corresponding to Figure 12A The vertical cross-sectional view of the plane;

[0036] Figure 13 This is a vertical cross-sectional view of an exemplary structure after the formation of the optically transparent layer, color filter, and lens according to an embodiment of the present disclosure;

[0037] Figure 14 This is a vertical cross-sectional view of an exemplary structure after the carrier substrate has been removed according to an embodiment of the present disclosure.

[0038] Figure 15 This is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure;

[0039] Figure 16 This is a flowchart illustrating exemplary processing steps for forming an image sensor according to embodiments of the present disclosure.

[0040] [Symbol Explanation]

[0041] 500, 510: Semiconductor substrate

[0042] 600: Front-side sensor element

[0043] 601: Substrate semiconductor layer

[0044] 602: Second conductive hinged photodiode layer

[0045] 603: First conductive hinged photodiode layer

[0046] 605: Transfer gate electrode

[0047] 606: Embedded second-conductivity hinged photodiode layer

[0048] 607: First conductive well

[0049] 608: Floating diffusion region

[0050] 609: Front surface

[0051] 611: Transfer transistor body region

[0052] 612: Active Region

[0053] 614: Gate dielectric

[0054] 614T: Transfer gate dielectric

[0055] 615: Gate electrode

[0056] 620: Shallow trench isolation structure

[0057] 630: Transfer transistor

[0058] 640: Reset transistor

[0059] 650: Source follower transistor

[0060] 660: Select Transistor

[0061] 670: Interconnect-level dielectric layer

[0062] 680: Metal interconnect structure

[0063] 682: Metal conductive through-hole structure

[0064] 684: Metal wire structure

[0065] 689: Joining buffer layer

[0066] 690: Carrier substrate

[0067] 709: Backside surface

[0068] 711: Connecting pad dielectric layer

[0069] 712: Hard mask layer

[0070] 719: Deep trench

[0071] 720: Deep trench isolation structure

[0072] 721: Dielectric metal oxide pad

[0073] 722: Dielectric isolation layer

[0074] 732: Anti-reflective coating

[0075] 734: Optical buffer layer

[0076] 740: Grid structure

[0077] 742: Dielectric lattice structure

[0078] 742L: Dielectric grid material layer

[0079] 744: Metallized Grid Structure

[0080] 744L: Metallized refractive material layer

[0081] 747: Photoresist layer

[0082] 770: Optically transparent layer

[0083] 780, 781, 782, 783: Color filters

[0084] 790: Optical lens

[0085] 800: Subpixel

[0086] 801: First subpixel

[0087] 801D: First Detector Area

[0088] 801S: First sensing circuit area

[0089] 802: Second subpixel

[0090] 802D: Second Detector Area

[0091] 802S: Third sensing circuit area

[0092] 803: Third subpixel

[0093] 803D: Third Detector Area

[0094] 803S: Third sensing circuit area

[0095] 900: pixels

[0096] 1000: Array

[0097] 1610, 1620, 1630, 1640: Steps

[0098] 6051: First Edge

[0099] 6052: Second Edge

[0100] 6053: Third Edge

[0101] 6054: Fourth Edge

[0102] A-A', B-B'-B” : Hinged vertical plane

[0103] C1, C2, C3, Cj, C(N-1), CN: Columns

[0104] COLBUS: Column output bus

[0105] FD: Floating Diffusion Region

[0106] GC: Geometric Center

[0107] hd1, hd2: Horizontal direction

[0108] P11, P12, P13, P1N, P21, P22, P23, P31, P32, P33, Pij, PM1, PMN: Pixels

[0109] R1,R2,R3,Ri,R(M-1),RM: row

[0110] RST: Reset transistor

[0111] SEL: Select Transistor

[0112] SF: Source Follower

[0113] TG: Transfer gate electrode

[0114] UC: Unit

[0115] α: Total azimuth extension angle

[0116] α1: First azimuth extension angle

[0117] α2: Second azimuth extension angle Detailed Implementation

[0118] The following disclosure provides numerous different embodiments or examples to implement different features of the provided object. Specific examples of components and arrangements described below are provided to simplify this disclosure. Of course, these are merely examples and not intended to limit this disclosure. For example, in the description, a first feature is formed on or over a second feature; this may include embodiments where the first and second features are formed in direct contact, or embodiments where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or words may be repeated in various instances in this disclosure. This repetition is for the purpose of brevity and clarity, but is not in itself intended to specify relationships between the various embodiments and / or architectures discussed.

[0119] Furthermore, spatial relative terms such as "below," "below," "lower," "above," and "upper" may be used here to facilitate the explanation of the relationship between one element or feature as illustrated in the accompanying drawings and another element (or other elements or features). These spatially relative terms are intended to cover not only the orientation shown in the accompanying drawings but also different orientations of the device during use or operation. The device may be positioned in different ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can also be interpreted accordingly.

[0120] The embodiments disclosed herein relate to a semiconductor device, and more particularly to a device comprising a metal-oxide-semiconductor (MOS) photodetector such as an image sensor, and a method thereof for forming the same.

[0121] Generally, the structures and methods of the embodiments disclosed herein can be used to provide image sensors with a faster charge transfer speed than a pinned photodiode layer. The pinned photodiode layer can be used as a charge collection region, from which charge is collected and transferred to a floating diffusion region via a semiconductor channel located below the transfer gate electrode. The transfer gate electrode can have a non-linear shape. Therefore, the transfer gate electrode can provide a smaller average distance between the pinned photodiode layer and the floating diffusion region. The horizontal cross-sectional shape of the floating diffusion region can be selected such that the entire transfer gate electrode has the same channel length. Therefore, the horizontal cross-sectional shape of the floating diffusion region can be non-rectangular, and this non-rectangular shape can be annular, arc-shaped, have protruding portions, or have multiple separated portions.

[0122] In one embodiment, the floating diffusion region may partially or completely laterally surround the transfer gate electrode. The transfer gate electrode may partially or completely laterally surround the hinged photodiode layer. In another embodiment, the floating diffusion region may include a laterally projecting portion protruding toward the geometric center of the hinged photodiode layer. In yet another embodiment, multiple floating diffusion regions may be formed in different peripheral regions of the hinged photodiode layer.

[0123] Figure 1A This is a plan view of a first configuration of the pixel array of an image sensor according to an embodiment of the present disclosure. Figure 1B This is a plan view of a second configuration of the pixel array of an image sensor according to another embodiment of this disclosure. Figure 1A and Figure 1BThe plan view shown illustrates a first configuration and a second configuration of the array 1000 of pixels 900 of the image sensor. The image sensor may be a backside illuminated (BSI) image sensor device. However, it should be understood that the embodiments disclosed herein can also be used in a front side illuminated (FSI) image sensor.

[0124] To generate an image from the image sensor, each pixel 900 represents a minimum unit area. The region containing the array 1000 of pixels 900 is referred to herein as the pixel array region. Pixels 900 within the pixel array region can be arranged in rows and columns. For example, the pixel array region can contain M rows and N columns, where M and N are in the range of 1 to 2. 16 Integers between, for example, 2 8 Up to 2 14 The rows of pixel 900 can be consecutively numbered integers from 1 to M, and the columns of pixel 900 can be consecutively numbered integers from 1 to N. Pixel P ij This refers to pixel 900 located in the i-th row and j-th column.

[0125] Each pixel 900 includes at least one photodetector for detecting radiation within a given wavelength range. Each pixel 900 may include multiple photodetectors for detecting radiation within a corresponding wavelength range. The wavelength ranges of radiation detected by the multiple photodetectors may be different. In one embodiment, each pixel 900 may include multiple sub-pixels, each sub-pixel including a corresponding combination of a photodetector and electronic circuitry for detecting radiation impinging on the photodetector. For example, pixel 900 may include sub-pixels for detecting radiation in the red light wavelength range (e.g., 635 nm to 700 nm), sub-pixels for detecting radiation in the green light wavelength range (e.g., 520 nm to 560 nm), and sub-pixels for detecting radiation in the blue light wavelength range (e.g., 450 nm to 490 nm), these sub-pixels being referred to as red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.

[0126] Generally, pixel 900 generates information about the illumination radiation in the unit detection area. Subpixels generate information related to the intensity of illumination radiation within a specific wavelength range detected in the unit detection area. Monochrome pixel 900 may contain only a single subpixel. Pixel 900 used to detect the spectral distribution of illumination radiation contains multiple subpixels having at least two different detection wavelength ranges. Multiple photodetectors in the pixel array area may include multiple photodiodes, multiple complementary metal-oxide-semiconductor (CMOS) image sensors, multiple charge-coupled device (CCD) sensors, active sensors, passive sensors, other suitable sensors, or combinations thereof.

[0127] Figure 2A This is a plan view of the front-side sensor element within the region of a sub-pixel in a first configuration of a first exemplary structure according to an embodiment of the present disclosure. Figure 2B It is along Figure 2A The first illustrative vertical cross-sectional view of the hinged vertical plane B-B'-B". Figure 2C Is Figure 2A and Figure 2B A scaled-down plan view of the front-side sensor element within a pixel in the first configuration of the first exemplary structure. Figure 2D This is a plan view of the front-side sensor element within the region of a sub-pixel in a second configuration of a first exemplary structure according to an embodiment of the present disclosure. Figure 2E This is a plan view of the front-side sensor element within the region of a sub-pixel in a third configuration of a first exemplary structure according to an embodiment of the present disclosure. Figure 2F This is a plan view of the front-side sensor element within the region of a sub-pixel in a fourth configuration of a first exemplary structure according to an embodiment of the present disclosure. Figures 2A to 2F The various configurations of the first example structure are illustrated. Figures 2A to 2C The first configuration of the first example structure is illustrated. Figure 2D The second configuration of the first example structure is illustrated. Figure 2E The third configuration of the first example structure is illustrated. Figure 2F A fourth configuration of the first exemplary structure is illustrated. Various configurations of the first exemplary structure can be derived by changing the layout of the hinged photodiode layer, which includes the second conductive hinged photodiode layer 602, the floating diffusion region 608, and the transfer gate stack structure (614T, 605).

[0128] Figures 2A to 2FThe diagram illustrates a front-side sensor element 600 within a sub-pixel region of an image sensor. The semiconductor substrate 500 includes a substrate semiconductor layer 601. The front-side sensor element 600 refers to all elements of an image sensor that can be formed on the front surface 609 of the semiconductor substrate 500 or within the substrate semiconductor layer 601. Each sub-pixel may include a photodetector and sensing circuitry for that photodetector. A group of sub-pixels can be used for a single pixel, and can be as follows: Figure 1A or Figure 1B The diagram illustrates an array 1000 of pixels, or provides an image sensor in any other suitable array configuration. Each subpixel may contain a unit cell UC, which may be repeated along at least one horizontal direction (hd1, hd2) to provide a front-side sensing element for a single pixel 900, which may contain a single subpixel, two subpixels, or three or more subpixels. In one embodiment, multiple instances of the unit cell UC may be repeated along at least one horizontal direction (hd1, hd2). For example, the repeatable unit cell UC may be a unit cell UC of a two-dimensional array, which is replicated periodically along a first horizontal direction hd1 and periodically along a second horizontal direction hd2. As described above, the two-dimensional array may be a rectangular array or a hexagonal array. Thus, the second horizontal direction hd2 may or may not be perpendicular to the first horizontal direction hd1.

[0129] Each sub-pixel may be formed on or within a substrate semiconductor layer 601, which provides a front surface 609 and a rear surface. The substrate semiconductor layer 601 comprises a semiconductor material such as silicon, germanium, a silicon-germanium alloy, a compound semiconductor material, or any other semiconductor material whose bandgap does not exceed the energy of the photons to be detected. The material within the substrate semiconductor layer 601 may be selected based on the energy range (i.e., wavelength) of the photons to be detected by the sub-pixel. In one embodiment, the substrate semiconductor layer 601 may comprise single-crystal silicon. Commercially available single-crystal semiconductors may be used for the semiconductor substrate 500. The semiconductor substrate 500 provided by this processing step has a sufficiently high thickness to withstand standard complementary metal-oxide-semiconductor (CMOS) processing steps. For example, the thickness of the semiconductor substrate 500 may range from 200 micrometers to 1 millimeter, although less or more thickness may also be used.

[0130] The top of the substrate semiconductor layer 601 may be appropriately doped to have a first conductivity type, which may be P-type or N-type. For example, an epitaxial semiconductor deposition process may be performed to form a single-crystal epitaxial semiconductor material layer on top of the substrate semiconductor layer 601, such that the atomic concentration of the dopant of the first conductivity type is in the range of 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×1016 / cm 3 Although fewer or more atomic concentrations can also be used. The thickness of a single-crystal epitaxial semiconductor material layer can range from 1 micrometer to 10 micrometers, although fewer or more thicknesses can also be used.

[0131] A first conductivity well 607 can be formed by ion implantation around the region, wherein a shallow trench isolation structure 620 can subsequently be formed. The atomic concentration of the first conductivity dopant in the first conductivity well 607 ranges from 1.0 × 10⁻⁶. 15 / cm 3 Up to 1.0×10 18 / cm 3 Although fewer or more atomic concentrations can also be used. Shallow trench isolation structures 620 can be formed to provide electrical isolation from various elements within the sub-pixel.

[0132] At least one masked ion implantation process can be used to implant dopants of a second conductivity type through the front surface of the semiconductor substrate 500. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is P-type, then the second conductivity type is N-type, and vice versa. Various doped regions with dopants of the second conductivity type are formed by at least one masked ion implantation process. A second conductivity type hinged photodiode layer 602 can be formed below the front surface 609 of the semiconductor substrate 500, such that the periphery of the second conductivity type hinged photodiode layer 602 overlaps with the edge of the transfer gate electrode 605 in a plan view. The lateral extent of the second conductivity type hinged photodiode layer 602 can be limited to one side of the transfer gate electrode 605 to be subsequently formed. Therefore, at least one edge of the second conductivity type hinged photodiode layer 602 can be laterally separated from the shallow trench isolation structure 620 by a region, and this region can subsequently form the transfer gate electrode 605 and the floating diffusion region 608.

[0133] By implanting a dopant of the second conductivity type at a depth at the bottom of the first conductivity type well 607, a buried second conductivity type hinged photodiode layer 606 can be formed at a depth at the bottom of the first conductivity type well 607 below the second conductivity type hinged photodiode layer 602. The implantation energy of the dopant of the second conductivity type is higher than that during the implantation process of forming the second conductivity type hinged photodiode layer 602. The buried second conductivity type hinged photodiode layer 606 may be adjacent to the first conductivity type well 607. In one embodiment, each buried second conductivity type hinged photodiode layer 606 may have a periphery adjacent to the first conductivity type well 607.

[0134] In one embodiment, the PN junction between the embedded second conductive hinged photodiode layer 606 and the first conductive well 607 can extend continuously around the entire area of ​​the sub-pixel to form a generally cylindrical surface without any openings passing through it. The PN junction can extend continuously below a portion of the shallow trench isolation structure 620 that laterally surrounds the sub-pixel. The top of the embedded second conductive hinged photodiode layer 606 can be adjacent to the bottom of the second conductive hinged photodiode layer 602 within each sub-pixel. In each sub-pixel, the area of ​​the second conductive hinged photodiode layer 602 can be entirely located within the area of ​​the underlying embedded second conductive hinged photodiode layer 606.

[0135] In one embodiment, the depth of the top surface of the buried second conductive hinged photodiode layer 606 may be in the range of 400 nanometers to 1500 nanometers, although less or more depths may also be used. In one embodiment, the depth of the bottom surface of the buried second conductive hinged photodiode layer 606 may be in the range of 800 nanometers to 2500 nanometers, although less or more depths may also be used.

[0136] The unimplanted portion of the substrate semiconductor layer 601 covering the buried second conductivity hinged photodiode layer 606 is doped with a first conductivity type and can subsequently be used as the body region of a transfer transistor. Thus, the unimplanted portion of the substrate semiconductor layer 601 covering the buried second conductivity hinged photodiode layer 606 is referred to herein as the transfer transistor body region 611. In one embodiment, the buried second conductivity hinged photodiode layer 606 may have the same lateral extent as the transfer transistor 630 to be subsequently formed, and the buried second conductivity hinged photodiode layer 606 may partially overlap with a shallow trench isolation structure 620 surrounding the combination of the second conductivity hinged photodiode layer 602 and the transfer transistor body region 611.

[0137] Gate stack structures (614, 605, 615) can be formed on the front surface 609 of a semiconductor substrate 500 by depositing and patterning a layer stack including a gate dielectric layer and a gate electrode layer. Each patterned portion of the layer stack constitutes a gate stack structure (614, 605, 615), which can be a transfer gate stack structure (614T, 605) or a control gate stack structure (614, 615). Each transfer gate stack structure (614T, 605) includes a gate dielectric and a gate electrode, wherein the gate dielectric is referred to herein as transfer gate dielectric 614T, and the gate electrode is referred to herein as transfer gate electrode 605. Each transfer gate stack structure (614T, 605) is located between the second conductivity hinged photodiode layer 602 and the floating diffusion region 608. Each control gate stack structure (614, 615) includes a respective layer stack of gate dielectric 614 in the sensing circuit and gate electrodes 615 of other transistors. The aforementioned sensing circuit may include a reset transistor 640, a source follower transistor 650, a select transistor 660, and other suitable transistors that can be used to amplify the signal generated by the photodetector of the sub-pixel.

[0138] Various active regions (608, 612) with a second conductivity type are formed, including a floating diffused region 608 serving as the drain region of a transmission transistor 630. The second conductivity type hinged photodiode layer 602 accumulates charge (e.g., electrons in an embodiment with an N-type second conductivity type) during sensing (i.e., when a sub-pixel actively detects photons illuminating it, for example, for the purpose of capturing a frame or photograph) serving as the source region of the transmission transistor 630. The active region 612 includes the source and drain regions of various transistors (640, 650, 660) in the sensing circuit. The floating diffused region 608 is perpendicularly spaced from the buried second conductivity type hinged photodiode layer 606 by a transfer transistor body region 611.

[0139] A masked ion implantation process can be used to form the floating diffusion region 608 and the active region 612 by implanting doped ions of a second conductivity type. The combination of individual patterned photoresist layers and gate stack structures (614, 605, 615) can be used as an ion implantation barrier structure (i.e., a mask structure) during the ion implantation process. The depth of the bottom surface of the active region 612 can range from 100 nanometers to 600 nanometers, for example from 150 nanometers to 400 nanometers, although less or more depths can also be used.

[0140] The first conductive hinged photodiode layer 603 can be directly formed on top of the second conductive hinged photodiode layer 602 by implanting doped ions of the first conductivity type. The first conductive hinged photodiode layer 603 suppresses depletion at the interface between the second conductive hinged photodiode layer 602 and the first conductive hinged photodiode layer 603, and the first conductive hinged photodiode layer 603 electrically stabilizes the second conductive hinged photodiode layer 602. In all top views of the various exemplary structures disclosed herein, the first conductive hinged photodiode layer 603 is omitted to clearly show the lateral extent of the second conductive hinged photodiode layer 602 located below the first conductive hinged photodiode layer 603. The depth of the PN junction between the first conductive hinged photodiode layer 603 and the second conductive hinged photodiode layer 602 can range from 5 nanometers to 100 nanometers, although less or more depths can also be used.

[0141] An interconnect-level dielectric layer 670 may be formed on the front surface 609 of the semiconductor substrate 500, and a metal interconnect structure 680 connecting various nodes of transistors (630, 640, 650, 660) may be formed within each sub-pixel. The interconnect-level dielectric layer 670 may contain a corresponding dielectric material such as undoped silicate glass, doped silicate glass, organosilicon glass, porous dielectric material, or a combination thereof. A dielectric liner containing various dielectric materials (such as silicon nitride, silicon oxynitride, silicon oxycarbide, and / or dielectric metal oxides) may optionally be used in the interconnect-level dielectric layer 670. The metal interconnect structure 680 may contain various metal conductive via structures 682 and various metal line structures 684. For example, a floating diffusion region 608 may be connected to the gate electrode 615 of the source follower transistor 650 through a subset of the metal interconnect structure 680. The photodetector may include a transfer transistor 630, and the photodetector may be connected to a sensing circuit that includes additional transistors (640, 650, 660).

[0142] In one embodiment, the gate length of the transfer gate stack structure (614T, 605), i.e., the width of the transfer gate stack structure (614T, 605) along the horizontal direction connecting the second conductive hinged photodiode layer 602 and the floating diffusion region 608, can be uniform throughout the entire direction. For example, the gate length of the transfer gate stack structure (614T, 605) can be in the range of 50 nanometers to 500 nanometers, although less or more gate lengths can also be used. According to one embodiment of this disclosure, the pattern of the second conductive hinged photodiode layer 602, the transfer gate stack structure (614T, 605), and the floating diffusion region 608 can be selected such that the maximum value of the lateral spacing distance between any point in the second conductive hinged photodiode layer 602 and the floating diffusion region 608 is not greater than the sum of half the maximum lateral dimension of the second conductive hinged photodiode layer 602 and the transfer gate stack structure (614T, 605). The gate length of the transfer gate stack structure (614T, 605) can be the lateral distance between a pair of parallel sidewalls of the transfer gate stack structure (614T, 605).

[0143] A known photodetector structure has a rectangular second conductive hinged photodiode layer and a rectangular floating diffusion region of the same width. The maximum lateral spacing between points in the second conductive hinged photodiode layer and the floating diffusion region is the sum of the total length of the second conductive hinged photodiode layer along the direction of current during charge transfer and the gate length of the transfer gate electrode. Various embodiments disclosed herein can reduce the maximum lateral spacing between points in the second conductive hinged photodiode layer 602 and the floating diffusion region 608 to levels below those provided in known photodetector structures.

[0144] In one embodiment, a sub-pixel may include a second conductive hinged photodiode layer 602 and a floating diffusion region 608. The second conductive hinged photodiode layer 602 and the substrate semiconductor layer 601 form a PN junction. The floating diffusion region 608 is laterally spaced from and laterally surrounds the second conductive hinged photodiode layer 602. The sub-pixel may include at least one transfer gate stack structure (614T, 605). The at least one transfer gate stack structure (614T, 605) includes a corresponding transfer gate dielectric 614T (which is one of the gate dielectrics 614) and a corresponding transfer gate electrode 605. The at least one transfer gate stack structure (614T, 605) is located between the second conductive hinged photodiode layer 602 and the at least one floating diffusion region 608 (in the plan view, i.e., in the top view). The at least one transfer gate stack structure (614T, 605) may be a single transfer gate stack structure (614T, 605).

[0145] The geometric center GC of the second conductive hinged photodiode layer 602 is a point with a specific Cartesian coordinate system, which is the average of the Cartesian coordinates of all points within the second conductive hinged photodiode layer 602. Regardless of the Cartesian coordinate system used for the calculations, the position of the geometric center GC of the second conductive hinged photodiode layer 602 is the same. Because the second conductive hinged photodiode layer 602 always provides the same density, the geometric center GC of the second conductive hinged photodiode layer 602 is the same as the centroid of the second conductive hinged photodiode layer 602.

[0146] The transfer gate stack structure (614T, 605) is located in the peripheral region of the sub-pixel, and the second conductive hinged photodiode layer 602 is located in the central region of the sub-pixel. Therefore, the at least one transfer gate stack structure (614T, 605) at least partially and laterally surrounds the second conductive hinged photodiode layer 602.

[0147] In one embodiment, the transfer gate stack structure (614T, 605) can completely surround the entire region of the second conductive hinged photodiode layer 602. In this case, the transfer gate stack structure (614T, 605) surrounds the geometric center GC of the second conductive hinged photodiode layer 602 with a total azimuth extension angle α of 360 degrees. The total azimuth extension angle α is the sum of all angles surrounding the geometric center GC of the second conductive hinged photodiode layer 602, in which the transfer gate stack structure (614T, 605) is present.

[0148] Reference Figure 2D By changing the ring-shaped configuration of the second conductive hinged photodiode layer 602 to an arc-shaped configuration, so that the second conductive hinged photodiode layer 602 does not completely surround the second conductive hinged photodiode layer 602, thus it can be seen from Figures 2A to 2C A second configuration of the first exemplary structure is derived from a first configuration of the first exemplary structure. In this case, the total azimuth extension angle α of the transfer gate stack structure (614T, 605) surrounding the geometric center GC of the second conductive hinged photodiode layer 602 is reduced to an angle value of less than 360 degrees. In one embodiment, the total azimuth extension angle α surrounding the geometric center GC of the second conductive hinged photodiode layer 602 may be in the range of 240 degrees to less than 360 degrees (such as 355 degrees).

[0149] Reference Figure 2E This can be achieved by dividing the transfer gate stack structure (614T, 605) into multiple transfer gate stack structures (614T, 605) partially surrounding the entire region of the second conductivity hinged photodiode layer 602. Figure 2D The second configuration of the first exemplary structure shown derives a third configuration of the first exemplary structure. In such an embodiment, a single transfer gate stack structure (614T, 605) partially surrounds the geometric center GC of the second conductive hinged photodiode layer 602 with a total azimuth extension angle α ranging from 240 degrees to less than 360 degrees (such as 355 degrees).

[0150] Reference Figure 2F This can be achieved by using multiple transfer gate stack structures (614T, 605) instead of a single transfer gate stack structure (614T, 605). Figure 2E The third configuration of the first exemplary structure shown derives a fourth configuration of the first exemplary structure. In one embodiment, the plurality of transfer gate stack structures (614T, 605) partially surround the entire region of the second conductive hinged photodiode layer 602. In such an embodiment, the plurality of transfer gate stack structures (614T, 605) partially surround the second conductive hinged photodiode layer 602 with a total azimuth extension angle α ranging from 240 degrees to less than 360 degrees (such as 355 degrees) around the geometric center GC of the second conductive hinged photodiode layer 602. The total azimuth extension angle α is the sum of all azimuth angles surrounding the geometric center GC of the second conductive hinged photodiode layer 602, in which the transfer gate stack structures (614T, 605) are present. For example, the total azimuth extension angle α is the sum of the first azimuth extension angle α1 and the second azimuth extension angle α2. The first azimuth extension angle α1 surrounds the geometric center GC of the second conductive hinged photodiode layer 602, wherein one of the plurality of transfer gate stack structures (614T, 605) is present in the second conductive hinged photodiode layer 602, and the second azimuth extension angle α2 surrounds the geometric center GC of the second conductive hinged photodiode layer 602, wherein another of the plurality of transfer gate stack structures (614T, 605) is present in the second conductive hinged photodiode layer 602. When multiple transfer gate stack structures (614T, 605) are used, the plurality of transfer gate electrodes 605 are interconnected with each other through a metal interconnect structure 680. The metal interconnect structure 680 may include a metal wire structure 684 and a pair of metal conductive via structures, wherein the pair of metal conductive via structures contact the bottom surface of the metal wire structure 684 and the top surface of a corresponding one of the transfer gate electrodes 605.

[0151] Refer to together Figures 2A to 2F The sub-pixel may include a second conductive hinged photodiode layer 602 and at least one floating diffusion region 608 (which may be...). Figure 2A , Figure 2C , Figure 2DThe single floating diffusion region 608 shown is, or Figure 2E , Figure 2F Multiple floating diffusion regions 608 are shown. The second conductive hinged photodiode layer 602 forms a PN junction with the substrate semiconductor layer 601. At least one floating diffusion region 608 is laterally spaced from the periphery of the second conductive hinged photodiode layer 602, and at least one floating diffusion region 608 at least partially laterally surrounds the second conductive hinged photodiode layer 602 (i.e., Figure 2D , Figure 2E , Figure 2F The portion shown is horizontally enclosed, or Figure 2A , Figure 2C (As shown, completely laterally enclosed). A sub-pixel may include at least one transfer gate stack structure (614T, 605), each transfer gate stack structure (614T, 605) comprising a corresponding transfer gate dielectric 614T (which is one of the gate dielectrics 614) and a corresponding transfer gate electrode 605, the at least one transfer gate stack structure (614T, 605) being located between the second conductivity-type hinged photodiode layer 602 and the at least one floating diffusion region 608 (in a plan view, i.e., in a top view). The at least one transfer gate stack structure (614T, 605) may be as follows: Figure 2A , Figure 2C , Figure 2D , Figure 2E The single transfer gate stack structure shown (614T, 605), or Figure 2F The multiple transfer gate stack structures shown are (614T, 605).

[0152] Generally, the at least one transfer gate stack structure (614T, 605) is located in the peripheral region of the sub-pixel, and the second conductive hinged photodiode layer 602 is located in the central region of the sub-pixel. Therefore, the at least one transfer gate stack structure (614T, 605) at least partially and laterally surrounds the second conductive hinged photodiode layer 602.

[0153] In one embodiment, the at least one transfer gate stack structure (614T, 605) may be a single transfer gate stack structure (614T, 605) that completely surrounds the entire region of the second conductive hinged photodiode layer 602. In such an embodiment, the at least one transfer gate stack structure (614T, 605) surrounds the geometric center GC of the second conductive hinged photodiode layer 602 with a total azimuth extension angle α of 360 degrees, such as... Figure 2A and Figure 2DAs shown. The total azimuth extension angle α is the sum of all angles surrounding the geometric center GC of the second conductive hinged photodiode layer 602, in which a transfer gate stack structure (614T, 605) exists.

[0154] In one embodiment, the at least one transfer gate stack structure (614T, 605) may be a single transfer gate stack structure (614T, 605) that partially surrounds the entire region of the second conductive hinged photodiode layer 602. In such an embodiment, the single transfer gate stack structure (614T, 605) partially surrounds the second conductive hinged photodiode layer 602 with a total azimuth extension angle α ranging from 240 degrees to less than 360 degrees (such as 355 degrees) around the geometric center GC of the second conductive hinged photodiode layer 602, such as... Figure 2E As shown.

[0155] In one embodiment, the at least one transfer gate stack structure (614T, 605) may be a plurality of transfer gate stack structures (614T, 605), which partially surround the entire region of the second conductive hinged photodiode layer 602. In such an embodiment, the plurality of transfer gate stack structures (614T, 605) partially surround the second conductive hinged photodiode layer 602 with a total azimuth extension angle α ranging from 240 degrees to less than 360 degrees (such as 355 degrees) around the geometric center GC of the second conductive hinged photodiode layer 602, such as... Figure 2F As shown. The total azimuth extension angle α is the sum of all azimuth angles surrounding the geometric center GC of the second conductive hinged photodiode layer 602, wherein the second conductive hinged photodiode layer 602 contains transfer gate stack structures (614T, 605). For example, the total azimuth extension angle α is the sum of the first azimuth extension angle α1 and the second azimuth extension angle α2, where the first azimuth extension angle α1 surrounds the geometric center GC of the second conductive hinged photodiode layer 602, wherein the second conductive hinged photodiode layer 602 contains one of the plurality of transfer gate stack structures (614T, 605), and the second azimuth extension angle α2 surrounds the geometric center GC of the second conductive hinged photodiode layer 602, wherein the second conductive hinged photodiode layer 602 contains another of the plurality of transfer gate stack structures (614T, 605).

[0156] In embodiments where at least one transfer gate stack structure (614T, 605) comprises multiple transfer gate stack structures (614T, 605), the multiple transfer gate electrodes 605 are interconnected with each other through a metal interconnect structure 680. The metal interconnect structure 680 may include a metal line structure 684 and a pair of metal conductive via structures, the pair of metal conductive via structures contacting the bottom surface of the metal line structure 684 and the top surface of a corresponding one of the transfer gate electrodes 605.

[0157] Generally, the total azimuth extension angle α surrounds the geometric center GC of the second conductive hinged photodiode layer 602 and can be in the range of 240 degrees to 360 degrees. Figure 2A , Figure 2C , Figure 2D , Figure 2E and Figure 2F As shown.

[0158] In one embodiment, the at least one floating diffusion region 608 may comprise a single floating diffusion region 608 and / or be composed of a single floating diffusion region 608, wherein the single floating diffusion region 608 partially or completely surrounds the entire region of the second conductive hinged photodiode layer 602 as a single continuous structure. The single floating diffusion region 608 may completely surround the entire region of the second conductive hinged photodiode layer 602 as a single continuous structure, such as... Figure 2A As shown. Optionally, the aforementioned single floating diffusion region 608 may partially surround a region of the second conductive hinged photodiode layer 602 as a single continuous structure, such as... Figure 2D As shown.

[0159] In one embodiment, the at least one floating diffusion region 608 may comprise a plurality of floating diffusion regions 608, which are laterally separated from each other by a shallow trench isolation structure 620, such as Figure 2E and Figure 2F As shown. The plurality of floating diffusion regions 608 may partially surround the region of the second conductive hinged photodiode layer 602 with gaps therebetween. The plurality of floating diffusion regions 608 may be electrically interconnected with each other through a metal interconnect structure 680, which may include at least one metal wire structure 684 and at least two metal conductive via structures.

[0160] In one embodiment, the shallow trench isolation structure 620 laterally surrounds and contacts each of the at least one floating diffusion region 608. In one embodiment, the shallow trench isolation structure 620 is laterally spaced from the second conductivity type hinged photodiode layer 602 by a portion of doped semiconductor material having a first conductivity type (i.e., by a transfer transistor body region 611, wherein the transfer transistor body region 611 is the body region of the transfer transistor 630 and the transfer transistor body region 611 contains the semiconductor channel of the transfer transistor 630).

[0161] Generally, sensing circuitry (640, 650, 660) for each sub-pixel can be provided within the region of a unit cell UC. In one embodiment, the various transistors of the sensing circuitry (640, 650, 660) can be arranged side-by-side within the region of a strip located near the edge of the unit cell UC, and the strip extends along the entire length of one side of the unit cell UC or extends along at least 30% of the length of one side of the unit cell UC, such as... Figures 2A to 2F As shown. In other embodiments, various transistors of the sensing circuit (640, 650, 660) may be arranged around the floating diffusion region 608 of the transfer transistor 630 in a region near the corner of the unit cell UC.

[0162] The first exemplary structure includes at least one instance of a sub-pixel. The first exemplary structure may include an image sensor comprising a pixel array located on a semiconductor substrate 500. The first exemplary structure may include a plurality of sub-pixels located within corresponding pixels in the pixel array. In one embodiment, each pixel located within the pixel array includes a corresponding instance of a sub-pixel.

[0163] Figure 3A This is a plan view of the front-side sensing element within the region of a sub-pixel in the first configuration of the second exemplary structure according to an embodiment of the present disclosure. Figure 3B This is a plan view of the front-side sensing element within the region of a sub-pixel in a second configuration of a second exemplary structure according to an embodiment of the present disclosure. Figure 3C This is a plan view of the front sensing element within the region of a sub-pixel in a third configuration of a second exemplary structure according to an embodiment of the present disclosure. Figure 3D This is a plan view of the front sensing element within the region of a sub-pixel in the fourth configuration of the second exemplary structure according to the embodiments of this disclosure. Figure 3E This is a plan view of the front sensing element within the region of a sub-pixel in the fifth configuration of the second exemplary structure according to the embodiments of this disclosure. Figure 3F This is a plan view of the front sensing element within the region of a sub-pixel in the sixth configuration of the second exemplary structure according to the embodiments of this disclosure.

[0164] Reference Figure 3A The shape of the second conductive hinged photodiode layer 602, the transfer gate stack structure (614T, 605), and the floating diffusion region 608 can be changed by providing a protruding portion of the floating diffusion region 608 at or near the geometric center of the second conductive hinged photodiode layer 602 to derive the first configuration of the second exemplary structure.

[0165] The first configuration of the second exemplary structure includes two second conductivity hinged photodiode layers 602 forming a PN junction with the substrate semiconductor layer 601. A floating diffusion region 608 may be laterally spaced from the two second conductivity hinged photodiode layers 602. A transfer gate stack structure (614T, 605) including a transfer gate dielectric 614T and a transfer gate electrode 605 may be located between the two second conductivity hinged photodiode layers 602 and the floating diffusion region 608. Although in Figure 3A While the transfer gate dielectric 614T is not explicitly shown, it should be understood that the transfer gate dielectric 614T has the same area as the transfer gate electrode 605. The transfer gate stack structure (614T, 605) may be located between the floating diffusion region 608 and each of the two second conductivity type hinged photodiode layers 602.

[0166] In one embodiment, the gate length of the transfer gate stack structure (614T, 605), i.e. the width of the transfer gate stack structure (614T, 605) along the horizontal direction connecting each of the two second conductive hinged photodiode layers 602 and the floating diffusion region 608, may be uniform overall.

[0167] Each of the two second conductive hinged photodiode layers 602 provides a periphery in its horizontal shape, referred to herein as the periphery of the respective second conductive hinged photodiode layer 602. Thus, the two second conductive hinged photodiode layers 602 provide two peripheries. In one embodiment, the two second conductive hinged photodiode layers 602 may be laterally spaced from each other by corresponding portions of a transfer gate stack structure (614T, 605).

[0168] The transfer gate stack structure (614T, 605) may have a first edge 6051 and a second edge 6052, the first edge 6051 covering a first segment of the two peripheries of the two second conductive hinged photodiode layers 602, and the second edge 6052 covering a second segment of the two peripheries of the two second conductive hinged photodiode layers 602.

[0169] According to one embodiment of this disclosure, the floating diffusion region 608 may include a portion located between a first edge 6051 and a second edge 6052. In one embodiment, the first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) may be parallel to each other.

[0170] In one embodiment, the floating diffusion region 608 and the transfer gate stack structure (614T, 605) may include diagonally extending straight sections that extend to the corners of the unit cell UC. In this case, the first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) may not be parallel to one of the horizontal directions (hd1, hd2), and the unit cell UC repeats along the horizontal direction. The geometric center GC of the second conductive hinged photodiode layer 602 may be located within the region of the floating diffusion region 608. Sensing circuitry (640, 650, 660) within each unit cell UC may be formed on one side of the rectangular region of the unit cell UC. The first edge 6051 of the transfer gate stack structure (614T, 605) can be connected to the second edge 6052 of the transfer gate stack structure (614T, 605) through another edge of the transfer gate stack structure (614T, 605) located on a part of the shallow trench isolation structure 620.

[0171] Reference Figure 3B This can be achieved by shortening the diagonally extending straight portion of the floating diffusion region 608 and the transfer gate stack structure (614T, 605). Figure 3A The first configuration of the second instance structure shown derives the second configuration of the second instance structure. In such a case, they can be merged. Figure 3A The two second conductive hinged photodiode layers 602 in the first configuration of the second exemplary structure are used to form a single second conductive hinged photodiode layer 602. The first edge 6051 of the transfer gate stack structure (614T, 605) and the second edge 6052 of the transfer gate stack structure (614T, 605) can be completely connected to each other by covering a section of the periphery of the second conductive hinged photodiode layer 602 with the other edge of the transfer gate stack structure (614T, 605).

[0172] Reference Figure 3C Sensing circuits (640, 650, 660) can be formed within the corner regions of the rectangular area of ​​the unit cell UC to detect the signal from the target area. Figure 3AThe first configuration of the second exemplary structure leads to the third configuration of the second exemplary structure. The first edge 6051 of the transfer gate stack structure (614T, 605) and the second edge 6052 of the transfer gate stack structure (614T, 605) can be connected to each other by the other edge of the transfer gate stack structure (614T, 605) covering a portion of the shallow trench isolation structure 620.

[0173] Reference Figure 3D Sensing circuits (640, 650, 660) can be formed within the corner regions of the rectangular area of ​​the unit cell UC to detect the signal from the target area. Figure 3C The third configuration of the second exemplary structure leads to the fourth configuration of the second exemplary structure. The first edge 6051 of the transfer gate stack structure (614T, 605) and the second edge 6052 of the transfer gate stack structure (614T, 605) can be completely connected to each other by the other edge of a segment of the transfer gate stack structure (614T, 605) covering the periphery of the second conductive hinged photodiode layer 602.

[0174] Reference Figure 3E A fifth configuration of the second exemplary structure can be derived from the first or third configuration of the second exemplary structure by forming a floating diffusion region 608 and a transfer gate stack structure (614T, 605) with a straight portion extending from one side of a rectangular shape parallel to the unit cell UC. In this case, the first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) can be parallel to one of the horizontal directions (hd1, hd2), and the unit cell UC repeats along the horizontal direction. The first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) can be connected to each other by the other edge of the transfer gate stack structure (614T, 605) covering a portion of the shallow trench isolation structure 620.

[0175] Reference Figure 3FA sixth configuration of the second exemplary structure can be derived from the second or fourth configuration of the second exemplary structure by forming a floating diffusion region 608 and a transfer gate stack structure (614T, 605) with a straight portion extending from one side of a rectangular shape parallel to the unit cell UC. In this case, the first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) can be parallel to one of the horizontal directions (hd1, hd2), and the unit cell UC repeats along the horizontal direction. The first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) can be completely connected to each other by covering a section of the periphery of the second conductive hinged photodiode layer 602 with the other edge of the transfer gate stack structure (614T, 605).

[0176] Generally, the shapes of the second conductive hinged photodiode layer 602, the transfer gate stack structure (614T, 605), and the floating diffusion region 608 can be modified by providing a protruding portion of the floating diffusion region 608 at or near the geometric center of the second conductive hinged photodiode layer 602, to derive from the first exemplary structure. Figures 3A to 3F The second example structure is shown with various configurations.

[0177] The second exemplary structure includes various configurations comprising at least one second conductivity hinged photodiode layer 602 forming at least one PN junction with the substrate semiconductor layer 601. The at least one second conductivity hinged photodiode layer 602 may be as follows: Figure 3B , Figure 3D The single second-conductivity hinged photodiode layer 602 shown, or may be as follows Figure 3A , Figure 3C , Figure 3E The multiple second-conductivity hinged photodiode layers 602 shown.

[0178] Various configurations of the second exemplary structure include a floating diffusion region 608 laterally spaced from the at least one second conductive hinged photodiode layer 602. A transfer gate stack structure (614T, 605) including a transfer gate dielectric 614T and a transfer gate electrode 605 may be located between the at least one second conductive hinged photodiode layer 602 and the floating diffusion region 608. Although in Figures 3A to 3F While the transfer gate dielectric 614T is not explicitly shown, it should be understood that the transfer gate dielectric 614T provides the same horizontal cross-sectional shape as the transfer gate electrode 605 shown in each configuration. The transfer gate stack structure (614T, 605) may be located between the floating diffusion region 608 and each of the at least one second conductivity type hinged photodiode layer 602.

[0179] In one embodiment, the gate length of the transfer gate stack structure (614T, 605), i.e. the width of the transfer gate stack structure (614T, 605) along the horizontal direction connecting each second conductive hinged photodiode layer 602 and the floating diffusion region 608, can be uniform overall.

[0180] Each second conductive hinged photodiode layer 602 provides a periphery in its horizontal shape, referred to herein as the periphery of the corresponding second conductive hinged photodiode layer 602. Therefore, the at least one second conductive hinged photodiode layer 602 provides at least one periphery. In embodiments where the at least one second conductive hinged photodiode layer 602 comprises a single second conductive hinged photodiode layer 602, the at least one second conductive hinged photodiode layer 602 may be a single periphery. Optionally, in embodiments where the at least one second conductive hinged photodiode layer 602 comprises a plurality of second conductive hinged photodiode layers 602, the at least one second conductive hinged photodiode layer 602 provides a plurality of peripheries. In embodiments where a plurality of second conductive hinged photodiode layers 602 are present, the second conductive hinged photodiode layers 602 may be laterally spaced from each other by corresponding portions of the transfer gate stack structure (614T, 605).

[0181] The transfer gate stack structure (614T, 605) may have a first edge 6051 and a second edge 6052, the first edge 6051 covering a first segment of at least one periphery of the at least one second conductive hinged photodiode layer 602, and the second edge 6052 covering a second segment of the at least one periphery of the at least one second conductive hinged photodiode layer 602. In embodiments where the at least one periphery is formed by a single periphery of a single second conductive hinged photodiode layer 602, the first edge 6051 may cover the first segment of the periphery of the single second conductive hinged photodiode layer 602 and the second edge 6052 may cover the second segment of the periphery of the single second conductive hinged photodiode layer 602, such as... Figure 3B , Figure 3D , Figure 3F As shown. In the embodiment where at least one periphery comprises multiple peripheries of a plurality of second conductive hinged photodiode layers 602, a first edge 6051 may cover a segment of a periphery of one of the plurality of second conductive hinged photodiode layers 602 and a second edge 6052 may cover a segment of the periphery of the other of the plurality of second conductive hinged photodiode layers 602, as shown. Figure 3A , Figure 3C , Figure 3E As shown.

[0182] According to one embodiment of this disclosure, the floating diffusion region 608 may include a portion located between the first edge 6051 and the second edge 6052. In one embodiment, the first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) may be parallel to each other, such as... Figures 3A to 3F As shown.

[0183] In one embodiment, the first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) may be parallel to one of the horizontal directions (hd1, hd2), and the unit cell UC repeats along the horizontal direction, such as... Figure 3E and Figure 3F As shown. Optionally, the first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) may not be parallel to one of the horizontal directions (hd1, hd2), and the unit cell UC repeats along the horizontal direction, as shown. Figures 3A to 3D As shown.

[0184] In one embodiment, the first edge 6051 and the second edge 6052 of the transfer gate stack structure (614T, 605) can be completely connected to each other by the other edge of a segment of the transfer gate stack structure (614T, 605) covering a periphery of the second conductive hinged photodiode layer 602, as shown. Figure 3B , Figure 3D , Figure 3F As shown. Optionally, the first edge 6051 of the transfer gate stack structure (614T, 605) and the second edge 6052 of the transfer gate stack structure (614T, 605) can be connected to each other by another edge of the transfer gate stack structure (614T, 605) covering a portion of the shallow trench isolation structure 620, as shown. Figure 3A , Figure 3C , Figure 3E As shown.

[0185] Generally, the transfer gate stack structure (614T, 605) includes a third edge 6053 and a fourth edge 6054, with the third edge 6053 adjacent to the first edge 6051 and the fourth edge 6054 connected to the second edge 6052. Significant variations in the orientation of the multiple edges may occur where the third edge 6053 is adjacent to the first edge 6051 and / or where the fourth edge 6054 is connected to the second edge 6052. The angle between the third edge 6053 and the first edge 6051 can be orthogonal or non-orthogonal. In one embodiment, the angle between the third edge 6053 and the first edge 6051 can be in the range of 45 degrees to 135 degrees. The angle between the fourth edge 6054 and the second edge 6052 can be orthogonal or non-orthogonal. In one embodiment, the angle between the fourth edge 6054 and the second edge 6052 can be in the range of 45 degrees to 135 degrees.

[0186] In one embodiment, the protruding portion of the floating diffusion region 608 may extend laterally toward the geometric center of the at least one second conductive hinged photodiode layer 602. The geometric center GC of the at least one second conductive hinged photodiode layer 602 is a point having a specific Cartesian coordinate, which is the average of the Cartesian coordinates of all points within the at least one second conductive hinged photodiode layer 602. In one embodiment, the geometric center GC of the at least one second conductive hinged photodiode layer 602 may be located outside the at least one second conductive hinged photodiode layer 602 (i.e., outside the volume of the at least one second conductive hinged photodiode layer 602). The geometric center GC of the at least one second conductive hinged photodiode layer 602 may be located within or below the transfer gate stack structure (614T, 605) or the floating diffusion region 608. Specifically, the geometric center GC of the at least one second conductive hinged photodiode layer 602 may be located below the transfer gate stack structure (614T, 605), or the geometric center GC of the at least one second conductive hinged photodiode layer 602 may be located within or below the floating diffusion region 608.

[0187] Figures 3A to 3F An illustration shows an example where the geometric center GC of the at least one second conductive hinged photodiode layer 602 is located within or below the floating diffusion region 608. However, the geometric center GC of the at least one second conductive hinged photodiode layer 602 can be placed below the transfer gate stack structure (614T, 605) by modifying the shape of the transfer gate stack structure (614T, 605), thereby modifying the shape of the floating diffusion region 608 and the at least one second conductive hinged photodiode layer 602.

[0188] In one embodiment, the at least one second conductive hinged photodiode layer 602 comprises a single continuous second conductive hinged photodiode layer 602 or is composed of a single continuous second conductive hinged photodiode layer 602, wherein the single continuous second conductive hinged photodiode layer 602 comprises each portion of the at least one second conductive hinged photodiode layer 602, such as... Figure 3B , Figure 3D , Figure 3F As shown. In another embodiment, the at least one second conductive hinged photodiode layer 602 comprises a plurality of second conductive hinged photodiode layers 602, which are not in direct contact with each other. The plurality of second conductive hinged photodiode layers 602 are laterally separated by semiconductor material portions (such as the transfer transistor body region 611) below the transfer gate stack structure. The plurality of second conductive hinged photodiode layers 602 are doped with a first conductivity.

[0189] Generally, sensing circuitry (640, 650, 660) for each sub-pixel can be provided within the region of a unit cell UC. In one embodiment, the various transistors of the sensing circuitry (640, 650, 660) can be arranged side-by-side within the region of a strip located near the edge of the unit cell UC, and the strip extends along the entire length of one side of the unit cell UC or extends along at least 30% of the length of one side of the unit cell UC, such as... Figure 3A , Figure 3B , Figure 3E , Figure 3F As shown. In other embodiments, various transistors of the sensing circuit (640, 650, 660) may be arranged around the floating diffusion region 608 of the transfer transistor 630 in a region near the corner of the unit cell UC, such as Figure 3C , Figure 3D As shown.

[0190] The second exemplary structure includes at least one instance of a sub-pixel. The second exemplary structure may include an image sensor comprising a pixel array located on a semiconductor substrate 500. The second exemplary structure may include a plurality of sub-pixels located within corresponding pixels in the pixel array. In one embodiment, each pixel located within the pixel array includes a corresponding instance of a sub-pixel.

[0191] Figure 4A This is a plan view of the front sensing element within the region of a sub-pixel in the first configuration of the third exemplary structure according to the embodiments of this disclosure. Figure 4B This is a plan view of the front sensing element within the region of a sub-pixel in the second configuration of the third exemplary structure according to the embodiments of this disclosure. Figure 4CThis is a plan view of the front sensing element within the region of a sub-pixel in a third configuration of a third exemplary structure according to an embodiment of the present disclosure. Figure 4D This is a plan view of the front sensing element within the region of a sub-pixel in the fourth configuration of the third exemplary structure according to the embodiments of this disclosure. Figure 4E This is a plan view of the front sensing element within the region of a sub-pixel in the fifth configuration of the third exemplary structure according to the embodiments of this disclosure. Figure 4F This is a plan view of the front sensing element within the region of a sub-pixel in the sixth configuration of the third exemplary structure according to the embodiments of this disclosure.

[0192] Reference Figure 4A This illustrates a first configuration of the third exemplary structure. The shapes of the second conductive hinged photodiode layer 602, the transfer gate stack structure (614T, 605), and the floating diffusion regions 608 can be varied by providing a plurality of floating diffusion regions 608 around the second conductive hinged photodiode layer 602 to derive the first configuration of the third exemplary structure from the first exemplary structure or from the second exemplary structure. The plurality of floating diffusion regions 608 can be laterally spaced or electrically connected to each other through a metal interconnect structure 680. The metal interconnect structure 680 may include at least one metal line structure 684 and at least two metal conductive via structures.

[0193] The second conductive hinged photodiode layer 602 forms a PN junction with the substrate semiconductor substrate 601. The second conductive hinged photodiode layer 602 may be a single continuous structure located at the center of the sub-pixel, and may have a periphery extending to a shallow trench isolation structure 620 located at the periphery of the sub-pixel. The geometric center of the second conductive hinged photodiode layer 602 may be located within the second conductive hinged photodiode layer 602.

[0194] Multiple floating diffusion regions 608 are laterally spaced from the second conductive hinged photodiode layer 602. The multiple floating diffusion regions 608 are not in contact with each other. The multiple floating diffusion regions 608 are laterally spaced from each other through the second conductive hinged photodiode layer 602 and through multiple transfer gate stack structures (614T, 605). In one embodiment, the multiple floating diffusion regions 608 can be electrically connected (i.e., electrically short-circuited) to each other through a set of metal interconnect structures 680, which may include at least one metal line structure 684 and at least two metal conductive via structures.

[0195] Each transfer gate stack structure (614T, 605) includes a corresponding transfer gate dielectric 614T and a corresponding transfer gate electrode 605. Each transfer gate stack structure (614T, 605) may be located between the second conductive hinged photodiode layer 602 and a corresponding one of the plurality of floating diffusion regions 608.

[0196] In one embodiment, multiple discrete transfer gate stack structures (614T, 605) may be provided, which are not in direct contact with each other. In one embodiment, multiple discrete transfer gate electrodes 605 may be electrically connected (i.e., electrically short-circuited) to each other through a set of metal interconnect structures 680, which may include at least one metal line structure 684 and at least two metal conductive via structures.

[0197] Although the transfer gate dielectric 614T is not explicitly shown in the accompanying drawings, it should be understood that each transfer gate dielectric 614T has the same horizontal cross-sectional shape as the transfer gate electrode 605 shown in each configuration (located above the transfer gate dielectric 614T). In the plan view (i.e., in the top view), each transfer gate stack structure (614T, 605) may be located between each of the floating diffusion region 608 and the second conductivity-type hinged photodiode layer 602.

[0198] In one embodiment, the gate length of the transfer gate stack structure (614T, 605), that is, the width of the transfer gate stack structure (614T, 605) along the horizontal direction connecting the second conductive hinged photodiode layer 602 and the corresponding floating diffusion region 608, can be uniform in the entire direction.

[0199] In the illustrated example, the floating diffusion region 608 may be located in a corner region of the semiconductor material portion, which has a polygonal horizontal cross-sectional shape. This polygonal horizontal cross-sectional shape includes the floating diffusion region 608, the second conductive hinged photodiode layer 602, and the transfer transistor body region 611 below the transfer gate stack structure (614T, 605). The boundary of the semiconductor material portion may be defined by a continuous surrounding portion of the shallow trench isolation structure 620 that laterally surrounds the semiconductor material portion.

[0200] For example, the semiconductor material portion described above has a rectangular horizontal cross-section, and the semiconductor material portion has two, three, or four floating diffusion regions 608 at two, three, or four corners of the rectangular horizontal cross-section. In one embodiment, each floating diffusion region 608 may have a corresponding triangular horizontal cross-sectional shape, which may be a right-angled triangle.

[0201] Each transfer gate stack structure (614T, 605) may have a corresponding horizontal cross-sectional shape of a strip, the strip having a uniform width, the strip extending laterally at a non-zero angle relative to a first horizontal direction hd1 and at another non-zero angle relative to a second horizontal direction hd2. For example, the lateral extension direction of each transfer gate stack structure (614T, 605) has a range of 15 degrees to 75 degrees relative to the first horizontal direction hd1, such as 30 degrees to 60 degrees (e.g., 45 degrees).

[0202] In one embodiment, the total number of floating diffusion regions 608 may be two.

[0203] Reference Figure 4B This can be achieved by forming three floating diffusion regions 608 and three transfer gate stacked structures (614T, 605) from Figure 4A The first configuration of the third exemplary structure leads to the second configuration of the third exemplary structure. The three floating diffusion regions 608 described above can be interconnected with each other through a first subset of the metal interconnect structure 680. The three transfer gate dielectrics 614T of the three transfer gate stack structures (614T, 605) described above can be interconnected with each other through a second subset of the metal interconnect structure 680.

[0204] Reference Figure 4C This can be achieved by forming four floating diffusion regions 608 and four transfer gate stacked structures (614T, 605) from Figure 4B The second configuration of the third exemplary structure leads to the third configuration of the third exemplary structure. The four floating diffusion regions 608 described above can be interconnected with each other through a first subset of the metal interconnect structure 680. The four transfer gate dielectrics 614T of the four transfer gate stack structures (614T, 605) described above can be interconnected with each other through a second subset of the metal interconnect structure 680.

[0205] Reference Figure 4D The fourth configuration of the third exemplary structure can be derived from the first configuration of the third exemplary structure by connecting two transfer gate stack structures (614T, 605) to a single transfer gate stack structure (614T, 605) interconnected with an interconnect portion of a portion of the shallow trench isolation structure 620.

[0206] Reference Figure 4E The fifth configuration of the third exemplary structure can be derived from the second configuration of the third exemplary structure by connecting three transfer gate stack structures (614T, 605) to a single transfer gate stack structure (614T, 605) interconnected with an interconnect portion of a portion of the shallow trench isolation structure 620.

[0207] Reference Figure 4FA sixth configuration of the third exemplary structure can be derived from the third configuration of the third exemplary structure by connecting four transfer gate stack structures (614T, 605) to a single transfer gate stack structure (614T, 605) interconnected with an interconnect portion of a portion of the shallow trench isolation structure 620.

[0208] Refer to together Figures 4A to 4F In various configurations of the third exemplary structure, a plurality of floating diffusion regions 608 are provided around the second conductive hinged photodiode layer 602. These plurality of floating diffusion regions 608 may be laterally spaced from each other and may be electrically connected to each other through a metal interconnect structure 680. The metal interconnect structure 680 may include at least one metal wire structure 684 and at least two metal conductive via structures.

[0209] In one embodiment, the at least one transfer gate stack structure (614T, 605) described above may comprise a plurality of discrete transfer gate stack structures (614T, 605) that are not in direct contact with each other, such as... Figures 4A to 4C As shown. In one embodiment, the plurality of discrete transfer gate electrodes 605 of the plurality of discrete transfer gate stack structures (614T, 605) described above can be electrically connected to each other (i.e., electrically short-circuited) through a collection of metal interconnect structures 680, wherein the metal interconnect structure 680 may include at least one metal line structure 684 and at least two metal conductive via structures.

[0210] In one embodiment, the at least one transfer gate stack structure (614T, 605) described above may be constituted by a single transfer gate stack structure (614T, 605), which extends continuously over the entire top surface of the transfer transistor body region 611 as a single continuous structure, such as... Figures 4D to 4F As shown. In one embodiment, the aforementioned single transfer gate stack structure (614T, 605) may extend laterally over one or more portions of the shallow trench isolation structure 620 that protrudes inward toward the geometric center of the second conductive hinged photodiode layer 602, as shown. Figures 4D to 4F As shown. The above-described single transfer gate stack structure (614T, 605) can have the following characteristics: Figure 4D and Figure 4E The shape of the meandering line structure at the two different ends shown may have a shape like... Figure 4F The toroid shown is of a general shape.

[0211] In one embodiment, at least one transfer gate stack structure (614T, 605) described above can be provided as a single transfer gate stack structure (614T, 605) having multiple segments adjacent to each other to provide a single continuous structure. A first subset of the multiple segments of the single transfer gate stack structure (614T, 605) may cover a corresponding region on the top surface of the transfer transistor body region 611 located between the corresponding floating diffusion region 608 and the second conductive hinged photodiode layer 602. A second subset of the multiple segments of the single transfer gate stack structure (614T, 605) may cover a corresponding region of the shallow trench isolation structure 620. The multiple segments in the first subset and the multiple segments in the second subset may be interleaved to provide a single continuous structure of the transfer gate stack structure (614T, 605).

[0212] In embodiments where the shallow trench isolation structure 620 includes multiple portions protruding toward the geometric center of the second conductive hinged photodiode layer 602, each floating diffusion region 608 may have a triangular, quadrilateral, or pentagonal horizontal cross-sectional shape, depending on the position of the edge of the lateral protrusion of the shallow trench isolation structure 620, which is the intersection point where the outer straight edge of the transfer gate stack structure (614T, 605) intersects with the edge of the floating diffusion region 608.

[0213] In one embodiment, the shallow trench isolation structure 620 may laterally surround the floating diffusion region 608, and the shallow trench isolation structure 620 may contact each of the floating diffusion regions 608. In one embodiment, two floating diffusion regions 608 may be provided for each sub-pixel that do not contact each other, such as... Figure 4A As shown. In other embodiments, the floating diffusion region 608 may comprise three or more discrete floating diffusion regions 608 that do not contact each other, such as... Figure 4B and Figure 4C As shown.

[0214] Generally, sensing circuitry (640, 650, 660) for each sub-pixel can be provided within the region of a unit cell UC. In one embodiment, the transistors of the sensing circuitry (640, 650, 660) can be arranged side-by-side in a strip region located near the edge of the unit cell UC, the strip region extending along the entire length of one side of the unit cell UC or at least 30% of the length of that side of the unit cell UC, such as... Figures 4A to 4C As shown. In other embodiments, the individual transistors of the sensing circuits (640, 650, 660) may be disposed around the floating diffusion region 608 of the transfer transistor 630 in a region of a block located near a corner of the unit cell UC.

[0215] The third exemplary structure includes at least one instance of a sub-pixel. The third exemplary structure may include an image sensor comprising a pixel array located on a semiconductor substrate 500. The third exemplary structure may include a plurality of sub-pixels located within corresponding pixels in the pixel array. In one embodiment, each pixel located within the pixel array includes a corresponding instance of a sub-pixel.

[0216] Figure 5 This is a vertical cross-sectional view of an exemplary structure after the formation of a metal interconnect structure within an interconnect-level dielectric layer, according to an embodiment of this disclosure, and after attachment to a carrier substrate. (Refer to...) Figure 5 Additional interconnect dielectric layers 670 and additional metal interconnect structures 680 may be formed on the front side of the semiconductor substrate 500. The front side of the semiconductor substrate 500, the interconnect dielectric layer 670, and the components of the structures formed therein may be bonded to a carrier substrate 690. The carrier substrate 690 is temporarily attached to the components of the semiconductor substrate 500 and the interconnect dielectric layer 670 to provide for subsequent thinning of the semiconductor substrate 500 and subsequent processing of the components of the interconnect dielectric layer 670 and the thinned semiconductor substrate 500. The carrier substrate 690 may comprise semiconductor materials, insulating materials, and metallization materials, and the carrier substrate 690 may have a thickness ranging from 300 micrometers to 1 millimeter, although less or more thickness may also be used.

[0217] Any suitable bonding method can be used to bond the carrier substrate 690 to the front side of the interconnect-level dielectric layer 670. Exemplary bonding methods that can be used to bond the carrier substrate 690 to the interconnect-level dielectric layer 670 include, but are not limited to: oxide-to-oxide bonding, oxide-to-semiconductor bonding, fusion bonding, hybrid bonding, anodic bonding, direct bonding, other suitable bonding processes, and / or combinations thereof. Optionally, a bonding buffer layer 689 comprising an intermediate bonding material (e.g., silicon dioxide, silicon nitride, or a semiconductor material) can be used to provide bonding between the interconnect-level dielectric layer 670 and the carrier substrate 690.

[0218] Figure 6 This is a vertical cross-sectional view of an exemplary structure after thinning of a semiconductor substrate according to an embodiment of the present disclosure. (Refer to...) Figure 6For example, the back side of the semiconductor substrate 500 can be thinned using grinding, polishing, isotropic etching, and / or anisotropic etching processes. A carrier substrate 690 can provide mechanical support to the semiconductor substrate 500 during the thinning process. In one embodiment, the semiconductor substrate 500 can be thinned to a thickness ranging from 1 micrometer to 12 micrometers, for example, 1.5 micrometers to 8 micrometers. The semiconductor substrate 500 thinned after the thinning process is referred to herein as thinned semiconductor substrate 510 or semiconductor substrate 510. The thickness of the thinned semiconductor substrate 510 can be determined by the maximum depth of the deep trenches subsequently formed on the back side of the thinned semiconductor substrate 510. In one embodiment, the thickness of the thinned semiconductor substrate 510 can be selected such that the deep trenches 719 subsequently formed on the back side of the thinned semiconductor substrate 510 reach the proximal surfaces of the shallow trench isolation structure 620. The back surface 709 of the thinned semiconductor substrate 510 can be polished to provide a planar horizontal surface parallel to the front surface 609 of the thinned semiconductor substrate 510. The illustrated structure can then be flipped over for further processing.

[0219] Figure 7 This is a vertical cross-sectional view of an exemplary structure after a deep trench has been formed on the back side of a semiconductor substrate according to an embodiment of the present disclosure. (Refer to...) Figure 7 A selective connection pad dielectric layer 711 and a hard mask layer 712 may be formed on the back surface 709 of the semiconductor substrate 510. If the selective connection pad dielectric layer 711 is present, it may comprise a silicon dioxide layer and may have a thickness ranging from 5 nanometers to 50 nanometers. The hard mask layer 712 comprises an etch mask material that can be selectively removed from the connection pad dielectric layer 711 and / or selectively removed from the semiconductor substrate 510. For example, the hard mask layer 712 may comprise silicon nitride, borosilicate glass, or a metallization material. The hard mask layer 712 may have a thickness ranging from 50 nanometers to 800 nanometers, although less or more thickness may also be used.

[0220] A photoresist layer (not shown) can be applied to the hard mask layer 712, and the photoresist layer can be patterned by photolithography to form openings, which typically replicate the pattern of the shallow trench isolation structure 620 located beneath it. A first etching process can be performed to transfer the pattern in the photoresist layer through the hard mask layer 712 and the selective connection pad dielectric layer 711. A second anisotropic etching process can be performed to etch the unmasked portion of the semiconductor substrate 510, which transfers the pattern of the openings in the photoresist layer and the hard mask layer 712 through the semiconductor substrate 510. The depth of the deep trench 719 can be in the range of 1 micrometer to 10 micrometers, for example, 1.5 micrometers to 8 micrometers. During the second anisotropic etching process, the photoresist layer can be completely consumed. The deep trench 719 can be formed through the semiconductor substrate 510.

[0221] The deep trenches 719 define regions of sub-pixels 800. Each sub-pixel 800 may be located within a corresponding sub-pixel region, which is located within a region of a pixel, i.e., within the pixel region. For example, a region of a pixel may include a region of a first sub-pixel 801, a region of a second sub-pixel 802, and a region of a third sub-pixel 803. In the illustrated example, the first sub-pixel 801 may be formed in a region including a photodetector for detecting green light, the second sub-pixel 802 may be formed in a region including a photodetector for detecting red light, and the third sub-pixel 803 may be formed in a region including a photodetector for detecting blue light. Each sub-pixel 800 may include a volume containing a patterned columnar portion of a semiconductor substrate 510, which is laterally surrounded by a connected set of deep trenches 719. The pixel region of a pixel includes all the sub-pixel regions of the set of sub-pixels 800 contained in that pixel.

[0222] Figure 8 This is a vertical cross-sectional view of an exemplary structure after removing the hard mask layer and the connecting pad dielectric layer according to an embodiment of this disclosure. (Refer to...) Figure 8 The hard mask layer 712 can be selectively removed from the semiconductor substrate 510, the connection pad dielectric layer 711, and the shallow trench isolation structure 620. In the illustrated example, if the hard mask layer 712 comprises silicon nitride, a wet etching process using thermal phosphoric acid can be performed to remove the hard mask layer 712. Subsequently, the connection pad dielectric layer 711 can be selectively removed from the semiconductor substrate 510.

[0223] Figure 9 This is a vertical cross-sectional view of an exemplary structure after forming a dielectric metal oxide liner and a dielectric isolation layer according to an embodiment of this disclosure. (Refer to...) Figure 9The dielectric metal oxide liner 721 can be conformally deposited on the physically exposed surface of the semiconductor substrate 510. The dielectric metal oxide liner 721 can be formed on the sidewalls of the deep trench 719, on the back surface 709 of the semiconductor substrate 510, or on the surface of the shallow trench isolation structure 620, in which the shallow trench isolation structure 620 physically exposes the deep trench 719. The dielectric metal oxide liner 721 comprises a dielectric metal material having a dielectric constant greater than 7.9 (i.e., a high-k dielectric material). Exemplary dielectric metal oxide materials that can be used for the dielectric metal oxide liner 721 include hafnium dioxide, aluminum oxide, zirconium dioxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum pentoxide, strontium oxide, titanium dioxide, lanthanum oxide, barium oxide, or combinations thereof. The dielectric metal oxide pad 721 can be deposited using chemical vapor deposition or atomic layer deposition (ALD) processes. The thickness of the dielectric metal oxide pad 721 can range from 2 nanometers to 6 nanometers, although thinner or thicker thicknesses are also possible.

[0224] A dielectric metal oxide (DMO) pad 721 can be formed to provide negative charge trapping. For example, the DMO pad 721 can be deposited using a non-stoichiometric, oxygen-rich composition, or, for example, the DMO pad 721 can be surface-treated with plasma to achieve a non-stoichiometric, oxygen-rich surface compression. In such embodiments, the DMO pad 721 may comprise an oxygen-rich DMO material having negatively charged interstitial oxygen atoms and / or dangling or broken metal oxide bonds, thereby providing accumulation of negative charge within the DMO pad 721. In the illustrated example, the areal density of negative charge accumulated within the DMO pad 721 is 5.0 × 10⁻⁶. 9 electrons per square centimeter 2 ) to 1.0×10 14 Electrons per square centimeter, for example 1.0 × 10⁻⁶ 10 Electrons / cm² to 2.0 × 10⁻⁶ 13Electrons per square centimeter. The dielectric metal oxide material used for the dielectric metal oxide pad 721 can accumulate more negative charge than other dielectric materials (e.g., silicon nitride or silicon dioxide). The negative charge in the dielectric metal oxide pad 721 increases hole accumulation within the interface portion between the first conductive well 607 and the substrate semiconductor layer 601 of the semiconductor substrate 510. Depletion regions can be formed within multiple portions of the first conductive well 607 and the substrate semiconductor layer 601 of the semiconductor substrate 510, these portions being close to the dielectric metal oxide pad 721. Depletion regions reduce dark current and / or white pixels of the image sensor.

[0225] A dielectric isolation layer 722 can be formed by conformally depositing dielectric material in the remaining volume of the deep trench 719. The dielectric isolation layer 722 comprises a dielectric material, such as undoped silicate glass, doped silicate glass (e.g., borosilicate glass), or a combination thereof. The combination of dielectric metal oxide pad 721 and dielectric isolation layer 722 can fill the deep trench 719 (with or without seams and / or closed cavities).

[0226] Figure 10 This is a vertical cross-sectional view of an exemplary structure after forming a deep trench isolation structure according to an embodiment of the present disclosure. (Refer to...) Figure 10 The horizontal portions of the dielectric isolation layer 722 and the dielectric metal oxide pad 721 can be removed from the back surface 709 of the semiconductor substrate 510 via a planarization process. Recess etch or chemical mechanical planarization processes can be used to remove the horizontal portions of the dielectric isolation layer 722 and the dielectric metal oxide pad 721. In one embodiment, the dielectric metal oxide pad 721 can be used as an etch stop layer during the recess etch process for removing the horizontal portions of the dielectric isolation layer 722, or the dielectric metal oxide pad 721 can be used as a stop layer during the chemical mechanical planarization process for removing the horizontal portions of the dielectric isolation layer 722. The horizontal portions of the dielectric metal oxide pad 721 covering the back surface of the semiconductor substrate 510 can be subsequently removed by performing an isotropic etching process (e.g., a wet etching process), which selectively etches the material of the dielectric metal oxide pad 721 onto the semiconductor material of the semiconductor substrate 510. The remaining vertical extensions of the dielectric metal oxide liner 721 and the dielectric isolation layer 722 fill the deep trench 719 and are referred to herein as the deep trench isolation structure 720.

[0227] Figure 11This is a vertical cross-sectional view of an exemplary structure after forming an antireflective coating (ARC) layer, an optical refractive layer, a dielectric grating material layer, a metallized refractive material layer, and a patterned photoresist layer according to an embodiment of this disclosure. (Refer to...) Figure 11 Selective anti-reflective coating 732, optical buffer layer 734, dielectric grid material layer 742L and metallized refractive material layer 744L can then be deposited on the back surface 709 of semiconductor substrate 510.

[0228] The selective antireflective coating 732 comprises an antireflective coating material that reduces reflection between the semiconductor material of the semiconductor substrate 510 and the overlying material layer (i.e., optical buffer layer 734) of the semiconductor substrate 510. If the selective antireflective coating 732 is present, it may have a refractive index between that of the semiconductor material of the semiconductor substrate 510 and that of the optical buffer layer 734. The selective antireflective coating 732 may comprise a single material layer or a stack of multiple layers with gradually changing refractive indices. The selective antireflective coating 732 comprises an optically transparent material and may comprise semiconductor materials, insulating materials, conductive materials, and / or polymer materials. The antireflective coating 732 may have a thickness ranging from 50 nanometers to 300 nanometers, although thinner or thicker thicknesses are also possible.

[0229] The optical buffer layer 734 may comprise a semiconductor material (e.g., silicon, germanium, silicon-germanium alloy, or group III-V compound semiconductor material), a dielectric material (e.g., silicon dioxide, silicon oxynitride), or a dielectric metal oxide (e.g., aluminum oxide). The optical buffer layer 734 may comprise a material that facilitates the formation of trenches with high aspect ratios during subsequent anisotropic etching processes. The optical buffer layer 734 may be formed as an unpatterned (blanket) material layer having two horizontal planes parallel to the back surface 709 of the semiconductor substrate 510. The distal surface of the optical buffer layer 734 is one of the two horizontal planes of the optical buffer layer 734; in other words, the distal surface of the optical buffer layer 734 is the one of the two horizontal planes of the optical buffer layer 734 further away from the semiconductor substrate 510, i.e., the top surface of the optical buffer layer 734.

[0230] The dielectric grid material layer 742L may contain a dielectric material, such as silicon dioxide, a porous dielectric material, polyimide, or other dielectric materials. The thickness of the dielectric grid material layer 742L may range from 50 nanometers to 500 nanometers, although thinner or thicker thicknesses are also possible. The metallized refractive material layer 744L may contain a metallization material that provides high reflectivity. For example, the metallized refractive material layer 744L may contain silver, aluminum, copper, gold, or other highly reflective metallization materials. The thickness of the metallized refractive material layer 744L may range from 50 nanometers to 500 nanometers, although thinner or thicker thicknesses are also possible.

[0231] A photoresist layer 747 can be applied to the metallized refractive material layer 744L, and the photoresist layer 747 can be patterned by photolithography to form multiple openings in the region of the second conductive hinged photodiode layer 602, that is, multiple openings are formed in the region of the photodetector, which includes a corresponding PN junction between the second conductive hinged photodiode layer 602 and the first conductive well 607. The regions of multiple transistors of the sensing circuit (e.g., reset transistor 640, source follower transistor 650, select transistor 660) may or may not be covered by the photoresist layer 747.

[0232] Figure 12A This is a vertical cross-sectional view of an exemplary structure after forming a composite grid structure according to an embodiment of the present disclosure. Figure 12B yes Figure 12A The diagram shows the plan view of the illustrative structure. The hinged vertical plane A-A' corresponds to... Figure 12A The vertical cross-sectional view of the plane. (Refer to...) Figure 12A and Figure 12B A portion of the dielectric grid material layer 742L and the metallized refractive material layer 744L, which are not masked by the patterned portion of the photoresist layer 747, can be etched to form multiple openings therethrough. The remaining portion of the dielectric grid material layer 742L forms a dielectric grid structure 742, and the remaining portion of the metallized refractive material layer 744L forms a metallized grid structure. The stacking of the dielectric grid structure 742 and the metallized grid structure constitutes a grid structure 740, which is also referred to as a composite grid structure.

[0233] The grid structure 740 may cover the periphery of the second conductive hinged photodiode layer 602, and the grid structure 740 may define a light collection area for each photodetector located within a corresponding sub-pixel 800. Pixel 900 may include a set of sub-pixels for detecting light of different wavelengths. Each pixel 900 may be located within a corresponding pixel region, which includes a set of sub-pixels 800. For example, pixel 900 may include at least one instance of a first sub-pixel 801, at least one instance of a second sub-pixel 802, and at least one instance of a third sub-pixel 803. In the illustrated example, the pixel may include a first sub-pixel 801 (e.g., a green sub-pixel) located in a first sub-pixel region, two second sub-pixels 802 (e.g., two red sub-pixels) located in two second sub-pixel regions, and a third sub-pixel 803 (e.g., a blue sub-pixel) located in a third sub-pixel region. Generally, pixel 900 may include various combinations of at least two types of sub-pixels 800 for detecting light of different wavelength ranges. Alternatively, the image sensor may be a monochrome image sensor comprising a single type of sub-pixel 800. In such an embodiment, each pixel 900 may comprise only a single sub-pixel 800.

[0234] Generally, the grid structure 740 may include at least one metallized grid structure 744 having reflective sidewalls. The grid structure 740 may include a composite grid structure comprising a vertical stack of a metallized grid structure 744 with reflective sidewalls and a dielectric grid structure 742. The grid structure 740 may be formed on the distal surface of the optical buffer layer 734. The grid structure 740 includes an opening covering a corresponding one of a photodetector including the transfer transistor 630. A portion of the distal surface of the optical buffer layer 734 in contact with the bottom surface of the grid structure is a planar distal surface portion of the distal surface of the optical buffer layer 734. During an anisotropic etching process patterning the grid structure, portions of the distal surface of the optical buffer layer 734 not in contact with the grid structure 740 may be recessed vertically and collaterally relative to a horizontal plane including the bottom surface of the grid structure.

[0235] The grid structure 740 can divide each sub-pixel 800 into a detector region and a sensing circuit region. For example, the first sub-pixel 801 may include a first detector region 801D covering the second conductive hinged photodiode layer 602 of the first sub-pixel 801, and the first sub-pixel 801 may also include a first sensing circuit region 801S covering the sensing circuit (640, 650, 660) of the first sub-pixel 801. The second sub-pixel 802 may include a second detector region 802D covering the second conductive hinged photodiode layer 602 of the second sub-pixel 802, and the second sub-pixel 802 may also include a second sensing circuit region 802S covering the sensing circuit (640, 650, 660) of the second sub-pixel 802. The third sub-pixel 803 may include a third detector region 803D covering the second conductive hinged photodiode layer 602 of the third sub-pixel 803, and the third sub-pixel 803 may also include a third sensing circuit region 803S covering the sensing circuits (640, 650, 660) of the third sub-pixel 803. Generally, all sub-pixels in a group within pixel 900 can be arranged in any pattern, and the aforementioned arbitrary pattern facilitates the periodic repetition of pixels 900 within the array 100 of pixels 900.

[0236] Figure 13 This is a vertical cross-sectional view of an exemplary structure after the formation of the optically transparent layer, color filter, and lens according to an embodiment of the present disclosure. (Refer to...) Figure 13 An optically transparent layer 770 with a flat top surface can be formed on the grid structure 740. The optically transparent layer 770 can be formed by depositing a self-planarizing dielectric material such as flowable oxide (FOX). Alternatively, the transparent dielectric material can be deposited and planarized, for example by chemical mechanical planarization, to provide the optically transparent layer 770.

[0237] An optically transparent layer 770 extends vertically through an opening in the grating structure 740, and the optically transparent layer 770 provides a second refractive index different from the first refractive index. The optically transparent layer 770 is formed on the optical buffer layer 734.

[0238] Various color filter materials can be applied to the optically transparent layer 770, and these materials can be patterned to form various color filters 780. Each color filter 780 may include a first-type color filter 781 formed in the region of a first sub-pixel 801, a second-type color filter 782 formed in the region of a second sub-pixel 802, and a third-type color filter 783 formed in the region of a third sub-pixel 803. The composition of each filter material can be selected such that light within the target wavelength range passes through the filter material while light outside the target wavelength range is absorbed by the filter material.

[0239] An optical lens 790 can be formed on the color filter 780 by applying an optically transparent material to the color filter 780 and by patterning the optically transparent material into a material portion with a convex surface, wherein the convex surface is located at the center of the corresponding one of the lower openings within the grid structure 740.

[0240] Figure 14 This is a vertical cross-sectional view of an exemplary structure after the carrier substrate has been removed according to an embodiment of the present disclosure. (Refer to...) Figure 14 The carrier substrate 690 and the bonding buffer layer 689 (if present) can be separated from the interconnect dielectric layer 670. Before or after separating the carrier substrate 690 from the semiconductor substrate 510, the semiconductor substrate 510 and the device structure thereon can be singulated into discrete image sensors.

[0241] Generally, an array 1000 of pixels can be formed on a semiconductor substrate 510. Each pixel in the pixel array 1000 includes at least one sub-pixel, and each sub-pixel includes a corresponding photodetector (including a transfer transistor 630) and corresponding sensing circuits (640, 650, 660) located on the front surface of the semiconductor substrate 510. An optically transparent layer 770 can cover the array of mask structures.

[0242] Figure 15 This is a circuit diagram of a sub-pixel according to an embodiment of this disclosure. (Refer to...) Figure 15 This diagram illustrates a general circuit schematic of the combination of a photodetector (including a transfer transistor 630) and sensing circuitry (640, 650, 660) within each sub-pixel 800 of an embodiment of this disclosure. The transfer transistor 630 includes a PN junction between a combination of a second conductivity type hinged photodiode layer 602 and a buried second conductivity type hinged photodiode layer 606, and a substrate semiconductor layer 601 doped with a first conductivity type. A first conductivity type hinged photodiode layer 603 may be provided on the top side of the second conductivity type hinged photodiode layer 602 to provide charge pinning, thereby reducing dark current and white pixel effect. A set of substrate semiconductor layers 601, buried second conductivity type hinged photodiode layers 606, second conductivity type hinged photodiode layers 602, and first conductivity type hinged photodiode layers 603 serves as a pinned photodiode (PPD). The second conductive hinged photodiode layer 602 serves as the source region of the transfer transistor 630, and the floating diffusion region 608, labeled "FD" in the figures, serves as the drain region of the transfer transistor 630. The transfer gate electrode 605, labeled "TG" in the figures, controls the transfer of charge accumulated in the second conductive hinged photodiode layer 602 to the floating diffusion region 608. The transfer transistor 630 serves as a photodetector.

[0243] The sensing circuit (640, 650, 660) may include a reset transistor 640 (denoted as "RST" in the figures), which is used to immediately discharge the charge in the floating diffusion region 608 before sensing, such that the charge accumulated in the floating diffusion region 608 during sensing is linearly proportional to the charge accumulated in the second conductive hinged photodiode layer 602. The gate electrode of the source follower 650 (denoted as "SF" in the figures) is electrically connected to the floating diffusion region 608 through a set of metal interconnect structures. Therefore, the voltage at the gate electrode of the source follower 650 is proportional to the charge in the floating diffusion region 608. During a read operation, select transistor 660 (labeled "SEL" in the figure) is turned on to output the voltage at the common node of the source follower and select transistor 660 (modulated by the voltage at the gate electrode of source follower 650) to the column output bus (labeled "COLBUS" in the figure).

[0244] Figure 16 This is a flowchart illustrating exemplary processing steps for forming an image sensor according to embodiments of the present disclosure. (Refer to...) Figure 16 The present disclosure provides a general method for forming an image sensor according to embodiments thereof. (See also...) Figure 16 In step 1610, a front-side sensor element 600, such as a second conductive hinged photodiode layer 602, a floating diffusion region 608, and other active regions 612 of field-effect transistors (640, 650, 660), can be formed on the front side of the semiconductor substrate 500. As described above, the patterns of the floating diffusion region 608 and the second conductive hinged photodiode layer 602 can be selected. (Refer to...) Figure 16 In step 1620, a transfer gate stack structure (614T, 605) and other gate stack structures (614, 615) are formed on the front side of the semiconductor substrate 500. As described above, the pattern of the transfer gate stack structure (614T, 605) can be selected. (Refer to...) Figure 16 In step 1630, a deep trench isolation structure 720 can be formed from the back side of the semiconductor substrate 510, which can be provided by thinning the semiconductor substrate 500. (Refer to...) Figure 16 In step 1640, an anti-reflective coating 732, a grid structure 740, a color filter 780, and a lens 790 may be formed on the back side of the semiconductor substrate 510.

[0245] Referring to all the accompanying drawings and various embodiments of the present disclosure, a semiconductor structure is provided, including at least one example of a sub-pixel 800 located on a semiconductor substrate 510, the semiconductor substrate 510 including a doped substrate semiconductor layer 601 having a first conductivity type. Each of the at least one example of the sub-pixel 800 includes: a second conductivity type hinged photodiode layer 602, at least one floating diffusion region 608, and at least one transfer gate stack structure (614T, 605). The second conductivity type hinged photodiode layer forms a PN junction with the substrate semiconductor layer 601. The at least one floating diffusion region 608 is laterally spaced from the periphery of the second conductivity type hinged photodiode layer 602. The at least one floating diffusion region 608 at least partially laterally surrounds the second conductivity type hinged photodiode layer 602. The at least one transfer gate stack structure (614T, 605) includes a corresponding transfer gate dielectric 614T and a corresponding transfer gate electrode 605. At least one transfer gate stack structure (614T, 605) is located between the second conductive hinged photodiode layer 602 and at least one floating diffusion region 608. The at least one transfer gate stack structure (614T, 605) at least partially laterally surrounds the second conductive hinged photodiode layer 602 around its geometric center GC with a total azimuth extension angle α. The total azimuth extension angle α ranges from 240 degrees to 360 degrees. In some embodiments, the at least one transfer gate stack structure includes a single transfer gate stack structure completely surrounding a region of the second conductive hinged photodiode layer, and the total azimuth extension angle is 360 degrees. In some embodiments, the at least one transfer gate stack structure includes a plurality of transfer gate electrodes interconnected with each other via a plurality of metal interconnect structures, and the total azimuth extension angle ranges from 240 degrees to 355 degrees. In some embodiments, the at least one floating diffusion region includes a single floating diffusion region partially or completely surrounding a region of the second conductive hinged photodiode layer as a single continuous structure. In some embodiments, at least one floating diffusion region comprises a plurality of floating diffusion regions, which are laterally spaced from each other by a shallow trench isolation structure. In some embodiments, the shallow trench isolation structure contacts and laterally surrounds at least one floating diffusion region; and is laterally spaced from a hinged photodiode layer of a second conductivity type by a portion of a doped semiconductor material having a first conductivity type. In some embodiments, the semiconductor structure comprises an image sensor, the image sensor comprising a pixel array located on a semiconductor substrate; at least one instance of a subpixel comprises a plurality of subpixels located within a corresponding pixel in the pixel array; and each pixel in the pixel array comprises a corresponding instance of a subpixel.

[0246] According to one embodiment of the present disclosure, a semiconductor structure is provided, including at least one instance of a sub-pixel 800 located on a semiconductor substrate 510, the semiconductor substrate 510 including a substrate semiconductor layer 601 doped with a first conductivity type. Each of the at least one instance of the sub-pixel 800 includes: at least one second conductivity type hinged photodiode layer 602, a floating diffusion region 608, and a transfer gate stack structure (614T, 605). The at least one second conductivity type hinged photodiode layer 602 forms at least one PN junction with the substrate semiconductor layer 601. The floating diffusion region 608 is laterally spaced from the at least one second conductivity type hinged photodiode layer 602. The transfer gate stack structure (614T, 605) includes a transfer gate dielectric 614T and a transfer gate electrode 605, the transfer gate stack structure (614T, 605) being located between the floating diffusion region 608 and each of the at least one second conductivity type hinged photodiode layer 602. The transfer gate stack structure (614T, 605) has a first edge 6051 and a second edge 6052. The first edge 6051 covers a first segment of at least a periphery of at least one second conductive hinged photodiode layer 602, and the second edge 6052 covers a second segment of at least a periphery of at least one second conductive hinged photodiode layer 602. A floating diffusion region 608 includes a portion located between the first edge 6051 and the second edge 6052. In some embodiments, the first edge and the second edge of the transfer gate stack structure are parallel to each other. In some embodiments, the transfer gate stack structure includes a third edge and a fourth edge, the third edge being adjacent to the first edge and the fourth edge being adjacent to the second edge; the angle between the third edge and the first edge ranges from 45 degrees to 135 degrees; and the angle between the fourth edge and the second edge ranges from 45 degrees to 135 degrees. In some embodiments, the geometric center of at least one second conductive hinged photodiode layer is located outside the at least one second conductive hinged photodiode layer, and the geometric center of at least one second conductive hinged photodiode layer is located within or below the transfer gate stack structure or the floating diffusion region. In some embodiments, at least one second conductivity type hinged photodiode layer comprises a single continuous second conductivity type hinged photodiode layer, the single continuous second conductivity type hinged photodiode layer comprising each portion of the at least one second conductivity type hinged photodiode layer. In some embodiments, at least one second conductivity type hinged photodiode layer comprises a plurality of second conductivity type hinged photodiode layers that are not in direct contact with each other, but are laterally spaced by semiconductor material portions located below the transfer gate stack structure, the semiconductor material portions having a first conductivity type doping.In some embodiments, the semiconductor structure includes an image sensor, the image sensor including a pixel array located on a semiconductor substrate; at least one instance of a subpixel includes a plurality of subpixels located within a corresponding pixel in the pixel array; and each pixel in the pixel array includes a corresponding instance of a subpixel.

[0247] According to one embodiment of the present disclosure, a semiconductor structure is provided, including at least one instance of a sub-pixel 800 located on a semiconductor substrate 510, the semiconductor substrate 510 including a substrate semiconductor layer 601 doped with a first conductivity type. Each of the at least one instance of the sub-pixel 800 includes: a second conductivity type hinged photodiode layer 602, a plurality of floating diffusion regions 608, and at least one transfer gate stack structure (614T, 605). The second conductivity type hinged photodiode layer 602 forms a PN junction with the substrate semiconductor layer 601. The floating diffusion regions 608 are laterally spaced from the second conductivity type hinged photodiode layer 602. The at least one transfer gate stack structure (614T, 605) includes a corresponding transfer gate dielectric 614T and a corresponding transfer gate electrode 605. The at least one transfer gate stack structure (614T, 605) is located between the second conductivity type hinged photodiode layer 602 and a corresponding one of the plurality of floating diffusion regions 608. In some embodiments, the plurality of floating diffusion regions are not in contact with each other, wherein the plurality of floating diffusion regions are electrically connected to each other through a set of metal interconnect structures. In some embodiments, the semiconductor structure further includes a shallow trench isolation structure that laterally surrounds and contacts each of the plurality of floating diffusion regions. In some embodiments, at least one transfer gate stack structure includes a plurality of transfer gate stack structures, wherein the respective transfer gate electrodes of the plurality of transfer gate stack structures are electrically connected to each other through a set of metal interconnect structures. In some embodiments, the plurality of floating diffusion regions include three or more discontinuous floating diffusion regions that are not in contact with each other. In some embodiments, the semiconductor structure includes an image sensor, the image sensor including a pixel array located on a semiconductor substrate; at least one instance of a subpixel includes a plurality of subpixels located within a corresponding pixel in the pixel array; and each pixel in the pixel array includes a corresponding instance of a subpixel.

[0248] The various embodiments disclosed herein reduce the maximum charge propagation distance of charge accumulated in the second conductive hinged photodiode layer 602 during charge transfer to the floating diffusion region 608 by providing various novel layout features to at least one second pixel's second conductive hinged photodiode layer 602, at least one floating diffusion region 608, and at least one transfer gate stack structure (614T, 605). The faster charge transfer from the second conductive hinged photodiode layer 602 to the floating diffusion region 608 provides faster operation of the photodetector, and thus faster operation of the CMOS image sensor.

[0249] The foregoing has outlined the features of several embodiments, thus enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should recognize that this disclosure can be readily used as a basis to design or modify other processes and structures, thereby achieving the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The sub-pixel includes at least one sub-pixel located on a semiconductor substrate, the semiconductor substrate including a doped substrate semiconductor layer having a first conductivity type, wherein each of the at least one sub-pixel includes: A second conductive hinged photodiode layer, wherein the second conductive hinged photodiode layer and the substrate semiconductor layer form a PN junction; At least one floating diffusion region, the at least one floating diffusion region being laterally spaced from a periphery of the second conductive hinged photodiode layer, the at least one floating diffusion region at least partially laterally surrounding the second conductive hinged photodiode layer; and At least one transfer gate stack structure includes a corresponding transfer gate dielectric and a corresponding transfer gate electrode. The at least one transfer gate stack structure is located between the second conductive hinged photodiode layer and the at least one floating diffusion region. The at least one transfer gate stack structure at least partially laterally surrounds the second conductive hinged photodiode layer with a total azimuth extension angle around a geometric center of the second conductive hinged photodiode layer, wherein the total azimuth extension angle ranges from 240 degrees to 360 degrees.

2. The semiconductor structure according to claim 1, characterized in that, The at least one transfer gate stack structure includes a region of the second conductive hinged photodiode layer completely surrounded by a single transfer gate stack structure, and the total azimuth extension angle is 360 degrees.

3. The semiconductor structure according to claim 1, characterized in that, The at least one transfer gate stack structure includes a plurality of transfer gate electrodes, which are interconnected with each other through a plurality of metal interconnect structures, and the total azimuth extension angle ranges from 240 degrees to 355 degrees.

4. The semiconductor structure according to claim 1, characterized in that, The at least one floating diffusion region includes a region that partially or completely surrounds the second conductive hinged photodiode layer as a single continuous structure.

5. The semiconductor structure according to claim 1, characterized in that, The at least one floating diffusion region comprises multiple floating diffusion regions, which are laterally separated from each other by a shallow trench isolation structure.

6. The semiconductor structure according to claim 1, characterized in that, One of the shallow trench isolation structures contacts and laterally surrounds the at least one floating diffusion region; and the shallow trench isolation structure is laterally separated from the second conductivity hinged photodiode layer by a portion of a doped semiconductor material having the first conductivity type.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes an image sensor, which includes a pixel array located on the semiconductor substrate; the at least one sub-pixel includes a plurality of sub-pixels, the plurality of sub-pixels being located within a corresponding pixel in the pixel array; and each pixel in the pixel array includes a corresponding sub-pixel among the at least one sub-pixel.

8. A semiconductor structure, characterized in that, The sub-pixel includes at least one sub-pixel located on a semiconductor substrate, the semiconductor substrate including a doped substrate semiconductor layer having a first conductivity type, wherein each of the at least one sub-pixel includes: At least one second conductive hinged photodiode layer, wherein the at least one second conductive hinged photodiode layer forms at least one PN junction with the substrate semiconductor layer; A floating diffusion region, which is laterally spaced from the at least one second conductive hinged photodiode layer; and A transfer gate stack structure includes a transfer gate dielectric and a transfer gate electrode. The transfer gate stack structure is located between the floating diffusion region and each of the at least one second conductive hinged photodiode layer. The transfer gate stack structure has a first edge and a second edge. The first edge covers a first segment of at least one periphery of the at least one second conductive hinged photodiode layer, and the second edge covers a second segment of the at least one periphery of the at least one second conductive hinged photodiode layer. The floating diffusion region includes a portion located between the first edge and the second edge.

9. The semiconductor structure according to claim 8, characterized in that, The first edge and the second edge of the transfer gate stack structure are parallel to each other.

10. The semiconductor structure according to claim 8, characterized in that, in The transfer gate stack structure includes a third edge and a fourth edge, the third edge being adjacent to the first edge and the fourth edge being adjacent to the second edge; The angle between the third edge and the first edge ranges from 45 degrees to 135 degrees. and The angle between the fourth edge and the second edge ranges from 45 degrees to 135 degrees.

11. The semiconductor structure according to claim 8, characterized in that, The geometric center of the at least one second conductive hinged photodiode layer is located outside the at least one second conductive hinged photodiode layer, and the geometric center of the at least one second conductive hinged photodiode layer is located inside or below the transfer gate stack structure or the floating diffusion region.

12. The semiconductor structure according to claim 8, characterized in that, The at least one second conductive hinged photodiode layer comprises a single continuous second conductive hinged photodiode layer, wherein the single continuous second conductive hinged photodiode layer comprises each portion of the at least one second conductive hinged photodiode layer.

13. The semiconductor structure according to claim 8, characterized in that, The at least one second conductivity type hinged photodiode layer includes a plurality of second conductivity type hinged photodiode layers, which are not in direct contact with each other. The plurality of second conductivity type hinged photodiode layers are laterally separated by a semiconductor material portion located below the transfer gate stack structure. The semiconductor material portion has a doping of the first conductivity type.

14. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure includes an image sensor, which includes a pixel array located on the semiconductor substrate; the at least one sub-pixel includes a plurality of sub-pixels, the plurality of sub-pixels being located within a corresponding pixel in the pixel array; and each pixel in the pixel array includes a corresponding sub-pixel among the sub-pixels.

15. A semiconductor structure, characterized in that, The sub-pixel includes at least one sub-pixel located on a semiconductor substrate, the semiconductor substrate including a doped substrate semiconductor layer having a first conductivity type, wherein each of the at least one sub-pixel includes: A second conductive hinged photodiode layer, wherein the second conductive hinged photodiode layer and the substrate semiconductor layer form a PN junction; Multiple floating diffusion regions, said multiple floating diffusion regions being laterally spaced from the second conductive hinged photodiode layer; and At least one transfer gate stack structure includes a corresponding transfer gate dielectric and a corresponding transfer gate electrode. The at least one transfer gate stack structure is located between the second conductive hinged photodiode layer and a corresponding one of the plurality of floating diffusion regions. The at least one transfer gate stack structure has a first edge and a second edge. The first edge covers a first segment of at least one periphery of the second conductive hinged photodiode layer, and the second edge covers a second segment of the at least one periphery of the second conductive hinged photodiode layer.

16. The semiconductor structure according to claim 15, characterized in that, The plurality of floating diffusion regions are not in contact with each other, but are electrically connected to each other by a set of metal interconnect structures.

17. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure further includes a shallow trench isolation structure that laterally surrounds and contacts the second conductive hinged photodiode layer and each of the plurality of floating diffusion regions.

18. The semiconductor structure according to claim 15, characterized in that, The at least one transfer gate stack structure includes multiple transfer gate stack structures, and the multiple transfer gate electrodes of the multiple transfer gate stack structures are electrically connected to each other through a set of metal interconnect structures.

19. The semiconductor structure according to claim 15, characterized in that, The plurality of floating diffusion regions comprise three or more discontinuous floating diffusion regions that do not contact each other.

20. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure includes an image sensor, which includes a pixel array located on the semiconductor substrate; the at least one sub-pixel includes a plurality of sub-pixels, the plurality of sub-pixels being located within a corresponding pixel in the pixel array; and each pixel in the pixel array includes a corresponding sub-pixel among the at least one sub-pixel.

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