Circuit for time-to-digital converter, lidar and method of measuring time

Abstract

This invention provides a circuit for a time-to-digital converter (TDC), comprising: a counter configured to start counting a first clock pulse signal upon receiving a first control signal, and output a count value according to a second control signal; a synchronizer configured to output the second control signal to the counter according to a third control signal and the first clock pulse signal, and to output a time residual signal between the second control signal and the third control signal; a signal converter configured to receive the time residual signal and convert it into a voltage signal, wherein the amplitude of the voltage signal characterizes the length of the time residual signal; and an analog-to-digital converter configured to sample the voltage signal to output a sampled value. Based on the count value and the sampled value, the time difference between the first control signal and the third control signal is determined, thereby achieving high-precision and wide-range time measurement.

Description

Technical Field

[0001] This disclosure relates to the field of photoelectric detection, and more particularly to a circuit for a time-to-digital converter, a lidar including the circuit, and a method for measuring time via the circuit. Background Technology

[0002] As the most important module in a lidar system, the performance of the time-to-digital converter (TDC) directly affects the imaging quality. Therefore, designing a high-precision, wide-range TDC is one of the challenges faced by lidar systems.

[0003] In a lidar imaging system, the system reconstructs the distance information of the measured object based on the quantization result of the telemetry control (TDC). Generally, to detect greater distances, the system requires a wide measurement range for the TDC. Conversely, to present a clear image, the TDC needs high accuracy. However, there is a trade-off between high accuracy and wide measurement range; a high-precision TDC often struggles to achieve a wide measurement range, and vice versa. For high-precision TDCs, especially when the accuracy exceeds the gate delay of the manufacturing process, the design difficulty increases dramatically. This is because to achieve a resolution of tx, the TDC requires two digital signals with a spacing of tx within its internal circuitry, and the internal circuitry must be able to correctly identify these two signals. If the minimum gate delay of the manufacturing process is still greater than tx, then the TDC obviously cannot achieve a minimum resolution of tx in quantization accuracy. This is the difficulty encountered by high-precision TDCs.

[0004] The TDC (Transmission Control Unit) structure varies depending on the application scenario. Mainstream high-precision, wide-range TDCs employ a combination of coarse and fine counting. Coarse counting achieves the wide range, while fine counting achieves high precision. A typical TDC structure involves an oscillator composed of a NAND gate and an inverter starting to oscillate when the rising edge of the EN signal arrives. A counter records the number of rising edges at the oscillator output. When the rising edge of the Stop signal arrives, the counter stops counting. The Stop signal reads the oscillator's phase information at this moment, the oscillator loop breaks, and oscillation stops. The decoder encodes the oscillator's phase information, thus obtaining the fine count value. The counter's count value is the coarse count value, used to determine the TDC's range, while the oscillator's phase information is the fine count value, used to determine the TDC's precision.

[0005] In actual TDC design, in order to ensure the accuracy of TDC, that is, when external conditions such as temperature and power supply voltage change, the weight represented by each bit of the TDC quantization result remains unchanged, the oscillation period of the oscillator needs to be synchronized with the phase-locked loop (PLL). This requires the control voltage of the PLL to control the frequency of the oscillator.

[0006] Because the oscillator used in TDC is open-loop and not in the PLL loop, the low-frequency noise of the oscillator is not filtered out. The low-frequency noise of the oscillator is generally quite large. Specifically, the error of a single oscillation cycle of the oscillator will accumulate. When the measured time interval is long, the accumulated error will become very large. For example, if the clock period of TDC coarse counting is 1ns and the oscillator generates an error of 10ps per cycle, then if the measured time interval is 1μs, the accumulated error will reach 10ns. When the measured time is longer, the error of TDC will be even greater. Obviously, this is unacceptable for high-precision TDC. This is the disadvantage of TDC based on open-loop oscillators.

[0007] In practical TDC design, since the delay of an inverter is only affected by the power supply voltage and temperature, it is not conducive to PLL regulation of the oscillator frequency. Therefore, practical oscillators are mostly composed of delay units rather than inverters. Compared to inverters, delay units have a larger delay, which is even more detrimental to the design of high-precision TDCs. For example, in a 180nm process, the minimum delay of a delay unit can reach 100ps in the worst case, which limits the accuracy of TDCs. Overcoming the limitation of the minimum gate delay has become a bottleneck restricting the accuracy of TDCs.

[0008] Because open-loop oscillator-based time-division converters (TDCs) are susceptible to low-frequency noise, when the measured time interval is long, the accumulated error of the oscillator eventually leads to a large error in the TDC. A PLL-locked clock TDC can mitigate the impact of low-frequency noise. Its schematic diagram is shown below. Figure 9 As shown, the clock of the TDC counter uses a PLL-locked clock instead of an open-loop oscillator clock. This is because when the PLL is locked, the internal feedback loop of the PLL filters out the low-frequency noise of the voltage-controlled oscillator (VCO) in the loop, so the coarse count value of the counter will not accumulate errors. This solves the problem of TDC based on an open-loop oscillator.

[0009] TDC based on a PLL-locked clock is also a mainstream architecture. The PLL multiplies the reference clock provided by the external crystal oscillator to the target frequency and uses it as the reference clock for the counter. When the rising edge of the Start signal arrives, the counter starts counting. When the rising edge of the Stop signal arrives, the Stop signal, after passing through the synchronization circuit, generates a read signal and a level signal for fine counting. The read signal is used to read the counter's count value at this time to achieve coarse counting, while the fine counting level signal is used to trigger the VCO to achieve fine counting. Since the counting clock is a PLL-locked clock, there is no accumulated error in the counter's count value, thus ensuring the accuracy of the TDC.

[0010] Although there are many VCO structures, relatively few are suitable for TDC (Transient Voltage Controlled Oscillator). A typical VCO structure suitable for TDC is as follows: Figure 10 As shown, it is composed of cascaded even-numbered differential delay units. Since the number of delay units in the VCO is even, the output feedback to the input needs to be reversed; otherwise, the VCO loop will be locked due to positive feedback. When the EN signal from the synchronization circuit is valid, the VCO starts to oscillate. Depending on the oscillation time, the final phase state of the VCO will also be different. Encoding the phase state of the VCO yields the fine count value of the TDC. Since the VCO requires a long time to start oscillating in the free state, this time is detrimental to fine counting. Therefore, to avoid the VCO potentially being in an indeterminate state when it starts oscillating, all nodes of the VCO should be fixed to a certain state during the reset phase. In fact, the VCO is composed of delay units. Although there are many types of delay units, they are all limited by gate delay, which restricts the accuracy of the TDC. Therefore, how to overcome the limitation of gate delay has become a difficult problem in the development of high-precision TDC.

[0011] The content in the background section is merely technology known to the public and does not necessarily represent existing technology in this field. Summary of the Invention

[0012] In view of at least one deficiency of the prior art, the present invention designs a circuit that can be used in a time-to-digital converter to achieve a method for measuring time with high accuracy and wide range.

[0013] This invention provides a circuit that can be used in a time-to-digital converter, comprising:

[0014] The counter is configured to start counting the first clock pulse signal after receiving the first control signal, and output the count value according to the second control signal;

[0015] A synchronizer is configured to output a second control signal to the counter based on a third control signal and a first clock pulse signal, and to output a time residual signal between the second control signal and the third control signal;

[0016] A signal converter configured to receive the time residual signal and convert the time residual signal into a voltage signal, wherein the amplitude of the voltage signal characterizes the length of the time residual signal; and

[0017] An analog-to-digital converter is configured to sample the voltage signal to output sampled values.

[0018] According to one aspect of the invention, the system further includes a controller that receives a count value output by the counter and a sample value output by the analog-to-digital converter to determine time difference information between the first control signal and the third control signal.

[0019] According to one aspect of the invention, the counter is a synchronous counter configured to start counting the first clock pulse signal when the first control signal undergoes a transition, and to read the count of the first clock pulse signal when the second control signal undergoes a transition.

[0020] According to one aspect of the invention, it further includes a phase-locked loop (PLL) that receives the reference clock pulse signal and outputs a frequency-multiplied first clock pulse signal, wherein the counter and the synchronizer receive the first clock pulse signal from the PLL.

[0021] According to one aspect of the invention, the first control signal is configured to maintain a certain phase difference with the first clock pulse signal.

[0022] According to one aspect of the invention, the synchronizer is configured to output the second control signal aligned with the rising edge of the first clock pulse signal.

[0023] According to one aspect of the invention, the signal converter is an integrator, the signal converter is coupled to the synchronizer and configured to receive the time residual signal and the third control signal, and to start converting the time residual signal when the third control signal undergoes a jump to obtain the voltage signal corresponding to the time residual signal.

[0024] According to one aspect of the invention, the analog-to-digital converter is a Flash analog-to-digital converter, which is coupled to the signal converter and configured to receive the voltage signal.

[0025] According to one aspect of the invention, the counter and the phase-locked loop constitute a coarse counting unit, and the synchronizer, the signal converter, and the analog-to-digital converter constitute a fine counting unit, wherein the circuit may include multiple fine counting units, and for each fine counting unit:

[0026] Each receives its corresponding third control signal and a first control signal corresponding to the coarse counting unit, respectively, to read the sampled value corresponding to the third control signal, and...

[0027] The coarse counting unit is then output a corresponding second control signal so that it reads the count value corresponding to the third control signal.

[0028] According to one aspect of the invention, the controller determines the time difference information between the first control signal and each of the third control signals based on each third control signal corresponding to each fine counting unit.

[0029] According to one aspect of the invention, the synchronizer includes a first D flip-flop and a second D flip-flop, an inverter, and a NAND gate connected in series, wherein the first D flip-flop receives the third control signal, the output of the first D flip-flop is coupled to the input of the second D flip-flop, the second D flip-flop outputs the second control signal, the inverter receives the third control signal, the output of the inverter is coupled to one input of the NAND gate, and the other input of the NAND gate receives the second control signal and outputs the time residual signal.

[0030] The present invention also provides a lidar, comprising:

[0031] A transmitting unit configured to emit a detection laser beam for detecting a target object;

[0032] A receiving unit configured to receive the echo reflected from the probe laser beam on the target object and convert it into an electrical signal;

[0033] The circuit described above is coupled to the transmitting unit and the receiving unit to determine the flight time of the echo; wherein, when the transmitting unit emits a probe laser beam, it sends a first control signal to the circuit, and when the receiving unit receives the echo signal, it sends a third control signal to the circuit.

[0034] The present invention also provides a method for measuring time using a time-to-digital converter, comprising:

[0035] S101: When the counter receives the first control signal, it starts counting the first clock pulse signal;

[0036] S102: Receive the third control signal and the first clock pulse signal through the synchronizer, generate the second control signal and output it to the counter, and output the time residual signal of the second control signal relative to the third control signal;

[0037] S103: When the counter receives the second control signal, it outputs a count value;

[0038] S104: The time residual signal is converted into a voltage signal by a signal converter, wherein the amplitude of the voltage signal can characterize the length of the time residual signal;

[0039] S105: Sample the voltage signal using an analog-to-digital converter and output the sampled value.

[0040] According to one aspect of the invention, the method further includes step S106: obtaining the time difference between the first control signal and the third control signal by a controller based on the count value and the sampled value.

[0041] According to one aspect of the present invention, wherein step S101 includes: starting to count the first clock pulse signal by means of the counter when the first control signal undergoes a transition; and step S103 includes: reading and counting the first clock pulse signal by means of the counter when the second control signal undergoes a transition.

[0042] According to one aspect of the invention, it further includes:

[0043] The first control signal is configured to maintain a certain phase difference with the first clock pulse signal by receiving a reference clock pulse signal through a phase-locked loop and generating a frequency-multiplied first clock pulse signal.

[0044] The first clock pulse signal is output to the counter and synchronizer, wherein the second control signal is configured to align with the rising edge of the first clock pulse signal.

[0045] According to one aspect of the invention, step S104 includes:

[0046] The time residual signal and the third control signal are received by an integrator, and the conversion of the time residual signal begins when the third control signal undergoes a jump.

[0047] According to one aspect of the invention, steps S101-103 are performed simultaneously with steps S104-105.

[0048] According to one aspect of the invention, the method is implemented via the circuit described in the circuit.

[0049] Because the Time-to-Digital Converter (TDC) of this invention employs a combination of coarse and fine counting, and the fine counting of the TDC converts the time signal into a voltage signal by integrating the fine counting time, and finally quantizes it through an analog-to-digital converter (ADC), processing the digital signal in an analog manner, the accuracy of the TDC is not limited by gate delay, and the TDC can achieve very high accuracy. It achieves both a wide dynamic range and high accuracy, solving the traditional TDC's trade-off between range and accuracy.

[0050] The features and advantages described in this specification are not exhaustive; in particular, many additional features and advantages will be apparent to those skilled in the art when viewed in conjunction with the accompanying drawings and description. Furthermore, it should be noted that the terminology used in this specification has been chosen primarily for readability and instructional purposes and may not have been selected to describe or limit the inventive step of the invention. Attached Figure Description

[0051] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure. In the drawings:

[0052] Figure 1 A circuit diagram for a time-to-digital converter according to an embodiment of the present invention is shown;

[0053] Figure 2 A timing diagram of a circuit that can be used in a time-to-digital converter according to an embodiment of the present invention is shown;

[0054] Figure 3 The schematic diagram of a D flip-flop in the prior art and its timing diagram in metastable state are shown.

[0055] Figure 4a A schematic diagram of a synchronizer according to an embodiment of the present invention is shown;

[0056] Figure 4b A timing diagram of a synchronizer according to an embodiment of the present invention is shown;

[0057] Figure 5a A schematic diagram of an integrator according to an embodiment of the present invention is shown;

[0058] Figure 5b A timing diagram of an integrator according to an embodiment of the present invention is shown;

[0059] Figure 6 A schematic diagram of an analog-to-digital converter according to an embodiment of the present invention is shown;

[0060] Figure 7 A lidar according to an embodiment of the present invention is shown;

[0061] Figure 8 A flowchart of a method for measuring time using a time-to-digital converter according to an embodiment of the present invention is shown;

[0062] Figure 9 A schematic diagram of an existing time-to-digital converter is shown; and

[0063] Figure 10 A schematic diagram of an existing voltage-controlled oscillator is shown. Detailed Implementation

[0064] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0065] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0066] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0067] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0068] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0069] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0070] One embodiment of the present invention designs a circuit for a time-to-digital converter (TDC) that enables high-precision and wide-range time measurement. The wide range is achieved through a counter, while the high precision is achieved by integrating the time residual to convert the time-domain quantity to a voltage-domain quantity, followed by sampling and quantization via an analog-to-digital converter (ADC). This analog-to-digital signal processing eliminates or mitigates the limitation of gate delay on the accuracy of the TDC. A detailed description is provided below with reference to the accompanying drawings.

[0071] Figure 1 A circuit 10, which can be used in a time-to-digital converter (TDC) according to a first embodiment of the present invention, is shown. Figure 1 As shown, circuit 10 includes: counter 11, synchronizer 13, signal converter 14, and analog-to-digital converter (ADC) 15. Counter 11 receives a first clock pulse signal Fout and a first control signal Start, and receives a second control signal READ from synchronizer 13.

[0072] Specifically, counter 11 is configured to start counting pulses of the first clock pulse signal Fout after receiving the first control signal Start, and to output the count value when receiving the second control signal READ. That is, counter 11 can obtain the pulse count value of the first clock pulse signal Fout between the first control signal Start and the second control signal READ.

[0073] The synchronizer 13 is configured to receive a first clock pulse signal Fout and generate a second control signal READ and a time residual signal ΔT between the second control signal READ and the third control signal Stop, based on a third control signal Stop. The synchronizer 13 outputs the second control signal READ to the counter 11 so that the counter 11 reads the obtained pulse count value; and the synchronizer 13 outputs the time residual signal ΔT between the second control signal and the third control signal to the signal converter 14.

[0074] According to a preferred embodiment of the present invention, synchronizer 13 is configured to output the second control signal READ aligned with the rising edge of the first clock pulse signal Fout.

[0075] More preferably, the time residual signal ΔT is used to indicate the time difference between the rising edge of the third control signal Stop and the rising edge of the second control signal READ.

[0076] Next, the signal converter 14 receives the time residual signal ΔT from the synchronizer 13. The signal converter 14 is configured to receive the time residual signal ΔT and convert it into a voltage signal. Specifically, the signal converter 14 can obtain a voltage signal corresponding to the duration of the time residual signal ΔT by performing continuous integration over its duration. The amplitude of the output voltage signal is proportional to the duration of the time residual signal ΔT.

[0077] According to a preferred embodiment of the present invention, referring to FIG. 5, the signal converter 14 is an integrator that receives the time residual signal ΔT and converts it into a voltage signal. The voltage signal output by the integrator has a linear relationship with the time residual ΔT, which will be described in detail below.

[0078] The analog-to-digital converter 15 receives the voltage signal and samples it to output sampled values ​​(e.g., a binary digital sequence).

[0079] Specifically, the analog-to-digital converter 15 samples, quantizes, and encodes the amplitude of the voltage signal output by the signal converter 14 to obtain digital encoding information corresponding to the time residual ΔT, thus allowing for intuitive reading of the fine-count time information. Preferably, when the time range and the corresponding maximum voltage range are determined, since the time residual is linearly related to the voltage amplitude, the correspondence between the ADC's digital encoding information and the time information can be directly established, and the time information can then be read based on the ADC's digital encoding.

[0080] In one embodiment, an 8-bit ADC is used, and the time range of the fine counting unit is [0, 1ns]. Then, the digital encoding range of the ADC [0, 255] can be directly correlated with the time value of [0, 1ns]. When the digital encoding information read by the ADC is 127, the corresponding time information is 500ps.

[0081] According to a preferred embodiment of the present invention, such as Figure 1 As shown, circuit 10 also includes a phase-locked loop (PLL) 12. The PLL 12 receives a reference clock pulse signal Fin, multiplies the frequency of Fin, and outputs a higher-frequency first clock pulse signal Fout. Figure 1 As shown, both the counter 11 and the synchronizer 13 receive the first clock pulse signal Fout from the phase-locked loop 12.

[0082] The reference clock pulse signal Fin comes from an external crystal oscillator (or alternatively, circuit 10 may also include a crystal oscillator). Because crystal oscillators have good frequency stability, a highly stable reference clock pulse signal Fin can be obtained through a properly designed phase-locked loop (PLL), ensuring the performance of the circuit used in the time-to-digital converter. Furthermore, since the system clock typically requires a higher frequency signal, the reference clock pulse signal Fin from the external crystal oscillator needs to be multiplied to a higher frequency via PLL 12, outputting the first clock pulse signal Fout to counter 11 to meet the system clock requirements. Simultaneously, this multiplied signal, as a coarse-counting time reference, provides finer time granularity (relative to the reference clock pulse), resulting in better timing performance.

[0083] According to a preferred embodiment of the present invention, such as Figure 1 As shown, circuit 10 also includes controller 16, which receives the count value output by counter 11 and the sample value output by analog-to-digital converter 15 to determine the time difference information between the first control signal Start and the third control signal Stop.

[0084] Specifically, the controller determines the coarse counting time from the start to the end of the count (i.e. when the count value is read from the second control signal Read) of the counter 11 based on the count value of the pulse count output by the counter 11 and the duration of a single pulse cycle of the first clock pulse signal Fout. Furthermore, based on the sampled value read from the analog-to-digital converter 15, the controller determines the time residual ΔT between the jump of the third control signal Stop and the end of the count of the counter 11. The controller then subtracts the time residual ΔT from the coarse counting time to obtain the time difference information between the first control signal Start and the third control signal Stop.

[0085] It should be noted that those skilled in the art will readily understand that the phase-locked loop 12 is not essential. As long as a stable clock pulse signal can be obtained as a counting reference for the coarse and fine counting units, the solution of the present invention can still be implemented. That is, the present invention is not limited to generating and providing the first clock pulse signal Fout through the phase-locked loop 12; the first clock pulse signal Fout can also be provided by other electronic circuits, or the first clock pulse signal Fout can be directly input.

[0086] refer to Figure 1 and Figure 2 The working principles of the coarse counting unit and the fine counting unit, as well as the working principle of circuit 10, are described respectively. Figure 1 In the circuit of the illustrated embodiment, counter 11 constitutes a coarse counting unit, which performs coarse counting based on the first clock pulse signal Fout, the first control signal Start, and the second control signal READ output by phase-locked loop 12; synchronizer 13, signal converter 14, and analog-to-digital converter 15 constitute a fine counting unit, which performs fine counting based on the first clock pulse signal Fout and the third control signal Stop output by phase-locked loop 12. Figure 2 It shows Figure 1 The timing diagram of the circuit shown.

[0087] like Figure 2 The phase-locked loop 12 multiplies the reference clock pulse signal Fin from the external crystal oscillator to a higher frequency first clock pulse signal Fout, and outputs the first clock pulse signal Fout to the counter 11 and the synchronizer 13. When the rising edge of the first control signal Start arrives, the counter 11 starts counting the first clock pulse signal Fout. That is, the first control signal Start can be considered as the enable signal of the counter 11, or the first control signal Start can be used as the reset signal of the counter 11. Each time the rising edge of the first control signal Start arrives, the counter 11 is reset to zero and starts counting again.

[0088] Preferably, as those skilled in the art will understand, in some embodiments, the counter 11 can also be triggered by the falling edge of the first control signal Start, and these are all within the protection scope of the present invention.

[0089] Since the first control signal Start and the first clock pulse signal Fout are the enable signal and clock signal of counter 11, respectively, preferably, the first control signal Start and the first clock pulse signal Fout maintain a fixed phase difference to avoid metastability problems. (That is, as shown in the image) Figure 2 As shown, this results in a certain time difference between the rising edge of the first control signal Start and the rising edge of the first clock pulse signal Fout.

[0090] Metastability refers to a state where, when a signal arrives near the rising edge of a clock signal, the signal setup and hold time is insufficient, and the internal nodes of the flip-flop fail to establish a definite state, resulting in an indeterminate output. (Reference) Figure 3 , Figure 3 The text uses a D flip-flop as an example to illustrate metastability. The S and C signals are input to the D flip-flop as the enable and clock signals, respectively, and the output is a Y signal. When the rising edge of the S signal arrives near the rising edge of the C signal, due to insufficient setup time, the output Y signal may be either 0 or 1. The solid and dashed lines in the diagram represent these two possible states. In both cases, the output will become 1 after the next rising edge of the C signal. However, the indeterminate state of the output within this cycle is sufficient to cause discrepancies in subsequent digital logic circuits, leading to errors in the digital circuitry.

[0091] According to the present invention, by maintaining a fixed phase difference between the first control signal Start and the first clock pulse signal Fout, the metastability problem can be effectively eliminated or mitigated.

[0092] Preferably, the fixed phase difference between the first control signal Start and the first clock pulse signal Fout can be determined by pre-setting the phase difference between the first control signal Start and the reference clock pulse signal Fin.

[0093] Specifically, by pre-setting the phase difference between the first control signal Start and the reference clock pulse signal Fin, it can be ensured that the phase relationship between the reference clock pulse signal Fin and the first clock pulse signal Fout after passing through the phase-locked loop 12 is also determined. Therefore, the phase difference between the first control signal Start and the first clock pulse signal Fout is also determined.

[0094] According to one embodiment of the present invention, the counter 11 is a synchronous counter configured to start counting the first clock pulse signal Fout when the first control signal Start undergoes a transition (e.g., rising edge), and to read the count value of the counter 11 when the second control signal READ undergoes a transition (e.g., rising edge).

[0095] According to a preferred embodiment, counter 11 is a synchronous counter. Synchronous counter 11 includes multiple D flip-flops, and the first clock pulse signal Fout can simultaneously act on each flip-flop. By using a synchronous counter, the step-by-step delay problem encountered by asynchronous flip-flops is overcome, improving the counter's operating efficiency and reducing the output phase difference between each flip-flop. Since the counting clock of counter 11 is the first clock pulse signal Fout after being frequency-multiplied and locked by phase-locked loop 12, when phase-locked loop 12 is locked, the internal feedback loop of phase-locked loop 12 filters out the low-frequency noise of the voltage-controlled oscillator (VCO) in the loop. Therefore, the coarse count value of counter 11 will not accumulate delay errors. This solves the problem existing in the prior art based on open-loop oscillator-based TDC, thereby achieving a wide range of TDC.

[0096] Next, combined Figure 1 , Figure 2 as well as Figure 4a , Figure 4b Specifically, in the circuit of this scheme, based on synchronizer 13 and counter 11, the second control signal READ is generated according to the third control signal Stop, thereby realizing coarse counting and obtaining the time residual signal ΔT.

[0097] The coarse counting unit operates as follows: Phase-locked loop 12 receives the reference clock pulse signal Fin and outputs a multiplied first clock pulse signal Fout; when the rising edge of the first control signal Start arrives, counter 11 starts counting the first clock pulse signal Fout; when the rising edge of the second control signal READ arrives, counter 11 reads the count from the first clock pulse signal Fout and outputs the count value to controller 16, obtaining a coarse count based on the count value. The timing relationship of each signal is as follows: Figure 2 As shown. In an embodiment of the present invention, the second control signal READ is obtained by processing the third control signal Stop by the synchronizer 13, so as to avoid metastability problems caused by the overlap of rising edges between the third control signal Stop and the first pulse signal Fout.

[0098] Specifically, the structure of the synchronizer 13 according to an embodiment of the present invention is as follows: Figure 4aAs shown, synchronizer 1 includes a first D flip-flop 131 and a second D flip-flop 132 connected in series, an inverter 133, and a NAND gate 134. The first D flip-flop 131 receives a third control signal Stop, the second D flip-flop 132 outputs a second control signal READ, the inverter 133 receives the third control signal Stop and outputs it to the NOR gate 134, and the other input of the NOR gate 134 receives the second control signal READ and outputs a time residual signal ΔT. The remaining input of each of the first D flip-flop 131 and the second D flip-flop 132 is connected to a first clock pulse signal Fout as a synchronization clock CLK.

[0099] refer to Figure 4b , Figure 4b Showing with Figure 4a The timing diagram corresponding to synchronizer 13 is shown below. The first D flip-flop 131 and the second D flip-flop 132 are respectively connected to Fout as the synchronization clock CLK. When the third control signal Stop changes at a certain moment, the first D flip-flop 131 subsequently changes, outputting a pulse as shown in Q1. The second D flip-flop 132 receives the timing pulse shown in Q1 and correspondingly outputs a second control signal READ aligned with CLK. The signal after the third control signal Stop passes through inverter 133, and together with the second control signal READ, serves as the input to NOR gate 134, which outputs the corresponding time residual signal ΔT.

[0100] exist Figure 1 In the embodiment shown in Figure 4, the third control signal Stop passes through synchronizer 13, which can avoid or mitigate the metastability problem caused by the asynchronous operation of the third control signal Stop and the CLK signal (the first clock pulse signal Fout). As shown in Figure 4, the third control signal Stop and the CLK signal maintain a certain phase difference, and the rising edges of the second control signal READ and the CLK signal are aligned. At the transition time of the third control signal Stop (e.g., ... Figure 4b (as shown by the dashed line) to the Count readout time point (e.g.) Figure 4b The time between (as shown by the dashed line) is the value of the time residual signal ΔT.

[0101] Subsequently, after obtaining the time residual signal ΔT, the circuit according to this scheme uses signal converter 14 and analog-to-digital converter 15 to obtain the sampled value corresponding to the time residual signal ΔT.

[0102] Preferably, the obtained signal residual information ΔT can be used as the residual input signal ΔT' of the signal converter 14 after being inverted.

[0103] As mentioned earlier, similar to the time residual signal ΔT, the input signal ΔT' actually indicates the delay of the transition time of the second control signal READ relative to the actual transition time of the third control signal Stop. Integrator 14 receives the residual input signal ΔT' and converts it into a voltage signal; the magnitude of the integrated voltage reflects the duration of the time residual. Figure 5 shows the structure of integrator 14 according to an embodiment of the present invention, which works by using current to charge and discharge capacitor C, thus converting the time-domain signal into a voltage-domain signal. In this embodiment, integrator 14 receives the residual input signal ΔT' and receives the third control signal Stop as an enable signal EN. When the enable signal EN is low and the residual input signal ΔT' is high, the integrator is in a reset phase, and the output voltage is reset to V. REF When the enable signal EN goes high and the residual input signal ΔT' goes low, the current I draws the charge stored in the capacitor C. Since the current used to draw the charge is relatively constant, the slope of the integrator output voltage is also constant. This means that the magnitude of the integrator voltage is proportional to the length of the residual input signal ΔT', thus realizing the conversion of a time-domain quantity to a voltage-domain quantity. When the residual input signal ΔT' goes high again, and when the time residual signal ΔT is low, the value of the integrator output voltage no longer changes. In the context of this invention, the time residual signal ΔT and the residual input signal ΔT' are not strictly distinguished.

[0104] The voltage signal output by the integrator and the residual input signal ΔT' can be expressed by the following formula:

[0105] V RAMP =K*ΔT';

[0106] Among them, V RAMP The rising slope K is fixed based on the inherent properties of the device. Therefore, the residual input signal ΔT', that is, the time residual ΔT', can be determined based on the final output voltage value.

[0107] like Figure 1 As shown, in this embodiment, the integrator 14 receives the third control signal Stop and the residual input signal ΔT, and starts to convert the time residual signal ΔT when the rising edge of the third control signal Stop arrives, so as to obtain the integral voltage corresponding to the length of the residual input signal ΔT.

[0108] The analog-to-digital converter 15 receives the voltage signal output from the integrator 14, samples and quantizes it to obtain the corresponding digital code, and outputs the sampled value to the controller to determine the fine count. The accuracy of the analog-to-digital converter determines the accuracy of the fine count; the higher the accuracy of the analog-to-digital converter, the higher the accuracy of the TDC. However, higher accuracy also means larger power consumption and larger area. Therefore, a trade-off must be considered when determining the accuracy of the analog-to-digital converter. For example, using an 8-bit analog-to-digital converter can achieve an accuracy on the order of 10 ps.

[0109] Preferably, the analog-to-digital converter 15 according to a preferred embodiment of the present invention is a Flash analog-to-digital converter. In the embodiments of the present invention, since the results of TDC time quantization are already divided into coarse counting and fine counting, the accuracy of the analog-to-digital converter used for fine counting does not need to be very high, but the speed of the analog-to-digital converter needs to be very fast, otherwise it will affect the speed of the next TDC. The Flash analog-to-digital converter is suitable for fine counting due to its high speed and low accuracy. Its schematic diagram is as follows. Figure 6 As shown, the Flash analog-to-digital converter generates the reference voltage required for quantization by dividing the voltage through a series of resistors (resistors R1, R2, R3, ..., Rn in the figure). The input voltage is compared with the reference voltage, and the signal Dout output by the decoder after comparison is the quantization result of the analog-to-digital converter.

[0110] Synchronizer 13, based on the third control signal Stop and the first clock pulse signal Fout, outputs the second control signal READ to counter 11 to read the current coarse count value. Simultaneously, it outputs the time residual signal ΔT between the second control signal READ and the third control signal Stop to integrator 14. Integrator 14 converts the time residual signal ΔT into a voltage signal based on the third control signal Stop. Analog-to-digital converter 15 samples and quantizes this voltage signal, then outputs the sampled value (e.g., a binary digital sequence) to the controller, thereby obtaining the fine count. The timing relationship of each signal is as follows: Figure 2 As shown.

[0111] In this embodiment, the time is divided into two parts: coarse counting and fine counting. The coarse counting is achieved by counter 11, while the fine counting is achieved by converting the time signal into a voltage signal and then quantizing it by analog-to-digital converter 15. The accuracy of TDC is determined by the accuracy of analog-to-digital converter 15. In this way, the accuracy of TDC is no longer limited by gate delay and D flip-flop setup and hold time. Therefore, high-precision TDC can be achieved with lower process requirements.

[0112] Since coarse counting is achieved through the counting value of sampling counter 11, the coarse counting unit composed of counter 11 and phase-locked loop 12 can be shared by multiple time-to-digital converters (TDCs), thereby reducing chip area and power consumption during design. For example, a coarse counting unit is composed of phase-locked loop 12 and counter 11, and a fine counting unit is composed of synchronizer 13, integrator 14, and analog-to-digital converter 15. The circuit includes multiple fine counting units, where multiple fine counting units can share a single coarse counting unit. For example, in the case of N fine counting units: each unit receives its corresponding third control signal Stop_1, Stop_2, Stop_3, ..., Stop_N, as well as a first clock pulse signal Fout from the coarse counting unit, and outputs second control signals READ_1, READ_2, READ_3, ..., READ_N corresponding to the N third control signals to the coarse counting unit, so that the coarse counting unit reads the count value corresponding to each second control signal. Meanwhile, the controller 16 determines the time residual signals ΔT_1, ΔT_2, ΔT_3, ..., ΔT_N between the respective third control signals Stop_1, Stop_2, Stop_3, ..., Stop_N and the corresponding second control signals READ_1, READ_2, READ_3, ..., READ_N according to each fine counter unit, and outputs the corresponding sampled values ​​to the controller 16 after passing through the integrator 14 and the analog-to-digital converter 15, so that the controller 16 can calculate the time difference information corresponding to each fine counter.

[0113] Figure 7 A lidar 20 according to an embodiment of the present invention is shown, comprising: a transmitting unit 21, a receiving unit 22, and a circuit 10 for measuring time as described above. The transmitting unit includes one or more lasers configured to emit a probe laser beam L1 for detecting a target object OB. The probe laser beam L1 undergoes diffuse reflection on the target object OB, and a portion of the echo L1' returns to the lidar and is received by the receiving unit, which converts it into an electrical signal. The receiving unit may include a photoelectric converter such as an avalanche photodiode (APD) or a single-photon avalanche diode (SPAD). In one embodiment, the circuit 10 is coupled to the transmitting unit 21 and the receiving unit 22 to determine the time of flight of the echo. For example, when the transmitting unit emits the probe laser beam, a first control signal Start is sent to the circuit, and when the receiving unit receives the echo signal, a third control signal Stop is sent to the circuit.

[0114] The present invention also relates to a method 100 for measuring time using a time-to-digital converter, such as... Figure 8 As shown below, please refer to... Figure 8 Detailed description.

[0115] In step S101: When the counter receives the first control signal, it starts counting the first clock pulse signal.

[0116] In step S102: The third control signal and the first clock pulse signal are received through the synchronizer, a second control signal is generated and output to the counter, and the time residual signal of the second control signal relative to the third control signal is output.

[0117] In step S103: When the counter receives the second control signal, it outputs a count value.

[0118] In step S104: the time residual signal is converted into a voltage signal by a signal converter, wherein the amplitude of the voltage signal can characterize the length of the time residual signal.

[0119] In step S105: The voltage signal is sampled by an analog-to-digital converter, and the sampled value is output.

[0120] According to an embodiment of the present invention, the method 100 further includes step S106: the controller obtains the time difference between the first control signal and the third control signal based on the count value and the sampled value.

[0121] According to a preferred embodiment of the present invention, step S101 includes: starting to count the first clock pulse signal Fout by the counter 11 when the first control signal Start undergoes a transition; step S103 includes: reading and counting the first clock pulse signal Fout by the counter 11 when the second control signal READ undergoes a transition.

[0122] According to a preferred embodiment of the present invention, the method further includes: receiving a reference clock pulse signal Fin through a phase-locked loop 12 and generating a frequency-multiplied first clock pulse signal Fout, wherein the first control signal Start is configured to maintain a certain phase difference with the first clock pulse signal Fout; and outputting the first clock pulse signal Fout to the counter 11 and the synchronizer 13, wherein the second control signal READ is configured to align with the rising edge of the first clock pulse signal Fout.

[0123] According to a preferred embodiment of the present invention, step S104 includes: receiving the time residual signal ΔT and the third control signal Stop through integrator 14, and starting to convert the time residual signal ΔT when the third control signal Stop undergoes a jump.

[0124] According to one embodiment of the present invention, steps S101-103 are performed synchronously with steps S104-105, that is, coarse counting and fine counting are performed synchronously.

[0125] According to a preferred embodiment of the present invention, the method is implemented by the circuit described above.

[0126] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit that can be used in a time-to-digital converter, comprising: The counter is configured to start counting the first clock pulse signal after receiving the first control signal, and output the count value according to the second control signal; The first control signal includes a start signal; the second control signal includes a read signal. A synchronizer is configured to output a second control signal to the counter based on a third control signal and a first clock pulse signal, and to output a time residual signal between the second control signal and the third control signal to a signal converter, wherein the synchronizer is configured to output the second control signal aligned with the rising edge of the first clock pulse signal; the third control signal includes a stop signal; The signal converter is configured to receive the time residual signal and convert the time residual signal into a voltage signal, wherein the amplitude of the voltage signal can characterize the length of the time residual signal; An analog-to-digital converter configured to sample the voltage signal to output sampled values; and The controller receives the count value output by the counter and the sample value output by the analog-to-digital converter, and determines the time difference information between the first control signal and the third control signal, including: determining the coarse counting time between the start signal and the read signal based on the count value and the duration of a single pulse period of the first clock pulse signal; Based on the sampled value, the fine counting time between the stop signal and the read signal is determined; the coarse counting time is subtracted from the fine counting time to obtain the time difference information between the start signal and the stop signal.

2. The circuit of claim 1, wherein the counter is a synchronous counter, the counter being configured to start counting the first clock pulse signal when the first control signal undergoes a transition, and to read and count the first clock pulse signal when the second control signal undergoes a transition.

3. The circuit as described in claim 1 or 2 further includes a phase-locked loop (PLL), wherein the PLL receives a reference clock pulse signal and outputs a first clock pulse signal with a multiplied frequency, and the counter and the synchronizer receive the first clock pulse signal from the PLL.

4. The circuit of claim 3, wherein the first control signal is configured to maintain a certain phase difference with the first clock pulse signal.

5. The circuit of claim 1 or 2, wherein the signal converter is an integrator, the signal converter is coupled to the synchronizer and configured to receive the time residual signal and the third control signal, and to begin converting the time residual signal when the third control signal undergoes a jump to obtain the voltage signal corresponding to the time residual signal.

6. The circuit of claim 1, wherein the analog-to-digital converter is a Flash analog-to-digital converter, the analog-to-digital converter is coupled to the signal converter and configured to receive the voltage signal.

7. The circuit as described in claim 3, wherein the counter and the phase-locked loop constitute a coarse counting unit, and the synchronizer, the signal converter, and the analog-to-digital converter constitute a fine counting unit, wherein, The circuit may include multiple fine counting units, for each fine counting unit: Each receives its corresponding third control signal to read the sampled value corresponding to the third control signal, and... The coarse counting unit outputs a corresponding second control signal so that the coarse counting unit reads the count value corresponding to the second control signal based on the previously obtained first control signal.

8. The circuit as claimed in claim 7, wherein, The controller determines the time difference information between the first control signal and each of the third control signals based on the third control signals corresponding to each fine counting unit.

9. The circuit of claim 1 or 2, wherein the synchronizer comprises a first D flip-flop and a second D flip-flop, an inverter, and a NAND gate connected in series, wherein the first D flip-flop receives the third control signal, the output of the first D flip-flop is coupled to the input of the second D flip-flop, the second D flip-flop outputs the second control signal, the inverter receives the third control signal, the output of the inverter is coupled to one of the inputs of the NAND gate, and the other input of the NAND gate receives the second control signal and outputs the time residual signal.

10. A lidar, comprising: A transmitting unit configured to emit a detection laser beam for detecting a target object; A receiving unit configured to receive the echo reflected from the probe laser beam on the target object and convert it into an electrical signal; The circuit according to any one of claims 1-9, wherein the circuit is coupled to the transmitting unit and the receiving unit to determine the flight time of the echo; wherein, when the transmitting unit emits a probe laser beam, it sends a first control signal to the circuit, and when the receiving unit receives the echo signal, it sends a third control signal to the circuit.

11. A method for measuring time using the circuit according to any one of claims 1-9, comprising: S101: When the counter receives the first control signal, it starts counting the first clock pulse signal; The first control signal includes a start signal; S102: Receive a third control signal and a first clock pulse signal via a synchronizer, generate a second control signal and output it to the counter, and output a time residual signal of the second control signal relative to the third control signal, wherein the second control signal is configured to be aligned with the rising edge of the first clock pulse signal; the second control signal includes a read signal; the third control signal includes a stop signal; S103: When the counter receives the second control signal, it outputs a count value; as well as, S104: The time residual signal is converted into a voltage signal by a signal converter, wherein the amplitude of the voltage signal can characterize the length of the time residual signal; S105: Sample the voltage signal using an analog-to-digital converter and output the sampled value; S106: The controller obtains the time difference between the first control signal and the third control signal based on the count value and the sampled value, including: determining the coarse counting time between the start signal and the read signal based on the count value and the duration of a single pulse period of the first clock pulse signal; Based on the sampled value, the fine counting time between the stop signal and the read signal is determined; the coarse counting time is subtracted from the fine counting time to obtain the time difference information between the start signal and the stop signal.

12. The method of claim 11, wherein step S101 comprises: The counter starts counting the first clock pulse signal when the first control signal undergoes a jump. Step S103 includes: using the counter to read and count the first clock pulse signal when the second control signal undergoes a jump.

13. The method of claim 12, further comprising: The first control signal is configured to maintain a certain phase difference with the first clock pulse signal by receiving a reference clock pulse signal through a phase-locked loop and generating a frequency-multiplied first clock pulse signal. The first clock pulse signal is output to the counter and synchronizer.

14. The method of claim 11, wherein step S104 comprises: The time residual signal and the third control signal are received by an integrator, and the conversion of the time residual signal begins when the third control signal undergoes a jump.

15. The method of claim 11, wherein steps S101-103 are performed simultaneously with steps S104-105.

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