光学装置的晶圆级制造
By integrating photonic and electronic wafers at the wafer level and exposing edge couplers, the manufacturing complexity and cost of grating couplers are addressed, enabling efficient optical input/output suitable for high data rate transceiver modules and in-package optical applications.
CN114616655BActive Publication Date: 2026-07-17CISCO TECHNOLOGY INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CISCO TECHNOLOGY INC
- Filing Date
- 2020-11-05
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing photonic chip grating couplers are sensitive to wavelength and polarization, and their manufacturing process is complex and costly, reducing manufacturing yield.
Method used
Photonic wafers and electronic wafers using edge couplers are bonded at the wafer level, and electrical connections are achieved through through-holes in the interposer wafer. The edge couplers are exposed after dicing, simplifying the manufacturing process and improving coupling efficiency.
Benefits of technology
It reduces the cost and complexity of downstream manufacturing processes, improves manufacturing yield, supports high-speed optical input/output, reduces parasitic effects, and is suitable for high data rate transceiver modules and in-package optical applications.
✦ Generated by Eureka AI based on patent content.
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Figure CN114616655B_ABST
Abstract
本文描述的各方面包括一种方法，该方法包括：将光子晶圆与电子晶圆进行接合以形成晶圆组件；去除晶圆组件的衬底以暴露光子晶圆或电子晶圆的表面；在光子晶圆的金属层与电子晶圆的金属层之间形成电连接；以及通过在所暴露的表面处将中介层晶圆与晶圆组件进行接合来将中介层晶圆添加至晶圆组件。中介层晶圆包括与光子晶圆和电子晶圆中的一者或两者的金属层电耦合的贯穿过孔。该方法还包括切割晶圆组件以形成多个管芯。每个管芯的相应边缘耦合器在通过切割形成的界面处被光学暴露。
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