Task monitoring method, recording medium, and computer device

Abstract

This invention discloses a task monitoring method, a recording medium, and a computer device. One embodiment of the method for monitoring multiple tasks includes the following steps: when each of the multiple tasks, which operates through a series of sequentially executed work states, enters a new work state, a work state entry flag recorded in a designated storage unit is queried; and the query result of the work state entry flag is used to determine whether each of the multiple tasks is in an abnormal state.

Description

Technical Field

[0001] The present invention relates to a task monitoring method and an apparatus for implementing the method, and more particularly to a task monitoring method for monitoring tasks running in an operating system (OS) and an apparatus for implementing the method. Background Technology

[0002] In a microcontroller unit (MCU), application software is modularized and designed as software components, and the functionality of these components is implemented through runnable code units. Within the MCU, a task is a unit of job scheduling where the OS allocates resources to run the software. Application software runs as a runnable unit mapped to a task.

[0003] In microcontrollers with multi-core architectures, additional microcontrollers for monitoring tasks have historically been used to detect real-time errors that may occur during software execution. This increases costs due to the additional monitoring microcontroller, and when using additional semiconductor chips (such as the additional microcontroller chip), communication between the chips must be configured, thus increasing the CPU load on the main microcontroller.

[0004] Therefore, a method is needed whereby, when monitoring for real-time errors in a detection task, the monitoring function is performed solely by the microcontroller itself, without using additional microcontrollers or other modules. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a task monitoring method and an apparatus for implementing the method, that is, in the absence of an additional microcontroller or other module, real-time errors of the task can be detected solely by the microcontroller itself.

[0006] Another technical problem to be solved by the present invention is to provide a task monitoring method and an apparatus for implementing the method, namely, in a microcontroller unit with a multi-core structure, it is possible to monitor whether each of multiple tasks is running normally without increasing the CPU load.

[0007] Another technical problem to be solved by the present invention is to provide a task monitoring method and an apparatus for implementing the method, namely, in a microcontroller unit with a multi-core structure, the omission or error of a task can be monitored by recording the working status of each of multiple tasks in another storage area and querying them.

[0008] The technical problems of this invention are not limited to those mentioned above. Those skilled in the art can clearly understand other technical problems not mentioned through the following description.

[0009] A method for monitoring multiple tasks according to an embodiment of the present invention for solving the aforementioned technical solution includes the following steps: when each of the multiple tasks, which are running through a series of sequential working states, enters a new working state, a working state entry flag recorded in a specified storage unit is queried; and the query result of the working state entry flag is used to determine whether each of the multiple tasks is in an abnormal state.

[0010] As one embodiment, when each of the plurality of tasks, which are run through a series of sequential working states, enters a new working state, the step of querying the working state entry flag of the record in the specified storage unit includes the following steps: setting the execution cycle of the task with the shortest execution cycle among the plurality of tasks as the query cycle of the working state entry flag; and querying the value of the working state entry flag of the record in the specified storage unit in each set query cycle.

[0011] As one embodiment, the series of working states may include: a first state, adding the task to the buffer and requesting an interrupt; a second state, scheduling the task added to the buffer to the OS; a third state, the task performing work through the scheduling; and a fourth state, the task completing its work.

[0012] As one embodiment, when each of the plurality of tasks running through a series of sequential working states enters a new working state, the step of querying the working state entry flag recorded in a specified storage unit includes the following steps: setting a normal working time for each working state of each task based on the execution cycle of each task; and storing the working state entry flag when each of the tasks enters a new working state within the set normal working time.

[0013] As an example, the step of determining whether each of the plurality of tasks is in an abnormal state by using the query result of the work state entry flag may include the following steps: when there is a work state in the series of work states that does not store the work state entry flag, the corresponding task is determined to be in an abnormal state.

[0014] As an example, when there is a working state in the series of working states where the working state entry flag is not stored, the step of determining the corresponding task as an abnormal state may include the following steps: determining that an error has occurred in a working state where the working state entry flag is not stored.

[0015] As one embodiment, the method may further include the following steps: calculating the number of the plurality of tasks before running the plurality of tasks; when the plurality of tasks have finished running, confirming whether the number of tasks that have completed normal operation is consistent with the number of tasks calculated before running; and when the number of tasks that have completed normal operation is inconsistent with the number of tasks calculated before running, determining that a task omission has occurred.

[0016] As one embodiment, the step of calculating the number of the plurality of tasks before running the plurality of tasks may include the following steps: at the initialization time of the operating system, the number of the plurality of tasks is calculated by running the initial cycle task of each of the plurality of tasks.

[0017] As one embodiment, when the plurality of tasks are completed and running, the step of confirming whether the number of tasks that have completed normal operation is consistent with the number of tasks calculated before running includes the following steps: at each time point when the plurality of tasks are completed and running, storing the number of tasks that have completed normal operation in the plurality of tasks in a designated storage unit; and comparing the number of stored tasks with the number of tasks calculated before running.

[0018] As an example, the step of determining whether each of the plurality of tasks is in an abnormal state by using the query result of the working state entry flag may further include the following step: when the task is in an abnormal state or an error occurs, reset the CPU.

[0019] As one embodiment, the specified storage unit may be a local storage area (LMU).

[0020] As one embodiment, the method may further include the following steps: allocating dynamic memory for recording flag variables of the first task among the plurality of tasks at the time point of execution; and returning the dynamic memory when the last task among the plurality of tasks completes execution.

[0021] The task monitoring method can be executed in a platform with a multi-core architecture that includes multiple cores running one or more of the multiple tasks and a monitoring core that monitors whether each of the multiple tasks is in an abnormal state.

[0022] A computer-readable non-transitory recording medium of one embodiment of the present invention for solving the aforementioned technical problem may store a computer program that causes a computer to perform the method.

[0023] A multi-core computer device according to an embodiment of the present invention for solving the aforementioned technical problem includes: a multi-core processor including multiple cores running one or more of a plurality of tasks and a monitoring core running a monitoring operation for each of the plurality of tasks; and a local storage area allocated with flag variables for each of the plurality of tasks. The processor executes a computer program containing instructions for performing the following operations: querying a work state entry flag recorded in the local storage area when each of the plurality of tasks, which runs through a series of sequential work states, enters a new work state; and using the query result of the work state entry flag to determine whether each of the plurality of tasks is in an abnormal state.

[0024] As one embodiment, the series of working states may include: a first state, adding the task to the buffer and requesting an interrupt; a second state, scheduling the task added to the buffer to the OS; a third state, the task performing work through the scheduling; and a fourth state, the task completing its work. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an embodiment of the present invention.

[0026] Figure 2 This is a flowchart illustrating a task monitoring method according to an embodiment of the present invention.

[0027] Figure 3 This is a block diagram of a computer device with a multi-core architecture according to another embodiment of the present invention.

[0028] Figure 4 Examples of monitoring the working status of tasks in a multi-core environment are shown, illustrating several embodiments of the present invention.

[0029] Figures 5 to 7 This is an example illustrating how flags are recorded based on whether a task has entered each working state, according to various embodiments of the present invention.

[0030] Figure 8 This is an example of determining whether a task is missing by comparing the number of normally running tasks with the actual number of tasks in various embodiments of the present invention.

[0031] Figure 9 The logic illustrates the number of actual tasks to be mastered in various embodiments of the present invention.

[0032] Figure 10 Examples illustrating how flag variables for tasks in various embodiments of the present invention are allocated to memory are shown.

[0033] Figure 11Examples of exception handling are shown when an error occurs in a task according to several embodiments of the present invention.

[0034] Figure 12 This is a hardware structure diagram of an exemplary computer device for implementing the methods of various embodiments of the present invention. Detailed Implementation

[0035] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. (Refer to the accompanying drawings) Figure 1 As will become clearer from the detailed embodiments described below, the advantages, features, and methods of implementing the present invention will become more apparent. However, the inventive concept is not limited to the following embodiments, but can be implemented in many different ways. The following embodiments are provided to complete the inventive concept and to fully convey the scope of the invention to those skilled in the art, the inventive concept being defined by the claims.

[0036] When labeling structural elements in the various figures, the same reference numerals should be assigned to the same structural elements whenever possible, even if they appear in different figures. Furthermore, in describing the present invention, detailed descriptions of related well-known structures or functions will be omitted if it is determined that such detailed descriptions would obscure the main points of the invention.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by those skilled in the art. Furthermore, unless explicitly defined otherwise, commonly used dictionary definitions should not be interpreted in an unusual or excessive manner. The terminology used in this specification is for illustrative purposes and is not intended to limit the invention. In this specification, singular forms include plural forms unless otherwise explicitly disclosed in the sentence.

[0038] Furthermore, when describing the structural elements of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the structural element from other structural elements, and the nature, order, or sequence of the corresponding structural elements are not limited by these terms. When a structural element is "connected," "combined," or "linked" with other structural elements, the structural element may be directly connected or linked to other structural elements, or it may be "connected," "combined," or "linked" between various structural elements.

[0039] Hereinafter, several embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic diagram of an embodiment of the present invention. (Refer to...) Figure 1In a microcontroller unit with a single-core structure, it is possible to monitor for errors that may occur during the execution of the first task 11 and the second task 12.

[0041] In the illustrated example, the first task 11 and the second task 12 operate through a series of sequential working states. These working states may include: a first state (A), adding the task to a buffer and requesting an interrupt; a second state (B), scheduling the task added to the buffer to the OS; a third state (C), where the task performs its work through scheduling; and a fourth state (D), where the task completes its work.

[0042] The first task 11 and the second task 12 can be monitored at a specified time interval 231. As an example, the specified time interval 231 can be set to the execution cycle of the task with the shortest execution cycle among multiple tasks.

[0043] As an example, whenever the first task 11 and the second task 12 respectively enter one of a series of working states (A, B, C, D), a working state entry flag can be recorded in a designated storage unit. In this case, it can be determined whether the first task 11 and the second task 12 are in an abnormal state by querying the working state entry flag recorded in the designated storage unit.

[0044] According to the embodiments of the present invention described above, in the absence of additional microcontroller units or other modules, real-time errors of a task can be detected solely by its own microcontroller unit.

[0045] Figure 2 This is a flowchart illustrating a task monitoring method according to an embodiment of the present invention.

[0046] The method of this invention embodiment can be used through Figure 3 The multi-core computer device 10 shown is... Figure 12 The computer device 100 shown is in operation. The multi-core computer device 10 or computer device 100 that runs the method of this embodiment can be a computer device with an application runtime environment. The description of the entity executing a portion of the work included in the method of this embodiment may be omitted; in this case, the entity is the multi-core computer device 10 or computer device 100.

[0047] Reference Figure 2First, in operation S21, whenever each of the multiple tasks running through a series of sequentially executed working states enters a new working state, the working state entry flag recorded in a designated storage unit is queried. For example, the designated storage unit can be the Local Memory Unit (LMU). The series of working states may include: a first state, adding a task to a buffer and requesting an interrupt; a second state, scheduling the task added to the buffer to the OS; a third state, the task performs its work through scheduling; and a fourth state, the task completes its work.

[0048] As an example, operation S21 may include: setting the execution cycle of the task with the smallest execution cycle among multiple tasks as the query cycle of the work state entry flag; and querying the value of the work state entry flag recorded in the specified storage unit in each set query cycle.

[0049] As an example, operation S21 may include: setting the normal working time of each working state of each task based on the execution cycle of each task; and storing a working state entry flag when each task enters a new working state within the set normal working time.

[0050] Next, in task S22, the query results of the task status entry flag are used to determine whether each of the multiple tasks is in an abnormal state.

[0051] As one embodiment, operation S22 may include the following operation: when there is a work state in a series of work states where the work state entry flag is not stored, the corresponding task is determined to be in an abnormal state. Furthermore, operation S22 may include the following operation: determining that an error has occurred in a work state where the work state entry flag is not stored.

[0052] As one embodiment, the method may further include: calculating the number of multiple tasks before running multiple tasks; confirming whether the number of tasks that have completed normal operation is consistent with the number of tasks calculated before running when multiple tasks have completed running; and determining that a task omission has occurred when the number of tasks that have completed normal operation is inconsistent with the number of tasks calculated before running.

[0053] In this scenario, when calculating the number of multiple tasks, at the OS initialization point, the number of tasks is calculated by running the initial cycle task of each of the multiple tasks. Furthermore, at the completion point of each of the multiple tasks, the number of tasks that have completed normal operation is stored in a designated memory location. By comparing the stored number of tasks with the number of tasks calculated before execution, it is confirmed whether any tasks have been missed.

[0054] As an example, operation S22 may also include resetting the CPU when the task is in an abnormal state or an error occurs.

[0055] As one embodiment, the method may further include: allocating dynamic memory for recording task flag variables at the time of the first task in a plurality of tasks; and returning the dynamic memory when the last task in the plurality of tasks completes execution. Thus, memory can be efficiently allocated when monitoring tasks.

[0056] As one embodiment, the method can be executed in a multi-core platform comprising multiple cores running one or more tasks and a monitoring core that monitors whether each of the multiple tasks is in an abnormal state. Thus, by separating the core running the multiple tasks from the core monitoring the multiple tasks, increased CPU load can be prevented, and the problem of task execution delays caused by monitoring tasks can be resolved.

[0057] According to the method of the present invention, task omissions or errors can be monitored by recording the working status of each of multiple tasks in a separate storage area and querying it. Therefore, it is possible to monitor whether each of multiple tasks is running normally without increasing CPU load.

[0058] Figure 3 This is a block diagram of a multi-core computer device according to another embodiment of the present invention. (Refer to...) Figure 3 The computer device 10 of this embodiment includes: a multi-core processor including multiple cores 31, 32, 33 and a monitoring core 34, wherein the multiple cores 31, 32, 33 run one or more of multiple tasks, and the monitoring core 34 monitors whether each of the multiple tasks is in an abnormal state; and a storage area 35 for storing flag variables related to the working state of each of the multiple tasks.

[0059] Each of a plurality of tasks running on at least one of the plurality of cores 31, 32, 33 is executed through a series of sequential working states. The series of working states may include: a first state (A), adding a task to a buffer and requesting an interrupt; a second state (B), scheduling the task added to the buffer to the OS; a third state (C), through the scheduling, the task performs work; and a fourth state (D), the task completes its work.

[0060] As one embodiment, whenever multiple tasks are run and a new working state is entered, a working state entry flag can be recorded (written) in storage area 35. For example, storage area 35 can be a local storage unit (LMU). For instance, when a task completes the execution of the first state (A) in a series of working states and enters the second state (B), the value of the working state entry flag relative to the first state (A) can be recorded as "1" to indicate that the first state (A) was executed normally.

[0061] As an example, the monitoring core 34 can query (Read) the working status entry flag recorded in the storage area 35 in order to monitor whether each of the multiple tasks is in an abnormal state.

[0062] That is, during the execution of multiple tasks on multiple cores 31, 32, and 33, the working status entry flag of each task can be recorded in storage area 35. By querying the working status entry flag recorded in storage area 35 in monitoring core 34, it is possible to monitor whether each of the multiple tasks is in an abnormal state. Thus, by separating the core running the tasks from the core monitoring the tasks, the increase in CPU load caused by monitoring work can be prevented.

[0063] Figure 4 Examples of monitoring the working status of tasks in a multi-core environment are shown, illustrating several embodiments of the present invention. (Refer to...) Figure 4 In a microcontroller unit with a multi-core architecture, it is possible to monitor for errors that may occur during the execution of the first task 11 and the second task 12.

[0064] In the example shown, the first task 11 runs on the first core 21, and the second task 12 runs on the second core 22. The first task 11 can sequentially execute a series of working states 111, 112, 113, and 114, and the second task 12 can sequentially execute a series of working states 121, 122, 123, and 124.

[0065] In this scenario, among the series of working states 121, 122, 123, and 124 executed by the second task 12, the first working state 121 can run on the first core 21. The series of working states executed sequentially by the first task 11 and the second task 12 may include: a first state (A), adding the task to the buffer and requesting an interrupt; a second state (B), scheduling the task added to the buffer to the OS; a third state (C), the task performing its work through scheduling; and a fourth state (D), the task completing its work.

[0066] As one embodiment, the first task 11 and the second task 12 running on the first core 21 and the second core 22 can be monitored at predetermined time intervals 231. As an example, the predetermined time interval 231 can be set to the execution cycle of the task with the shortest execution cycle among multiple tasks.

[0067] As an example, whenever the first task 11 and the second task 12 each enter a new working state of A, B, C, D, a working state entry flag can be recorded in a designated storage unit. By querying the working state entry flag recorded in the storage unit, it can be monitored whether the first task 11 and the second task 12 are in an abnormal state.

[0068] According to the embodiment, in a multi-core microcontroller unit, it is possible to monitor whether each of multiple tasks is running normally without increasing the CPU load.

[0069] Figures 5 to 7 This is an example illustrating how flags are recorded based on whether a task has entered each working state, according to various embodiments of the present invention.

[0070] Reference Figure 5 During the execution of the first task 41, the second task 42, and the third task 43 in the first core 21, the second core 22, and the third core 23, flags related to a series of working states of each task can be stored.

[0071] In the example shown, during the execution of the first task 41 and the second task 42, when a series of work states A, B, C, and D are executed normally, the value of the work state entry flag relative to each work state A, B, C, and D is recorded as "1".

[0072] However, in the case of the third task 43, among a series of working states A, B, C, and D, the first state A is executed normally, thus the value of the working state entry flag relative to the first state A is recorded as "1". However, as the second state B is not executed, the working state entry flags relative to the second state B, the third state C, and the fourth state C are not recorded. In this case, when the working state entry flag is not recorded, 45 can be automatically recorded as the default value "0".

[0073] In the example shown, it can be determined that the task omission 44 caused by the failure to execute the second state B may be due to an ISR problem caused by the interruption executed in the first state A.

[0074] Reference Figure 6During the execution of the first task 51 and the second task 52, when a series of working states A, B, C, and D are executed normally, the value of the working state entry flag relative to each working state A, B, C, and D is recorded as "1".

[0075] However, in the case of the third task 53, among a series of working states A, B, C, and D, the first state A and the second working state B are executed normally, so the value of the working state entry flag relative to the first state A and the second working state B is recorded as "1". However, as the third state C is not executed, the working state entry flag relative to the third state C and the fourth state C is not recorded, or it can be automatically recorded as the default value "0".

[0076] In the example shown, it can be determined that the task omission 54 caused by the failure to execute the third state C may be due to a problem with the OS scheduling executed in the second state B.

[0077] Reference Figure 7 During the execution of the first task 61 and the second task 62, when a series of working states A, B, C, and D are executed normally, the value of the working state entry flag relative to each working state A, B, C, and D is recorded as "1".

[0078] However, in the case of the third task 63, among a series of working states A, B, C, and D, the first working state A, the second working state B, and the third working state C are executed normally, so the value of the working state entry flag relative to the first working state A, the second working state B, and the third working state C is recorded as "1". However, as the fourth working state C is not executed, the working state entry flag relative to the fourth working state C is not recorded, or it can be automatically recorded as the default value "0".

[0079] In the example shown, it can be determined that the task omission 64 caused by the failure to execute the fourth state D may have occurred due to a problem with the task being executed in the third state C.

[0080] As described above, according to an embodiment of the present invention, during the execution of a task, the status entry flag of the working state recorded in a designated storage unit can be used to monitor in real time whether the task is executed normally.

[0081] Figure 8 This is an example of determining whether a task is missing by comparing the number of normally operating tasks with the actual number of tasks in various embodiments of the present invention. See also... Figure 8 When the values ​​of the entry flags for a series of working states A, B, C, and D, which are executed sequentially relative to the fifth task 75, are all recorded as "0", it can be determined that the fifth task 75 has been omitted.

[0082] As an example, instead of determining whether a task is missing by querying the value of the work status entry flag, it is also possible to determine whether a task is missing by comparing the number of tasks that are normally executed among multiple tasks with the actual number of tasks.

[0083] In the example shown, when multiple tasks 71, 72, 73, 74, 75, and 76 are scheduled to run sequentially on multiple cores 21, 22, and 23, the number of tasks that completed normal operation is stored at the time of each task's completion. When the last task 76 completes, the stored number of tasks 78 is queried to confirm whether it matches the actual number of tasks. As an example, if the stored number of tasks 78 that completed normal operation for the last task 76 is "5", and the actual number of tasks is "6", it can be determined that a task has been missed. In this case, task 75, whose number of tasks that completed normal operation was not stored, can be identified as the missed task.

[0084] Figure 9 The logic for determining the number of actual tasks in various embodiments of the present invention is illustrated. (Refer to...) Figure 9 When multiple tasks 81, 82, 83, 84, 85, and 86 are scheduled to run sequentially on multiple cores 21, 22, and 23, the actual number of tasks can be calculated at the time of OS initialization by running the initial cycle task of each of the multiple tasks.

[0085] In the example shown, when the initial cycle task of each task is run at the point when the OS is initialized, a flag representing the actual number of tasks can be incremented by 1 and stored upon completion of each task. For example, when the first task 81 completes, 810 "1" is stored in the flag (Chain_Cnt); when the second task 82 completes, the stored flag is incremented by 1 and stored as 820 "2". In this way, when the sixth task 86, as the final task, completes, 860 "6" is stored in the flag, thus calculating the actual number of tasks as "6". The actual number of tasks calculated in this way can be compared with the number of tasks that completed normally to determine if any tasks were missed.

[0086] Figure 10 Examples illustrating how flag variables for tasks in various embodiments of the present invention are allocated to memory are shown. (See also...) Figure 10 , Figure 10 This illustrates an example of allocating memory to store flag variables representing a series of operational states performed by each of the multiple tasks 91, 92, 93 during the monitoring of multiple tasks 91, 92, 93.

[0087] In the example shown, at the start time of the first task 91 among multiple tasks 91, 92, and 93, dynamic memory 94 is allocated to store flag variables corresponding to a series of working states. When the last task 93 finishes running, the dynamic memory 95 is returned, thus enabling efficient memory utilization. In this case, for example, the dynamic memory storing the flag variables can be allocated to and managed in the local memory area 35 (LMU). Therefore, the monitoring core 34, which performs task monitoring, only queries (Reads) the flag variables stored in the local memory area (LMU), thus preventing data conflicts and exhibiting high performance.

[0088] Figure 11 Examples of exception handling are shown when an error occurs in a task according to several embodiments of the present invention. (Refer to...) Figure 11 During the execution of multiple tasks (1010), tasks in an abnormal state or that have encountered errors can be detected by monitoring tasks (1020). In this case, when an abnormal state or error is detected, exception handling work (1030) can be performed to store information related to the abnormal state and error of the task (1031) and reset (1032) the CPU (1032).

[0089] In this case, before resetting the CPU, information related to the error can be stored in memory, such as the task ID and error type as the cause of the error.

[0090] Furthermore, at firmware initialization point 1040, the reset information can be updated and the updated reset information can be provided to the user.

[0091] Figure 12 This is a hardware structure diagram of an exemplary computer device for implementing the methods of various embodiments of the present invention.

[0092] like Figure 12 As shown, the computer device 100 may include one or more processors 101, a bus 107, a network interface 102, a memory 103 for loading a computer program 105 executed by the processor 101, and a register 104 for storing the computer program 105. However, Figure 12 Only structural elements relevant to embodiments of the invention are shown. Therefore, anyone skilled in the art will understand that, apart from… Figure 12 In addition to the structural elements shown, other general structural elements may also be included.

[0093] The processor 101 controls all the operations of the various structures of the computer device 100. For example, the processor 101 may be implemented as a microcontroller unit with a multi-core architecture.

[0094] As one embodiment, the processor 101 may be implemented as a multi-core ECU including multiple cores and a monitoring core, wherein the multiple cores run one or more of a plurality of tasks, and the monitoring core runs monitoring work for each of the plurality of tasks.

[0095] Furthermore, processor 101 may include at least one of a central processing unit (CPU), a microprocessor unit (MPU), a micro controller unit (MCU), a graphics processing unit (GPU), or any processor of any form known in the art. Moreover, processor 101 can perform operations for at least one application or program used to run the methods / work of various embodiments of the present invention. Computer device 100 may include more than one processor.

[0096] Memory 103 stores various data, instructions, and / or information. Memory 103 can load more than one program 105 from register 104 to run the methods / operations of various embodiments of the present invention. For example, when computer program 105 is loaded into memory 103, logic (or modules) can be implemented on memory 103. Memory 103 can be, for example, RAM, but is not limited to this.

[0097] Bus 107 provides communication functionality between the structural elements of computer device 100. Bus 107 can be implemented as various types of buses, such as address bus, data bus, and control bus.

[0098] Network interface 102 supports wired and wireless Internet communication of computer device 100. Network interface 102 can support various communication methods besides Internet communication. Therefore, network interface 102 may include communication modules known in the art.

[0099] Register 104 may non-temporarily store one or more computer programs 105. Register 104 may include non-volatile memory such as flash memory, hard disk, removable disk, or any form of computer-readable recording medium within the scope of this invention.

[0100] Computer program 105 may contain one or more instructions that implement the methods / operations of various embodiments of the present invention. When computer program 105 is loaded into memory 103, processor 101 executes the one or more instructions, thereby enabling the execution of the methods / operations of various embodiments of the present invention.

[0101] As one embodiment, computer program 105 may include instructions for performing the following tasks: querying a work state entry flag recorded in the local storage area when each of the plurality of tasks, which is operated through a series of work states in sequence, enters a new work state; and using the query result of the work state entry flag to determine whether each of the plurality of tasks is in an abnormal state.

[0102] Above, refer to Figures 1 to 12 This document describes various embodiments of the present invention and the effects based on these embodiments. The effects of the technical concept of the present invention are not limited to those mentioned above; those skilled in the art will clearly understand other effects not mentioned from the following description.

[0103] The technical concept of the present invention described above can be implemented in computer-readable code on a computer-readable medium. For example, the computer-readable recording medium can be a removable recording medium (CD, DVD, Blu-ray disc, USB storage device, removable hard disk) or a fixed recording medium (ROM, RAM, hard disk equipped with a computer). The computer program recorded on the computer-readable recording medium can be transmitted to other computer devices via a network such as the Internet and set on those other computer devices, thereby allowing it to be used on those computer devices.

[0104] Even though it has been described that all structural elements constituting an embodiment of the present invention are combined into one or work by combination, the technical concept of the present invention is not limited to such embodiments. That is, as long as it is within the scope of the purpose of the present invention, all structural elements can be selectively combined into more than one to work.

[0105] Although multiple tasks are shown in a specific order in the accompanying drawings, this should not be interpreted as meaning that the tasks should be run in the shown order or sequential order, or that running all the shown tasks is necessary to obtain the desired result. Multitasking and parallel processing may also be advantageous in certain situations. Furthermore, in the illustrated embodiments, the separation of multiple structures should not be construed as necessarily requiring such separation; it should be understood that the illustrated program components and systems are typically integrated into a single software product or packaged into multiple software products.

[0106] The embodiments of the present invention have been described above with reference to the accompanying drawings. Those skilled in the art can implement the present invention in other specific ways without changing the described technical concept or essential features. Therefore, the embodiments described above are illustrative in all respects and are not intended to limit the present invention. The scope of protection of the present invention is interpreted by the appended claims, and all technical concepts within the equivalent scope fall within the scope of protection of the technical concept defined by the present invention.

Claims

1. A task monitoring method of monitoring a plurality of tasks executed by a computer apparatus of a multi-core structure, characterized by, The multi-core architecture includes multiple cores running one or more of the multiple tasks and a monitoring core running a monitoring task for each of the multiple tasks. The task monitoring method includes the following steps: As each of the plurality of tasks, which operate through a series of sequential working states, enters a new working state, the plurality of cores record a working state entry flag for the executed task in their local storage area. The monitoring core queries the working status entry flag of the local storage area; as well as The monitoring core uses the query results of the working status entry flag to determine whether each of the multiple tasks is in an abnormal state. The monitoring check only queries the working status entry flag. The series of working states include: In the first state, the task is added to the buffer and an interrupt is requested; In the second state, the task added to the buffer is scheduled to the operating system; In the third state, the task performs its work through the aforementioned scheduling; and In the fourth state, the task is completed.

2. The task monitoring method according to claim 1, characterized in that, When each of the plurality of tasks, which runs through a series of sequential work states, enters a new work state, the step of querying the work state entry flag recorded in the local storage area includes the following steps: The execution cycle of the task with the shortest execution cycle among the multiple tasks is set as the query cycle of the work status entry flag; as well as In each set query cycle, the value of the working status entry flag of the record in the local storage area is queried.

3. The task monitoring method according to claim 1, characterized in that, When each of the plurality of tasks, which runs through a series of sequential work states, enters a new work state, the step of querying the work state entry flag recorded in the local storage area includes the following steps: The normal working time for each working state of each task is set based on the execution cycle of each task. as well as When each of the tasks enters a new working state within the set normal working time, the working state entry flag is stored.

4. The task monitoring method according to claim 1, characterized in that, The step of determining whether each of the plurality of tasks is in an abnormal state by using the query results of the work state entry flag includes the following steps: when there is a work state in the series of work states that does not store the work state entry flag, the corresponding task is determined to be in an abnormal state.

5. The task monitoring method according to claim 4, characterized in that, When there is a working state in the series of working states where the working state entry flag is not stored, the step of determining the corresponding task as an abnormal state includes the following steps: determining that an error has occurred in a working state where the working state entry flag is not stored.

6. The task monitoring method of claim 1, wherein, It also includes the following steps: Calculate the number of the multiple tasks before running them; When the multiple tasks are completed and running, it is confirmed whether the number of tasks that have completed normal operation is consistent with the number of tasks calculated before running. as well as When the number of tasks that have been completed normally is inconsistent with the number of tasks calculated before the operation, it is determined that a task omission has occurred.

7. The task monitoring method according to claim 6, characterized in that, The step of calculating the number of the plurality of tasks before running the plurality of tasks includes the following steps: at the initialization time of the operating system, the number of the plurality of tasks is calculated by running the initial cycle task of each of the plurality of tasks.

8. The task monitoring method according to claim 6, characterized in that, When the multiple tasks have completed running, the step of confirming whether the number of tasks that have completed running normally is consistent with the number of tasks calculated before running includes the following steps: At each completion time point of the plurality of tasks, the number of tasks that have completed normal operation among the plurality of tasks is stored in the local storage area; as well as Compare the number of tasks stored with the number of tasks calculated before execution.

9. The task monitoring method according to claim 1, characterized in that, The step of determining whether each of the plurality of tasks is in an abnormal state by using the query result of the working state entry flag further includes the following step: when the task is in an abnormal state or an error occurs, the central processing unit is reset.

10. The task monitoring method according to claim 1, characterized in that, It also includes the following steps: At the point in time when the first of the plurality of tasks is running, dynamic memory is allocated for recording the flag variables of the task; and When the last of the multiple tasks completes execution, the dynamic memory is returned.

11. A computer-readable, non-transitory recording medium, characterized in that, The computer program stores a computer program that causes a computer to perform the method according to any one of claims 1 to 10.

12. A multi-core computer device, characterized in that, include: A multi-core processor includes multiple cores that run one or more of a plurality of tasks and a monitoring core that runs a monitoring task for each of the plurality of tasks; as well as The local storage area is allocated to store the flag variables for each of the multiple tasks. The processor executes a computer program, the computer program containing instructions for performing the following tasks: As each of the plurality of tasks, which operate through a series of sequential working states, enters a new working state, the plurality of cores record a working state entry flag for the executed task in the local storage area. The monitoring core queries the working status entry flag of the local storage area; as well as The monitoring core uses the query results of the working status entry flag to determine whether each of the multiple tasks is in an abnormal state. The monitoring check only queries the working status entry flag. The series of working states include: In the first state, the task is added to the buffer and an interrupt is requested; In the second state, the task added to the buffer is scheduled to the operating system; In the third state, the task performs its work through the aforementioned scheduling; and In the fourth state, the task is completed.

Images