Simulation verification system and simulation verification method

Abstract

The embodiment of the present disclosure relates to the technical field of simulation, in particular to a simulation verification system and a simulation verification method, the simulation verification system comprises: a processor, which is connected with an interface of a first memory particle and is configured to: perform signal interaction with the first memory particle via the interface, the first memory particle being a finished product; a collection module, which is configured to: collect at least one command sequence transmitted by the interface during the signal interaction, and generate excitation data corresponding to the command sequence based on the command sequence; and a simulation module, which is used for performing simulation operation on a memory design to be verified, and is also used for receiving the excitation data to perform simulation verification on the simulation operation. The embodiment of the present disclosure is beneficial to improving the authenticity of simulation verification on the memory design to be verified.

Description

Technical Field This disclosure relates to the field of simulation technology, and in particular to a simulation verification system and simulation verification method. Background Technology Memory is a crucial component of a computer. It serves as a storage medium for running programs and necessary data, and it can directly exchange data with the Central Processing Unit (CPU). Memory chips are the basic units of memory. Typically, to ensure memory reliability, simulation calculations are performed during the memory chip design phase, and the simulation results are verified to improve the accuracy of the simulation.

[0001] However, currently, when simulating and verifying memory designs, there is a problem of low accuracy in the simulation results. Summary of the Invention This disclosure provides a simulation verification system and a simulation verification method, which at least helps to improve the authenticity of simulation verification of memory designs to be verified.

[0002] This disclosure provides a simulation verification system, including: a processor connected to an interface of a first memory chip, configured to: interact with the first memory chip via the interface, wherein the first memory chip is a finished product; a data acquisition module configured to: acquire at least one command sequence transmitted through the interface during signal interaction, and generate stimulus data corresponding to the command sequence based on the command sequence; and a simulation module, which performs simulation calculations on the memory design to be verified, and is also used to receive stimulus data to perform simulation verification on the simulation calculations.

[0003] In some embodiments, the command sequence is a valid command sequence, which is a command sequence transmitted from the interface during the period when the level of the chip select signal received by the first memory chip is at a preset level. The acquisition module is further configured to: monitor the level of the chip select signal received by the first memory chip, and acquire the command sequence transmitted from the interface during the period when the chip select signal is detected to be at the preset level, so as to obtain a valid command sequence.

[0004] In some embodiments, the acquisition module includes: a monitoring unit configured to monitor the level of the chip select signal; and an acquisition unit configured to acquire a command sequence during the period when the monitoring unit detects that the chip select signal is at a preset level, so as to obtain a valid command sequence with a preset length.

[0005] In some embodiments, the acquisition unit is configured to start acquiring the command sequence when the monitoring unit detects the falling edge of the chip select signal.

[0006] In some embodiments, the monitoring unit is further configured to monitor the acquisition time of the acquisition unit, and the acquisition unit is further configured to: when the monitoring unit detects that the acquisition time of the acquisition unit has reached a preset clock cycle, stop acquiring the command sequence in order to obtain a valid command sequence with a preset length.

[0007] In some embodiments, the acquisition module further includes a counting unit, which is configured to: set a count value for the acquisition unit to acquire a valid command sequence; receive the count value; and based on the count value, enable the acquisition unit to start acquiring the command sequence from the falling edge of the nth chip select signal and stop acquiring the command sequence when the mth falling edge of the chip select signal is reached, where n≥1 and m≥n.

[0008] In some embodiments, the counting unit is an adder counter.

[0009] In some embodiments, the acquisition module further includes a storage unit and a conversion unit. The storage unit is configured to store the command sequence sequentially based on the acquisition order of the command sequence and transmit the command sequence sequentially to the conversion unit. The conversion unit is used to generate excitation data corresponding to the command sequence sequentially based on the acquisition order and transmit the excitation data sequentially to the simulation module based on the acquisition order.

[0010] In some embodiments, the storage unit is a FIFO circuit.

[0011] According to some embodiments of this disclosure, another aspect of this disclosure also provides a simulation verification method, including: providing a processor, the processor being connected to an interface of a first memory chip, the processor interacting with the first memory chip via the interface, the first memory chip being a finished product; during the signal interaction, acquiring at least one command sequence transmitted by the interface; generating stimulus data corresponding to the command sequence based on the command sequence; providing a simulation module, the simulation module performing simulation calculations on the memory design to be verified and receiving the stimulus data for simulation verification.

[0012] In some embodiments, the acquisition step of acquiring the command sequence includes: monitoring the level of the chip select signal; acquiring the command sequence transmitted from the interface while the chip select signal is monitored to be at a preset level; monitoring the duration of the acquired command sequence, and stopping the acquisition of the command sequence when the duration is monitored to reach a preset clock cycle, so as to obtain a command sequence with a preset length.

[0013] In some embodiments, the preset clock period is 4 clock cycles.

[0014] In some embodiments, the method for acquiring a command sequence further includes: setting a count value for the command sequence acquisition step; based on the count value, starting the command sequence acquisition step when the nth chip select signal with a preset level is detected, and stopping the acquisition step when the mth chip select signal with a preset level is detected, wherein n≥1 and m≥n.

[0015] In some embodiments, after detecting the (m+1)th chip select signal with a preset level, excitation data is generated based on the acquired command sequence.

[0016] In some embodiments, stimulus data is generated sequentially based on the acquisition order of the command sequence, and the stimulus data is transmitted to the simulation module sequentially based on the acquisition order of the command sequence.

[0017] The technical solution provided in this disclosure has at least the following advantages: The technical solution of the simulation verification system provided in this disclosure includes: acquiring the command sequence of the processor and the actual first memory chip during actual interaction, and using the actual command sequence as stimulus data. The simulation module then verifies the simulation operation of the memory to be verified based on the stimulus data. On the one hand, using the actually acquired command sequence as stimulus data can increase the completeness and authenticity of the simulation verification results. On the other hand, the first memory chip can be actually interacted with different types of processors to obtain different command sequences, thereby providing stimulus data applicable to different manufacturers and increasing the compatibility of the simulation verification. Attached Figure Description One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a connection diagram of a simulation verification system provided in one embodiment of the present disclosure; Figure 2 This is a connection diagram of another simulation verification system provided in an embodiment of the present disclosure; Figure 3 A flowchart of a simulation verification method provided in another embodiment of this disclosure. Detailed Implementation As can be seen from the background technology, there is currently a problem with the low realism of simulation verification when performing simulation verification on memory to be verified.

[0019] Analysis revealed that one reason for the low realism of simulation verification of the memory under test is that the stimulus data used in the simulation verification is crucial to the completeness and accuracy of the design. Currently, the method for verifying memory under test typically involves generating stimulus data using a simulation system based on the understanding of the SPEC (Specification Specification) to verify the memory design. However, due to inconsistent interpretations of SPECs by different manufacturers, the generated stimulus data will also differ depending on the interpretation of the SPEC. This means the stimulus data represents only one interpretation of the SPEC, resulting in low realism of the simulation verification of the memory design under test. Furthermore, the manufactured memory chips lack compatibility, leading to low reliability when interacting with different processors.

[0020] This disclosure provides a simulation verification system, comprising a processor connected to an interface of a first memory chip, configured to: interact with the first memory chip via the interface, wherein the first memory chip is a finished product; a data acquisition module configured to: acquire at least one command sequence transmitted through the interface during signal interaction, and generate stimulus data corresponding to the command sequence based on the command sequence; and a simulation module configured to perform simulation calculations on the memory design to be verified, and also to receive the stimulus data to perform simulation verification on the simulation calculations.

[0021] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0022] Figure 1 This is a connection diagram of a simulation verification system provided in one embodiment of the present disclosure.

[0023] refer to Figure 1The simulation verification system includes: a processor 100, which is connected to an interface of a first memory chip 110 and is configured to interact with the first memory chip 110 via the interface, wherein the first memory chip 110 is a finished product; an acquisition module 120, which is configured to acquire at least one command sequence transmitted through the interface during the signal interaction and generate stimulus data corresponding to the command sequence based on the command sequence; and a simulation module 130, which is used to perform simulation calculations on the memory design to be verified and is also used to receive stimulus data to perform simulation verification on the simulation calculations.

[0024] The first memory chip 110 is a finished product, meaning it is manufactured and processed according to certain specifications and is ready for direct use. Based on the command sequence of actual signal interaction between the finished memory chip and the processor 100, stimulus data is generated and the memory to be verified is simulated. This ensures high reliability and realism in the simulation verification, making the results more reliable and referential. Specifically, in some embodiments, when selecting the first memory chip 110, it is necessary to choose a product with a structure similar to or even identical to the design of the memory to be verified.

[0025] The first memory chip 110 is located in the memory module and is used to store data that the processor 100 is about to process. Specifically, the first memory chip 110 is organized by bytes, and each byte in the first memory chip 110 corresponds to an address. Different bytes in the first memory chip 110 constitute different commands. In some embodiments, the memory design to be verified can be a DRAM (Dynamic Random Access Memory) memory design.

[0026] In some embodiments, the processor 100 can interact with a memory module having a first memory chip 110. When interacting with the memory chip, the processor 100 issues an access request to the memory chip to obtain commands from the memory chip and initiate a series of operations defined by the commands. Specifically, since different bytes in the memory chip constitute different commands, and each byte corresponds to an address, the processor 100 obtaining commands from the memory chip essentially means accessing the address corresponding to the corresponding command in the memory chip. In some embodiments, the processor 100 can be a central processing unit (CPU), such as a processor configured on a system-on-a-chip (SOC); in other embodiments, the processor 100 can also be a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0027] The command sequence is a linear queue formed by sequentially concatenating bytes as the basic unit. In the circuit constituting the first memory chip 110, the command sequence is a combination of different high and low voltage levels. The processor 100 reads the command sequence sequentially and executes it.

[0028] In some embodiments, the command sequence is a valid command sequence, which is the command sequence transmitted from the interface during the period when the level of the chip select signal received by the first memory chip 110 is a preset level. The acquisition module 120 is further configured to: monitor the level of the chip select signal received by the first memory chip 110, and acquire the command sequence transmitted from the interface during the period when the chip select signal is detected to be at the preset level, so as to obtain a valid command sequence. During the period when the chip select signal is at the preset level, the first memory chip 110 enters the circuit working state, so that when the processor 100 accesses the first memory chip 110, the first memory chip 110 can realize data input and output. That is, the processor 100 can obtain the command sequence in the first memory chip 110 and execute it. Therefore, the command sequence transmitted through the interface during the period when the chip select signal is at the preset level is a valid command sequence. The valid command sequence is acquired, and corresponding stimulus data is generated based on the valid command sequence, so that the stimulus data corresponds to the command sequence corresponding to the processor 100 when actually executing the command in the first memory chip 110. Therefore, when performing simulation verification on the memory design to be verified based on the stimulus data, the simulation verification results become more reliable. In some embodiments, multiple valid command sequences can be obtained, and these multiple valid command sequences have different combinations of high and low levels, thereby constituting different commands.

[0029] refer to Figure 2 , Figure 2 This is a connection diagram of another simulation verification system provided in one embodiment of the present disclosure. In some embodiments, the acquisition module 120 includes: a monitoring unit 121 configured to monitor the level of the chip select signal; and an acquisition unit 122 configured to acquire a command sequence while the monitoring unit 121 detects that the chip select signal is at a preset level, so as to obtain a valid command sequence with a preset length. The length of the valid command sequence refers to the number of bits of binary code in the valid command sequence. Since bytes are composed of binary code, the length of the valid command sequence is the number of bytes that make up the valid command sequence. The preset length of the valid command sequence can be set by the user according to different simulation verification needs. For example, in some embodiments, the preset length can be set to the total number of bytes in the valid command sequence. In some embodiments, the acquisition unit 122 can be an FPGA (Field Programmable Gate Array). The FPGA can achieve high-speed acquisition of valid command sequences, which is beneficial for timely acquisition of valid command sequences transmitted through the interface during the interaction between the processor 100 and the first memory chip 110, thereby ensuring that the acquired valid command sequences meet expectations and improving the completeness and reliability of simulation verification.

[0030] In some embodiments, the monitoring unit 121 is further configured to monitor the acquisition time of the acquisition unit 122. The acquisition unit 122 is further configured to stop acquiring the command sequence when the monitoring unit detects that the acquisition time of the acquisition unit 122 has reached a preset clock cycle, so as to obtain a valid command sequence with a preset length. That is, by controlling the acquisition time of the acquisition unit 122 for the command sequence, the length of the acquired valid command sequence is adjusted. It can be understood that the longer the acquisition time of the acquisition unit 122 for the command sequence, the longer the length of the acquired valid command sequence. In some embodiments, the preset clock cycle can be set to the time required for the processor 100 to access the first memory chip 110 once. That is, within the preset clock cycle, the processor 100 accesses the first memory chip 110 once and obtains a command, and then executes the corresponding action according to the obtained command. In this way, the valid command sequence acquired by the acquisition unit 122 corresponds to the command corresponding to the processor 100 actually executing one action, which helps to increase the realism of the simulation verification of the memory design to be verified.

[0031] In some embodiments, the acquisition unit 122 is configured to begin acquiring the command sequence when the monitoring unit 121 detects a falling edge of the chip select signal. The falling edge of the chip select signal refers to the instant the chip select signal level changes from high to low. That is, the first memory chip 110 enters the circuit operating state at the moment the chip select signal level changes from high to low, realizing data input and output. Setting the chip select signal to be active low minimizes the power consumption of chip select control and prevents external interference from entering the controlled first memory chip 110, thus ensuring the reliability of the first memory chip 110's operation. Setting the acquisition unit 122 to begin acquiring the command sequence at the moment the chip select signal level changes from high to low allows the acquisition unit 122 to start acquiring from the first byte constituting the valid command sequence, resulting in a more complete valid command sequence. This improves the completeness and effectiveness of the simulation verification results of the memory design under verification.

[0032] In some embodiments, the acquisition module 120 further includes a counting unit 123, configured to: set a count value for the acquisition unit 122 to acquire valid command sequences; the acquisition unit 122 receives the count value and, based on the count value, causes the acquisition unit 122 to start acquiring the command sequence from the falling edge of the nth chip select signal and stop acquiring the command sequence when the falling edge of the mth chip select signal is reached, where n≥1 and m≥n. When the processor 100 interacts with the first memory chip 110, it obtains one command from the first memory chip 110 for each access request sent to the first memory chip 110, that is, the processor 100 sequentially obtains at least one command from the first memory chip 110. The count value is set such that, in some embodiments, when n>1, the acquisition unit 122 does not acquire the command sequence corresponding to the first command obtained by the processor 100 from the first memory chip 110. The count value can be verified according to different user needs for simulation verification of the memory design to be verified. Users can collect the valid command sequence corresponding to the nth command to the mth command obtained by the processor 100 from the first memory chip 110 according to different needs, so as to adapt to different simulation verification requirements.

[0033] Specifically, in some embodiments, the counting unit 123 can be an adder counter. Specifically, when the adder counter detects a falling edge of the chip select signal, the value in the adder counter is incremented by 1, and it is determined whether the current count value is within a preset count value range. If the current count value is not within the preset count value range, the value in the adder counter is incremented by 1 again when the next falling edge of the chip select signal arrives, and it is determined whether the current count value is within the preset count value range. This process is repeated until the count value in the adder counter is within the preset count value range, at which point the acquisition unit 122 acquires the command sequence to obtain a valid command sequence. Afterward, the acquisition unit 122 begins acquiring the command sequence every time a falling edge of the chip select signal arrives, and the adder counter continuously counts the number of falling edges of the chip select signal until the count value in the adder counter exceeds the preset count value range. When the count value in the adder counter exceeds the preset count value range, it indicates that the acquisition unit 122 has completed acquiring the valid command sequence required by the user, and the acquisition unit 122 will not continue to acquire the command sequence.

[0034] In some embodiments, the acquisition module 120 further includes a storage unit 124 and a conversion unit 125. The storage unit 124 is configured to: store the command sequence sequentially based on the acquisition order of the command sequence, and transmit the command sequence sequentially to the conversion unit 125. The conversion unit 125 is configured to: generate stimulus data corresponding to the command sequence sequentially based on the acquisition order, and transmit the stimulus data sequentially to the simulation module 130 based on the acquisition order. The simulation module 130 includes a simulation model, which is used to perform simulation calculations on the memory design to be verified, specifically: simulating the interaction between the memory design to be verified and the processor 100. In some embodiments, to improve the accuracy of the simulation verification of the memory design to be verified, the simulated processor 100 interacting with the memory design to be verified and the first memory chip 110 interacting with the actual processor 100 in the simulation model are the same processor 100 used when interacting with the actual processor 100. That is, in the simulation model, the order in which the simulated processor 100 accesses the memory design to be verified to obtain different commands in the memory design to be verified is the same as the order in which the actual processor 100 accesses the first memory chip 110 and obtains different commands in the first memory chip 110. In other words, the stimulus data generated sequentially based on the acquisition order of the command sequence corresponds to the order in which the simulated processor 100 acquires commands from the memory design to be verified in the simulation model. Therefore, by transmitting the stimulus data sequentially to the simulation module 130 based on the acquisition order of the command sequence, the stimulus data can verify the behavior of the memory design to be verified when the simulated processor 100 in the simulation model accesses the memory design, thereby improving the accuracy and effectiveness of the simulation verification.

[0035] Specifically, in some embodiments, after acquiring a command sequence, the acquisition unit 122 transmits the command sequence to the storage unit 124, thus enabling sequential storage of the command sequences. In some embodiments, the storage unit 124 can be a FIFO (First Input First Output) circuit, which reads data sequentially according to the order in which it is written. Specifically, the FIFO circuit includes multiple sub-storage units arranged in a queue, where each sub-storage unit stores a command sequence. The FIFO circuit also includes two position pointers: a write pointer pointing to the first sub-storage unit in the queue, and a read pointer pointing to the last sub-storage unit. When the FIFO circuit receives a write command, the command sequence is written to the sub-storage unit pointed to by the write pointer, and then the write pointer is incremented. When the FIFO circuit receives a read command, the read pointer is incremented, and the command sequence in the sub-storage unit pointed to by the read pointer is read. Since the write pointer points to the first sub-store unit of the queue and the read pointer points to the last sub-store unit of the queue, each time a command sequence is stored, the current command sequence is stored in the sub-store unit at the front of the queue, and each time a command is read, the command sequence is read from the last sub-store unit in the current queue. This ensures that storage unit 124 can store the command sequence one by one according to the acquisition order, and generate stimulus data sequentially according to the acquisition order of the command sequence. In some embodiments, the FIFO circuit can be a Block RAM (Block Random Access Memory) located in the FPGA.

[0036] The conversion unit 125 is communicatively connected to the storage unit 124. The conversion unit 125 receives command sequences output by the storage unit 124 one by one and converts the command sequences into stimulus data. Specifically, each time the conversion unit 125 receives a command sequence, it converts the command sequence into stimulus data and transmits the stimulus data to the simulation module 130 for simulation. This allows the conversion module to convert command sequences sequentially, which helps to ensure the orderliness of simulation verification in the simulation module 130, thereby improving the accuracy of the simulation verification.

[0037] In some embodiments, the conversion unit 125 and the storage unit 124 can communicate using the USB communication protocol. The conversion unit 125 can be configured with a PyUSB module to communicate with the storage unit 124. Based on this, in some embodiments, the conversion unit 125 can be a PyUSB-based Python script. The Python script can generate excitation data based on the binary code constituting the command sequence. In some embodiments, the excitation data is an excitation waveform; therefore, the Python script can generate the excitation waveform based on the binary code of the command sequence and the mathematical expression of the waveform.

[0038] In some embodiments, the simulation module 130 and the acquisition module 120 can share a bus system, and data can be stored on the bus. The data can be read out by the internal bus clock pointing to the address where the data is stored on the bus. Therefore, in some embodiments, after generating stimulus data, the stimulus data can be driven onto the bus. When the simulation module 130 reads the stimulus data, it can read the stimulus data by the internal bus clock pointing to the address where the stimulus data is stored on the bus.

[0039] The simulation module 130 performs simulation verification of the memory to be verified based on the stimulus data as follows: the simulation model in the simulation module 130 receives the stimulus data; the simulation model starts simulation calculation of the memory design to be verified based on the stimulus data; the simulation model ends the simulation calculation of the memory to be verified; the simulation model obtains the simulation output data of the memory design to be verified; and the verification results are analyzed based on the simulation output data of the memory design to be verified.

[0040] In the simulation verification system provided in the above embodiments, the simulation module 130 verifies the simulation operation of the memory to be verified by acquiring the command sequence of the processor 100 and the actual first memory chip 110 during actual interaction and using the actual command sequence as stimulus data. On the one hand, using the actually acquired command sequence as stimulus data can increase the completeness and authenticity of the simulation verification results. On the other hand, the first memory chip 110 can be actually interacted with different types of processors 100 to obtain different command sequences, thereby serving as stimulus data applicable to different manufacturers and increasing the compatibility of simulation verification.

[0041] Another embodiment of this disclosure provides a simulation verification method, which can be applied to the simulation verification system provided in the previous embodiment. The simulation verification method provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0042] Figure 3 A flowchart of a simulation verification method provided in another embodiment of this disclosure includes: Provides processor 100 (reference) Figure 1Processor 100 and first memory chip 110 (reference) Figure 1 The processor 100 communicates with the first memory chip 110 via an interface, and the first memory chip 110 is a finished product. In some embodiments, the processor 100 can interact with a memory module containing the first memory chip 110. When interacting with the memory chip, the processor 100 issues an access request to the memory chip to obtain commands from the memory chip and initiate a series of operations defined by the commands. Specifically, the memory chip is organized by bytes. In the first memory chip 110, different bytes constitute different commands, and each byte corresponds to an address. That is, the processor 100 obtains commands from the memory chip by accessing the address corresponding to the corresponding command in the memory chip. In some embodiments, the processor 100 can be a central processing unit; in other embodiments, the processor 100 can also be a network processor, a digital signal processor, an application-specific integrated circuit or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. In some embodiments, before the processor 100 interacts with the first memory chip 110, the processor 100 and the first memory chip 110 need to be initialized respectively. This allows interference to be eliminated and it can be determined which command sequences are within the acquisition range when collecting command sequences during the signal interaction between the processor 100 and the first memory chip 110 based on a pre-set acquisition range. This enables acquisition as needed.

[0043] During signal interaction, at least one command sequence transmitted through the acquisition interface is collected. Based on the command sequence during actual signal interaction between the finished memory chip and the processor 100, stimulus data is generated and the memory to be verified is simulated and verified, resulting in higher reliability and realism of the simulation verification and more referential results. In some embodiments, an FPGA can be used to acquire the command sequence. The FPGA can achieve high-speed acquisition of valid command sequences, which is beneficial for timely acquisition of valid command sequences transmitted through the interface during the interaction between the processor 100 and the first memory chip 110, thereby ensuring that the acquired valid command sequences meet expectations and improving the completeness and reliability of the simulation verification. In some embodiments, the FPGA can acquire the command sequence according to the Universal Asynchronous Receiver / Transmitter (UART) protocol. Specifically, a power-on-initialization step is required for the FPGA before acquiring the command sequence.

[0044] In some embodiments, the acquisition step of acquiring the command sequence includes: monitoring the level of the chip select signal; in some embodiments, a monitoring tool in the FPGA can be used to monitor the level of the chip select signal. Specifically, in some embodiments, the FPGA can be started before the processor 100 performs a signal interaction step with the first memory chip 110, so that the monitoring tool in the FPGA can start monitoring the level of the chip select signal before the processor 100 performs a signal interaction step with the first memory chip 110. In this way, it can be ensured that the monitoring tool starts monitoring from the moment the processor 100 interacts with the first memory chip 110, preventing the problem of incomplete command sequence acquisition due to incomplete monitoring of the chip select signal level, which is beneficial to improving the accuracy and completeness of subsequent simulation verification of the memory design to be verified.

[0045] While the chip select signal is at a preset level, a command sequence transmitted from the interface is acquired. During this period, the command sequence transmitted via the interface is considered a valid command sequence, and the processor 100 executes corresponding actions based on this valid command sequence. In some embodiments, the acquisition of the command sequence can be set to begin when the falling edge of the chip select signal is detected. That is, the first memory chip 110 enters the circuit operating state and realizes data input and output when the chip select signal level changes from high to low. Therefore, setting the acquisition of the command sequence to begin when the chip select signal level changes from high to low allows acquisition to start from the first byte constituting the valid command sequence, resulting in a more complete valid command sequence. This improves the completeness and effectiveness of the simulation verification results of the memory design under verification.

[0046] The duration of the acquired command sequence is monitored, and acquisition of the command sequence is stopped when the monitored duration reaches a preset clock cycle, so as to obtain a command sequence with a preset length. The length of the acquired effective command sequence is adjusted by controlling the acquisition time of the command sequence. In some embodiments, the preset clock cycle can be set to the time required for the processor 100 to access the first memory chip 110 once, that is, within the preset clock cycle, the processor 100 accesses the first memory chip 110 once and obtains a command, and then executes the corresponding action according to the obtained command. In this way, the acquired effective command sequence corresponds to the command corresponding to the processor 100 actually executing one action, which helps to increase the realism of the simulation verification of the memory design to be verified. Specifically, in some embodiments, the preset clock cycle can be set to 4 clock cycles.

[0047] In some embodiments, the method for acquiring command sequences further includes: setting a count value for the command sequence acquisition steps; based on the count value, starting the command sequence acquisition steps when the nth chip select signal with a preset level is detected, and stopping the acquisition steps when the mth chip select signal with a preset level is detected, where n≥1 and m≥n. The count value can be verified according to different user needs for simulation verification of the memory design to be verified. Users can acquire the valid command sequences corresponding to the nth command to the mth command obtained by the processor 100 from the first memory chip 110 according to different needs, to adapt to different simulation verification requirements.

[0048] In some embodiments, a counter can be used to set the count value. Specifically, when the counter detects a falling edge of the chip select signal, the value in the counter is incremented by 1, and it is determined whether the current count value is within a preset count value range. If the current count value is not within the preset count value range, the counter is incremented by 1 again when the next falling edge of the chip select signal arrives, and it is determined whether the current count value is within the preset count value range. This process is repeated until the count value in the counter is within the preset count value range, at which point the command sequence is acquired to obtain a valid command sequence.

[0049] Generate stimulus data corresponding to the command sequence based on the command sequence; provide a simulation module, which performs simulation calculations on the memory design to be verified and receives the stimulus data for simulation verification.

[0050] According to the first memory chip 110 (reference) Figure 1 ) and processor 100 (reference) Figure 1 The command sequence used for actual signal interaction generates stimulus data, which is used to simulate and verify the memory to be verified, thus making the simulation and verification of the memory to be verified more reliable and realistic.

[0051] Specifically, in some embodiments, after detecting the (m+1)th chip select signal with a preset level, stimulus data is generated based on the acquired command sequence. That is, when the number of times the chip select signal is at the preset level exceeds a preset count value range, the acquisition of the command sequence stops, and stimulus data is generated based on the acquired command sequence. This ensures that the acquired command sequence is within the preset count value range, allowing the user to obtain the required command sequence. In some embodiments, an adder counter continuously counts the number of falling edges of the chip select signal until the count value in the adder counter exceeds a preset count value range, i.e., the count value in the adder counter is m+1. When the count value in the adder counter exceeds m+1, it indicates that the valid command sequence required by the user has been acquired, and therefore, the acquisition of the command sequence will not continue.

[0052] In some embodiments, stimulus data is generated sequentially based on the acquisition order of the command sequence, and the stimulus data is transmitted sequentially to the simulation module based on the acquisition order of the command sequence. Transmitting the stimulus data sequentially to the simulation module based on the acquisition order of the command sequence allows the stimulus data to affect the simulation processor 100 (reference) in the simulation model. Figure 1 When accessing the memory design to be verified, the behavior of the memory design to be verified one by one, which helps to improve the accuracy and effectiveness of simulation verification.

[0053] Specifically, in some embodiments, the command sequence is stored immediately after each acquisition, thus enabling sequential storage of the command sequences. In some embodiments, a FIFO circuit can be configured to store the command sequences, and the FIFO circuit can read the data sequentially according to the order in which the data was written to the FIFO circuit. In some embodiments, the FIFO circuit can be a Block RAM located in the FPGA.

[0054] In some embodiments, a conversion unit can convert the command sequence to generate stimulus data. In some embodiments, the conversion unit communicates with the Block RAM in the FPGA via a USB communication protocol. Therefore, in some embodiments, the conversion unit can be a PyUSB-based Python script, which can generate stimulus data based on the binary code constituting the command sequence. In some embodiments, the Block RAM and the Python script can share a bus system, where data can be stored on the bus and read out by an internal bus clock pointing to the address where the data is stored on the bus. Therefore, in some embodiments, before generating stimulus data, a data pointer needs to be sent via USB in the FPGA to point to the address where the command sequence is stored on the bus, thereby outputting the data to the Python script.

[0055] In some embodiments, after the Python script generates stimulus data, it can drive the stimulus data onto the bus. When the simulation module reads the stimulus data, it can use the internal bus clock to point to the address where the stimulus data is stored on the bus, thereby reading the stimulus data. The method for the simulation module to perform simulation verification of the memory to be verified based on the stimulus data can be as follows: the simulation model in the simulation module receives the stimulus data; the simulation model starts simulation calculations on the memory design to be verified based on the stimulus data; the simulation model ends the simulation calculations on the memory to be verified; the simulation model obtains the simulation output data of the memory design to be verified; and the verification results are analyzed based on the simulation output data of the memory design to be verified.

[0056] In the simulation verification method provided in the above embodiments, the processor 100 (reference) is obtained. Figure 1 ) and the actual first memory chip 110 (reference) Figure 1 The simulation module 130 uses the actual command sequence obtained during the actual interaction as stimulus data to perform simulation operations on the memory to be verified. On the one hand, using the actual command sequence as stimulus data can increase the completeness and authenticity of the simulation verification results. On the other hand, the first memory chip 110 can actually interact with different types of processors 100 to obtain different command sequences, thus providing stimulus data applicable to different manufacturers and increasing the compatibility of the simulation verification.

[0057] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A simulation verification system, characterized in that, include: The processor, connected to an interface of a first memory chip, is configured to: interact with the first memory chip via the interface, wherein the first memory chip is a finished product; The acquisition module is configured to: acquire at least one command sequence transmitted by the interface during the signal interaction, and generate excitation data corresponding to the command sequence based on the command sequence; The simulation module is used to perform simulation calculations on the memory design to be verified, and the simulation module is also used to receive the stimulus data to perform simulation verification on the simulation calculations.

2. The simulation verification system according to claim 1, characterized in that, The command sequence is a valid command sequence, which is the command sequence transmitted from the interface during the period when the level of the chip select signal received by the first memory chip is a preset level. The acquisition module is further configured to: monitor the level of the chip select signal received by the first memory chip, and acquire the command sequence transmitted from the interface during the period when the chip select signal is detected to be at the preset level, so as to obtain the valid command sequence.

3. The simulation verification system according to claim 2, characterized in that, The acquisition module includes: A monitoring unit, configured to monitor the level of the chip select signal; The acquisition unit is configured to acquire the command sequence during the period when the monitoring unit detects that the chip select signal is at the preset level, so as to obtain the valid command sequence with a preset length.

4. The simulation verification system according to claim 3, characterized in that, The acquisition unit is configured to start acquiring the command sequence when the monitoring unit detects the falling edge of the chip select signal.

5. The simulation verification system according to claim 3 or 4, characterized in that, The monitoring unit is also used to monitor the acquisition time of the acquisition unit. The acquisition unit is further configured to: when the monitoring unit detects that the acquisition time of the acquisition unit has reached a preset clock cycle, stop acquiring the command sequence in order to obtain the valid command sequence with a preset length.

6. The simulation verification system according to claim 3, characterized in that, The acquisition module further includes a counting unit, which is configured to: set the acquisition unit to acquire a count value of the valid command sequence; the acquisition unit receives the count value and, based on the count value, enables the acquisition unit to start acquiring the command sequence from the falling edge of the nth chip select signal and stop acquiring the command sequence when the mth falling edge of the chip select signal is reached, where n≥1 and m≥n.

7. The simulation verification system according to claim 6, characterized in that, The counting unit is an adder counter.

8. The simulation verification system according to claim 1, characterized in that, The acquisition module also includes: The storage unit is configured to: store the command sequence sequentially based on the acquisition order of the command sequence, and transmit the command sequence sequentially to the conversion unit; The conversion unit is used to generate the excitation data corresponding to the command sequence in sequence based on the acquisition order, and to transmit the excitation data to the simulation module in sequence based on the acquisition order.

9. The simulation verification system according to claim 8, characterized in that, The storage unit is a FIFO circuit.

10. A simulation verification method, comprising: A processor is provided, which is connected to an interface of a first memory chip. The processor interacts with the first memory chip via the interface, and the first memory chip is a finished product. During the signal interaction, at least one command sequence transmitted by the interface is acquired; Generate stimulus data corresponding to the command sequence based on the command sequence; A simulation module is provided, which performs simulation calculations on the memory design to be verified and receives the stimulus data for simulation verification.

11. The simulation verification method according to claim 10, characterized in that, The acquisition steps for acquiring the command sequence include: Monitor the level of the chip select signal; While the chip select signal is detected to be at a preset level, the command sequence transmitted from the interface is acquired; The duration of the acquired command sequence is monitored, and when the duration reaches a preset clock cycle, the acquisition of the command sequence is stopped to obtain the command sequence with a preset length.

12. The simulation verification method according to claim 11, characterized in that, The preset clock cycle is 4 clock cycles.

13. The simulation verification method according to claim 11, characterized in that, The method for collecting the command sequence further includes: Set a count value for the steps of collecting the command sequence; Based on the count value, the acquisition step is started when the nth chip select signal with a preset level is detected, and the acquisition step is stopped when the mth chip select signal with a preset level is detected, where n≥1 and m≥n.

14. The simulation verification method according to claim 13, characterized in that, After detecting the (m+1)th chip select signal with a preset level, the excitation data is generated based on the acquired command sequence.

15. The simulation verification method according to claim 14, characterized in that, Based on the acquisition order of the command sequence, the stimulus data is generated sequentially, and based on the acquisition order of the command sequence, the stimulus data is transmitted to the simulation module sequentially.

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