Integrated circuit, method of operating the same, and display system including the same

Abstract

The present application relates to an integrated circuit, an operating method thereof, and a display system including the same. An integrated circuit capable of gating a clock signal to reduce power consumption during a vertical front porch interval includes a control signal generator configured to change a gate control signal from a low level to a high level according to a timing when a data enable signal changes from a high level to a low level, and change the gate control signal from the high level to the low level after a predetermined horizontal back porch interval from a rising edge of a horizontal synchronization signal; and a clock gate circuit configured to stop a flip of a first clock signal input through a first input terminal to output a second clock signal held at a low level through a first output terminal when the gate control signal of the high level is input to a control terminal, and restore the flip of the first clock signal to output the second clock signal flipped between a high level and a low level through the first output terminal when the gate control signal of the low level is input to the control terminal.

Description

Technical Field

[0001] This disclosure relates to controlling a clock signal for a display, and more specifically, to gating a clock signal. Background Technology

[0002] The use of display devices that can support a first frame rate (e.g., 60 Hz) and a second frame rate (e.g., 120 Hz) and can operate at either the first or the second frame rate is increasing.

[0003] In the case of such a display device, in order to achieve very smooth and seamless frequency changes, the display device can be driven at the first frame rate and the second frame rate by synchronizing the vertical synchronization time of one cycle of the first frame rate with the vertical synchronization time of one cycle of the second frame rate and increasing the vertical edge spacing of the vertical synchronization signal corresponding to the first frame rate.

[0004] However, when the vertical edge interval of the vertical sync signal is long during the first frame rate of driving the display device, the clock signal may toggle during the vertical edge interval, thus increasing the power consumption of circuits that operate using the clock signal. Summary of the Invention

[0005] To address the aforementioned issues, this disclosure aims to provide an integrated circuit capable of gating clock signals to reduce power consumption during the vertical leading edge interval, a method of operating the integrated circuit, and a display system including the integrated circuit.

[0006] According to one aspect of this disclosure, an integrated circuit for gating a clock signal includes: a control signal generator configured to change a gating control signal from low to high based on a timing when a data enable signal changes from high to low, and to change the gating control signal from high to low after a predetermined horizontal trailing edge interval from the rising edge of a horizontal sync signal; and a clock gating circuit configured to stop the toggling of a first clock signal input through a first input terminal to output a second clock signal held at a low level through a first output terminal when a high-level gating control signal is input to a control terminal, and to resume the toggling of the first clock signal to output a second clock signal toggling between high and low levels through a first output terminal when a low-level gating control signal is input to the control terminal.

[0007] According to another aspect of this disclosure, a display system includes a display device and a driver integrated circuit (IC) configured to control the operation of the display device, wherein the driver IC includes: a control signal generator configured to change a gating control signal from low to high at a timing when a data enable signal changes from high to low, and to change the gating control signal from high to low after a predetermined horizontal trailing edge interval from the rising edge of a horizontal sync signal; and a clock gating circuit configured to stop the toggling of a first clock signal input through a first input terminal to output a second clock signal held at a low level through a first output terminal when a high-level gating control signal is input to a control terminal, and to resume the toggling of the first clock signal to output a second clock signal toggling between high and low levels through a first output terminal when a low-level gating control signal is input to the control terminal.

[0008] According to another aspect of this disclosure, an operation method for an integrated circuit for a gated clock signal includes the following steps: when a data enable signal changes from a high level to a low level, changing a gate control signal from a low level to a high level; stopping the toggling of a first clock signal input through a first input terminal in response to the high-level gate control signal to output a second clock signal that remains at a low level to a first output terminal; changing the gate control signal from a high level to a low level after a predetermined horizontal trailing edge interval from the rising edge of a horizontal synchronization signal; and resuming the toggling of the first clock signal in response to the low-level gate control signal to output a second clock signal that toggles between a high level and a low level to the first output terminal. Attached Figure Description

[0009] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings: Figure 1 This is a block diagram of a display system according to an embodiment of the present disclosure; Figure 2 This is a block diagram of a control circuit and a timing controller included in a driver integrated circuit (IC) according to embodiments of the present disclosure; and Figure 3 It is a timing diagram used to describe the operation of a driver IC according to an embodiment of the present disclosure. Detailed Implementation

[0010] In this specification, it should be noted that similar reference numerals already used to denote similar elements in other figures are used for elements as much as possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are irrelevant to the essential configuration of this disclosure will be omitted. The terminology described in this specification should be understood as follows.

[0011] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following description of embodiments in conjunction with the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0012] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the illustrated details. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the essential points of this disclosure.

[0013] When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Unless otherwise stated, singular terms may include plural forms.

[0014] When interpreting a component, although there is no explicit description, the component is interpreted as including a range of error.

[0015] When describing temporal relationships, such as when time sequence is described as “after,” “following after,” “next,” and “before,” discontinuous cases may be included unless “only” or “directly” is used.

[0016] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0017] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, "at least one of the first, second, and third items" means a combination of all items derived from two or more of the first, second, and third items, as well as the first, second, or third item.

[0018] Features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, and may interoperate with each other in various ways and be technically driven, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other or may be implemented together in an interdependent relationship.

[0019] In the following description, embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 This is a block diagram of a display system according to an embodiment of the present disclosure.

[0021] like Figure 1 As shown, the display system 100 according to an embodiment of the present disclosure includes a host system 200, a driver integrated circuit (IC) 300, and a display device 400.

[0022] The display system 100 may be an electronic device that includes a display device 400, such as a mobile device that uses the voltage of a battery as its operating voltage.

[0023] Examples of mobile devices may include at least one of laptop computers, mobile internet devices (MIDs), Internet of Things (IoT) devices, tablet PCs, and smartphones.

[0024] The host system 200 may be a control device capable of controlling the operation of the driver IC 300, and may be, but is not limited to, a central processing unit (CPU) or an application processor (AP). The host system 200 generates a command APC indicating whether to operate the display device 400 at a first frame rate (e.g., 60 Hz) or at a second frame rate (e.g., 120 Hz), and sends the command APC to the driver IC 300.

[0025] The host system 200 can determine whether the application running in the display system 100 is a game application or an application capable of scrolling web pages (or web documents, hereinafter referred to as "web documents").

[0026] When it is determined that the game application is not running or the web document is not being scrolled, the host system 200 generates an APC command instructing the display device 400 to operate at a first frame rate. When it is determined that the game application is running or the web document is being scrolled, the host system 200 generates an APC command instructing the display device 400 to operate at a second frame rate.

[0027] The command APC includes at least one of a first value HBPV indicating the horizontal trailing edge interval HBP of the horizontal synchronization signal Hsync relative to each frame rate and a second value VFPV indicating the vertical leading edge interval VFP of the vertical synchronization signal Vsync.

[0028] In the implementation, at least one of the first value HBPV and the second value VFPV for each frame rate can be stored or programmed in register 310. That is, the command APC includes at least one of the first value HBPV and the second value VFPV for the first frame rate or at least one of the first value HBPV and the second value VFPV for the second frame rate.

[0029] In this implementation, the first value HBPV and the second value VFPV can be set differently depending on the frame rate. For example, the second value VFPV at a first frame rate (e.g., 60 Hz) can be set to a second value VFPV greater than that at a second frame rate (e.g., 120 Hz).

[0030] The driver IC 300 for controlling the operation of the display device 400 includes a register 310, a control circuit 320, a timing controller 330, and a data drive circuit 340.

[0031] The control circuit 320 determines the toggle timing and toggle stop timing of the first clock signal CLK1 in response to the control signal. The control circuit 320 can output the first clock signal CLK1 as the second clock signal CLK2 by stopping or resuming the toggle of the first clock signal CLK1.

[0032] The control circuit 320 generates a gating control signal based on at least one of the following: a horizontal synchronization signal, a first value HBPV indicating the horizontal trailing edge interval HBP of the horizontal synchronization signal, a second value VFPV indicating the vertical leading edge interval VFP of the vertical synchronization signal, and a data enable signal. The control circuit 320 determines the toggle timing and toggle stop timing of the first clock signal CLK1 in response to the gating control signal.

[0033] The timing controller 330 controls the operation of the data driving circuit 340 and the gating driving circuit 440 according to the timing signal. Specifically, according to this disclosure, the timing controller 330 can send a signal for driving the display device 400 to the display device 400 through the data driving circuit 340 according to the second clock signal CLK2 provided from the control circuit 320, or send a signal to the gating driving circuit 440 according to the first clock signal CLK1.

[0034] In an embodiment, the timing controller 330 can generate a data timing control signal for controlling the operation of the data drive circuit 340 or a gating timing control signal for controlling the operation of the gating drive circuit 440 based on timing signals including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the clock signals CLK1 and CLK2, and the data enable signal DE.

[0035] The data timing clock signal may include the source start pulse (SSP), the source sampling clock (SSC), the source output enable signal, etc., and the gating timing control signal may include the gating start pulse (GSP), the gating shift clock (GSC), the gating output enable signal, etc.

[0036] The data driving circuit 340 provides data DATA input from the timing controller 330 to each pixel 410 of the display device 400 via the data line 420, based on the second clock signal CLK2 and the data timing clock signal.

[0037] although Figure 1 As not shown in the figure, the data drive circuit 340 may include components such as a digital processor, an analog processor, etc.

[0038] Display device 400 may be a flat panel display device capable of performing display functions and touch sensing functions. Examples of flat panel display devices include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0039] The display device 400 includes pixels 410, data lines 420, and gating lines 430, with each pixel 410 connected to one of the data lines 420 and one of the gating lines 430. The display device 400 may include a gating drive circuit 440. In this case, the display device 400 may be a touch-enabled display panel (also known as a "touchscreen panel"), and each pixel 410 may be a pixel including an OLED.

[0040] Data line 420 provides the pixel 410 with the data voltage applied from driver IC 300. Gating line 430 provides the pixel 410 with a gating signal provided from gating drive circuit 440.

[0041] Figure 2 It is a block diagram including the control circuitry and timing controller in the driver IC according to embodiments of the present disclosure, and Figure 3 It is a timing diagram used to describe the operation of a driver IC according to an embodiment of the present disclosure.

[0042] Reference Figure 2 The control circuit 320 for controlling the provision of the clock signal includes a control signal generator 322 and a clock gating circuit 324. Although Figure 2 For ease of description, the control circuit 320 is illustrated to include a data processing logic circuit 326, but the data processing logic circuit 326 may be located outside the control circuit 320.

[0043] The control signal generator 322 receives a first clock signal CLK1, a horizontal synchronization signal Hsync, a data enable signal DE, a first value HBPV indicating the horizontal trailing edge interval HBP of the horizontal synchronization signal Hsync, and a second value VFPV indicating the vertical leading edge interval VFP of the vertical synchronization signal Vsync.

[0044] In an implementation, the control signal generator 322 may additionally receive frame rate information FRR regarding the frame rate of the display device 400.

[0045] The control signal generator 322 generates a gating control signal CTRL that changes to a high or low level based on at least one of the horizontal synchronization signal Hsync, the data enable signal DE, the first value HBPV, and the second value VFPV.

[0046] In the implementation, when the rising edge of the horizontal synchronization signal Hsync is detected, the control signal generator 322 changes the gating control signal CTRL from high level to low level at a timing point after the horizontal trailing edge interval HBP corresponding to the first value HBPV from the rising edge.

[0047] In this configuration, the control signal generator 322 can change the gating control signal CTRL from high to low before the data enable signal DE changes from low to high. This is to prevent the first data from being unprocessed when the second clock signal CLK2 is resumed to toggle after the data enable signal DE goes high.

[0048] Subsequently, when the data enable signal DE is detected to change from high level to low level, the control signal generator 322 changes the gating control signal CTLR from low level to high level.

[0049] In this scenario, the control signal generator 322 can change the gating control signal CTRL from low to high after a certain period of time following the transition of the data enable signal DE from high to low (e.g., after the first clock signal CLK1 or the second clock signal CLK2 has toggled again for a certain period of time). This is to ensure sufficient data processing margin.

[0050] When the last data enable signal DE in a frame is detected, the control signal generator 322 can keep the gating control signal CTRL at a high level during the vertical leading edge interval VFP of the vertical synchronization signal after the last data enable signal DE changes from high to low (or after a certain time has elapsed after the last data enable signal DE changes from high to low).

[0051] In this scenario, to detect the last data enable signal DE among the data enable signals DE included in a frame, the control signal generator 322 may additionally receive a vertical synchronization signal Vsync, a third value VBPV indicating the vertical trailing edge interval VBP of the vertical synchronization signal Vsync, and a fourth value VACV indicating the vertical active interval V_active of the vertical synchronization signal Vsync. In this case, the control signal generator 322 may determine the time point after counting the sum of the third value VBPV and the fourth value VACV after detecting the rising edge of the vertical synchronization signal Vsync as the time point when the last data enable signal DE in the corresponding frame changes from high to low (i.e., the time point when the last data enable signal DE ends).

[0052] The clock gating circuit 324 includes a control terminal 324-1, a first input terminal 324-2, and a first output terminal 324-3. In response to the gating control signal CTRL input to the control terminal 324-1, the clock gating circuit 324 determines whether to stop or resume the toggling of the first clock signal CLK1 input to the first input terminal 324-2. The clock gating circuit 324 can output the first clock signal CLK1 as the second clock signal CLK2 through the first output terminal 324-3 by stopping or resuming the toggling of the first clock signal CLK1.

[0053] Specifically, when a high-level gating control signal is input to control terminal 324-1, clock gating circuit 324 determines to stop the toggling of the first clock signal CLK1 and outputs a second clock signal CLK2 that remains at a low level. When a low-level gating control signal is input to control terminal 324-1, clock gating circuit 324 determines to resume the toggling of the first clock signal CLK1 and outputs a second clock signal CLK2 that toggles between high and low levels.

[0054] The above reference will be described below through examples. Figure 3 The operation of the control signal generator 322 and the clock gating circuit 324 is described.

[0055] When the rising edge of the horizontal synchronization signal Hsync is detected at the first time point T1 or the fourth time point T4, the control signal generator 322 changes the gating control signal CTRL from high to low at a timing interval HBP, which is the horizontal trailing edge interval corresponding to the first value HBPV, starting from the rising edge. In this case, the first value can be set differently according to the first frame rate or the second frame rate.

[0056] In an implementation, when the rising edge of the horizontal synchronization signal Hsync is detected, the control signal generator 322 according to this disclosure can change the gating control signal CTRL from high to low after the time interval HBP corresponding to the first value HBPV and before the data enable signal DE changes from low to high.

[0057] For example, the control signal generator 322 counts the horizontal trailing edge interval HBP corresponding to the first value HBPV from the first time point T1 or the fourth time point T4, and when it is determined that the counting time is greater than the horizontal trailing edge interval HBP, it changes the gating control signal CTRL from high level to low level before the data enable signal DE changes from low level to high level.

[0058] The clock gating circuit 324 responds to the low-level gating control signal CTRL by resuming the toggling of the first clock signal CLK1, and sends the second clock signal CLK2, which toggles between high and low levels, to the first output terminal 324-3. As the gating control signal CTRL goes low, the clock gating circuit 324 can output the toggling (toggling can also be called oscillation) second clock signal CLK2.

[0059] When the data enable signal DE is changed from high to low at time point T2 or time point T5, the control signal generator 322 changes the gating control signal CTRL from low to high.

[0060] like Figure 3 As shown, the control signal generator 322 changes the gating control signal CTRL from low to high after a certain period of time following the data enable signal DE changing from high to low (for example, after the first clock signal CLK1 or the second clock signal CLK2 has toggled again for a certain period of time). This is to ensure data processing margin.

[0061] The clock gating circuit 324 stops the toggle of the first clock signal CLK1 in response to a high-level gating control signal CTRL, so as to send the second clock signal CLK2, which is kept at a low level, to the first output terminal 324-3. Therefore, the second clock signal CLK2 output from the clock gating circuit 324 remains at a low level, thereby reducing the power consumption caused by the toggle of the second clock signal CLK2.

[0062] At the third time point T3 or the sixth time point T6, when it is determined that the data enable signal DE is the last data enable signal DE in the corresponding frame, the control signal generator 322 keeps the gating control signal CTRL at a high level for the vertical leading edge intervals VFP_1 and VFP_2 corresponding to the second value VFPV after the last data enable signal DE changes from high to low (or for a certain period of time after the last data enable signal DE changes from high to low). In this case, the second value VFPV can be set differently according to the first frame rate or the second frame rate.

[0063] Therefore, during the vertical leading edge intervals VFP_1 and VFP_2, a low-level second clock signal CLK2 is output through the first output terminal 324-3.

[0064] In this disclosure, the gate control signal is kept high during each of the vertical leading edge intervals VFP_1 and VFP_2 for the following reasons. Because the vertical leading edge intervals VFP_1 and VFP_2 are set to be longer than other time intervals during which the data enable signal DE of a frame is not output, the gate control signal CTRL can be prevented from going low again. This continuously stops the toggling of the second clock signal CLK2 by keeping the gate control signal high during the vertical leading edge intervals VFP_1 and VFP_2, thereby greatly reducing power consumption.

[0065] In this implementation, the control signal generator 322 can determine the time point after the sum of a third value VBPV (representing the vertical trailing edge interval VBP) and a fourth value VACV (representing the vertical active interval V_active) is counted after the rising edge of the vertical synchronization signal Vsync is detected as the time point when the last data enable signal DE in the corresponding frame ends. In this case, the third value VBPV and the fourth value VACV can be set differently according to either the first frame rate or the second frame rate.

[0066] Return to reference Figure 2 The data processing logic circuit 326 includes a second input terminal 326-2 for receiving data DATA and a clock input terminal 326-1 electrically connected to the first output terminal 324-3 of the clock gating circuit 324. The data processing logic circuit 326 processes the data DATA in response to the second clock signal CLK2 and sends the processed data to the timing controller 330.

[0067] Control circuit 320 includes a bypass line 328 electrically connected between the first input terminal 324-2 and the second pad PD2 of clock gating circuit 324. The bypass line 328 provides a continuously toggling first clock signal CLK1 to the in-panel strobe (GIP) controller 334 via the second pad PD2. Therefore, the first clock signal CLK1, which toggles continuously even during the vertical leading edge interval VFP of each frame, is output to the GIP controller 334.

[0068] The timing controller 330 includes a first pad PD1 electrically connected to the first output terminal 324-3 of the clock gating circuit 324 and a second pad PD2 electrically connected to the bypass line 328.

[0069] The timing controller 330 includes a source driver 332 and a GIP controller 334.

[0070] The source driver 332 responds to the second clock signal CLK2 input through the first pad PD1 and sends the data processed by the data processing logic circuit 326 to the display device 400 through the data driving circuit 340.

[0071] The source driver 332 does not directly drive the data lines 420 arranged on the display device 400, but instead sends the data DATA sent from the host system 200 to the data driver circuit 340 in response to (or synchronized with) the second clock signal CLK2. The data driver circuit 340 actually drives the data lines 420 arranged on the display device 400.

[0072] The existence of a second clock signal CLK2 provided to the data processing logic circuit 326 and the source driver 332 for a time interval during which the gate control signal does not flip can reduce the power consumption of each of the data processing logic circuit 326 and the source driver 332.

[0073] The GIP controller 334 includes a gating control circuit 336, which sends gating pulses to the display device 400 in response to a first clock signal CLK1 input via the second pad PD2. The gating control circuit 336 does not directly drive the gating lines 430 arranged on the display device 400, but instead sends gating pulses to the gating drive circuit 440 in response to (or synchronized with) the first clock signal CLK1. The gating drive circuit 440 actually drives the gating lines 430 arranged on the display device 400 in response to the gating pulses.

[0074] The GIP controller 334 may also include a light emission control circuit 338 that controls the emission of light from light-emitting elements included in the display device 400 in response to a first clock signal CLK1 input via the second pad PD2. For example, a gating control circuit 336 supplies current to each light-emitting element, and the light emission control circuit 338 controls the emission of light from each light-emitting element.

[0075] Although the above embodiment describes the GIP controller 334 operating according to the first clock signal CLK1, in another embodiment, the GIP controller 334 may operate according to the second clock signal CLK2.

[0076] In this case, since the GIP controller 334 is provided with a second clock signal CLK2 that does not flip for some time intervals according to the gating control signal, the power consumption of the GIP controller 334 and the gating drive circuit 440 can be additionally reduced.

[0077] In one implementation, the control circuit 320 can control the gating (e.g., stopping and resuming its toggling) of the first clock signal CLK1 during the vertical leading edge interval VFP of the vertical synchronization signal Vsync, regardless of the command APC sent from the host system 200 and indicating the frequency corresponding to the frame rate of the display device 400.

[0078] For example, such as Figure 3 As shown, when the display device 400 operates at a first frame rate (e.g., 60 Hz), the vertical leading edge interval VFP_2 of the vertical sync signal Vsync is set to be longer than the vertical leading edge interval VFP_1 when the display device 400 operates at a second frame rate (e.g., 120 Hz), and when the display device 400 operates at the second frame rate, the vertical leading edge interval VFP_1 of the vertical sync signal Vsync is set to be shorter. The control signal generator 322 generates a high-level gating control signal CTRL during the vertical leading edge intervals VFP_1 and VFP_2 of the vertical sync signal Vsync, regardless of the frame rate of the display device 400.

[0079] Therefore, the clock gating circuit 324 generates a second clock signal CLK2 that does not flip during the vertical leading edge intervals VFP_1 and VFP_2 of the vertical synchronization signal Vsync in response to the high-level gating control signal CTRL, thereby minimizing power consumption.

[0080] In another embodiment, the control circuit 320 may generate a high-level gating control signal CTRL during the vertical leading edge interval VFP_2 of the vertical synchronization signal Vsync only when a command APC indicating that the display device 400 is operated at the first frame rate is received, thereby generating a second clock signal CLK2 that does not flip during the vertical leading edge interval VFP_2.

[0081] According to another embodiment, when a command APC is received instructing the display device 400 to operate at a second frame rate, the control circuit 320 can output a second clock signal CLK2 or a first clock signal CLK1 that flips even during the vertical leading edge interval VFP_1 of the vertical synchronization signal Vsync.

[0082] In the above embodiment, a high-level gating control signal CTRL is generated during the vertical leading edge interval VFP_2 only when the command APC indicating that the display device 400 is operated at the first frame rate is received. This is because the vertical leading edge interval VFP_2 when the display device 400 is operated at the first frame rate is set to be longer than when the display device 400 is operated at the second frame rate. Therefore, the power consumption rate when the display device 400 is operated at the first frame rate can be greater than the power consumption rate when the display device 400 is operated at the second frame rate.

[0083] According to this disclosure, power consumption caused by flipping clock signals can be reduced by gating the clock signal during the vertical leading edge interval of each different frame rate.

[0084] Those skilled in the art should understand that this disclosure may be implemented in other specific forms without altering its technical concept and essential characteristics.

[0085] All the methods and processes disclosed herein can be implemented, at least in part, using one or more computer programs or components. These components can be provided as a set of computer instructions by any conventional computer-readable or machine-readable medium, including volatile and non-volatile memory such as random access memory (RAM), read-only memory (ROM), flash memory, magnetic disk or optical disk, optical storage, or other storage media. The instructions can be provided as software or firmware and can be implemented, wholly or partially, in hardware configurations such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or any other similar devices. The instructions can be configured to be executed by one or more processors or other hardware configurations, and when executed, allow the processors or other hardware configurations to perform all or part of the methods and processes disclosed herein.

[0086] Therefore, the above embodiments should be understood as exemplary rather than limiting in every respect. The scope of this disclosure will be defined by the appended claims rather than the detailed description above, and all variations and modifications derived from the meaning and scope of the claims and their equivalents should be understood to be included within the scope of this disclosure.

[0087] Cross-references to related applications

[0088] This application claims the benefit of Korean Patent Application No. 10-2020-0171949, filed on December 10, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. An integrated circuit for gating clock signals, the integrated circuit comprising: A control signal generator configured to change a gating control signal from a low level to a high level in sync with a data enable signal changing from a high level to a low level, or to change the gating control signal from a low level to a high level at a predetermined time after the data enable signal changes from a high level to a low level, and to change the gating control signal from a high level to a low level after a predetermined horizontal trailing edge interval from the rising edge of the horizontal synchronization signal and before the data enable signal changes from a low level to a high level; as well as A clock gating circuit is configured to, when a high-level gating control signal is input to a control terminal, stop the toggling of a first clock signal input through a first input terminal to output a second clock signal that remains at the low level through a first output terminal, and when a low-level gating control signal is input to the control terminal, resume the toggling of the first clock signal to output a second clock signal that toggles between the high and low levels through the first output terminal.

2. The integrated circuit according to claim 1, further comprising: A data processing logic circuit, the data processing logic circuit including a clock input terminal connected to the first output terminal of the clock gating circuit and a second input terminal for receiving data; A bypass line, which is connected to the first input of the clock gating circuit and configured to bypass the first clock signal; as well as A timing controller, the timing controller including a first pad connected to the first output terminal of the clock gating circuit and a second pad connected to the bypass line.

3. The integrated circuit according to claim 2, wherein, The timing controller includes: A source driver configured to send data processed by the data processing logic circuitry to a display device via a data driving circuitry in response to a second clock signal input through the first pad; and A gating control circuit is configured to send a gating pulse to the display device in response to a first clock signal input through the second pad.

4. An integrated circuit for gating clock signals, the integrated circuit comprising: A control signal generator configured to change a gating control signal from a low level to a high level in sync with a data enable signal changing from a high level to a low level, or to change the gating control signal from a low level to a high level at a predetermined time after the data enable signal changes from a high level to a low level, and to change the gating control signal from a high level to a low level after a predetermined horizontal trailing edge interval from the rising edge of the horizontal synchronization signal and before the data enable signal changes from a low level to a high level; as well as A clock gating circuit is configured to, when a high-level gating control signal is input to the control terminal, stop the toggling of a first clock signal input through a first input terminal to output a second clock signal that remains at a low level through a first output terminal, and when a low-level gating control signal is input to the control terminal, resume the toggling of the first clock signal to output a second clock signal that toggles between the high and low levels through the first output terminal. During a predetermined vertical leading edge interval from the falling edge of the last data enable signal in a frame, the control signal generator holds the gating control signal at the high level.

5. The integrated circuit according to claim 4, wherein, The control signal generator receives a first command or a second command from the host system, and generates the high-level gating control signal when it receives the first command from the host system. The first command instructs the display device to operate at a first frame rate, and the second command instructs the display device to operate at a second frame rate higher than the first frame rate.

6. The integrated circuit according to claim 5, wherein, The vertical leading edge interval is set differently depending on the first frame rate or the second frame rate.

7. A display system, the display system comprising: The display device is configured to operate at a first frame rate or a second frame rate higher than the first frame rate. as well as A driver integrated circuit (IC) configured to control the operation of the display device. The driver IC includes: A control signal generator configured to synchronously change a gating control signal from low to high in conjunction with a data enable signal changing from high to low, or to change the gating control signal from low to high at a predetermined time after the data enable signal changes from high to low, and to change the gating control signal from high to low after a predetermined horizontal trailing edge interval from the rising edge of the horizontal synchronization signal and before the data enable signal changes from low to high; and A clock gating circuit is configured to, when a high-level gating control signal is input to a control terminal, stop the toggling of a first clock signal input through a first input terminal to output a second clock signal that remains at the low level through a first output terminal, and when a low-level gating control signal is input to the control terminal, resume the toggling of the first clock signal to output a second clock signal that toggles between the high and low levels through the first output terminal.

8. The display system according to claim 7, wherein, During a predetermined vertical leading edge interval from the falling edge of the last data enable signal in a frame, the control signal generator holds the gating control signal at the high level.

9. The display system according to claim 8, wherein, The vertical leading edge interval is set differently depending on the first frame rate or the second frame rate.

10. The display system according to claim 7, wherein, The control signal generator receives a first command or a second command from the host system, and generates the high-level gating control signal when it receives the first command from the host system. The first command instructs the display device to operate at the first frame rate, and the second command instructs the display device to operate at the second frame rate.

11. The display system according to claim 7, wherein, The driver IC includes: A data processing logic circuit, the data processing logic circuit including a clock input terminal connected to the first output terminal of the clock gating circuit and a second input terminal for receiving data; A bypass line, which is connected to the first input of the clock gating circuit and configured to bypass the first clock signal; A source driver configured to send data processed by the data processing logic circuitry to the display device via a data driving circuitry in response to a second clock signal output from the first output of the clock gating circuitry; and A gating control circuit is configured to send a gating pulse to the display device in response to the first clock signal input via the bypass line.

12. A method of operating an integrated circuit for gating clock signals, the method comprising the following steps: The gating control signal is changed from the low level to the high level synchronously with the data enable signal changing from the high level to the low level, or the gating control signal is changed from the low level to the high level at a predetermined time after the data enable signal changes from the high level to the low level; In response to the high-level gating control signal, the toggling of the first clock signal input through the first input terminal is stopped, so as to output a second clock signal that remains at the low level to the first output terminal; The gating control signal is changed from the high level to the low level after a predetermined horizontal trailing edge interval from the rising edge of the horizontal synchronization signal and before the data enable signal changes from the low level to the high level; and In response to the low level of the gating control signal, the toggling of the first clock signal is restored to output the second clock signal, which toggles between the high level and the low level, to the first output terminal.

13. The operating method according to claim 12, wherein, In the step of changing the gating control signal from the low level to the high level, the gating control signal remains at the high level for a predetermined vertical leading edge interval from the falling edge of the last data enable signal in a frame.

14. The operating method according to claim 12, wherein, The step of changing the gating control signal from the low level to the high level includes: receiving a first command or a second command from the host system, wherein the first command instructs the display device to operate at a first frame rate, and the second command instructs the display device to operate at a second frame rate higher than the first frame rate. When the first command is received from the host system, the gating control signal changes from the low level to the high level.

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