Ultra-small page buffer

Abstract

This application relates to a subminiature page buffer. An apparatus includes a memory array and a sense amplifier (SA) coupled with the memory array and with an input / output (I / O) data line. The SA is to receive a data bit associated with a program operation over the I / O data line. A digital-to-analog converter (DAC) is coupled with the SA, the DAC to convert the data bit to an analog voltage value. An analog memory element is coupled with the DAC, the analog memory element to store the analog voltage value for a period of time until the data bit is programmed to the memory array.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to ultra-small page buffers of memory devices. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] Embodiments of this disclosure provide an apparatus comprising: a memory array; a sense amplifier (SA) coupled to the memory array and to an input / output (I / O) data line, wherein the SA receives data bits associated with a programming operation via the I / O data line; a digital-to-analog converter (DAC) coupled to the SA, the DAC converting the data bits into analog voltage values; and an analog memory element coupled to the DAC, the analog memory element storing the analog voltage values ​​for a period of time until the data bits are programmed into the memory array.

[0004] Another embodiment of this disclosure provides an apparatus comprising: a memory array; a sense amplifier (SA) coupled to the memory array and to an input / output (I / O) data line, wherein the SA retrieves a data bit from the memory array in response to a read operation; a digital-to-analog converter (DAC) coupled to the SA, the DAC converting the data bit into an analog voltage value; and an analog memory element coupled to the DAC, the analog memory element storing the analog voltage value for a period of time until the data bit is transmitted to the I / O data line.

[0005] Another embodiment of this disclosure provides a method comprising: operating a page buffer circuit, the page buffer circuit including a sense amplifier (SA) coupled to a memory array and input / output (I / O) data lines, a digital-to-analog converter (DAC) coupled to the SA, and an analog memory element coupled to the DAC, wherein operating the page buffer circuit includes: sensing data bits received via the I / O data lines by the SA; converting the data bits into analog voltage values ​​by the DAC; and storing the analog voltage values ​​in the analog memory element for a period of time until the data bits are programmed into the memory array. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of some embodiments thereof.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 3A According to some embodiments Figure 1-2 An instance of a page buffer circuit in a memory device.

[0010] Figure 3B According to some embodiments Figure 3A An example of a page buffer circuit is a sense amplifier (SA).

[0011] Figure 3C According to some embodiments Figure 3A Examples of page buffer circuits simulate memory elements and transistor logic.

[0012] Figure 4 According to some embodiments, the SA signal at the transistor logic is connected to... Figures 3A-3C A set of corresponding timing diagrams relating the clock signal and analog signal values ​​within the page buffer circuit.

[0013] Figure 5 This is an example refresh operation of the voltage level five (L5) value stored on the analog memory component, based on a timing diagram of one embodiment and a corresponding set of digital and analog values.

[0014] Figure 6 Based on timing diagrams of some embodiments and corresponding sets of digital and analog values, this illustrates instance analog-to-digital (A2D) conversions of values ​​stored in an analog memory component.

[0015] Figure 7A Based on the timing diagram of the embodiment and a corresponding set of digital and analog values, it is shown that... Figures 3A-3C The page buffer circuit performs the steps of the read operation.

[0016] Figure 7B The graph, according to an embodiment, shows different analog voltage read levels that the sense amplifier to be copied to the page buffer circuit sends out on the I / O data lines.

[0017] Figure 8A This is a flowchart of an example method of operating the page buffer circuit according to an embodiment.

[0018] Figure 8B This is a flowchart of another example method of the operation page buffer circuit according to the embodiment.

[0019] Figure 9 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0020] Embodiments of this disclosure relate to ultra-small page buffers for memory devices within a memory subsystem. The memory subsystem may be a memory device, a memory module, or a hybrid of both. The following description is in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0021] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device. (The following text is in conjunction with...) Figure 1 Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0022] Memory devices can consist of bits arranged in a two-dimensional grid and are also called memory arrays. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also called bit lines) and rows (hereinafter also called word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can contain a group of memory cells, a group of word lines, a word line, or an individual memory cell.

[0023] In some memory subsystems, it is common to receive a request to perform a memory access operation, such as a data programming operation from the host system to the memory array of the memory device, and then receive a request to perform another memory access operation, such as a read operation, on the same data from the host system. The memory device being programmed contains multiple page buffers (also known as page caches).

[0024] The data to be programmed is stored in the page buffer circuitry while simultaneously being written to the appropriate cell in the memory array. Furthermore, when using a multi-pass programming scheme, certain page types of a given memory cell can be programmed at different times. For example, a quad-level cell (QLC) memory cell can have a total of four logical pages: a lower logical page (LP), a higher logical page (UP), an extra logical page (XP), and a highest logical page (TP), with each logical page storing one bit of data. Depending on the programming scheme, LP can be programmed, for example, in one pass, and UP, XP, and TP can be programmed in a second pass. Other programming schemes are also possible. However, in this example, before programming UP, XP, and TP in the second pass, data from LP can first be read from the memory cell and stored in the page buffer circuitry of the memory device. In this way, the page buffer circuitry holds a certain amount of data to be programmed into the memory array or being read from the memory array.

[0025] In some memory devices, adding an additional memory plane requires adding eight pages, each 64 kilobytes (KB) in size. This necessitates a considerable amount of additional page buffer space to accommodate the extra memory plane. For example, each page buffer circuit in a memory device includes a sense amplifier, which incorporates latches, capacitors, other circuitry, memory elements, and a processor. The memory elements can be digital memory elements, such as dynamic random access memory (DRAM), static random access memory (SRAM), or similar memory elements for storing data bits. The page buffer circuit also includes input / output (I / O) sub-circuit with latches and column select circuitry. As the size of memory devices increases, this page buffer expands throughout the device, potentially becoming a barrier to manufacturing larger memory devices and components.

[0026] This disclosure addresses the aforementioned and other drawbacks by reducing the size of the page buffer circuitry, thereby freeing up space for additional memory cells, for example, in NAND-type or other types of memory arrays. One method of reducing the page buffer circuitry size is to reduce the number of digital memory elements (e.g., data registers) required to buffer data being written to or read from the memory array. In various embodiments, two or more (e.g., multiple) digital memory elements in the page buffer circuitry are replaced by a single analog memory element that can store multiple different analog voltage values ​​(or states) corresponding to multiple different digital values ​​or states, for example, multiple data bits. Furthermore, the page buffer circuitry is logically configured to distinguish data bits associated with voltage values ​​stored on the analog memory element, for example, when performing digital-to-analog and analog-to-digital conversions between data bits and voltage values ​​(or states).

[0027] In one embodiment, the analog memory element is a capacitor. In another embodiment, the analog memory element is a power unit or energy unit that stores energy at a level commensurate with the analog voltage value or state corresponding to the digital bits stored (or to be stored) in the memory array. The disclosed page buffer circuit may also include a digital-to-analog converter (DAC) for converting data bits into analog voltage values ​​to be temporarily stored in the analog memory element. Furthermore, the page buffer circuit may also include an analog-to-digital converter (ADC) for converting the analog voltage values ​​of the analog memory element into data bits to be stored in the memory array or read out via I / O data lines of the I / O sub-circuit. In some embodiments, the circuitry of the DAC and ADC has overlapping components, thus requiring less space compared to the digital memory element replaced by the analog memory element.

[0028] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, reducing page buffer circuitry, which reduces the page buffer of the memory device by 40-50% or more without incurring additional latency or performance degradation. This significantly reduces the overhead of page buffer circuitry, thereby allowing the memory array area to grow without increasing the additional overhead of page buffers. Other advantages will be apparent to those skilled in the art who manage thermally dependent operations within the memory subsystem discussed below.

[0029] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0030] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing means (e.g., a processor).

[0032] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intervening components), whether wired or wireless, including connections of, for example, electrical, optical, magnetic and similar types.

[0033] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0034] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further use NVM High Speed ​​(NVMe) interface access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on changes in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash memory-based memories, crosspoint non-volatile memories can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] While non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processing device comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 may not include a memory subsystem controller 115, and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, memory device 130 includes a local media controller 135 that incorporates a memory subsystem controller 115 for performing operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. In various embodiments, memory device 130 includes page buffer circuitry 138 to temporarily store (e.g., buffer) data before it is stored in or read from memory device 130. Enhancements to several saving areas of page buffer circuitry 138 (or similar type of page cache) will be discussed in more detail below.

[0045] Figure 2 The first device and the present memory subsystem (e.g., in the form of a present memory device 130 according to the embodiment) are... Figure 1A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0046] Memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 204 ( Figure 2 (not shown) can be programmed as one of at least two target data states.

[0047] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 204. Memory device 130 also includes input / output (I / O) control circuitry 212 for managing the input of commands, addresses, and data into and from memory device 130. Address register 214 communicates with I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch address signals before decoding. Command register 224 communicates with I / O control circuitry 212 and the control logic of local media controller 135 to latch incoming commands.

[0048] A controller (e.g., a local media controller 135 within memory device 130) responds to commands to control access to memory cell array 204 and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to address commands.

[0049] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data as instructed by the local media controller 135 to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 220 to the memory cell array 204; then new data can be latched from I / O control circuitry 212 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 212 to output to memory subsystem controller 115; then new data can be transferred from data register 220 to cache register 218. Cache register 218 and / or data register 220 may form a page buffer of memory device 130 (e.g., may form part of said page buffer). The page buffer may further include sensing devices ( Figure 2 (Not shown in the diagram) is used to sense the data status of the memory cells in the memory cell array 204, for example, by sensing the status of the data lines connected to the memory cells. The status register 222 can communicate with the I / O control circuitry system 212 and the local memory controller 135 to lock status information for output to the memory subsystem controller 115.

[0050] Memory device 130 receives control signals from local media controller 135 via control link 232 at memory subsystem controller 115. For example, control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP). Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. Memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 234, and outputs data to memory subsystem controller 115 via I / O bus 234.

[0051] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 234 at I / O control circuitry system 212, and then written to command register 224. Addresses can be received via the input / output (I / O) pins [7:0] of the I / O bus 234 at I / O control circuitry system 212, and then written to address register 214. Data can be received via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device at I / O control circuitry system 212, and then written to cache register 218. The data can then be written to data register 220 to program the array of memory cells 204.

[0052] In this embodiment, cache register 218 may be omitted, and data may be written directly to data register 220. Data may also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0053] Those skilled in the art will understand that additional circuitry and signals can be provided, and Figure 2 The memory device 130 has been simplified. It should be recognized that the reference... Figure 2 The functions of the various block components described may not necessarily be divided into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component.

[0054] In addition, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0055] Figure 3A yes Figure 1-2 An example of a page buffer circuit 338 in one of the memory devices 130, such as memory device 330, according to some embodiments. In various embodiments, memory device 330 includes memory array 302 and page buffer circuit 338. In some embodiments, page buffer circuit 338 is Figure 1 Page buffer circuit 128.

[0056] In these embodiments, page buffer circuitry 338 includes a sense amplifier (SA) 308 coupled to memory array 302, I / O sub-circuit 312 coupled to SA 308, one or more analog memory elements 322, and transistor logic 328. Page buffer circuitry 338 may further include an ADC 316 coupled between SA 308 and one or more analog memory elements 322, and a DAC 318 coupled between SA 308 and analog memory elements 322. Transistor logic 328 may also be coupled to ADC 316 and DAC 318.

[0057] In one embodiment, analog memory element 322 is a capacitor, such as a high-capacity capacitor. In different embodiments, the capacitor may be, for example, a discrete component attached to a printed circuit board (PCB), or an integrated component formed within the substrate of a chip or die beneath page buffer circuitry 338. In another embodiment, analog memory element 322 is a power unit or energy unit that stores energy at a level commensurate with the analog voltage value or state corresponding to the digital bits stored (or to be stored) in memory array 302.

[0058] The memory device 330 may further include an I / O data line 314 coupled to the I / O sub-circuit 312. In one embodiment, the I / O data line 314 is coupled to a local media controller (e.g., local media controller 135) to exchange data bits with the host system 120, for example, by performing programming and reading operations. Furthermore, in one embodiment, the I / O sub-circuit 312 is part of or integrated therein with the SA 308, for example... Figure 3B As shown.

[0059] In some embodiments, SA 308, for example, uses I / O sub-circuit 312 to receive data bits associated with a programming operation via I / O data line 314. DAC 318 converts the data bits into analog voltage values. Analog memory element 322 stores the analog voltage values ​​for a period of time until the data bits are programmed into memory array 302. In one embodiment, the data bits are data pages to be stored in memory array 302. For example, ADC 316 may convert the analog voltage values ​​into data bits after the said period of time so that SA 308 can subsequently program the data bits into memory array 302.

[0060] In some embodiments, SA 308 retrieves data bits from memory array 302 in response to a memory operation. DAC 318 converts the data bits into analog voltage values. Analog memory element 322 stores the analog voltage values ​​for a period of time, for example, using I / O sub-circuit 312, until the data bits are transmitted to I / O data line 314. In one embodiment, the data bits are data pages previously stored in memory array 302. For example, ADC 316 may convert the analog voltage values ​​into data bits after the said period of time so that SA 308 can transmit the data bits via I / O data line 314.

[0061] Figure 3B According to some embodiments Figure 3A An example of the page buffer circuit 338 is a sense amplifier (SA) 308. SA 308 senses low-power signals from bit lines representing data bits (1 or 0) stored in memory cells of memory array 302 and amplifies small voltage swings to a recognizable level so that the data can be correctly interpreted by logic outside the memory. SA 308 can further reverse this operation of data bits received via I / O data line 314 to program said data bits into memory cells of memory array 302.

[0062] In this embodiment, the I / O sub-circuit 312 can be integrated into the SA 308. For example, the I / O sub-circuit 312 may include a pair of gate-connected transistors (DL and DLN) coupled to the I / O data line 314 via a common sense line (CSL). The sources of these gate-connected transistors may be coupled to a latch 332 of the SA 308. The latch 332 senses and holds an incoming bit (e.g., a digital value) between two sense amplifier terminals (SAB and SA).

[0063] For example, latch 332 may be a set / reset or SR latch, or a bistable multivibrator capable of maintaining two states, such as one state being equivalent to zero ("0") and the other state being equivalent to one ("1"). Latch 332 may include, for example, a pair of mutually coupled transistors, Sa_R and Sa_S. In one embodiment, when the gate of Sa_S goes high, latch 332 outputs a high voltage to the digital data line 336 of SA 308. Conversely, when the gate of Sa_R goes high, latch 332 outputs a low voltage to the digital data line 336.

[0064] A reset transistor (RST1) coupled to the source of the mutual-coupled transistor can be selectively activated to discharge the voltage on digital data line 336. Unless otherwise stated, the transistors mentioned herein are n-type metal-oxide-semiconductor (NMOS) devices. SA 308 may further include a sense amplifier capacitor (C saEach corresponding data bit is stored on the sense amplifier capacitor when the bit is programmed into the memory array 302 or read from the memory 302 along the bit line (BL) coupled to the digital data line 336. Figure 3B The other transistors shown in SA 308 support bit-to-memory array 302 for holding, power delivery, and programming.

[0065] For example, the bit line capacitor transistor (BLC1) can be inserted into digital data lines 336 and C. sa Together with the second set of enable transistors 342, they can be used to transfer data bits from the digital data line 336 to be stored in C. sa Programming is performed on it. The first group of enable transistors 346 can operate together with the Tc_UNK transistor to move the bit from the C sa Transfer to the positioning line.

[0066] Figure 3C According to some embodiments Figure 3A Examples of analog memory element 322 and transistor logic 328 in page buffer circuit 338. For example, in one embodiment, analog memory element 322 is a first capacitor (C1) with a higher capacitance, such as between approximately 7 and 9 nanofarads (ff), for example 8 ff. In different embodiments, the first capacitor C1 may be, for example, a discrete component attached to a printed circuit board (PCB), or an integrated component formed within the substrate of an integrated circuit device (e.g., located below page buffer circuit 338).

[0067] ADC 316 and DAC 318 can be coupled to C1 via an analog DC (A_DC) line. Furthermore, a pre-charge transistor (PRE1) can be coupled to a voltage supply and a first capacitor, charging the first capacitor to an initial voltage level. Analog memory element 322 may further include a second capacitor (C2) coupled in parallel with the first capacitor (C1) and approximately 4 to 20 times smaller than the first capacitor. For example, in one embodiment, the second capacitor is between 0.5 and 2 W / w, such as 1 W / w.

[0068] In some embodiments, the page buffer circuit 338 includes transistor logic 328 coupled between a first capacitor (C1) and a second capacitor (C2). Transistor logic 328 selectively enables the second capacitor (C2) to consume charge from the first capacitor (C1) until the first capacitor stores an analog voltage value representing a digital bit sensed by the sense amplifier. This process will be discussed in more detail with reference to FIG3.

[0069] In one embodiment, transistor logic 328 includes a clock enable transistor (CLK1) and an SA enable transistor (SA). When these transistors are turned on, the charge on C1 is equal to that on C2, causing the voltage on C1 to drop by an amount of charge (Q_DC), such as the consumed charge. Transistor logic 328 may further include a discharge transistor (RST2) coupled to a second capacitor (C2) to discharge the charge consumed from the first capacitor.

[0070] In some embodiments, transistor logic 328 further includes a boost device 350 coupled to a first capacitor (C1) and designed to provide a voltage boost to the charge stored in C1. The boost device 350 may be a p-type MOS (PMOS) device, a diode, or a similar device capable of providing a certain amount of voltage charge to C1. When an analog voltage value is sent to SA 308 for correct interpretation by SA 308, the voltage charge provided by the boost device 350 can increase the analog voltage value stored in the first capacitor (C1) by a set amount depending on the voltage level (L0-L7). For example, boosting to C1 can compensate for the threshold voltage (Vth) of the main transistor of ADC316 (see...). Figure 6 For example, the voltage levels of L0-L7 can be understood as corresponding to one or more logic states of a memory cell.

[0071] Figure 4 According to some embodiments, the SA signal at the transistor logic is connected to... Figures 3A-3C A set of corresponding timing diagrams relating the clock signal and analog signal values ​​within the page buffer circuit. The top portion of the diagram shows how analog voltage values ​​(A_DC) at different voltage levels (L0 to L7) can be stored, for example, in a multi-level cell (MLC). As previously mentioned, in this example, this analog voltage value replaces three bits, and therefore three digital registers and the effective page buffer. In one embodiment, the charge amount (e.g., 1Q) is represented as 0.2V, which can be the charge that C2 can consume. Thus, for each of the eight analog voltage values ​​(A_DC_7 to A_DC_0) associated with the threshold voltage values ​​L0 to L7, the 2.2V supply voltage can be equal to the highest analog voltage value (A_DC_7), the next lowest voltage value (A_DC_6) is 2.0V, or 0.2V lower than the highest analog voltage value, and so on. The numerical values ​​(SA_7 to SA_0) listed below the analog voltage values ​​show the corresponding values ​​detected by SA 308 for the corresponding analog voltage values ​​stored in the first capacitor (C1).

[0072] For further reference Figure 4The waveforms at the bottom of the figure illustrate the different signal values ​​within SA 308 of the page buffer circuit 338 and transistor logic 328, including CLK1, RST2, PRE1, SA_R, and CSL as described earlier. In one embodiment, after data enters the CSL line, the PRE1 signal can precharge C1 to an initial voltage value (e.g., to 2.2V), and RST1 can pre-discharge latch 332. This puts the page buffer circuit 338 in its initial state set and ready for operation. The RST2 signal can then release C2 during a non-clock cycle (e.g., before CLK1 goes high) because C2 operates in charge increments (0.2V in this example) to release C1, although other charge increments are contemplated.

[0073] Figure 5 This diagram illustrates an example refresh operation of a voltage level five (L5) value stored on an analog memory component, based on a timing diagram and a corresponding set of digital and analog values ​​from one embodiment. The analog voltage value stored in a first capacitor (C1) can be refreshed every time interval (e.g., every 100 microseconds (μs)) to ensure that the capacitor charge does not decrease below a variance threshold that would cause the analog voltage value to now correspond to an incorrect digital value or state. In some embodiments, the refresh time interval can vary with temperature; for example, a refresh time interval closer to 30 μs at 130°F is compared to 100 μs at 90°F. These values ​​and time intervals can be adjusted to different values.

[0074] In one embodiment, a refresh operation is performed by converting the analog voltage value back to the digital value or state held in SA 308, then converting it back to the analog voltage value again, and then restoring it to the first capacitor C1. Although Figure 5 The refresh of the analog voltage value associated with L5 is shown, but transistor logic 228 can cause a refresh of each analog voltage value associated with the threshold voltage values ​​(L1-L7), thereby causing a refresh of the UP and XP of the memory cell.

[0075] Figure 6 This is a timing diagram based on some embodiments and a corresponding set of digital and analog values, illustrating an instance of analog-to-digital (A2D) conversion of values ​​stored in an analog memory component. From left to right, the analog voltage values ​​(A_DC) at time zero (Time_0) corresponding to voltage values ​​L0-L7 are shown first. As time progresses on the timing diagram, SA 308 can be reset by asserting the RST1 and SA_R signals, and then the analog voltage values ​​on C1 are continuously boosted to update the corresponding digital values ​​or states of the bits in SA 308. The timing diagram shows the boosted values ​​to a fifth threshold voltage value (L5) for multiple possible digital states.

[0076] For reference Figure 3CAs discussed, when an analog voltage value is sent to SA 308 for correct interpretation by SA 308, the voltage charge provided by boost device 350 can increase the analog voltage value stored in the first capacitor (C1) by a set amount depending on the voltage level (L0-L7). For example, boosting to C1 can compensate for the threshold voltage (Vth) of the main transistor of ADC 316, which in one embodiment may be 2.3V. Therefore, the boost value can be calculated by subtracting the specific voltage associated with the threshold voltage value (L5 in this example) at each boost step from 2.3V. Table 1 shows a set of example boost values ​​for Boost_1 and Boost_2 steps according to an embodiment. Other boost values ​​with different Vth and different designs are contemplated.

[0077] Level Boost_1 Boost_2 L7 0.2 0 L6 0.4 0.2 L5 0.6 0.4 L4 0.8 0.6 L3 1.0 0.8 L2 1.2 1.0 L1 1.4 1.2 L0 1.6 1.4

[0078] Table 1

[0079] Figure 7A Based on the timing diagram of the embodiment and a corresponding set of digital and analog values, it is shown that... Figures 3A-3C The page buffer circuit 338 performs the steps of the read operation. The set of values ​​illustrates the behavior of the A_DC and sense amplifier (SA) values ​​relative to possible logic states (e.g., L0 to L7). By way of examples, threshold voltage read levels (digital and analog values) are shown with respect to read level valleys (e.g., the boundary between logic states L0 and L1 (@R2), the boundary between logic states L3 and L4 (@R4), and the boundary between logic states L5 and L6 (@R6)). Figure 7A A set of logic states is illustrated. Depending on the logic state of the cell coupled to page buffer circuit 338, the data value "1" can be interpreted based on the A_DC value of Vcc, and the data value "0" can be interpreted based on the A_DC value of ground (GND). These values ​​can be swapped depending on whether SA_R or SA_S of latch 332 is asserted (see [reference]). Figure 3B SA 308 (in the text).

[0080] Figure 7A The timing diagram represents the possible logic states of the memory cells (e.g., L0 to L7) and includes tracking of precharge (PRE1) and discharge (RST2) signals associated with the reset (SA_R) and set (SA_S) signals of latch 332 of SA 308. When these signals are asserted as shown, the bits read from memory array 302 are converted into analog voltage values ​​(A_DC), which are stored in the first capacitor C1. The order of the analog voltage values ​​for the three read levels (R2, R4, R6) is illustrated by example only. The analog voltage values ​​can be stored sequentially in the first capacitor C1 for a period of time until the data bit is transmitted to I / O data line 314.

[0081] For example, Figure 7B The graph, according to an embodiment, illustrates different analog voltage read levels read from the memory array 302 and copied from the first capacitor (C1) to the sense amplifier (SA) 308 of the page buffer circuit 338 for transmission on the I / O data line 314. In this way, C1 functions to temporarily buffer digital bits (other than the analog voltage value) during read operations while waiting for the digital bits to be transferred, for example, to the local media controller 135 and / or the host system 120.

[0082] Figure 8A This is a flowchart of an example method 800A for operating a page buffer circuit according to an embodiment. The page buffer circuit may be... Figure 3A The page buffer circuit 338 includes a sense amplifier (SA) coupled to the memory array and input / output (I / O) data lines, a digital-to-analog converter (DAC) coupled to the SA, and an analog memory element coupled to the DAC.

[0083] In operation 810, the operation page buffer circuit includes sensed data bits. For example, operation 810 may include data bits received via the I / O data line sensed by SA. SA may be... Figures 3A-3C The SA 308, and bits can be received from the local media controller 135 or the host system 120 via I / O data line 314.

[0084] In Operation 820, the operation page buffer circuitry includes a digital-to-analog converter. For example, Operation 820 may include a DAC that converts data bits into analog voltage values. The DAC could be... Figure 3A and Figure 3B The DAC 318 in the middle.

[0085] In operation 830, the operation page buffer circuit includes storage of analog voltage values. For example, operation 830 may include storing analog voltage values ​​by analog memory elements for a period of time until data bits are programmed into the memory array. The analog memory elements may be references... Figures 3A-3C The analog memory element 322 is discussed, and the memory array can be a memory array 302.

[0086] In another embodiment, the page buffer circuit further includes an analog-to-digital converter (ADC) coupled between the analog memory element and the SA. Additionally, the operating page buffer circuit may further include converting the analog voltage value into data bits by the ADC, and programming the data bits into the memory array by the SA after the said time period.

[0087] Figure 8B This is a flowchart of another example method 800B of operating the page buffer circuit according to the embodiment. The page buffer circuit may be... Figure 3AThe page buffer circuit 338 includes a sense amplifier (SA) coupled to the memory array and input / output (I / O) data lines, a digital-to-analog converter (DAC) coupled to the SA, and an analog memory element coupled to the DAC.

[0088] In operation 850, the operation page buffer circuitry includes retrieving data bits. For example, operation 850 may include retrieving data bits from the memory array by the SA in response to a read operation. The SA may be... Figures 3A-3C The SA 308 and the memory array can be memory array 302.

[0089] In operation 860, the operation page buffer circuitry includes a digital-to-analog converter. For example, operation 860 may include a digital-to-analog converter (DAC) that converts data bits into analog voltage values. The DAC could be... Figure 3A and Figure 3B The DAC 318 in the middle.

[0090] In operation 870, the operation page buffer circuit includes storage of analog voltage values. For example, operation 870 could include storing analog voltage values ​​in an analog memory element for a period of time until data bits are transferred to the I / O data line. The analog memory element could be... Figures 3A-3C The analog memory element 322, and the I / O data line can be I / O data line 314.

[0091] In another embodiment, the page buffer circuit further includes an analog-to-digital converter (ADC) coupled between the analog memory element and the SA. Additionally, the operating page buffer circuit may further include the conversion of an analog voltage value into data bits by the ADC, and the transfer of the data bits to the I / O data line by the SA after the stated time period.

[0092] Figure 9 An example machine of computer system 900 is shown, wherein an instruction set can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 900 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110, or may be used to perform controller operations (e.g., execute an operating system to perform operations related to...). Figure 1 (Operation corresponding to the memory subsystem controller 115). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0093] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0094] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 910 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0095] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 902 is configured to execute instructions 928 for performing the operations and steps discussed herein. Computer system 900 may further include network interface device 912 for communication via network 920.

[0096] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium) on which one or more instruction sets 928 or software embodying any one or more methods or functions described herein are stored. The instructions 928 may also reside wholly or at least partially within main memory 904 and / or processing device 902 during execution of the computer system 900, which also constitute machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or main memory 904 may correspond to... Figure 1 The memory subsystem 110.

[0097] Although machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "computer-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0098] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, algorithms are conceived as self-consistent sequences of operations that produce desired results. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0099] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0100] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0101] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0102] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0103] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. An apparatus for memory operations, comprising: a memory array; a sense amplifier (SA) coupled with the memory array and with an input / output (I / O) data line, wherein the SA is to receive data bits associated with a program operation through the I / O data line; a digital-to-analog converter (DAC) coupled with the SA, the DAC to convert the data bits to an analog voltage value; an analog memory element coupled with the DAC, the analog memory element to store the analog voltage value for a time period; and an analog-to-digital converter (ADC) coupled between the analog memory element and the SA, wherein the ADC is to convert the analog voltage value to the data bits after the time period, and wherein the SA is to program the data bits to the memory array.

2. The apparatus of claim 1, wherein the data bits comprise a page of data to be stored in the memory array.

3. The apparatus of claim 1, wherein the analog memory element is a capacitor.

4. The apparatus of claim 3, wherein the apparatus is an integrated circuit device, and wherein the capacitor is located within a substrate of the integrated circuit device.

5. The apparatus of claim 3, wherein the capacitor is sized between 7 and 9 femto Farads.

6. The apparatus of claim 3, wherein the capacitor is a first capacitor, the apparatus further comprising: a pre-charge transistor coupled with a voltage supply and the first capacitor, the pre-charge transistor to charge the first capacitor to an initial voltage level; a second capacitor coupled in parallel with the first capacitor and 4 to 20 times smaller than the first capacitor; and transistor logic coupled between the first capacitor and the second capacitor, the transistor logic to selectively enable the second capacitor to drain charge from the first capacitor until the first capacitor stores the analog voltage value.

7. The apparatus of claim 6, wherein the transistor logic comprises a clock enable transistor and a SA enable transistor.

8. The apparatus of claim 6, wherein the transistor logic comprises a discharge transistor coupled with the second capacitor to cause the second capacitor to discharge charge drained from the first capacitor.

9. An apparatus for memory operations, comprising: a memory array; a sense amplifier (SA) coupled with the memory array and with an input / output (I / O) data line, wherein the SA is to retrieve data bits from the memory array in response to a read operation; a digital-to-analog converter (DAC) coupled with the SA, the DAC to convert the data bits to an analog voltage value; and an analog memory element coupled with the DAC, the analog memory element to store the analog voltage value for a time period until the data bits are transferred to the I / O data line.

10. The apparatus of claim 9, wherein the data bits comprise a page of data stored in the memory array. ​ ​ ​ ​ 11. The device of claim 9, further comprising an analog-to-digital converter (ADC) coupled between the analog memory element and the SA, wherein the ADC is to convert the analog voltage value to the data bit after the time period, and wherein the SA is to output the data bit via the I / O data line.

12. The device of claim 9, wherein the analog memory element is a capacitor.

13. The device of claim 12, wherein the device is an integrated circuit device, and wherein the capacitor is located within a substrate of the integrated circuit device.

14. The device of claim 12, wherein the capacitor is sized between 7 and 9 femtofarads.

15. The device of claim 12, wherein the capacitor is a first capacitor, the device further comprising: a pre-charge transistor coupled with a voltage supply and the first capacitor, the pre-charge transistor to charge the first capacitor to an initial voltage level; a second capacitor coupled in parallel with the first capacitor and 4 to 20 times smaller than the first capacitor; and transistor logic coupled between the first capacitor and the second capacitor, the transistor logic to selectively enable the second capacitor to consume charge from the first capacitor until the first capacitor stores the analog voltage value.

16. The device of claim 15, wherein the transistor logic comprises a clock enable transistor and a SA enable transistor.

17. The device of claim 15, wherein the transistor logic comprises a discharge transistor coupled with the second capacitor to cause the second capacitor to discharge charge consumed from the first capacitor.

18. A method for memory operations, comprising: operating a page buffer circuit, the page buffer circuit comprising a sense amplifier (SA) coupled with a memory array and an input / output (I / O) data line, a digital-to-analog converter (DAC) coupled with the SA, an analog memory element coupled with the DAC, and an analog-to-digital converter (ADC) coupled between the analog memory element and the SA, wherein operating the page buffer circuit comprises: sensing, by the SA, a data bit received through the I / O data line; converting, by the DAC, the data bit to an analog voltage value; storing the analog voltage value in the analog memory element for a time period; converting, by the ADC, the analog voltage value to the data bit; and programming, by the SA, the data bit to the memory array after the time period. ​ ​

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