Semiconductor memory device

Abstract

A semiconductor memory device is disclosed. The semiconductor memory device includes: a substrate including a cell region and a peripheral region defined around the cell region, the cell region including an active region defined by an element separation film; a storage pad connected to the active region of the cell region; a peripheral gate structure disposed on the substrate of the peripheral region; peripheral contact plugs disposed on both sides of the peripheral gate structure and connected to the substrate; a first interlayer insulating film disposed on the storage pad and the peripheral contact plugs, and comprising a nitride-based insulating material; and an information storage cell connected to the storage pad, wherein the thickness of the first interlayer insulating film located on the upper surface of the storage pad is less than the thickness of the first interlayer insulating film located on the upper surface of the peripheral contact plugs.

Description

Technical Field

[0001] Some example embodiments relate to a semiconductor memory device and / or a method for manufacturing a semiconductor memory device, and more specifically, to a semiconductor memory device having multiple intersecting wirings and buried contacts and / or a method for manufacturing the semiconductor memory device. Background Technology

[0002] As semiconductor devices become increasingly integrated, circuit patterns become more refined to accommodate more semiconductor devices within the same area. For example, as the integration density of semiconductor devices increases, the design rules for semiconductor device components decrease and / or become more complex.

[0003] In highly scaled semiconductor devices, the process of forming multiple wirings and multiple buried contacts (BCs) placed between the wirings becomes increasingly complex and / or difficult. Summary of the Invention

[0004] Some example embodiments provide semiconductor memory devices that can improve reliability and performance.

[0005] Optionally or additionally, some example embodiments also provide a method for manufacturing a semiconductor memory device that can improve reliability and performance.

[0006] However, some aspects of the exemplary embodiments are not limited to those set forth herein. Some aspects and others of the exemplary embodiments will become more apparent to those skilled in the art upon which the exemplary embodiments pertain, by referring to the detailed description of the exemplary embodiments given below.

[0007] According to some example embodiments, a semiconductor device is provided, the semiconductor device comprising: a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including an active region defined by an element separation film; a storage pad connected to the active region of the cell region; a peripheral gate structure located on the substrate of the peripheral region; peripheral contact plugs located on both sides of the peripheral gate structure and connected to the substrate; a first interlayer insulating film located on the storage pad and on the peripheral contact plugs, and comprising a nitride-based insulating material; and information storage circuitry connected to the storage pad. The thickness of the first interlayer insulating film located on the upper surface of the storage pad is less than the thickness of the first interlayer insulating film located on the upper surface of the peripheral contact plugs.

[0008] According to some example embodiments, a semiconductor device is provided, the semiconductor device comprising: a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including an active region defined by a device separation film; a cell separation film defining the cell region in the substrate; a storage pad connected to the active region of the cell region; a peripheral gate structure located on the substrate of the peripheral region; peripheral contact plugs located on both sides of the peripheral gate structure and connected to the substrate, the upper surface of the peripheral contact plugs being coplanar with the upper surface of the storage pad; a first interlayer insulating film located on the storage pad and on the peripheral contact plugs, and comprising a nitride-based insulating material; and a capacitor including a lower electrode connected to the storage pad, a capacitor dielectric film located on the lower electrode, and an on-plate electrode located on the capacitor dielectric film. The upper surface of the first interlayer insulating film includes a stepped structure on the cell separation film.

[0009] According to some example embodiments, a semiconductor device is provided, the semiconductor device comprising: a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including an active region defined by an element separation film; a cell separation film defining the cell region of the substrate; a bit line structure including cell conductors and a cell line capping film located on the cell conductors, the bit line structure being located on the substrate of the cell region; a cell gate electrode disposed within the substrate of the cell region and intersecting the cell conductors; a storage pad located on a side surface of the bit line structure and connected to the active region of the cell region; a peripheral gate structure located on the substrate of the peripheral region; peripheral contact plugs located on both sides of the peripheral gate structure and connected to the substrate; a capacitor including a lower electrode connected to the storage pad, a capacitor dielectric film located on the lower electrode, and an on-plate electrode located on the capacitor dielectric film; a lower interlayer insulating film located on the peripheral contact plug and comprising a nitride-based insulating material, the ends of the lower interlayer insulating film being covered by the on-plate electrode; and an upper interlayer insulating film located on the lower interlayer insulating film and covering the sidewalls of the on-plate electrode. The lower interlayer insulating film is not located on the upper surface of the storage pad.

[0010] According to some example embodiments, a method for manufacturing a semiconductor memory device is provided, the method comprising: providing a substrate including a cell region and a peripheral region surrounding the cell region; forming a cell gate electrode in the substrate of the cell region; forming a bit line structure including a cell conductor and a cell line capping film on the cell conductor, the bit line structure being located on the substrate of the cell region; forming a peripheral gate structure including a peripheral gate conductive film and a peripheral capping film on the peripheral gate conductive film, the peripheral gate structure being located on the substrate of the peripheral region; forming a memory pad on a side surface of the bit line structure; forming peripheral contact plugs on both sides of the peripheral gate structure, the peripheral contact plugs being formed simultaneously with the memory pad; forming a pre-lower interlayer insulating film covering the upper surface of the peripheral contact plugs and the upper surface of the memory pad; removing a portion of the pre-lower interlayer insulating film to form a lower interlayer insulating film exposing the upper surface of the memory pad, the lower interlayer insulating film covering the upper surface of the peripheral contact plugs; forming an etch stop film covering the cell region and the peripheral region, the etch stop film being located on the lower interlayer insulating film; and forming a lower electrode penetrating the etch stop film and connected to the memory pad. Attached Figure Description

[0011] The above and other aspects and features of some exemplary embodiments will become more apparent from a detailed description of some exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 These are schematic layout diagrams of semiconductor memory devices according to some example embodiments;

[0013] Figure 2 yes Figure 1 A schematic layout diagram of area R1;

[0014] Figure 3 yes Figure 1 A schematic layout diagram of area R2;

[0015] Figure 4A and Figure 4B It is along Figure 1 Example sectional view taken by line AA;

[0016] Figure 5 It is along Figure 3 A sectional view taken by line BB;

[0017] Figure 6 It is along Figure 3 A cross-sectional view taken by line CC;

[0018] Figure 7 and Figure 8 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0019] Figure 9These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0020] Figure 10 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0021] Figure 11 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0022] Figure 12 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0023] Figure 13 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0024] Figure 14 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0025] Figure 15 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0026] Figure 16 and Figure 17 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0027] Figure 18 These are diagrams used to explain semiconductor memory devices according to some example embodiments;

[0028] Figure 19 This is a layout diagram used to explain a semiconductor memory device according to some example embodiments;

[0029] Figure 20 This is a perspective view used to explain a semiconductor memory device according to some example embodiments;

[0030] Figure 21 It is along Figure 19 A cross-sectional view taken from lines DD and EE;

[0031] Figure 22 This is a layout diagram used to explain a semiconductor memory device according to some example embodiments;

[0032] Figure 23 These are perspective views used to explain semiconductor memory devices according to some example embodiments; and

[0033] Figures 24A to 27B This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor memory device according to some example embodiments. Detailed Implementation

[0034] Figure 1 This is a schematic layout diagram of a semiconductor memory device according to some example embodiments. Figure 2 yes Figure 1 A schematic layout diagram of area R1. Figure 3 yes Figure 1 A schematic layout diagram of area R2. Figure 4A and Figure 4B It is along Figure 1 Example sectional view taken by line AA. Figure 5 It is along Figure 3 The sectional view taken by line BB. Figure 6 It is along Figure 3 The sectional view taken by the CC line.

[0035] For reference Figure 4A and Figure 4B This may be an example cross-sectional view of the transistor forming region of the peripheral circuit / peripheral logic region (referred to herein as the peripheral region).

[0036] In the accompanying drawings relating to semiconductor memory devices according to some example embodiments, although DRAM (Dynamic Random Access Memory) is shown as an example, the example embodiments are not limited thereto.

[0037] Reference Figures 1 to 3 A semiconductor memory device according to some example embodiments may include a cell region 20, a cell region separation film 22, and a peripheral region 24.

[0038] The unit region separation membrane 22 can be formed along the periphery / boundary of the unit region 20. The unit region separation membrane 22 can separate the unit region 20 and the peripheral region 24. The peripheral region 24 can be defined around the unit region 20.

[0039] The cell region 20 may include multiple cell active regions ACT. The cell active regions ACT may be formed on a substrate ( Figure 4A The unit element separation membrane in (100) of the unit element ( Figure 5 and Figure 6 (105) is defined. As the design rules for semiconductor memory devices become less restrictive, the cell active region ACT can be arranged in the form of diagonal (or slanted) bars as shown. For example, the cell active region ACT can extend along a third direction D3. The third direction D3 can form an angle of approximately 70 degrees with the first direction D1; however, the example embodiment is not limited thereto.

[0040] Multiple gate electrodes may be disposed across the cell active region ACT along a first direction D1. The multiple gate electrodes may extend parallel to each other. The multiple gate electrodes may be, or correspond to, for example, multiple rows / multiple word lines WL. The word lines WL may be disposed at equal intervals. The width of the word lines WL, the pitch of the word lines WL, and / or the spacing between the word lines WL may be determined according to design rules.

[0041] Each active cell region ACT can be divided into three parts by two word lines WL extending along a first direction D1. The active cell region ACT may include a memory connection region and a bit line connection region. The bit line connection region may be located at the center of the active cell region ACT, and the memory connection region may be located at the ends of the active cell region ACT. Although the active cell region ACT is shown as a sloping bar, the example embodiment is not limited thereto. For example, the active cell region ACT may include or may have an extension (e.g., a wing) at the center of each active cell region ACT.

[0042] Multiple columns / multiple bit lines BL extending along a second direction D2 orthogonal to the word line WL can be set on the word line WL. Multiple bit lines BL can extend parallel to each other. Bit lines BL can be set at equal intervals. The width of the bit lines BL and / or the pitch of adjacent bit lines BL and / or the spacing between bit lines BL can be determined according to design rules.

[0043] The boundary bit line BL_IF may extend alongside the bit line BL along the second direction D2. At least a portion of the boundary bit line BL_IF may be configured to overlap with the cell region separation film 22 in the first direction D1. Unlike the illustrated configuration, the semiconductor memory device according to some example embodiments may not include the boundary bit line BL_IF. Furthermore, dummy bit lines (not shown) and / or dummy source regions (not shown) and / or dummy word lines (not shown) may exist within the cell region 20.

[0044] The peripheral gate PR_ST1 may extend along the second direction D2 next to the boundary bit line BL_IF. The peripheral gate PR_ST1 may be located at the boundary between the cell region separation film 22 and the peripheral region 24. Unlike the illustrated configuration, in a semiconductor memory device according to some example embodiments, the peripheral gate PR_ST1 may extend along the first direction D1. Furthermore, a semiconductor memory device according to some example embodiments may not include either or both of the boundary bit line BL_IF and the peripheral gate PR_ST1.

[0045] A semiconductor memory device according to some example embodiments may include various contact arrangements formed on a cell active region ACT. These various contact arrangements may include, for example, digital line contacts or direct contacts DC, buried contacts BC, and bonding pads LP.

[0046] Here, the direct contact DC can refer to the contact that electrically connects the active region ACT of the cell to the bit line BL. The buried contact BC can refer to the contact that connects the active region ACT of the cell to the lower electrode of the capacitor. Figure 5 and Figure 6 The contact element (191) is used. Given the arrangement, the contact area between the buried contact element BC and the active area ACT of the cell can be small. Therefore, a conductive bonding pad LP can be introduced to increase the contact area with the active area ACT of the cell and to increase the contact area with the lower electrode of the capacitor (…). Figure 5 and Figure 6 The contact area is 191). Contact resistance can be reduced by including conductive bonding pads LP.

[0047] The bonding pad LP can be disposed between the active area ACT of the cell and the buried contact BC, and can also be disposed between the buried contact BC and the lower electrode of the capacitor. Figure 5 and Figure 6 Between 191). In a semiconductor memory device according to some example embodiments, a bonding pad LP may be disposed between the buried contact BC and the lower electrode of the capacitor. By increasing the contact area through the introduction of the bonding pad LP, the contact resistance between the cell active region ACT and the lower electrode of the capacitor can be reduced, which can result in improved sensing margin and / or improved performance of the semiconductor device.

[0048] Direct contacts (DC) can be connected to the bit line connection area. Buried contacts (BC) can be connected to the storage connection area. When buried contacts (BC) are located at both ends of the cell active region (ACT), the bonding pad (LP) can be configured to partially overlap with the buried contacts (BC) to be adjacent to both ends of the cell active region (ACT). Optionally or additionally, the buried contacts (BC) can be formed as a separation membrane between the cell active region (ACT) and the cell element located between adjacent word lines (WL) and adjacent bit lines (BL). Figure 5 and Figure 6 105) stacked.

[0049] The word line WL can be formed as a buried structure within the substrate 100. The word line WL can span the active cell ACT and be positioned between the direct contact DC and the buried contact BC. As shown, two word lines WL can be configured to intersect a single active cell ACT. Since the active cell ACT extends along the third direction D3, the word line WL can have an angle of less than 90 degrees with the active cell ACT.

[0050] The direct contact DC and the buried contact BC can be arranged symmetrically. Therefore, the direct contact DC and the buried contact BC can be arranged in a straight line along the first direction D1 and the second direction D2 (e.g., they can be arranged collinearly). On the other hand, unlike the direct contact DC and the buried contact BC, the bonding pad LP can be arranged in a zigzag pattern along the second direction D2 of the bit line BL. Furthermore, the bonding pad LP can be arranged to overlap with the same side surface portion of each bit line BL along the first direction D1 of the word line WL. For example, each of the bonding pads LP of the first line overlaps with the left side surface of the corresponding bit line BL, and each of the bonding pads LP of the second line can overlap with the right side surface of the corresponding bit line BL.

[0051] Reference Figures 1 to 6 A semiconductor memory device according to some example embodiments may include a plurality of cell gate structures 110, a plurality of bit line structures 140ST, a plurality of memory pads 160, information storage cells 190, peripheral gate structures 240ST, and peripheral contact plugs 260.

[0052] Substrate 100 may include cell regions 20, cell region separation films 22, and peripheral regions 24. Substrate 100 may be or may include a single-crystal semiconductor substrate (such as a silicon substrate or SOI (silicon-on-insulator)). Alternatively, substrate 100 may include, but is not limited to, silicon-germanium, SGOI (silicon-germanium-on-insulator), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Substrate 100 may be doped, for example, lightly doped with boron; however, the exemplary embodiments are not limited thereto.

[0053] Multiple cell gate structures 110, multiple bit line structures 140ST, multiple storage pads 160, and information storage circuits / cells 190 can be disposed in cell region 20. Peripheral gate structures 240ST and peripheral contact plugs 260 can be disposed in peripheral region 24.

[0054] A unit element separation membrane 105 can be formed inside the substrate 100 of the unit region 20. The unit element separation membrane 105 can have an STI (shallow trench isolation) structure with excellent / sufficient element separation characteristics. The unit element separation membrane 105 can define the unit active region ACT within the unit region 20. The unit active region ACT defined by the unit element separation membrane 105 can be as follows: Figure 2 The diagram shows an island shape including a short axis and a long axis. The active cell region ACT can be in the form of a slant line with an angle of less than 90 degrees relative to the word line WL formed on the unit element separation membrane 105. Furthermore, the active cell region ACT can be in the form of a slant line with an angle of less than 90 degrees relative to the bit line BL formed on the unit element separation membrane 105.

[0055] The unit region separation membrane 22 can form a unit boundary separation membrane with an STI structure. The unit region 20 can be defined by the unit region separation membrane 22.

[0056] The unit element separation membrane 105 and the unit region separation membrane 22 may include, but are not limited to, at least one of, for example, silicon oxide membrane, silicon nitride membrane, and silicon oxynitride membrane. Although Figure 5 and Figure 6 The illustration shows that both the unit element separation film 105 and the unit region separation film 22 are formed as a single insulating film, but this is only for ease of explanation, and the example embodiment is not limited thereto. Depending on the width of the unit element separation film 105 and the width of the unit region separation film 22, both the unit element separation film 105 and the unit region separation film 22 can be formed as a single insulating film, or they can be formed as multiple insulating films. Furthermore, the depth of the unit region separation film 22 can be deeper than the depth of each of the unit element separation films 105; however, the example embodiment is not limited thereto.

[0057] although Figure 5 The upper surface of the unit element separation membrane 105, the upper surface of the substrate 100, and the upper surface of the unit region separation membrane 22 are shown to be disposed on the same plane, but this is only for ease of explanation and the example embodiment is not limited thereto.

[0058] A cell gate structure 110 may be formed in the substrate 100 and the cell element separation film 105. The cell gate structure 110 may be formed across the cell element separation film 105 and the cell active region ACT defined by the cell element separation film 105. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate cap pattern 113, and a cell gate cap conductive film 114 formed within the substrate 100 and the cell element separation film 105. Here, the cell gate electrode 112 may be or correspond to a word line WL. Unlike the illustrated configuration, the cell gate structure 110 may not include the cell gate cap conductive film 114.

[0059] The cell gate insulating film 111 can be used as the dielectric of the transistor corresponding to the cell. The cell gate insulating film 111 can extend along the sidewalls and bottom surface of the cell gate trench 115. The cell gate insulating film 111 can extend along at least a portion of the contour of the cell gate trench 115. The cell gate insulating film 111 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material can include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0060] The unit gate electrode 112 can be used as the gate of the transistor corresponding to the unit. The unit gate electrode 112 can be formed on the unit gate insulating film 111. The unit gate electrode 112 can fill a portion of the unit gate trench 115. The unit gate cap conductive film 114 can extend along the upper surface of the unit gate electrode 112.

[0061] The unit gate electrode 112 may include at least one of the following: metal, metal alloy, conductive metal nitride, conductive metal carbonitride, conductive metal carbide, metal silicide, doped semiconductor material (such as doped polysilicon), conductive metal oxynitride, and conductive metal oxide. The unit gate electrode 112 may include, but is not limited to, materials such as TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, and IrO. x RuO x At least one of the following combinations. The unit gate cap conductive film 114 may include, but is not limited to, for example, polysilicon or polysilicon-germanium.

[0062] A cell gate cap pattern 113 may be disposed on the cell gate electrode 112 and the cell gate cap conductive film 114. The cell gate cap pattern 113 may fill the remaining cell gate trench 115 after the cell gate electrode 112 and the cell gate cap conductive film 114 are formed. Although the cell gate insulating film 111 is shown extending along the sidewalls of the cell gate cap pattern 113, the exemplary embodiment is not limited thereto. The cell gate cap pattern 113 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof.

[0063] Although not shown, at least one impurity-doped region may be formed on at least one side of the cell gate structure 110. The impurity-doped region may include impurities such as at least one of arsenic and phosphorus; however, the example embodiment is not limited thereto. The impurity-doped region may be used as the source / drain region of a transistor.

[0064] Bit line structure 140ST may correspond to the drain (or source) of the transistor corresponding to the cell. Bit line structure 140ST may include cell conductor 140 and cell line capping film 144. Cell conductor 140 may be formed on substrate 100 on which cell gate structure 110 is formed and cell element separation film 105. Cell conductor 140 may intersect with cell element separation film 105 and cell active region ACT defined by cell element separation film 105. Cell conductor 140 may be formed to intersect with cell gate structure 110. Here, cell conductor 140 may correspond to bit line BL.

[0065] The unit conductor 140 may be or may include a multilayer film. The unit conductor 140 may include, for example, a first unit conductive film 141, a second unit conductive film 142, and a third unit conductive film 143. The first to third unit conductive films 141, 142, and 143 may be sequentially stacked on the substrate 100 and the unit element separation film 105. Although the unit conductor 140 is shown as a three-layer film, the example embodiment is not limited thereto, and more or fewer films may be included in the unit conductor 140.

[0066] The first to third conductive films 141, 142, and 143 may each comprise, for example, at least one of a doped semiconductor material (such as doped polysilicon), a conductive silicide compound, a conductive metal nitride, a metal, and a metal alloy. For example, the first conductive film 141 comprises a doped semiconductor material (such as doped polysilicon), the second conductive film 142 comprises at least one of a conductive silicide compound and a conductive metal nitride, and the third conductive film 143 may include, but is not limited to, at least one of a metal and a metal alloy.

[0067] Bit line contact 146 may be formed between cell conductor 140 and substrate 100. For example, cell conductor 140 may be formed on bit line contact 146. For example, bit line contact 146 may be formed at the point where cell conductor 140 intersects with the central portion of cell active region ACT having an island shape. Bit line contact 146 may be formed between bit line connection region of cell active region ACT and cell conductor 140.

[0068] Bit line contact 146 can electrically connect unit wire 140 and substrate 100. Here, bit line contact 146 can be or correspond to direct contact DC. Bit line contact 146 can include at least one of, for example, a doped semiconductor material (such as doped polysilicon), a conductive silicide compound, a conductive metal nitride, and a metal.

[0069] exist Figure 5In the region where it overlaps with the upper surface of the bit line contact 146, the unit conductor 140 may include a second unit conductive film 142 and a third unit conductive film 143. In the region where it does not overlap with the upper surface of the bit line contact 146, the unit conductor 140 may include a first unit conductive film to a third unit conductive film 141, 142 and 143.

[0070] although Figure 5 The bit line contact 146 is shown not disposed between the cell conductor 140 and the substrate 100 closest to the cell region separation membrane 22, but the example embodiment is not limited to this. Unlike the illustrated configuration, the bit line contact 146 may be disposed between the cell conductor 140 and the substrate 100 closest to the cell region separation membrane 22.

[0071] A cell line cover film 144 may be disposed on the cell conductor 140. The cell line cover film 144 may extend along the upper surface of the cell conductor 140 in a second direction D2. In this case, the cell line cover film 144 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride. In a semiconductor memory device according to some example embodiments, the cell line cover film 144 may include, for example, a silicon nitride film. Although the cell line cover film 144 is shown as a single film, the example embodiments are not limited thereto. As an example, unlike the illustrated construction, the cell line cover film 144 may have a double-film structure. As another example, the cell line cover film 144 may have a three-layer film structure. As yet another example, the cell line cover film 144 may have a quadruple or more film structure. Furthermore, the example embodiments are not limited to the above, and the above features are not necessarily mutually exclusive.

[0072] The unit insulating film 130 can be formed on the substrate 100 and the unit element separation film 105. More specifically, the unit insulating film 130 can be formed on the substrate 100 in which the bit line contact 146 and the storage contact 120 are not formed, and on the unit element separation film 105 and the unit region separation film 22. The unit insulating film 130 can be formed between the substrate 100 and the unit wire 140, and between the unit element separation film 105 and the unit wire 140.

[0073] Although the unit insulating film 130 may be or correspond to a single film, the unit insulating film 130 may be or include a multilayer film comprising a first unit insulating film 131 and a second unit insulating film 132 as shown. For example, the first unit insulating film 131 may include a silicon oxide film, and the second unit insulating film 132 may include a silicon nitride film, but is not limited thereto. Unlike the illustrated construction, the unit insulating film 130 may be, but is not limited to, a three-layer film comprising a silicon oxide film, a silicon nitride film, and a silicon oxide film. The unit insulating film 130 may be formed using an oxidation process and / or a deposition process; however, the example embodiment is not limited thereto.

[0074] The unit buffer membrane 101 can be disposed between the unit insulating membrane 130 and the unit region separation membrane 22. The unit buffer membrane 101 may include, but is not limited to, a silicon oxide membrane.

[0075] The unit line spacer 150 can be disposed on the sidewalls of the unit conductor 140 and the unit line cover film 144. In the portion of the unit conductor 140 where the bit line contact 146 is formed, the unit line spacer 150 can be formed on the substrate 100 and the unit element separation film 105. The unit line spacer 150 can be disposed on the sidewalls of the unit conductor 140, the unit line cover film 144, and the bit line contact 146.

[0076] However, in the remaining portions of the unit conductor 140 where the bit contact 146 is not formed, the unit line spacer 150 may be disposed on the unit insulating film 130. The unit line spacer 150 may be disposed on the sidewalls of the unit conductor 140 and the sidewalls of the unit line cover film 144.

[0077] Although the unit line spacer 150 may be or correspond to a single film, the unit line spacer 150 may be or may include multiple films comprising the first to fourth unit line spacers 151, 152, 153, and 154 as shown. For example, the first to fourth unit line spacers 151, 152, 153, and 154 may include, but are not limited to, silicon oxide films, silicon nitride films, silicon oxynitride (SiON) films, silicon carbonitride (SiOCN) films, air such as clean dry air (CDA), and combinations thereof.

[0078] For example, the second unit line spacer 152 may not be disposed on the unit insulating film 130, but may be disposed on the sidewall of the bit line contact 146. Figure 3 and Figure 5 In the middle, the bit line structure 140ST can extend along the second direction D2. The unit line spacer 150 can be disposed on the long sidewall extending along the second direction D2 in the sidewall of the bit line structure 140ST.

[0079] exist Figure 5 In this configuration, a dummy bit line structure 140ST_1 can be disposed on the cell region separation film 22. The dummy bit line structure 140ST_1 can have the same structure as the bit line structure 140ST, but may not be electrically active during operation of the semiconductor device. For example, the dummy bit line structure 140ST_1 may include cell conductors 140 and cell line capping films 144. Here, the cell conductors 140 of the dummy bit line structure 140ST_1 may correspond to the boundary bit line BL_IF.

[0080] A protective pattern / fence pattern 170 may be disposed on the substrate 100 and the cell element separation film 105. The fence pattern 170 may be formed to be stacked with the cell gate structure 110 and the cell element separation film 105 formed in the substrate 100. The fence pattern 170 may be disposed between bit line structures 140ST extending along the second direction D2. The fence pattern 170 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0081] Storage contacts 120 can be disposed between adjacent cell conductors 140 along a first direction D1. Storage contacts 120 can be disposed between adjacent fence patterns 170 along a second direction D2. Storage contacts 120 can be stacked with the substrate 100 and the cell element separation membrane 105 between adjacent cell conductors 140. Storage contacts 120 can be connected to the storage connection area of ​​the cell active region ACT. Here, storage contacts 120 can correspond to cell contacts / buried contacts BC.

[0082] The storage contact 120 may include at least one of, for example, a doped semiconductor material (such as doped polysilicon), a conductive silicide compound, a conductive metal nitride, and a metal.

[0083] Storage pad 160 may be formed on storage contact 120. Storage pad 160 may be electrically connected to storage contact 120. Storage pad 160 may be connected to the storage connection area of ​​the cell active area ACT. Here, storage pad 160 may correspond to bonding pad LP.

[0084] The storage pad 160 may be stacked on a portion of the upper surface of the bit line structure 140ST. The storage pad 160 may include at least one of, for example, a doped semiconductor material (such as doped polysilicon), a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

[0085] A pad separation insulating film 180 can be formed on the storage pad 160 and the bit line structure 140ST. For example, the pad separation insulating film 180 can be disposed on the cell line cover film 144. The pad separation insulating film 180 can define the storage pad 160 forming multiple isolation regions. The pad separation insulating film 180 may not cover the upper surface of the storage pad 160. The pad separation insulating film 180 can fill the pad separation recess 180R. The pad separation recess 180R can separate adjacent storage pads 160. For example, based on the upper surface of the substrate 100, the height of the upper surface 160US of the storage pad can be the same as the height of the upper surface of the pad separation insulating film 180.

[0086] The pad separation insulating film 180 includes an insulating material and can electrically separate the plurality of storage pads 160 from each other. For example, the pad separation insulating film 180 may include at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbonitride film, and a silicon carbonitride film.

[0087] A peripheral element separation membrane 26 may be formed in the substrate 100 of the peripheral region 24. The peripheral element separation membrane 26 may define a peripheral active region within the peripheral region 24. Although the upper surface of the peripheral element separation membrane 26 is shown as being disposed in the same plane as the upper surface of the substrate 100, the exemplary embodiment is not limited thereto. The peripheral element separation membrane 26 may include, but is not limited to, at least one of, for example, silicon oxide film, silicon nitride film, and silicon oxynitride film. The peripheral element separation membrane 26 may comprise the same or different material as the unit element separation membrane 105 and / or the unit region separation membrane 22, and may be formed simultaneously with or at different times than any one or both of the unit element separation membrane 105 and / or the unit region separation membrane 22.

[0088] The peripheral gate structure 240ST can be disposed on the substrate 100 of the peripheral region 24. The peripheral gate structure 240ST can be disposed on the peripheral active region defined by the peripheral element separation film 26.

[0089] The peripheral gate structure 240ST may include a peripheral gate insulating film 230, a peripheral gate conductive film 240, and a peripheral capping film 244 sequentially stacked on the substrate 100. The peripheral gate structure 240ST may include peripheral spacers 245 disposed on the sidewalls of the peripheral gate conductive film 240 and the sidewalls of the peripheral capping film 244.

[0090] The peripheral gate conductive film 240 may include a first to a third peripheral conductive film 241, 242, and 243 sequentially stacked on the peripheral gate insulating film 230. As an example, an additional conductive film may not be disposed between the peripheral gate conductive film 240 and the peripheral gate insulating film 230. As another example, unlike the illustrated configuration, an additional conductive film (such as a work function conductive film) may be disposed between the peripheral gate conductive film 240 and the peripheral gate insulating film 230.

[0091] Although the two peripheral gate structures 240ST are shown disposed between adjacent peripheral element separation films 26, this is for ease of explanation only, and the exemplary embodiment is not limited thereto. The peripheral gate structure 240ST may correspond to the gate of a peripheral transistor (such as a transistor used in row decoding, column decoding, and / or in a buffer, and / or in other logic functions performed in a semiconductor device). The peripheral gate structure 240ST may correspond to a planar CMOS transistor and may correspond to an N-type transistor gate or a P-type transistor gate; however, the exemplary embodiment is not limited thereto.

[0092] A barrier conductive structure 240ST_1 may be disposed between the cell region 20 and the peripheral region 24. Although a portion of the barrier conductive structure 240ST_1 is shown stacked with the cell region separation film 22, the example embodiment is not limited thereto. The barrier conductive structure 240ST_1 may be the conductive structure closest to the dummy bit line structure 140ST_1 in the first direction D1.

[0093] The barrier conductive structure 240ST_1 may include a barrier gate insulating film 230_1, a barrier wire 240_1, and a barrier capping film 244_1 sequentially stacked on the substrate 100. The barrier conductive structure 240ST_1 may include barrier spacers 245_1 disposed on the sidewalls of the barrier wire 240_1 and the sidewalls of the barrier capping film 244_1. Here, the barrier wire 240_1 may correspond to the boundary peripheral gate PR_ST1.

[0094] The blocking wire 240_1 may include a first_1 blocking conductive film to a first_3 blocking conductive film 241_1, 242_1 and 243_1 sequentially stacked on the blocking gate insulating film 230_1. The stacked film structure of the blocking wire 240_1 between the blocking gate insulating film 230_1 and the blocking cover film 244_1 may be the same as the stacked film structure of the peripheral gate conductive film 240; however, the example embodiment is not limited thereto.

[0095] The peripheral gate structure 240ST and the barrier conductive structure 240ST_1 can be formed at the same level. Here, the term "at the same level" means that both are formed by the same manufacturing process. The peripheral gate conductive film 240 and the barrier conductor 240_1 can have the same stacked structure as the stacked structure of the unit conductor 140.

[0096] The first peripheral conductive film 241 and the first_1 blocking conductive film 241_1 may contain the same material as the first unit conductive film 141. The second peripheral conductive film 242 and the first_2 blocking conductive film 242_1 may contain the same material as the second unit conductive film 142. The third peripheral conductive film 243 and the first_3 blocking conductive film 243_1 may contain the same material as the third unit conductive film 143. Any of the first peripheral conductive film 241 and the first_1 blocking conductive film 241_1, the second peripheral conductive film 242 and the first_2 blocking conductive film 242_1, and the third peripheral conductive film 243 and the first_3 blocking conductive film 243_1 may contain the same material as each other.

[0097] The peripheral gate insulating film 230 and the barrier gate insulating film 230_1 may comprise the same material and may be formed simultaneously; however, the example embodiment is not limited thereto. The peripheral gate insulating film 230 and the barrier gate insulating film 230_1 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide.

[0098] The peripheral spacer 245 and the barrier spacer 245_1 may comprise the same material and may be formed simultaneously; however, the exemplary embodiment is not limited thereto. The peripheral spacer 245 and the barrier spacer 245_1 may comprise at least one of, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon carbonitride, and combinations thereof. Although the peripheral spacer 245 and the barrier spacer 245_1 are shown as a single film, this is only for ease of explanation, and the exemplary embodiment is not limited thereto. The peripheral spacer 245 and the barrier spacer 245_1 may be multiple films.

[0099] The outer cover film 244 and the barrier cover film 244_1 may comprise the same material and may be formed simultaneously; however, the example embodiment is not limited thereto. The outer cover film 244 and the barrier cover film 244_1 may comprise at least one of, for example, silicon nitride, silicon oxynitride, and silicon oxide.

[0100] A down-etch stop film 250 may be disposed on the substrate 100. The down-etch stop film 250 may be formed along the contour of the peripheral gate structure 240ST and the contour of the blocking conductive structure 240ST_1. The down-etch stop film 250 may extend along the sidewall of the dummy bit line structure 140ST_1. The down-etch stop film 250 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

[0101] The lower peripheral interlayer insulating film 290 can be disposed on the lower etch stop film 250. The lower peripheral interlayer insulating film 290 can be disposed around the peripheral gate structure 240ST. The lower peripheral interlayer insulating film 290 can be disposed on the cell region separation film 22 between the dummy bit line structure 140ST_1 and the blocking conductive structure 240ST_1.

[0102] The lower peripheral interlayer insulating film 290 may include an oxide-based insulating material. The upper surface of the lower peripheral interlayer insulating film 290 may be disposed on the same plane as the lower etch stop film 250 extending along the upper surface of the peripheral gate structure 240ST.

[0103] The upper peripheral interlayer insulating film 291 can be disposed on the peripheral gate structure 240ST and the lower peripheral interlayer insulating film 290. The upper peripheral interlayer insulating film 291 can cover the peripheral gate structure 240ST and the lower peripheral interlayer insulating film 290. For example, based on the upper surface of the substrate 100, the height of the upper surface of the upper peripheral interlayer insulating film 291 can be the same as the height of the upper surface of the cell line cover film 144.

[0104] The upper peripheral interlayer insulating film 291 comprises a material different from that of the lower peripheral interlayer insulating film 290. The upper peripheral interlayer insulating film 291 may include, for example, a nitride-based insulating material, and may not include an oxide-based insulating material. For example, the upper peripheral interlayer insulating film 291 may include silicon nitride.

[0105] Peripheral contact plugs 260 can be disposed on both sides of the peripheral gate structure 240ST. Peripheral contact plugs 260 can penetrate the upper peripheral interlayer insulating film 291 and the lower peripheral interlayer insulating film 290 and extend to the substrate 100 of the peripheral region 24. Peripheral contact plugs 260 are connected to the substrate 100 of the peripheral region 24. Peripheral wiring 265 can be disposed on the upper peripheral interlayer insulating film 291. Peripheral contact plugs 260 and peripheral wiring 265 can be separated by wiring separation recesses 280R. The width of the wiring separation recesses 280R can be various.

[0106] The peripheral contact plug 260 and peripheral wiring 265 may comprise the same material as the storage pad 160 and may be formed simultaneously with each other. The peripheral contact plug 260 and peripheral wiring 265 may be formed at the same level as the storage pad 160.

[0107] The upper surface 260US of the peripheral contact plug can be disposed on the same plane as the upper surface 265US of the peripheral wiring. The upper surface 265US of the peripheral wiring can be disposed on the same plane as the upper surface 160US of the storage pad.

[0108] The first interlayer insulating film 295 can be disposed on the unit region 20 and the peripheral region 24. The first interlayer insulating film 295 can be disposed on the storage pad 160, the peripheral contact plug 260, and the peripheral wiring 265. The first interlayer insulating film 295 can be disposed on the upper peripheral interlayer insulating film 291.

[0109] For example, refer to Figure 5The first thickness t1 of the first interlayer insulating film 295 located on the upper surface 160US of the storage pad is less than / thinner than the second thickness t2 of the first interlayer insulating film 295 located on the upper surface 260US of the peripheral contact plug. The thickness of the first interlayer insulating film 295 located on the upper surface 260US of the peripheral contact plug can be the same as the thickness of the first interlayer insulating film 295 located on the upper surface 265US of the peripheral wiring.

[0110] The first interlayer insulating film 295 may include a first lower interlayer insulating film 296 and a first upper interlayer insulating film 297. For example, the first upper interlayer insulating film 297 may be an upper etch stop film.

[0111] In a semiconductor memory device according to some example embodiments, a first lower interlayer insulating film 296 may be disposed on the upper surface 260US of the peripheral contact plug and the upper surface 265US of the peripheral wiring. The first lower interlayer insulating film 296 is not disposed on the upper surface 160US of the storage pad.

[0112] A first upper interlayer insulating film 297 may be disposed on the upper surface 260US of the peripheral contact plug, the upper surface 265US of the peripheral wiring, and the upper surface 160US of the storage pad. A first lower interlayer insulating film 296 covers the upper surface 260US of the peripheral contact plug and the upper surface 265US of the peripheral wiring.

[0113] In a semiconductor memory device according to some example embodiments, the difference between a first thickness t1 and a second thickness t2 of a first interlayer insulating film 295 may be caused by or related to the thickness of a first lower interlayer insulating film 296.

[0114] The first lower interlayer insulating film 296 can fill the wiring separation recess 280R. In Figure 4A In the middle, the first lower interlayer insulating film 296 can completely fill the wiring separation recess 280R. In Figure 4B In this process, the air gap AG surrounded by the first lower interlayer insulating film 296 can be set inside the wiring separation recess 280R.

[0115] The upper surface 295US of the first interlayer insulating film may include a stepped structure 295US_ST. The first lower interlayer insulating film 296 includes a terminal 296EP. The stepped structure 295US_ST of the first interlayer insulating film 295 may be formed at the terminal 296EP of the first lower interlayer insulating film.

[0116] In a semiconductor memory device according to some example embodiments, the first lower interlayer insulating film 296 does not extend into the cell region 20. Optionally, the end 296EP of the first lower interlayer insulating film may be positioned on the cell region separation film 22. The first lower interlayer insulating film 296 includes the end 296EP of the first lower interlayer insulating film disposed on the cell region separation film 22. The end 296EP of the first lower interlayer insulating film may be disposed in a position that is vertically superimposed (in the fourth direction D4) on the upper surface of the cell region separation film 22. Hereinafter, the term "vertical direction" or "vertical" will be described as the fourth direction D4, which is perpendicular to the surface of the substrate 100.

[0117] The stepped structure 295US_ST of the first interlayer insulating film 295 can be formed on / defined by the unit region separation film 22.

[0118] As an example, each of the first lower interlayer insulating film 296 and the first upper interlayer insulating film 297 may each comprise a nitride-based insulating material. The first lower interlayer insulating film 296 and the first upper interlayer insulating film 297 may each comprise at least one of, for example, silicon nitride, silicon carbonitride, silicon carbonitride oxycarbonate, and silicon boron nitride (SiBN).

[0119] As another example, the first lower interlayer insulating film 296 may comprise a nitride-based insulating material. The first upper interlayer insulating film 297 may comprise, for example, silicon oxycarbide (SiOC).

[0120] By setting the second thickness t2 of the first interlayer insulating film 295 on the upper surface 260US of the peripheral contact plug to be greater than the first thickness t1 of the first interlayer insulating film 295 on the upper surface 160US of the storage pad, the first interlayer insulating film 295 can protect or help protect the lower peripheral interlayer insulating film 290 during the etching process included in the manufacturing process of the information storage unit 190, for example, protecting or helping to protect the lower peripheral interlayer insulating film 290 from incidental etching. During the etching process included in the manufacturing process of the information storage unit 190, the first interlayer insulating film 295 can prevent or reduce the possibility of defects caused by etching the lower peripheral interlayer insulating film 290 and / or the impact of defects caused by etching the lower peripheral interlayer insulating film 290.

[0121] Information storage circuit / unit 190 may be disposed on storage pad 160. Information storage unit 190 may be electrically connected to storage pad 160. A portion of information storage unit 190 may be disposed in first upper interlayer insulating film 297. Information storage unit 190 may include, but is not limited to, a capacitor. Information storage unit 190 includes a first lower electrode 191, a first capacitor dielectric film 192, and a first upper electrode 193. For example, the first upper electrode 193 may be a plate electrode in the form of a plate (or referred to as a "plate-shaped upper electrode" or "plate-like upper electrode").

[0122] Optionally or additionally, the information storage unit 190 may include a memristor and / or may include a hysteresis device and / or other nonlinear circuitry. Optionally or additionally, the information storage unit 190 may be a two-terminal circuit, a three-terminal circuit, or a device having more than three circuits. The information storage unit 190 may be able to store information based on its electrical and / or magnetic and / or physical properties.

[0123] A first lower electrode 191 may be disposed on the storage pad 160. The first lower electrode 191 is shown as having a cylindrical shape, but the exemplary embodiment is not limited thereto. The first lower electrode 191 may have a cylindrical shape. A first capacitor dielectric film 192 is formed on the first lower electrode 191. The first capacitor dielectric film 192 may be formed along the contour of the first lower electrode 191. A first upper electrode 193 may be formed on the first capacitor dielectric film 192. The first upper electrode 193 may enclose the outer wall of the first lower electrode 191.

[0124] In a semiconductor memory device according to some example embodiments, a first capacitor dielectric film 192 may include a first portion vertically stacked with a first upper electrode 193 and a second portion not vertically stacked with the first upper electrode 193. The second portion of the first capacitor dielectric film 192 is the portion not covered by the first upper electrode 193.

[0125] In a semiconductor memory device according to some example embodiments, a first upper electrode 193 may cover a portion of a first lower interlayer insulating film 296. The first upper electrode 193 may be vertically stacked with the first lower interlayer insulating film 296. The first lower interlayer insulating film 296 may include a first portion vertically stacked with the first upper electrode 193 and a second portion not vertically stacked with the first upper electrode 193.

[0126] The first upper electrode 193 may cover the end 296EP of the first lower interlayer insulating film. The stepped structure 295US_ST of the first interlayer insulating film 295 may be formed at a position vertically stacked with the first upper electrode 193. The first upper interlayer insulating film 297 extends between the first lower interlayer insulating film 296 and the first upper electrode 193.

[0127] The first lower electrode 191 and the first upper electrode 193 may include, but are not limited to, doped semiconductor materials (such as doped polycrystalline silicon), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (e.g., one or more of ruthenium, iridium, titanium, and tantalum), and conductive metal oxides (e.g., one or more of iridium oxide and niobium oxide). The first upper electrode 193 is shown as a single film, but is not limited thereto. The first upper electrode 193 may include multiple conductive films, and each conductive film may include a different conductive material from each other.

[0128] The first capacitor dielectric film 192 may include, but is not limited to, one of, for example, silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, and combinations thereof. In a semiconductor memory device according to some example embodiments, the first capacitor dielectric film 192 may have a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In a semiconductor memory device according to some example embodiments, the first capacitor dielectric film 192 may include a dielectric film containing hafnium (Hf). In a semiconductor memory device according to some example embodiments, the first capacitor dielectric film 192 may have a stacked film structure of a ferroelectric material film and a paraelectric material film.

[0129] Although the height of the first lower electrode 191 is shown as similar to the height from the upper surface of the substrate 100 to the upper surface 160 μs of the storage pad, this is only for ease of explanation, and the exemplary embodiment is not limited thereto. The edge of the first upper electrode 193 is shown as having an L-shape, but the exemplary embodiment is not limited thereto.

[0130] The second interlayer insulating film 292 can be disposed on the first interlayer insulating film 295. The second interlayer insulating film 292 covers the sidewall 193SW of the first upper electrode.

[0131] The first capacitor dielectric film 192 may extend along the boundary between the first interlayer insulating film 295 and the second interlayer insulating film 292. The first upper interlayer insulating film 297 extends between the first lower interlayer insulating film 296 and the second interlayer insulating film 292.

[0132] The second interlayer insulating film 292 may include, but is not limited to, an insulating material based on oxides. The second interlayer insulating film 292 may include a material with etch selectivity, for example, etched more slowly than the first upper interlayer insulating film 297.

[0133] Figure 7 and Figure 8 These are diagrams used to explain semiconductor memory devices according to some example embodiments. For ease of explanation, the description will primarily focus on usage. Figures 1 to 6 The points described are different.

[0134] Reference Figure 7 and Figure 8 In a semiconductor memory device according to some example embodiments, a first capacitor dielectric film 192 is disposed in a portion vertically stacked with a first upper electrode 193. The first capacitor dielectric film 192 is not disposed in a portion not vertically stacked with the first upper electrode 193.

[0135] The first capacitor dielectric film 192 does not include a portion protruding beyond the sidewall 193SW of the first upper electrode in the first direction D1. The first capacitor dielectric film 192 does not extend along the boundary between the first interlayer insulating film 295 and the second interlayer insulating film 292. The first capacitor dielectric film 192 is not disposed between the first interlayer insulating film 295 and the second interlayer insulating film 292.

[0136] The first capacitor dielectric film 192 is not formed on the upper surface 295US of the first interlayer insulating film that is not covered by the first upper electrode 193. The first interlayer insulating film 295 may contact the second interlayer insulating film 292 (e.g., in direct contact).

[0137] The first lower interlayer insulating film 296 may include a first portion 296_1 vertically stacked with the first upper electrode 193 and a second portion 296_2 not vertically stacked with the first upper electrode 193. The first capacitor dielectric film 192 is stacked with the first portion 296_1 of the first lower interlayer insulating film in the fourth direction D4. The first capacitor dielectric film 192 is not stacked with the second portion 296_2 of the first lower interlayer insulating film in the fourth direction D4.

[0138] The first capacitor dielectric film 192 does not extend along the upper surface 295US of the first interlayer insulating film covering the peripheral gate structure 240ST.

[0139] Figure 9 These are diagrams used to explain semiconductor memory devices according to some example embodiments. For ease of explanation, the description will primarily focus on usage. Figure 7 and Figure 8 The points described are different.

[0140] Reference Figure 9 In a semiconductor memory device according to some example embodiments, the thickness t31 of the first portion 296_1 of the first lower interlayer insulating film may be greater than or equal to the thickness t32 of the second portion 296_2 of the first lower interlayer insulating film.

[0141] Near the sidewall 193SW of the first upper electrode, the upper surface 295US of the first interlayer insulating film may have another stepped structure.

[0142] According to some example embodiments, the portion of the first lower interlayer insulating film 296 that is not vertically stacked with the first upper electrode 193 and the first upper interlayer insulating film 297 can be etched. In this case, the thickness t31 of the first portion 296_1 of the first lower interlayer insulating film can be greater than the thickness t32 of the second portion 296_2 of the first lower interlayer insulating film.

[0143] In this case, the first interlayer insulating film located on the upper surface 260US of the peripheral contact plug ( Figure 4A 295) includes a second portion 296_2 of the first lower interlayer insulating film. The second thickness t2 of the first interlayer insulating film located on the upper surface 260US of the peripheral contact plug can be the same as the thickness t32 of the second portion 296_2 of the first lower interlayer insulating film. Furthermore, in the portion vertically stacked with the first upper electrode 193, the sum of the thicknesses of the first lower interlayer insulating film 296 and the first upper interlayer insulating film 297 can be the sum of the thickness t31 of the first portion 296_1 of the first lower interlayer insulating film and the first thickness t1 of the first upper interlayer insulating film 297.

[0144] In some example embodiments, unlike the illustrated configuration, the first upper interlayer insulating film 297, which is not vertically stacked with the first upper electrode 193, may be etched. However, the first lower interlayer insulating film 296, which is not vertically stacked with the first upper electrode 193, may not be etched. In this case, the thickness t31 of the first portion 296_1 of the first lower interlayer insulating film may be the same as the thickness t32 of the second portion 296_2 of the first lower interlayer insulating film.

[0145] In this case, the first interlayer insulating film located on the upper surface 260US of the peripheral contact plug ( Figure 4A 295) includes a first lower interlayer insulating film 296. The second thickness t2 of the first interlayer insulating film located on the upper surface 260US of the peripheral contact plug may be the same as the thickness t32 of the second portion 296_2 of the first lower interlayer insulating film.

[0146] In some example embodiments, unlike the configuration shown, portions of the first upper interlayer insulating film 297 that are not vertically stacked with the first upper electrode 193 can be etched. In this case, the thickness t31 of the first portion 296_1 of the first lower interlayer insulating film can be the same as the thickness t32 of the second portion 296_2 of the first lower interlayer insulating film.

[0147] In this case, the first interlayer insulating film located on the upper surface 260US of the peripheral contact plug ( Figure 4A295) includes a portion of the first lower interlayer insulating film 296 and a first upper interlayer insulating film 297. The second thickness t2 of the first interlayer insulating film located on the upper surface 260US of the peripheral contact plug may be the sum of the thickness t32 of the second portion 296_2 of the first lower interlayer insulating film and the thickness of the remaining first upper interlayer insulating film 297.

[0148] Figure 10 These are diagrams used to explain semiconductor memory devices according to some example embodiments. For ease of explanation, the description will primarily focus on usage. Figure 1 and Figure 6 The points described are different.

[0149] Reference Figure 10 In a semiconductor memory device according to some example embodiments, the first upper electrode 193 is not vertically stacked with the first lower interlayer insulating film 296.

[0150] The first lower interlayer insulating film 296 does not include the portion that is vertically stacked with the first upper electrode 193.

[0151] The first upper electrode 193 does not cover the end 296EP of the first lower interlayer insulating film. The stepped structure 295US_ST of the first interlayer insulating film 295 can be formed at a position where it is not vertically stacked with the first upper electrode 193.

[0152] Unlike the illustrated configuration, the first upper electrode 193 may cover a portion of the first interlayer insulating film 295, but may not cover the first lower interlayer insulating film 296. In this case, the first upper electrode 193 does not cover the end 296EP of the first lower interlayer insulating film. Alternatively, the stepped structure 295US_ST of the first interlayer insulating film 295 may be formed at a position vertically stacked with the first upper electrode 193.

[0153] Figure 11 These are diagrams used to explain semiconductor memory devices according to some example embodiments. For ease of explanation, the description will primarily focus on usage. Figure 10 The points described are different.

[0154] Reference Figure 11 The semiconductor memory device according to some example embodiments may also include dielectric film spacers 192SP formed in a stepped structure 295US_ST of a first interlayer insulating film 295.

[0155] The dielectric film spacer 192SP comprises the same material as the first capacitor dielectric film 192. The dielectric film spacer 192SP can be formed while removing the portion of the first capacitor dielectric film 192 that is not vertically stacked with the first upper electrode 193.

[0156] Figure 12 These are diagrams used to explain semiconductor memory devices according to some example embodiments. Figure 13 These are diagrams used to explain semiconductor memory devices according to some example embodiments. Figure 14 These are diagrams used to explain semiconductor memory devices according to some example embodiments. Figure 15 These are diagrams used to explain semiconductor memory devices according to some example embodiments. For ease of explanation, the description will primarily focus on usage. Figures 1 to 6 The points described are different.

[0157] Reference Figures 12 to 14 In a semiconductor memory device according to some example embodiments, a first lower interlayer insulating film 296 may be formed to extend into the cell region 20.

[0158] A portion of the first lower interlayer insulating film 296 may be formed at a position overlapping with the cell region 20. A portion of the first lower interlayer insulating film 296 may be disposed on the cell region 20.

[0159] exist Figure 12 In this configuration, the first lower interlayer insulating film 296 does not extend to the storage pad 160 closest to the cell region separation film 22. The first lower interlayer insulating film 296 does not cover the upper surface 160US of the storage pad closest to the cell region separation film 22.

[0160] exist Figure 13 and Figure 14 In this configuration, the first lower interlayer insulating film 296 may extend to the storage pad 160 adjacent to the cell region separation film 22. The first lower interlayer insulating film 296 may cover at least a portion of the upper surface 160US of the storage pad adjacent to the cell region separation film 22.

[0161] exist Figure 13 In this configuration, the first lower electrode 191 can pass through the first lower interlayer insulating film 296 and the first upper interlayer insulating film 297, and is connected to the storage pad 160. Figure 14 In this configuration, the first lower electrode 191 does not penetrate the first lower interlayer insulating film 296. The first lower electrode 191 is not connected to the storage pad 160 closest to the cell region separation film 22.

[0162] exist Figure 13 and Figure 14 In this example, although the first lower interlayer insulating film 296 is shown as extending to the storage pad 160 adjacent to the cell region separation film 22, this is only for ease of explanation and the example embodiment is not limited thereto.

[0163] Reference Figure 15 In a semiconductor memory device according to some example embodiments, the first lower interlayer insulating film 296 does not extend to the cell region separation film 22.

[0164] The first lower interlayer insulating film 296 does not include the portion vertically stacked with the unit region separation film 22. The end 296EP of the first lower interlayer insulating film can be positioned on the peripheral region 24.

[0165] The first upper electrode 193 is not vertically stacked with the first lower interlayer insulating film 296.

[0166] Unlike the configuration shown, the first upper electrode 193 may be vertically stacked with the first lower interlayer insulating film 296. The first lower interlayer insulating film 296 may include a portion vertically stacked with the first upper electrode 193.

[0167] Figure 16 and Figure 17 These are diagrams used to explain semiconductor memory devices according to some example embodiments. Figure 18 These are diagrams used to explain semiconductor memory devices according to some example embodiments. For ease of explanation, the description will primarily focus on usage. Figures 1 to 6 The points described are different.

[0168] Reference Figure 16 and Figure 17 In a semiconductor memory device according to some example embodiments, the first lower interlayer insulating film 296 may include a plurality of insulating films 296a and 296b sequentially stacked on the substrate 100.

[0169] The first lower interlayer insulating film 296 may include a first_1 lower interlayer insulating film 296a and a first_2 lower interlayer insulating film 296b located on the first_1 lower interlayer insulating film 296a. In some example embodiments, the first_1 lower interlayer insulating film 296a may be independently used as an embedded interlayer insulating film.

[0170] The first lower interlayer insulating film 296a and the first lower interlayer insulating film 296b may be disposed on the upper surface 260US of the peripheral contact plug and the upper surface 265US of the peripheral wiring. The first lower interlayer insulating film 296a and the first lower interlayer insulating film 296b are not disposed on the upper surface 160US of the storage pad. The first lower interlayer insulating film 296a and the first lower interlayer insulating film 296b cover the upper surface 260US of the peripheral contact plug and the upper surface 265US of the peripheral wiring. The first lower interlayer insulating film 296a and the first lower interlayer insulating film 296b do not cover the upper surface 160US of the storage pad.

[0171] Although the first lower interlayer insulating film 296 is shown as comprising two insulating films, this is only for ease of explanation, and the example embodiment is not limited thereto.

[0172] Reference Figure 18In a semiconductor memory device according to some example embodiments, the portion of the wiring separation recess 280R is not filled with the first lower interlayer insulating film 296 and the first upper interlayer insulating film 297.

[0173] In the wiring separation recess 280R, the space not filled with the first lower interlayer insulating film 296 and the first upper interlayer insulating film 297 can be filled with the first capacitor dielectric film 192 and / or the second interlayer insulating film 292.

[0174] The exemplary embodiments are not limited to the exemplary embodiments described above. Furthermore, the exemplary embodiments described above are not necessarily mutually exclusive. For example, some exemplary embodiments may include some features described with reference to one accompanying drawing, and may also include other features described with reference to another accompanying drawing.

[0175] Figure 19 This is a layout diagram used to explain a semiconductor memory device according to some example embodiments. Figure 20 This is a perspective view used to explain a semiconductor memory device according to some example embodiments. Figure 21 It is along Figure 19 The sectional view taken from lines DD and EE.

[0176] For reference Figure 19 It can be Figure 1 An enlarged view of region R1 (cell region). Furthermore, in... Figure 19 In a semiconductor memory device applied to a cell region, a cross-section of the boundary portion of the cell region (e.g., Figure 3 BB is different Figure 5 The cross-section.

[0177] Reference Figures 19 to 21 A semiconductor memory device according to some example embodiments may include a substrate 100, a plurality of first conductive lines 420, a channel layer 430, a gate electrode 440, a gate insulating film 450, and a capacitor 480. A semiconductor memory device according to some example embodiments may be a memory device including a vertical channel transistor (VCT). A vertical channel transistor may refer to a structure in which the channel length of the channel layer 430 extends vertically from the substrate 100.

[0178] A lower insulating layer 412 may be disposed on a substrate 100. A plurality of first conductive lines 420 located on the lower insulating layer 412 may be spaced apart from each other in a first direction D1 and extend along a second direction D2. A plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 to fill the spaces between the plurality of first conductive lines 420. The plurality of first insulating patterns 422 may extend along the second direction D2. The upper surfaces of the plurality of first insulating patterns 422 may be disposed at the same level as the upper surfaces of the plurality of first conductive lines 420. The plurality of first conductive lines 420 may serve as / correspond to bit lines.

[0179] The plurality of first conductive lines 420 may include doped semiconductor materials (such as doped polysilicon), metals, conductive metal nitrides, conductive metal silicides, conductive metal oxides, or combinations thereof. For example, the plurality of first conductive lines 420 may be made of, but are not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x Or a combination thereof. The plurality of first conductive lines 420 may comprise a single layer or multiple layers of the aforementioned materials. In an example embodiment, the plurality of first conductive lines 420 may comprise graphene, carbon nanotubes, or a combination thereof.

[0180] The channel layer 430 can be arranged in a matrix form spaced apart in a first direction D1 and a second direction D2 on a plurality of first conductors 420. The channel layer 430 can have a first width along the first direction D1 and a first height along a fourth direction D4, and the first height can be greater than the first width. Here, the fourth direction D4 intersects the first direction D1 and the second direction D2, and can be, for example, a direction perpendicular to the upper surface of the substrate 100. For example, the first height can be, but is not limited to, about 2 to 10 times the first width. The bottom of the channel layer 430 serves as / corresponds to a third source / drain region (not shown), the upper part of the channel layer 430 serves as / corresponds to a fourth source / drain region (not shown), and the portion of the channel layer 430 between the third source / drain region and the fourth source / drain region can be used as a channel region (not shown).

[0181] In an example embodiment, the channel layer 430 may include an oxide semiconductor, and the oxide semiconductor may include, for example, In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn zO、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y O or a combination thereof. The channel layer 430 may comprise a single layer or multiple layers of oxide semiconductor. In some example embodiments, the channel layer 430 may have a band gap energy greater than that of silicon. For example, the channel layer 430 may have a band gap energy of about 1.5 eV to 5.6 eV. For example, the channel layer 430 may have optimal channel performance when it has a band gap energy of about 2.0 eV to 4.0 eV. For example, the channel layer 430 may be, but is not limited to, polycrystalline or amorphous. In example embodiments, the channel layer 430 may comprise graphene, carbon nanotubes, or a combination thereof.

[0182] Gate electrode 440 may extend along a first direction D1 on both sidewalls of channel layer 430. Gate electrode 440 has a first sub-gate electrode 440P1 facing a first sidewall of channel layer 430 and a second sub-gate electrode 440P2 facing a second sidewall opposite to the first sidewall of channel layer 430. Since a single channel layer 430 is disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor device may have a dual-gate transistor structure. However, the technical concept of some exemplary embodiments is not limited thereto. The second sub-gate electrode 440P2 is omitted, and only the first sub-gate electrode 440P1 facing the first sidewall of channel layer 430 may be formed to achieve a single-gate transistor structure. The material included in gate electrode 440 may be interpreted the same as that of unit gate electrode 112.

[0183] The gate insulating film 450 surrounds the sidewalls of the channel layer 430 and can be disposed between the channel layer 430 and the gate electrode 440. For example, as Figure 19As shown, the entire sidewall of the channel layer 430 may be surrounded by the gate insulating film 450, and a portion of the sidewall of the gate electrode 440 may contact the gate insulating film 450. In some example embodiments, the gate insulating film 450 extends along the extension direction of the gate electrode 440 (i.e., the first direction D1), and among the sidewalls of the channel layer 430, only the two sidewalls facing the gate electrode 440 may contact the gate insulating film 450. In example embodiments, the gate insulating film 450 may be composed of a silicon oxide film, a silicon oxynitride film, a high dielectric constant material having a higher dielectric constant than that of a silicon oxide film, or a combination thereof.

[0184] Multiple second insulating patterns 432 may extend along a second direction D2 on multiple first insulating patterns 422. A channel layer 430 may be disposed between two adjacent second insulating patterns 432. Furthermore, a first buried layer 434 and a second buried layer 436 may be disposed in the space between two adjacent channel layers 430 between two adjacent second insulating patterns 432. The first buried layer 434 may be disposed at the bottom of the space between two adjacent channel layers 430. The second buried layer 436 may be formed to fill the remaining space between two adjacent channel layers 430 located on the first buried layer 434. The upper surface of the second buried layer 436 is positioned at the same level as the upper surface of the channel layer 430, and the second buried layer 436 may cover the upper surface of the gate electrode 440. Conversely, the multiple second insulating patterns 432 may be formed by a material layer continuous with the multiple first insulating patterns 422, or the second buried layer 436 may also be formed by a material layer continuous with the first buried layer 434.

[0185] Capacitor contacts 460 may be disposed on the channel layer 430. The capacitor contacts 460 are arranged vertically stacked with respect to the channel layer 430, and may be in a matrix configuration spaced apart in a first direction D1 and a second direction D2. The capacitor contacts 460 may be made of, but are not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO. x RuO x Or a combination thereof. The upper insulating layer 462 may surround the sidewalls of the capacitor contact 460 on a plurality of second insulating patterns 432 and a second buried layer 436.

[0186] A unit etch stop film 470 can be disposed on the upper insulating layer 462. A capacitor 480 can be disposed on the unit etch stop film 470. The unit etch stop film 470 can correspond to Figure 6 The first upper interlayer insulating film 297.

[0187] The capacitor 480 may include a second lower electrode 482, a second capacitor dielectric film 484, and a second upper electrode 486. The second lower electrode 482 may penetrate the unit etch stop film 470 and be electrically connected to the upper surface of the capacitor contact 460. The second lower electrode 482 may be, but is not limited to, formed in a cylindrical shape extending along a fourth direction D4. In an example embodiment, the second lower electrode 482 is configured to be vertically stacked with the capacitor contact 460 and may be arranged in a matrix form spaced apart in a first direction D1 and a second direction D2. In contrast, a bonding pad (not shown) may be further disposed between the capacitor contact 460 and the second lower electrode 482, and the second lower electrode 482 may be arranged in a hexagonal shape.

[0188] Figure 22 This is a layout diagram used to explain a semiconductor memory device according to some example embodiments. Figure 23 This is a perspective view used to explain a semiconductor memory device according to some example embodiments.

[0189] Reference Figure 22 and Figure 23 A semiconductor memory device according to some example embodiments may include a substrate 100, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, and a capacitor 480. A semiconductor memory device according to some example embodiments may be a memory device including a vertical channel transistor (VCT).

[0190] Multiple active regions AC can be defined on the substrate 100 by a first element separation pattern 412A and a second element separation pattern 414A. A channel structure 430A can be disposed inside each active region AC. The channel structure 430A may include a first active post 430A1 and a second active post 430A2 that extend vertically, and a connector 430L connected to the bottom of the first active post 430A1 and the bottom of the second active post 430A2, respectively. A first source / drain region SD1 can be disposed inside the connector 430L. A second source / drain region SD2 can be disposed above the first active post 430A1 and the second active post 430A2. The first active post 430A1 and the second active post 430A2 can each form an independent unit memory cell.

[0191] Multiple first conductors 420A may extend in a direction intersecting each of the multiple active regions AC, for example, along a second direction D2. One of the multiple first conductors 420A may be disposed on a connector 430L between a first active post 430A1 and a second active post 430A2. One first conductor 420A may be disposed on a first source / drain region SD1. Another first conductor 420A adjacent to one first conductor 420A may be disposed between two channel structures 430A. One of the multiple first conductors 420A may serve as a common bit line included in two unit memory cells formed by the first active post 430A1 and the second active post 430A2 disposed on both sides of the first conductor 420A.

[0192] A contact gate electrode 440A may be disposed between two adjacent channel structures 430A along the second direction D2. For example, the contact gate electrode 440A may be disposed between a first active post 430A1 included in a channel structure 430A and a second active post 430A2 of a channel structure 430A adjacent to the first active post 430A1. A contact gate electrode 440A may be shared by the first active post 430A1 and the second active post 430A2 disposed on two sidewalls of the contact gate electrode 440A. A gate insulating film 450A may be disposed between the contact gate electrode 440A and the first active post 430A1, and between the contact gate electrode 440A and the second active post 430A2. A plurality of second conductors 442A may extend along the first direction D1 on the upper surface of the contact gate electrode 440A. The plurality of second conductors 442A may serve as word lines of a semiconductor device.

[0193] Capacitor contact 460A can be disposed on channel structure 430A. Capacitor contact 460A can be disposed on second source / drain region SD2, and capacitor 480 can be disposed on capacitor contact 460A.

[0194] Figures 24A to 27B This is a diagram illustrating intermediate stages of a method for manufacturing / manufacturing a semiconductor memory device according to some example embodiments. In the description of the manufacturing method, the use of [specific terms / phrases] will be briefly explained or omitted. Figures 1 to 18 The explanation is a repetition of the content.

[0195] Reference Figures 1 to 3 , Figure 24A and Figure 24B A substrate 100 is provided, comprising a unit region 20, a peripheral region 24, and a unit region separation membrane 22.

[0196] A cell gate structure 110 can be formed inside the substrate 100 of the cell region 20. The cell gate structure 110 can extend along a first direction D1. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate cap pattern 113, and a cell gate cap conductive film 114.

[0197] Subsequently, a unit insulating film 130 can be formed on the unit region 20. The unit insulating film 130 can expose the substrate 100 of the peripheral region 24. The unit insulating film 130 can be formed using an oxidation process and / or a deposition process such as chemical vapor deposition.

[0198] Subsequently, a bitline structure 140ST can be formed on the substrate 100 of the cell region 20. The bitline structure 140ST may include cell conductors 140 and cell line capping films 144. The cell conductors 140 can be formed using CVD and / or physical vapor deposition (PVD) processes. The cell line capping films 144 can be formed using CVD processes.

[0199] A peripheral gate structure 240ST can be formed on the substrate 100 of the peripheral region 24. The peripheral gate structure 240ST may include a peripheral gate insulating film 230, a peripheral gate conductive film 240, a peripheral capping film 244, and a peripheral spacer 245. The peripheral gate structure 240ST can be formed using one or more oxidation processes, one or more CVD processes, and / or one or more PVD processes.

[0200] Subsequently, a storage pad 160 can be formed on the side surface of the bit line structure 140ST. The storage pad 160 can be separated by a pad separation recess 180R. Furthermore, peripheral contact plugs 260 can be formed on both sides of the peripheral gate structure 240ST. Peripheral wiring 265 can be formed on the peripheral gate structure 240ST. The peripheral contact plugs 260 and the peripheral wiring 265 can be separated by a wiring separation recess 280R. One or more of oxidation processes, one or more of CVD processes, and / or one or more of PVD processes may be present.

[0201] For example, storage pad 160, peripheral contact plug 260 and peripheral wiring 265 can be formed simultaneously.

[0202] Reference Figure 25A and Figure 25B A pre-layer insulating film 296p can be formed on the storage pad 160, the peripheral contact plug 260 and the peripheral wiring 265.

[0203] The pre-applied interlayer insulating film 296p covers the upper surface 260µs of the peripheral contact plug, the upper surface 265µs of the peripheral wiring, and the upper surface 160µs of the storage pad. The pre-applied interlayer insulating film 296p can fill the pad separation recess 180µs and the wiring separation recess 280µs.

[0204] Reference Figure 26A and Figure 26B By removing a portion of the pre-lower interlayer insulating film 296p, a first lower interlayer insulating film 296 can be formed to expose the upper surface 160µs of the storage pad.

[0205] The first lower interlayer insulating film 296 can cover the upper surface 260US of the peripheral contact plug and the upper surface 265US of the peripheral wiring.

[0206] While forming the first lower interlayer insulating film 296, a pad separation insulating film 180 is formed in the pad separation recess 180R.

[0207] Subsequently, a first upper interlayer insulating film 297 is formed on the first lower interlayer insulating film 296, covering the unit region 20, the peripheral region 24, and the unit region separation film 22. As a result, a first interlayer insulating film 295 is formed.

[0208] The first upper interlayer insulating film 297 may be an upper etch stop film. The first upper interlayer insulating film 297 covers the upper surface 160 μs of the storage pad exposed by the first lower interlayer insulating film 296.

[0209] Reference Figure 27A and Figure 27B A first lower electrode 191 can be formed that penetrates the first upper interlayer insulating film 297. The first lower electrode 191 is connected to the storage pad 160.

[0210] Subsequently, a first capacitor dielectric film 192 is formed on the first lower electrode 191. The first capacitor dielectric film 192 can be formed along the contour of the first lower electrode 191.

[0211] Subsequently, a pre-top electrode 193p is formed on the first capacitor dielectric film 192. The pre-top electrode 193p may cover the unit region 20, the peripheral region 24, and the unit region separation film 22.

[0212] Subsequently, the pre-upper electrode 193p can be patterned to form the first upper electrode. Figure 5 (of 193).

[0213] In summarizing the detailed description, those skilled in the art will understand that many variations and / or modifications, as well as additions and / or deletions, can be made to the exemplary embodiments without fundamentally departing from the principles of some exemplary embodiments. Therefore, the disclosed exemplary embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes a cell region and a peripheral region surrounding the cell region, the cell region including an active region defined by an element separation membrane; Storage pad, connected to the active area of ​​the cell region; The peripheral gate structure is located on the substrate in the peripheral region; Peripheral contact plugs are located on both sides of the peripheral gate structure and connected to the substrate; The first interlayer insulating film is located on the storage pad and on the peripheral contact plug, and includes a nitride-based insulating material; as well as Information storage circuitry, connected to the storage pad. The thickness of the first interlayer insulating film on the upper surface of the storage pad is less than the thickness of the first interlayer insulating film on the upper surface of the peripheral contact plug.

2. The semiconductor memory device according to claim 1, wherein, The first interlayer insulating film includes a lower interlayer insulating film and an upper interlayer insulating film located on the lower interlayer insulating film, and The lower interlayer insulating film is located on the upper surface of the peripheral contact plug, but not on the upper surface of the storage pad.

3. The semiconductor memory device according to claim 2, wherein, The first interlayer insulating film also includes an embedded interlayer insulating film. The lower interlayer insulating film is located on the embedded interlayer insulating film, and The interlayer insulating film is not located on the upper surface of the storage pad.

4. The semiconductor memory device according to claim 2, wherein, The upper interlayer insulating film is located on the upper surface of the storage pad and the upper surface of the peripheral contact plug.

5. The semiconductor memory device according to claim 1, wherein, The information storage circuit includes a lower electrode connected to the storage pad, a capacitor dielectric film located on the lower electrode, and an on-plate electrode located on the capacitor dielectric film.

6. The semiconductor memory device according to claim 5, further comprising: The second interlayer insulating film is disposed on the first interlayer insulating film and covers the sidewalls of the plate electrode. In this process, the second interlayer insulating film is in direct contact with the first interlayer insulating film.

7. The semiconductor memory device of claim 5, further comprising: The second interlayer insulating film is located on top of the first interlayer insulating film and covers the sidewalls of the plate electrodes. The capacitor dielectric film extends along the boundary between the first interlayer insulating film and the second interlayer insulating film.

8. The semiconductor memory device according to claim 5, wherein, The first interlayer insulating film includes a lower interlayer insulating film and an upper interlayer insulating film located on the lower interlayer insulating film. The lower interlayer insulating film is located on the upper surface of the peripheral contact plug, but not on the upper surface of the storage pad. The lower interlayer insulating film includes a first portion that is vertically stacked with the electrodes on the plate and a second portion that is not vertically stacked with the electrodes on the plate.

9. The semiconductor memory device according to claim 8, wherein, The thickness of the first part of the lower interlayer insulating film is greater than the thickness of the second part of the lower interlayer insulating film.

10. The semiconductor memory device according to claim 1, wherein, The upper surface of the peripheral contact plug and the upper surface of the storage pad are on the same plane.

11. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes a cell region and a peripheral region surrounding the cell region, the cell region including an active region defined by an element separation membrane; A unit separation membrane that defines a unit region within a substrate; Storage pad, connected to the active area of ​​the cell region; The peripheral gate structure is located on the substrate in the peripheral region; Peripheral contact plugs are located on both sides of the peripheral gate structure and connected to the substrate. The upper surface of the peripheral contact plugs and the upper surface of the storage pad are on the same plane. The first interlayer insulating film is located on the storage pad and on the peripheral contact plug, and includes a nitride-based insulating material; as well as The capacitor includes a lower electrode connected to a storage pad, a capacitor dielectric film located on the lower electrode, and an on-plate electrode located on the capacitor dielectric film. The upper surface of the first interlayer insulating film includes a stepped structure located on the unit separation film.

12. The semiconductor memory device according to claim 11, wherein, The thickness of the first interlayer insulating film on the upper surface of the peripheral contact plug is greater than the thickness of the first interlayer insulating film on the upper surface of the storage pad.

13. The semiconductor memory device according to claim 11, wherein, The first interlayer insulating film includes a lower interlayer insulating film and an upper interlayer insulating film located on the lower interlayer insulating film. The lower interlayer insulating film includes the ends located on the unit separation film, and The stepped structure is defined by the ends of the lower interlayer insulating film.

14. The semiconductor memory device according to claim 13, wherein, The interlayer insulating film comprises multiple insulating films sequentially stacked on the substrate.

15. The semiconductor memory device according to claim 11, wherein, The stepped structure is located at a position where it is vertically superimposed on the electrodes on the plate.

16. The semiconductor memory device of claim 11, further comprising: The second interlayer insulating film is located on top of the first interlayer insulating film and covers the sidewalls of the plate electrodes. In this process, the second interlayer insulating film is in direct contact with the first interlayer insulating film.

17. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes a cell region and a peripheral region surrounding the cell region, the cell region including an active region defined by an element separation membrane; A unit separation membrane defines a unit region of the substrate; Bitline structure, including unit wires and unit line cover film located on the unit wires, the bitline structure is located on the substrate of the unit region; The unit grid electrode is disposed inside the substrate of the unit region and intersects with the unit wire; Storage pads are located on the side surface of the bitline structure and connected to the active region of the cell region; The peripheral gate structure is located on the substrate in the peripheral region; Peripheral contact plugs are located on both sides of the peripheral gate structure and connected to the substrate; A capacitor includes a lower electrode connected to a storage pad, a capacitor dielectric film located on the lower electrode, and an on-plate electrode located on the capacitor dielectric film. The lower interlayer insulating film, located on the peripheral contact plug and comprising a nitride-based insulating material, has its ends covered by on-board electrodes. as well as The upper interlayer insulating film is located on top of the lower interlayer insulating film and covers the sidewalls of the plate electrodes. The lower interlayer insulating film is not located on the upper surface of the storage pad.

18. The semiconductor memory device of claim 17, further comprising: An etching stop film is located on the upper surface of the storage pad. The etching stop film extends between the lower interlayer insulating film and the electrode on the board.

19. The semiconductor memory device of claim 18, wherein, The etching stop film extends between the lower interlayer insulating film and the upper interlayer insulating film.

20. The semiconductor memory device of claim 17, wherein, The capacitor dielectric film is not located between the lower interlayer insulating film and the upper interlayer insulating film.

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