Chip-under-test circuit, method, and test apparatus
CN114627949BActive Publication Date: 2026-08-28CHANGXIN MEMORY TECH INC
Patent Information
- Application Number
- CN202210236722.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-11
- Publication Date
- 2026-08-28
- Estimated Expiration
- 2042-03-11
AI Technical Summary
Technical Problem
若采用不准确的芯片地址对待测芯片进行测试，则可能会输入或输出错误的信号，影响测试结果
Benefits of technology
[0043]本公开实施例中，通过锁存待测芯片的数据信号而产生的测试数据信号与测试命令信号进行组合逻辑而得到调整命令信号，如此调整命令信号就有了数据信号的信息，后续调整命令信号就能根据数据信号的信息确定需要进行数值调整的待测芯片，实现了待测芯片的可寻址性，从而能够对每个待测芯片的单独测试。
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN114627949B_ABST
Abstract
The embodiment of the present disclosure discloses a test circuit, method and test equipment of a chip under test, wherein the test circuit of the chip under test comprises: a test command generation circuit configured to generate a test command signal based on an enable signal in a test mode; a latched data generation circuit configured to latch a data signal of the chip under test based on a clock signal and generate a test data signal; and an adjustment command generation circuit connected to the test command generation circuit and the latched data generation circuit, configured to generate an adjustment command signal based on the test command signal and the test data signal.
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Citation Information
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