A multilayer semiconductor material structure and a method of fabrication

Abstract

The application discloses a multilayer semiconductor material structure and a preparation method, and belongs to the technical field of semiconductors, and solves the problems of poor heat dissipation, high cost and incapability of batch production of semiconductor materials in the prior art. The multilayer semiconductor material structure comprises a high-thermal-conductivity supporting substrate and a crystallized device functional layer; the device functional layer is arranged on the high-thermal-conductivity supporting substrate, and a surface layer of the device functional layer is a single crystal structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a multilayer semiconductor material structure and its preparation method. Background Technology

[0002] Gallium oxide (Ga2O3) crystal is a novel ultra-wide bandgap semiconductor material. Compared to common third-generation semiconductors, it has a wider bandgap, a higher electric breakdown field, and a Baliga figure of merit that is four times that of GaN and more than ten times that of SiC. Therefore, under the same breakdown voltage conditions, the theoretical on-resistance of a Ga2O3 unipolar device is only 1 / 10 that of SiC and 1 / 3 that of GaN. This helps reduce power loss during power supply circuitry and maximizes the power density of the device. Furthermore, Ga2O3 single-crystal substrates can be grown using a solution method, offering a significant advantage in fabrication cost compared to SiC and GaN.

[0003] Although Ga2O3 materials are inexpensive to fabricate and offer excellent device performance, their extremely low thermal conductivity (10-25 W / mK) causes severe localized self-heating during device operation, leading to faster device degradation and shorter lifespan. This significantly limits their application under high-power conditions, especially as the thermal conductivity of Ga2O3-based materials is further reduced by size effects, doping, and alloying. Therefore, achieving effective heat dissipation in Ga2O3 devices is one of the main challenges to their widespread application. Current research on Ga2O3 devices mainly focuses on improving electrical performance, with only a few studies reported on thermal performance and thermal management. A very promising solution is to heterogeneously integrate Ga2O3 with a high thermal conductivity substrate.

[0004] MJTadjer et al. transferred Ga2O3 nanoribbons with (100) crystal planes onto a single-crystal diamond substrate via mechanical exfoliation and fabricated Ga2O3 nanofilm field-effect transistors; although the weak van der Waals bonding between the Ga2O3 nanofilm and the diamond substrate resulted in very low interfacial thermal conductivity (17 MW / m²), 2 While the thermal conductivity of diamond is relatively low (K), Ga2O3 devices achieve a DC power density of 60 W / mm². Mechanical exfoliation of transferred nanoribbons is only suitable for standalone devices and cannot meet the requirements for mass production and large-scale application of Ga2O3 devices.

[0005] Z. Cheng et al. attempted to directly grow Ga2O3 on single-crystal diamond using atomic layer deposition (ALD), achieving a high thermal conductivity interface between Ga2O3 and diamond. While ALD can directly grow Ga2O3 and achieve a high thermal conductivity interface, the Ga2O3 film exhibits very poor crystallinity, exhibiting a nanocrystalline polycrystalline structure with thermal conductivity approaching that of amorphous Ga2O3, making it unsuitable for device fabrication.

[0006] F. Mu et al. achieved surface-activated room-temperature heterogeneous bonding integration of a 2-inch Ga2O3 single-crystal substrate and a SiC substrate, and combined this with ion implantation lift-off technology to achieve the transfer of single-crystal gallium oxide thin films. Surface-activated room-temperature bonding can achieve very high-performance gallium oxide heterogeneous integration, but the bonding process is complex, costly, and prone to introducing interface defects.

[0007] Therefore, there is an urgent need to develop heterogeneous integration technology of Ga2O3 and high thermal conductivity substrates that can be applied on a large scale.

[0008] In addition, materials such as silicon, silicon carbide, GaN, alumina, germanium, carbon, AlN, ZnO, GaAs, and AlGaN also have similar problems with poor heat dissipation. Summary of the Invention

[0009] Based on the above analysis, the present invention aims to provide a multilayer semiconductor material structure and preparation method to solve the problems of poor heat dissipation, high cost, and inability to mass-produce semiconductor materials in the prior art.

[0010] The objective of this invention is mainly achieved through the following technical solutions:

[0011] On one hand, the present invention provides a multilayer semiconductor material structure, including a high thermal conductivity support substrate and a crystallized device functional layer; the device functional layer is disposed on the high thermal conductivity support substrate, and the surface layer of the device functional layer is a single crystal structure.

[0012] In one possible design, the crystal structure of the device's functional layer has a microstructure gradient from single crystal to polycrystalline from the surface to the interface;

[0013] Alternatively, the crystal structure of the device functional layer may be such that the portion of the device functional layer near the surface and interface is all single crystal, while the portion of the surface and interface towards the middle has a microstructure gradient from single crystal to polycrystalline.

[0014] In one possible design, the functional layer of the device is a single-layer structure composed of one of the following materials: gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN, with a thickness of 100 nm to 50 μm.

[0015] In one possible design, the device functional layer includes a first thin film layer and a second thin film layer; the first thin film layer is disposed on the high thermal conductivity support substrate, and the second thin film layer is disposed on the first thin film layer;

[0016] The first thin film layer is a single-layer structure or a composite layer structure composed of one or more of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN, SiN, SiO2, HfO2, SiNO, SiCO, and AlON materials, with a thickness of 100nm-50um.

[0017] The second thin film layer is a single-layer structure or a composite layer structure composed of one or more of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN materials, with a thickness of 100nm-50um.

[0018] In one possible design, the high thermal conductivity support substrate material is one or more composites of diamond, SiC, AlN, BN, BeO, AlSiC, CuW, and CuMo.

[0019] On the other hand, the present invention provides a method for preparing a multilayer semiconductor material structure, comprising the following steps:

[0020] A device functional layer is formed on a high thermal conductivity support substrate;

[0021] A single-crystal substrate is attached to the surface of the functional layer of the device;

[0022] Annealing at 300℃-1800℃;

[0023] After cooling, the single-crystal substrate is peeled off to obtain the multilayer semiconductor material structure.

[0024] In one possible design, the method for forming the device functional layer on a high thermal conductivity support substrate is one or more of chemical vapor deposition, atomic layer deposition, molecular beam deposition, HVPE, physical sputtering, and plasma-enhanced CVD.

[0025] In one possible design, the device functional layer includes a first thin film layer and a second thin film layer;

[0026] The process of forming a device functional layer on a high thermal conductivity support substrate is as follows: a first thin film layer with a thickness of 100 nm to 50 μm is deposited on the high thermal conductivity support substrate; then the substrate is planarized and smoothed, and then a second thin film layer with a thickness of 100 nm to 50 μm is deposited.

[0027] In one possible design, the functional layer of the device is a single-layer thin film with a thickness of 100-50 μm. After the thin film is formed on a high thermal conductivity support substrate, it is planarized and smoothed, and then a single crystal substrate is attached to the surface of the smoothed thin film.

[0028] In one possible design, the functional layers of the device are planarized and smoothed, with a surface roughness between 0.1 nm and 10 nm.

[0029] Compared with the prior art, the present invention can achieve at least one of the following technical effects:

[0030] 1) The multilayer semiconductor material structure device of the present invention has a functional layer disposed on a high thermal conductivity support substrate, and the functional layer is at least partially crystallized thin film layer. The near-surface layer of the functional layer is a single crystal structure. The structure of the present invention not only forms a high thermal conductivity interface and improves the heat dissipation efficiency of the functional film layer, but also ensures the practicality of the functional layer. The manufacturing process is simple, and it can be manufactured in large size and in batches at low cost.

[0031] 2) It can be used to make high-performance MOSFETs, HEMTs, or Schottky diodes with high heat dissipation capabilities, and is not limited to horizontal or vertical devices.

[0032] 3) In order to enhance interfacial adsorption, release stress and enhance interfacial thermal conductivity, the functional layer of the device includes a first thin film layer and a second thin film layer; the first thin film layer has a thermal expansion coefficient that is closer to that of the high thermal conductivity substrate and a higher chemical affinity.

[0033] Other features and advantages of the invention will be set forth in the following description, and in part will be obvious from the description or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0034] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0035] Figure 1 Schematic diagram of a high thermal conductivity support substrate;

[0036] Figure 2 This is a schematic diagram of the fabrication process of a multilayer semiconductor material structure according to one embodiment;

[0037] Figure 3 This is a schematic diagram of the fabrication process of a multilayer semiconductor material structure according to another embodiment;

[0038] Figure 4This is a schematic diagram of the fabrication process of a multilayer semiconductor material structure according to another embodiment;

[0039] Figure 5 This is a schematic diagram of the thin film crystallization process;

[0040] Figure 6 This is a schematic diagram of the cross-section of a multilayer semiconductor material structure after patterning and etching.

[0041] Figure 7 This is a schematic diagram of the cross-section of another multilayer semiconductor material structure after patterning and etching.

[0042] Figure 8 This is a schematic diagram of the cross-section of another multilayer semiconductor material structure after patterning and etching.

[0043] Figure 9 This is a planar schematic diagram of a multilayer semiconductor material structure after patterning and etching.

[0044] Figure label:

[0045] 1-High thermal conductivity support substrate; 101-First surface; 102-Second surface; 2-Device functional layer; 201-First thin film layer; 202-Second thin film layer; 3-Single crystal substrate. Detailed Implementation

[0046] The embodiments of the present invention will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts disclosed in the present invention.

[0047] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0048] In the context of this invention, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0049] A multilayer semiconductor material structure includes a high thermal conductivity support substrate 1 and a crystallized device functional layer 2; the device functional layer 2 is disposed on the high thermal conductivity support substrate 1, and the near-surface layer of the device functional layer 2 is a single crystal structure.

[0050] The crystallized device functional layer 2 has a microstructure gradient from single crystal to polycrystalline from the surface to the interface. The surface layer near the surface has a high-quality single crystal structure with a fixed orientation, such as

[0001] ,

[001] ,

[111] ,

[110] , etc.

[0051] Compared with the prior art, the multilayer semiconductor material structure device functional layer 2 of the present invention is disposed on a high thermal conductivity support substrate 1, and the device functional layer 2 is at least partially crystallized thin film layer. The near-surface layer of the device functional layer 2 is a single crystal structure. The structure of the present invention not only forms a high thermal conductivity interface and improves the heat dissipation efficiency of the device functional layer 2, but also ensures the practicality of the device functional layer 2 and can be used for device fabrication.

[0052] Specifically, the high thermal conductivity support substrate 1 (thermal conductivity greater than 100 W / m·K) is made of one or more composites of diamond, SiC, AlN, BN, BeO, AlSiC, CuW, and CuMo. The crystal form and orientation are not limited; it can be single crystal, polycrystalline, or amorphous.

[0053] When the high thermal conductivity support substrate 1 is a single crystal, the crystal structure of the crystallized device functional layer 2 is that the part of the device functional layer 2 near the surface and interface is a single crystal, and the part of the surface and interface towards the middle is a microstructure gradient from single crystal to polycrystalline.

[0054] like Figure 1 As shown, the high thermal conductivity support substrate 1 includes a first surface 101 and a second surface 102. The roughness of the first surface 101 is less than 1000 nm. If the surface is too rough, it will result in high subsequent processing costs. Preferably, the roughness of the second surface 102 of the substrate is 1 nm-20 μm.

[0055] In one embodiment of the present invention, the device functional layer 2 is a single layer made of one of the following materials: gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN, etc.

[0056] In another embodiment of the present invention, in order to enhance interfacial adsorption, release stress and enhance interfacial thermal conductivity, the device functional layer 2 includes a first thin film layer 201 and a second thin film layer 202; the first thin film layer 201 has a thermal expansion coefficient closer to that of the high thermal conductivity support substrate 1 and a higher chemical affinity, and is disposed on the high thermal conductivity support substrate 1 with a thickness of 100nm-50um, and the second thin film layer 202 is disposed on the first thin film layer 201 with a thickness of 100nm-50um. The first thin film layer 201 is a single-layer structure composed of one of the following materials: gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN, SiN, SiO2, HfO2, SiNO, SiCO, AlON, etc., or a multi-layer composite layer structure obtained by depositing multiple materials separately; the second thin film layer 202 is a single-layer structure composed of one of the following materials: gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN, etc., or a multi-layer composite layer structure obtained by depositing multiple materials separately.

[0057] This invention also provides a method for preparing a multilayer semiconductor material structure, comprising the following steps:

[0058] A device functional layer 2 is formed on a high thermal conductivity support substrate 1;

[0059] A single-crystal substrate 3 is attached to the surface of the functional layer 2 of the device;

[0060] annealing;

[0061] After cooling, the single crystal substrate 3 is peeled off to obtain a multilayer semiconductor material structure.

[0062] like Figure 5 As shown, this invention involves attaching a low-defect-density single-crystal substrate 3 to the surface of the functional layer 2 of the device as an initial nucleation substrate. After heating and annealing, the surface of the functional layer 2 undergoes solid-state epitaxial crystallization along the surface of the initial nucleation substrate, with the orientation consistent with that of the initial nucleation substrate. After cooling, the initial nucleation substrate (i.e., the single-crystal substrate 3) is peeled off. The crystal structure of the crystallized functional layer 2 exhibits a microstructure gradient from single-crystal to polycrystalline from the surface to the interface, with the surface portion exhibiting a high-quality single-crystal structure. This invention offers a simple fabrication method and forms a single-crystal structure on the surface of the functional layer 2, ensuring the practicality of the functional layer 2 and enabling its use in device fabrication.

[0063] When the high thermal conductivity support substrate 1 is a single crystal, annealing will produce the same nucleation effect as the single crystal substrate 3 attached to the surface of the device functional layer 2. At this time, the crystal structure of the crystallized device functional layer 2 is as follows: the part of the device functional layer 2 near the surface and interface is a single crystal, and the part of the surface and interface towards the middle is a microstructure gradient from single crystal to polycrystalline.

[0064] For example, the material of the single crystal substrate 3 can be sapphire, the thickness of the single crystal substrate 3 is in the range of 50um-1000um, and the surface roughness is between 0.1nm-10nm, to ensure full contact with the surface of the device functional layer 2.

[0065] The method for forming the device functional layer 2 on the high thermal conductivity support substrate 1 is one or more of chemical vapor deposition, atomic layer deposition, molecular beam deposition, HVPE, physical sputtering, and plasma-enhanced CVD.

[0066] Before attaching the single-crystal substrate 3, the functional layer 2 of the device is planarized and smoothed to achieve a surface roughness between 0.1 nm and 10 nm. The specific operations for planarization and smoothing are chemical mechanical polishing and plasma treatment.

[0067] The annealing temperature is 300-1800℃. To prevent high thermal stress during annealing, the heating and annealing rate should not exceed 50℃ / min, and the holding time should be 5-100min.

[0068] In one embodiment of the present invention, such as Figure 2 As shown, a high thermal conductivity support substrate 1 is first provided. A device functional layer 2 is deposited on the first surface 101 of the high thermal conductivity support substrate 1. This layer is a single-layer structure composed of one of the following materials: gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN. The thickness is between 100 nm and 50 μm, and the crystal structure is amorphous. Then, the substrate is planarized and smoothed to achieve a surface roughness between 0.1 nm and 10 nm. After planarization and smoothing, the thickness is 50 nm to 45 μm. Finally, annealing is performed to crystallize the substrate.

[0069] In another embodiment of the invention, such as Figure 3As shown, to enhance interfacial adsorption, release stress, and improve interfacial thermal conductivity, the structure is changed to another multilayer structure. The device functional layer 2 includes a first thin film layer 201 and a second thin film layer 202. First, a high thermal conductivity support substrate 1 is provided, and a first thin film layer 201 is deposited on the first surface 101 of the high thermal conductivity support substrate 1. The first thin film layer 201 is a single-layer structure or a multilayer composite layer structure composed of one or more of the following materials: gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN, SiN, SiO2, HfO2, SiNO, SiCO, AlON, etc. The thickness of the first thin film layer 201 is 100nm to 50um, and the crystal structure is amorphous. Then, it is planarized and smoothed to make its surface roughness between 0.1nm and 50nm. Then, a second thin film layer 202 is deposited. The second thin film layer 202 is surface-smoothed. The second thin film layer 202 is a single-layer structure or a multi-layer composite structure composed of one of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN materials. The thickness is between 100nm and 50um, and the surface roughness is between 0.1nm and 10nm. Then, it is annealed to crystallize it. The crystallized thin film crystal structure has a microstructure gradient from single crystal to polycrystalline from the surface to the interface. The crystal near the surface is a high-quality single crystal structure with a fixed orientation, such as

[0001] ,

[001] ,

[111] ,

[110] , etc.

[0070] In another embodiment of the invention, such as Figure 4 As shown, the same device functions include a first thin film layer 201 and a second thin film layer 202; after depositing the first thin film layer 201, planarization and smoothing are omitted, and the second thin film layer 202 is directly deposited, and then the second thin film layer 202 is planarized and smoothed.

[0071] The multilayer semiconductor material structure obtained from the fabrication can also have the structure described above, followed by patterning and etching. Possible cross-sections include... Figure 6-8 As shown. Possible floor plans are as follows. Figure 9 As shown, but not limited to circular substrates and small square pieces.

[0072] Example 1

[0073] First, a high thermal conductivity support substrate 1 is provided, which is made of diamond and has a thickness of 100-200um. The roughness of the first surface 101 is 1nm and the roughness of the second surface 102 is 20nm.

[0074] A gallium oxide layer with a thickness of 200 nm was deposited on a high thermal conductivity support substrate 1 using chemical vapor deposition.

[0075] The gallium oxide layer was planarized and smoothed to achieve a roughness of 0.5 nm.

[0076] A sapphire single-crystal substrate 3, with a thickness of 500 μm and a roughness of 0.3 nm, was attached to a planarized and smoothed gallium oxide layer. Then, a heat annealing process was performed: the temperature was increased to 600 °C at a rate of 1 °C / min, held for 30 min, and then cooled at a rate of 1 °C / min. After cooling, the single-crystal substrate 3 was removed, resulting in a multilayer semiconductor material structure.

[0077] Example 2

[0078] First, a high thermal conductivity support substrate 1 is provided, which is made of silicon carbide and has a thickness of 400 μm. The roughness of the first surface 101 is 0.3 nm and the roughness of the second surface 102 is 10 nm.

[0079] An Al2O3 layer with a thickness of 100 nm was deposited on a high thermal conductivity support substrate 1 using the atomic layer substrate method.

[0080] A gallium oxide layer with a thickness of 200 nm was deposited on the Al2O3 layer using chemical vapor deposition. The gallium oxide layer was then planarized and smoothed to a roughness of 0.5 nm.

[0081] A single-crystal alumina substrate, 3, with a thickness of 50 micrometers and a roughness of 0.3 nm, was attached to a gallium oxide layer. Then, a heat annealing process was performed: the temperature was increased to 600°C at a rate of 1°C / min, held for 30 minutes, and then cooled at a rate of 1°C / min. After cooling, the single-crystal substrate 3 was removed, resulting in a multilayer semiconductor material structure.

[0082] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0083] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for preparing a multilayer semiconductor material structure, characterized in that, Includes the following steps: A device functional layer is formed on a high thermal conductivity support substrate; the high thermal conductivity support substrate is a single crystal. A device functional layer is formed on the high thermal conductivity support substrate, and an interface is formed between the high thermal conductivity support substrate and the device functional layer. A single-crystal substrate is attached to the surface of the functional layer of the device, and the single-crystal substrate serves as the initial substrate for nucleation. Annealing at 300℃-1800℃; During annealing, solid-phase epitaxial crystallization occurs in the portion of the functional layer of the device near the surface and interface, forming a single crystal; After cooling, the single-crystal substrate is peeled off to obtain the multilayer semiconductor material structure. The multilayer semiconductor material structure includes a high thermal conductivity support substrate and a crystallized device functional layer; the device functional layer is disposed on the high thermal conductivity support substrate. The crystal structure of the device functional layer is such that the part of the device functional layer near the surface and interface is all single crystal, and the part of the surface and interface towards the middle is a microstructure gradient from single crystal to polycrystalline. The single-crystal portion of the device's functional layer near the surface and interface forms a highly thermally conductive interface.

2. The method for preparing a multilayer semiconductor material structure according to claim 1, characterized in that, Methods for forming device functional layers on high thermal conductivity support substrates include one or more of chemical vapor deposition, atomic layer deposition, molecular beam deposition, HVPE, physical sputtering, and plasma-enhanced CVD.

3. The method for preparing a multilayer semiconductor material structure according to claim 1, characterized in that, The functional layer of the device includes a first thin film layer and a second thin film layer; The process of forming a device functional layer on a high thermal conductivity support substrate is as follows: a first thin film layer with a thickness of 100 nm to 50 μm is deposited on the high thermal conductivity support substrate; then the substrate is planarized and smoothed, and then a second thin film layer with a thickness of 100 nm to 50 μm is deposited.

4. The method for preparing a multilayer semiconductor material structure according to claim 1, characterized in that, The functional layer of the device is a single-layer thin film with a thickness of 100-50 μm. After the thin film is formed on a high thermal conductivity support substrate, it is planarized and smoothed, and then a single crystal substrate is attached to the surface of the smoothed thin film.

5. The method for preparing a multilayer semiconductor material structure according to any one of claims 1-4, characterized in that, The functional layers of the device are planarized and smoothed, with a surface roughness between 0.1 nm and 10 nm.

6. A multilayer semiconductor material structure, prepared by the preparation method according to any one of claims 1-5, characterized in that, It includes a high thermal conductivity support substrate and a crystallized device functional layer; the device functional layer is disposed on the high thermal conductivity support substrate, and the surface layer of the device functional layer has a single crystal structure; The crystal structure of the device functional layer is such that the part of the device functional layer near the surface and interface is all single crystal, and the part of the surface and interface towards the middle is a microstructure gradient from single crystal to polycrystalline. The single-crystal portion of the near-surface layer of the device's functional layer, close to the surface and interface, forms a highly thermally conductive interface.

7. The multilayer semiconductor material structure according to claim 6, characterized in that, The functional layer of the device is a single-layer structure composed of one of the following materials: gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN, with a thickness of 100nm-50um.

8. The multilayer semiconductor material structure according to claim 6, characterized in that, The device functional layer includes a first thin film layer and a second thin film layer; the first thin film layer is disposed on the high thermal conductivity support substrate, and the second thin film layer is disposed on the first thin film layer; The first thin film layer is a single-layer structure or a composite layer structure composed of one or more of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN, SiN, SiO2, HfO2, SiNO, SiCO, and AlON materials, with a thickness of 100nm-50um. The second thin film layer is a single-layer structure or a composite layer structure composed of one or more of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN materials, with a thickness of 100nm-50um.

9. The multilayer semiconductor material structure according to claim 6, characterized in that, The high thermal conductivity support substrate material is one or more composites of diamond, SiC, AlN, BN, BeO, AlSiC, CuW, and CuMo.

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