Semiconductor structure, method of manufacturing the same, semiconductor memory, and electronic device

Abstract

The present disclosure provides a semiconductor structure, a method for manufacturing the semiconductor structure, a semiconductor memory and an electronic device. The method comprises: providing a semiconductor substrate; forming a mask layer on the semiconductor substrate; patterning the mask layer to form a first mask pattern; depositing a silicon oxide film layer on the first mask pattern; removing the first mask pattern and the silicon oxide film layer on top of the first mask pattern to form a silicon oxide pattern; forming a silicon nitride film layer on the side of the silicon oxide pattern to form a second mask pattern; and patterning the semiconductor substrate using the second mask pattern as a mask to form the semiconductor structure. In the present disclosure, the silicon nitride film layer reinforces the silicon oxide pattern, minimizes the critical dimension difference between the top and bottom of the silicon oxide pattern, and eliminates the poor tilting or peeling of the silicon oxide pattern. The critical dimension of the final pattern of the film layer under the silicon oxide pattern can be optimized.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, a semiconductor memory, and an electronic device. Background Technology

[0002] With the continuous advancement of semiconductor technology, the functionality of devices is becoming increasingly powerful, but the difficulty of semiconductor manufacturing is also increasing daily. Photolithography is the most critical production technology in semiconductor manufacturing. In processes below 20nm, the extremely small spacing between adjacent metal interconnects causes interference between adjacent light rays during photolithography, resulting in blurred edges and defects. To solve this problem, Double Pattern Technology (DPT) was adopted. The principle of DPT is to decompose a high-density circuit pattern into two discrete, lower-density patterns, and then fabricate them onto a wafer.

[0003] In the DPT process, controlling the critical dimensions and patterns (CD and Pattern) of each film layer is extremely difficult. Controlling the silicon oxide film solely through the etching process can lead to critical dimension differences between the top and bottom of the silicon oxide film, resulting in poor patterning or lifting, which may prevent the final pattern of the underlying film from forming correctly. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor structure and its fabrication method, a semiconductor memory, and an electronic device.

[0005] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0006] Provide semiconductor substrates;

[0007] A mask layer is formed on a semiconductor substrate;

[0008] The mask layer is patterned to form the first mask pattern;

[0009] A silicon oxide film is deposited on the first mask pattern;

[0010] Remove the first mask pattern and the silicon oxide film layer on top of it to form a silicon oxide pattern;

[0011] A silicon nitride film is formed along the side of the silicon oxide pattern to form a second mask pattern;

[0012] Using the second mask pattern as a mask, the semiconductor substrate is patterned to form the semiconductor structure.

[0013] According to some embodiments of this disclosure, patterning the mask layer to form a first mask pattern includes:

[0014] A bottom anti-reflective coating and a photoresist layer are sequentially formed on the mask layer;

[0015] The photoresist layer is exposed and developed to etch the mask layer into the first mask pattern.

[0016] According to some embodiments of this disclosure, when the mask layer is a single-layer structure, the mask layer includes a hard mask layer located on a semiconductor substrate; when the mask layer is a multilayer structure, the mask layer includes a hard mask layer located on a semiconductor substrate and a silicon oxynitride layer located on the hard mask layer.

[0017] According to some embodiments of this disclosure, the deposition of a silicon oxide film layer on the first mask pattern includes:

[0018] A silicon oxide film is deposited on the first mask pattern using atomic layer deposition (ALD) technology.

[0019] According to some embodiments of this disclosure, the semiconductor substrate includes a substrate and a first film layer, a second film layer and a third film layer sequentially deposited on the substrate.

[0020] According to some embodiments of this disclosure, the first film layer is a silicon oxide layer, the second film layer is a polycrystalline silicon layer, and the third film layer is an α-carbon layer.

[0021] A second aspect of this disclosure provides a semiconductor structure fabricated based on the method described in the first aspect, comprising:

[0022] Substrate; and

[0023] A first film layer, a second film layer, and a patterned third film layer are sequentially stacked on a substrate;

[0024] The top of the third film layer is covered with a silicon oxide film layer.

[0025] A third aspect of this disclosure provides a semiconductor memory, including the semiconductor structure described in the second aspect.

[0026] This disclosure provides a fourth aspect of an electronic device, including the semiconductor memory described in the third aspect.

[0027] The advantages of this disclosure compared to the prior art are:

[0028] (1) In this disclosure, the silicon oxide pattern is reinforced by a silicon nitride film layer, which minimizes the critical size difference between the top and bottom of the silicon oxide pattern.

[0029] (2) This disclosure can eliminate defects such as silicon oxide patterning or lifting.

[0030] (3) Through this disclosure, the critical dimensions of the final pattern of the film layer in the semiconductor substrate beneath the silicon oxide pattern can be optimized. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0032] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure provided in this disclosure is shown;

[0033] Figures 2 to 10 This is a cross-sectional structural diagram of the semiconductor structure fabrication process in a specific embodiment of this disclosure. Detailed Implementation

[0034] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0035] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0036] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0037] To address the problems existing in the prior art, this disclosure provides a semiconductor structure and its fabrication method, a semiconductor memory, and an electronic device, which will be described below with reference to the accompanying drawings.

[0038] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure provided in this disclosure is shown. This method is applicable to Double Pattern Technology (DPT). Figure 1 As shown, the method includes:

[0039] Step S101: Provide a semiconductor substrate;

[0040] Step S102: Form a mask layer on the semiconductor substrate;

[0041] Step S103: Pattern the mask layer to form the first mask pattern;

[0042] Step S104: Deposit a silicon oxide film on the first mask pattern;

[0043] Step S105: Remove the first mask pattern and the silicon oxide film layer on top of it to form a silicon oxide pattern;

[0044] Step S106: A silicon nitride film layer is formed along the side of the silicon oxide pattern to form a second mask pattern;

[0045] Step S107: Using the second mask pattern as a mask, pattern the semiconductor substrate to form the semiconductor structure.

[0046] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0047] Figures 2 to 10 This is a cross-sectional structural diagram of the semiconductor structure fabrication process in a specific embodiment of this disclosure.

[0048] Please refer to Figure 2 In step S101, a semiconductor substrate 100 is provided, which may include a substrate 110 and a first film layer 120, a second film layer 130 and a third film layer 140 sequentially deposited on the substrate 110.

[0049] Specifically, the first film layer 120 can be a silicon oxide layer, serving as a pad; the second film layer 130 can be a polysilicon layer (POLY); and the third film layer is an α-carbon layer (ACL).

[0050] Please refer to Figure 3In step S102, a mask layer 200 is formed on the semiconductor substrate 100. Specifically, the mask layer 200 can be a single-layer structure or a multi-layer structure. When the mask layer is a single-layer structure, the mask layer 200 includes a hard mask layer 210 located on the semiconductor substrate 100. When the mask layer is a multi-layer structure, the mask layer 200 includes a hard mask layer 210 located on the semiconductor substrate and a silicon oxynitride layer 220 located on the hard mask layer 210. Figure 3 This example uses a mask layer as a multi-layer structure.

[0051] Specifically, the hard mask layer 210 can be a spin-on hard mask material (SOH). The silicon oxynitride layer 220 is a silicon oxynitride material (SiON).

[0052] Please refer to Figure 4 and Figure 5 In step S103, the mask layer 200 is patterned to form a first mask pattern 300, such as... Figure 5 As shown. This step can specifically include: sequentially forming a bottom anti-reflective coating 230 and a photoresist layer 240 on the mask layer 200, such as... Figure 4 As shown, the photoresist layer 240 is exposed and developed to etch the mask layer 200 into the first mask pattern 300.

[0053] Please refer to Figure 6 In step S104, a silicon oxide film 400 is deposited on the first mask pattern 300. Specifically, the silicon oxide film 400 can be deposited on the first mask pattern 300 using an atomic layer deposition (ALD) process.

[0054] Please refer to Figure 7 In step S105, the first mask pattern 300 and its top silicon oxide film layer are removed to form the silicon oxide pattern 500, which can be done using existing etching processes.

[0055] It is worth mentioning that when the silicon oxide pattern 500 is fabricated through an etching process, there may be a critical dimensional difference between the top and bottom of the silicon oxide pattern 500, which may cause poor pattern tilting or lifting.

[0056] Therefore, please refer to Figure 8 and Figure 9 To avoid the above-mentioned defects, in step S106 of this embodiment, a silicon nitride film layer 600 is first formed on and around the silicon oxide pattern 500, such as... Figure 8As shown. Then, only the silicon nitride film layer 600 attached to the side of the silicon oxide pattern 500 is retained, and the other parts of the silicon nitride film layer 600 are removed to form the silicon nitride film layer 600 attached to the side of the silicon oxide pattern 500, thereby forming the second mask pattern 700, as shown. Figure 9 As shown.

[0057] Please refer to Figure 10 In step S107, the semiconductor substrate 100 is patterned using the second mask pattern 700 as a mask to form the above-mentioned semiconductor structure. Figure 10 The figure shows a pattern of the third film layer 140 in the semiconductor substrate 100. Part of the silicon oxide pattern 500 is retained in the figure. The second film layer 130 under the third film layer 140 can also be patterned (not shown).

[0058] As can be seen, in this embodiment, by forming a silicon nitride film layer 600 on the side of the silicon oxide pattern 500, the silicon oxide pattern 500 is strengthened, thereby eliminating the tilting or lifting defects of the silicon oxide pattern 500, so that the underlying semiconductor substrate 100 can be better patterned and the critical dimensions of the final pattern can be optimized.

[0059] The advantages of this disclosure compared to the prior art are:

[0060] (1) In this disclosure, the silicon oxide pattern is reinforced by a silicon nitride film layer, which minimizes the critical size difference between the top and bottom of the silicon oxide pattern.

[0061] (2) This disclosure eliminates the tilting or lifting of silicon oxide patterns.

[0062] bad.

[0063] (3) Through this disclosure, the critical dimensions of the final pattern of the film layer in the semiconductor substrate beneath the silicon oxide pattern can be optimized.

[0064] This disclosure also provides a semiconductor structure fabricated based on the method in the above embodiments, such as... Figure 10 As shown, it includes:

[0065] Substrate 110; and

[0066] A first film layer 120, a second film layer 130 and a patterned third film layer 140 are sequentially stacked on a substrate 110.

[0067] The top of the third film layer 140 is covered with a silicon oxide film layer 500.

[0068] Figures 2 to 10 This is a cross-sectional schematic diagram of the above semiconductor structure fabrication process.

[0069] Please refer to Figure 2 A semiconductor substrate 100 is provided, which may include a substrate 110 and a first film layer 120, a second film layer 130 and a third film layer 140 sequentially deposited on the substrate 110.

[0070] Specifically, the first film layer 120 can be a silicon oxide layer, serving as a pad; the second film layer 130 can be a polysilicon layer (POLY); and the third film layer is an α-carbon layer (ACL).

[0071] Please refer to Figure 3 A mask layer 200 is formed on the semiconductor substrate 100. Specifically, the mask layer 200 can be a single-layer structure or a multi-layer structure. When the mask layer is a single-layer structure, the mask layer 200 includes a hard mask layer 210 located on the semiconductor substrate 100. When the mask layer is a multi-layer structure, the mask layer 200 includes a hard mask layer 210 located on the semiconductor substrate and a silicon oxynitride layer 220 located on the hard mask layer 210. Figure 3 This example uses a mask layer as a multi-layer structure.

[0072] Specifically, the hard mask layer 210 can be a spin-on hard mask material (SOH). The silicon oxynitride layer 220 is a silicon oxynitride material (SiON).

[0073] Please refer to Figure 4 and Figure 5 The mask layer 200 is patterned to form a first mask pattern 300, such as... Figure 5 As shown. This step can specifically include: sequentially forming a bottom anti-reflective coating 230 and a photoresist layer 240 on the mask layer 200, such as... Figure 4 As shown, the photoresist layer 240 is exposed and developed to etch the mask layer 200 into the first mask pattern 300.

[0074] Please refer to Figure 6 A silicon oxide film 400 is deposited on the first mask pattern 300. Specifically, the silicon oxide film 400 can be deposited on the first mask pattern 300 using atomic layer deposition (ALD) technology.

[0075] Please refer to Figure 7 The first mask pattern 300 and its top silicon oxide film layer are removed to form the silicon oxide pattern 500, which can be done using existing related etching processes.

[0076] It is worth mentioning that when the silicon oxide pattern 500 is fabricated through an etching process, there may be a critical dimensional difference between the top and bottom of the silicon oxide pattern 500, which may cause poor pattern tilting or lifting.

[0077] Therefore, please refer to Figure 8 and Figure 9 To avoid the above defects, a silicon nitride film 600 is first formed on and around the silicon oxide pattern 500, such as... Figure 8 As shown. Then, only the silicon nitride film layer 600 attached to the side of the silicon oxide pattern 500 is retained, and the other parts of the silicon nitride film layer 600 are removed to form the silicon nitride film layer 600 attached to the side of the silicon oxide pattern 500, thereby forming the second mask pattern 700, as shown. Figure 9 As shown.

[0078] Please refer to Figure 10 Using the second mask pattern 700 as a mask, the semiconductor substrate 100 is patterned to form the aforementioned semiconductor structure. Figure 10 The figure shows a pattern of the third film layer 140 in the semiconductor substrate 100. Part of the silicon oxide pattern 500 is retained in the figure. The second film layer 130 under the third film layer 140 can also be patterned (not shown).

[0079] As can be seen, in this embodiment, by forming a silicon nitride film layer 600 on the side of the silicon oxide pattern 500, the silicon oxide pattern 500 is strengthened, thereby eliminating the tilting or lifting defects of the silicon oxide pattern 500, so that the underlying semiconductor substrate 100 can be better patterned.

[0080] The advantages of this disclosure compared to the prior art are:

[0081] (1) In this disclosure, the silicon oxide pattern is reinforced by a silicon nitride film layer, which minimizes the critical size difference between the top and bottom of the silicon oxide pattern.

[0082] (2) This disclosure eliminates the tilting or lifting of silicon oxide patterns.

[0083] bad.

[0084] (3) Through this disclosure, the critical dimensions of the final pattern of the film layer in the semiconductor substrate beneath the silicon oxide pattern can be optimized.

[0085] This disclosure also provides a semiconductor memory, which includes the semiconductor structure described in the above embodiments. The semiconductor memory may be, for example, a DRAM or other memory.

[0086] This disclosure also provides an electronic device that includes the semiconductor memory described in the above embodiments. The electronic device may be a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, or power bank.

[0087] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0088] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide semiconductor substrates; A mask layer is formed on a semiconductor substrate; The mask layer is patterned to form the first mask pattern; A silicon oxide film is deposited on the first mask pattern using atomic layer deposition (ALD) technology. Remove the first mask pattern and the silicon oxide film layer on top of it to form a silicon oxide pattern; A silicon nitride film is formed on and around the silicon oxide pattern. Then, only the silicon nitride film attached to the side of the silicon oxide pattern is retained, and the other parts of the silicon nitride film are removed to form a silicon nitride film attached to the side of the silicon oxide pattern, thereby forming a second mask pattern. Using the second mask pattern as a mask, the semiconductor substrate is patterned to form the semiconductor structure.

2. The method according to claim 1, characterized in that, The process of patterning the mask layer to form a first mask pattern includes: A bottom anti-reflective coating and a photoresist layer are sequentially formed on the mask layer; The photoresist layer is exposed and developed to etch the mask layer into the first mask pattern.

3. The method according to claim 1 or 2, characterized in that, When the mask layer is a single-layer structure, the mask layer includes a hard mask layer located on the semiconductor substrate; when the mask layer is a multilayer structure, the mask layer includes a hard mask layer located on the semiconductor substrate and a silicon oxynitride layer located on the hard mask layer.

4. The method according to claim 1, characterized in that, The semiconductor substrate includes a substrate and a first film layer, a second film layer and a third film layer deposited sequentially on the substrate.

5. The method according to claim 4, characterized in that, The first film layer is a silicon oxide layer, the second film layer is a polycrystalline silicon layer, and the third film layer is an α-carbon layer.

6. A semiconductor structure fabricated based on the method of any one of claims 1 to 5, characterized in that, include: substrate; as well as A first film layer, a second film layer, and a patterned third film layer are sequentially stacked on a substrate; The top of the third film layer is covered with a silicon oxide film layer.

7. A semiconductor memory, characterized in that, include: The semiconductor structure as described in claim 6.

8. An electronic device, characterized in that, include: The semiconductor memory as described in claim 7.

9. The electronic device according to claim 8 includes a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.

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