Method of manufacturing a semiconductor arrangement

Abstract

A method of fabricating a semiconductor arrangement includes forming a first molecular layer in a first wafer interface region of a first wafer, forming a second molecular layer in a second wafer interface region of a second wafer, forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, and annealing the first wafer and the second wafer to form a second molecular bond connecting the first wafer interface region to the second wafer interface region.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor configurations. Background Technology

[0002] Semiconductor configurations are used in a wide range of electronic devices, such as mobile phones, laptops, desktop computers, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronics. A semiconductor configuration may comprise a wafer having one or more of a substrate, doped regions, undoped regions, implanted regions, and isolation regions. Many devices include electronic components directly or indirectly coupled to the semiconductor configuration. Summary of the Invention

[0003] A method of manufacturing a semiconductor configuration includes: forming a first molecular ion layer in a first wafer interface region of a first wafer; forming a second molecular ion layer in a second wafer interface region of a second wafer; forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region; and annealing the first wafer and the second wafer to form the second molecular bond connecting the first wafer interface region to the second wafer interface region.

[0004] A method for manufacturing a semiconductor configuration includes: performing plasma treatment on a first wafer interface region of a first wafer; performing plasma treatment on a second wafer interface region of a second wafer; treating the first wafer interface region with deionized water after performing plasma treatment on the first wafer interface region of the first wafer; treating the second wafer interface region with deionized water after performing plasma treatment on the second wafer interface region of the second wafer; forming a silicon dioxide layer in the second wafer interface region after treating the second wafer interface region with deionized water; aligning a first surface of the first wafer interface region with a second surface of the second wafer interface region; applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region after aligning the first surface of the first wafer interface region with the second surface of the second wafer interface region; and annealing the first wafer and the second wafer to form molecular bonds connecting the first wafer interface region to the second wafer interface region.

[0005] A method for manufacturing a semiconductor configuration includes: forming a first silicon-oxygen molecular layer at a first wafer interface region of a first wafer; forming a second silicon-oxygen molecular layer at a second wafer interface region of a second wafer; treating the first silicon-oxygen molecular layer and the second silicon-oxygen molecular layer with deionized water molecules; aligning a first surface of the first wafer interface region with a second surface of the second wafer interface region; and annealing the first wafer and the second wafer to form covalent silicon-oxygen-silicon bonds at the interface between the first surface of the first wafer interface region and the second surface of the second wafer interface region to bond the first wafer to the second wafer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the various aspects of this disclosure are best understood in the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1 to 18 This is an illustration of semiconductor configurations at various stages of manufacturing, according to some embodiments.

[0008] Figure 19 This is an illustration of a method for manufacturing a semiconductor configuration according to some embodiments.

[0009] Figure 20 Exemplary computer-readable media according to some embodiments are shown. Detailed Implementation

[0010] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments or configurations discussed.

[0011] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship of one element or feature relative to another element or feature as shown in the diagrams. In addition to the orientations shown in the diagrams, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. Additionally, relational terms such as “connected to,” “adjacent to,” “coupled to,” and similar terms are used herein to describe direct and indirect relationships. “Direct” connection, proximity, or coupling may refer to a relationship in which no intervening component, device, or structure exists. “Indirect” connection, proximity, or coupling may refer to a relationship in which an intervening component, device, or structure exists.

[0012] This document provides one or more methods for manufacturing semiconductor configurations. The semiconductor configuration includes a device wafer having silicon regions, implantation regions, and an interconnect layer formed above the device wafer. Integrated circuit components are formed in the implantation regions and electrically coupled to the interconnect layer. Electronic components are coupled to the upper surface of the device wafer or to the upper surface of the interconnect layer. Warpage of the device wafer that would otherwise occur, such as due to the weight of electronic components coupled to the upper surface of the device wafer or the upper surface of the interconnect layer, is significantly reduced or eliminated by including a carrier wafer covalently bonded to the bottom surface of the device wafer. The combined thickness of the device wafer and the carrier wafer increases the rigidity or structural integrity of the semiconductor configuration and reduces or eliminates device wafer warpage.

[0013] The carrier wafer is adhered to the bottom surface of the device wafer by aligning the bottom surface of the device wafer with the top surface of the carrier wafer. The alignment surfaces are placed in physical contact at the interface between the bottom surface of the device wafer and the top surface of the carrier wafer. Force / pressure is applied to the device wafer and / or the carrier wafer in a direction toward the interface. The applied force / pressure causes molecular bonds (Van der Waals bonds) to form at the interface, thereby bonding the carrier wafer to the device wafer. These molecular bonds exist between silicon atoms in the device wafer and silicon dioxide molecules in the carrier wafer. The bonding strength between the carrier wafer and the device wafer is increased by a subsequent annealing process, which forms covalent bonds between the silicon and oxide of the device wafer and the silicon of the carrier wafer at the interface between the bottom surface of the device wafer and the top surface of the carrier wafer. These covalent bonds form a Si-Ox-Si interface.

[0014] Once the carrier wafer is bonded to the device wafer, the thickness of the carrier wafer can be reduced, thereby reducing the weight of the semiconductor configuration, while maintaining increased rigidity of the semiconductor configuration and resistance to warping of the device wafer.

[0015] Figures 1 to 18 This is an illustration of a semiconductor configuration 100 at various stages of manufacturing according to some embodiments.

[0016] Turning Figure 1 At least some of the semiconductor configurations 100 are formed in or on a first wafer 102, sometimes referred to as a device wafer. The thickness of the first wafer 102 is “t1” 101. The first wafer 102 includes a silicon region 106 comprising silicon (Si). In some embodiments, the first wafer 102 includes an implantation region 112. The implantation region 112 includes at least one of a p-type substrate (P-substrate) region, an n-type substrate (N-substrate) region, a doped region, or an undoped region. The first wafer 102 has an upper surface 104 above the implantation region 112 and a first wafer interface region 107 opposite to the upper surface 104. A silicon dioxide (SiO2) layer is formed in the first wafer interface region 107 by exposing the first wafer interface region 107 to oxygen (O2). Other configurations and / or compositions of the first wafer 102 are within the scope of this disclosure.

[0017] According to some embodiments, at least some of the doped regions of implantation region 112 are formed by at least one of ion implantation, molecular diffusion, or other suitable techniques. The number or amount of dopant implanted into implantation region 112 is controlled, for example, the concentration of dopant in implantation region 112 is controlled. In some embodiments, the energy of the dopant implanted into implantation region 112 is controlled, for example, the depth of dopant implantation in implantation region 112 is controlled. The depth of dopant in implantation region 112 is controlled by increasing or decreasing the voltage used to guide the dopant into implantation region 112. Thus, at least one of silicon region 106 or implantation region 112 includes at least one of p-type dopant or n-type dopant. In some embodiments, implantation region 112 comprises silicon region 106, or silicon region 106 comprises implantation region 112. Other configurations and / or compositions of silicon region 106 and implantation region 112 are within the scope of this disclosure.

[0018] According to some embodiments, the first wafer 102 includes one or more shallow trench isolation (STI) structures 114 formed in the implantation region 112. At least some of the one or more STI structures 114 are formed prior to the formation of other components of the implantation region 112. In some embodiments, forming the STI structure 114 includes etching trenches in the first wafer 102, depositing one or more dielectric materials to fill the trenches, and planarizing the top surface of the deposited dielectric material. The dielectric material of the STI structure 114 is at least one of oxides, nitrides, or other suitable materials. Other configurations and / or compositions of the STI structure 114 are within the scope of this disclosure.

[0019] According to some embodiments, the first wafer 102 includes one or more conductive regions 116. At least some of the one or more conductive regions 116 are located above or within the first wafer 102. At least some of the one or more conductive regions 116 are at least one of source or drain regions. At least some of the one or more conductive regions 116 include dopants implanted into the first wafer 102. Other configurations and / or compositions of the one or more conductive regions 116 are within the scope of this disclosure.

[0020] According to some embodiments, semiconductor configuration 100 includes transistor 118, which includes a dielectric region 120 and a gate electrode 122. The dielectric region 120 includes a dielectric material, such as at least one of oxides, nitrides, or other suitable materials. The gate electrode 122 includes a conductive material, such as at least one of polysilicon, metal, or other suitable materials. Other configurations and / or compositions of transistor 118 are within the scope of this disclosure.

[0021] According to some embodiments, the semiconductor configuration 100 includes one or more first dielectric layers 108a above the upper surface 104 of the first wafer 102. At least some of the one or more first dielectric layers 108a are interlayer dielectric (ILD) layers, which include at least one of tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), or other suitable materials. At least some of the one or more first dielectric layers 108a are formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, growth, or other suitable techniques. Other configurations and / or compositions of the first dielectric layer 108a are within the scope of this disclosure.

[0022] Semiconductor configuration 100 includes one or more second dielectric layers 108b above one or more first dielectric layers 108a. At least some of the one or more second dielectric layers 108b include at least one of TEOS, BPSG, FSG, PSG, BSG, or other suitable materials. At least some of the one or more second dielectric layers 108b are formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. At least some of the one or more second dielectric layers 108b have the same material composition as at least some of the one or more first dielectric layers 108a. Other configurations and / or compositions of the second dielectric layers 108b are within the scope of this disclosure.

[0023] Semiconductor configuration 100 includes forming one or more vertical interconnect accesses (VIAs) 124 through at least some of one or more first dielectric layers 108a and forming one or more metal layers 126 through at least some of one or more second dielectric layers 108b. According to some embodiments, at least some of the one or more metal layers 126 are electrically connected to at least some of the one or more VIAs 124, and at least some of the one or more VIAs 124 are electrically connected to one or more conductive regions 116, such that the metal layers of the one or more metal layers 126 and the VIAs of the one or more VIAs 124 provide an electrical path to the conductive regions of the one or more conductive regions 116 through the first dielectric layers 108a and the second dielectric layers 108b. Other configurations and / or compositions of the one or more VIAs 124 and / or the one or more metal layers 126 are within the scope of this disclosure.

[0024] In some embodiments, the semiconductor configuration 100 includes forming one or more interface VIAs 111 through at least some of the first dielectric layers 108a and / or at least some of the second dielectric layers 108b. According to some embodiments, the circumference of one or more interface VIAs 111 is larger than the circumference of one or more VIAs 124. Compared to one or more VIAs 124, at least some of the one or more interface VIAs 111 are configured to be electrically coupled to components formed above the one or more interface VIAs 111, resulting in low-resistance VIAs. Other configurations and / or compositions of the interface VIAs 111 are within the scope of this disclosure.

[0025] In some embodiments, at least some of one or more metal layers 126, at least some of one or more VIAs 124, or at least some of one or more interface VIAs 111 are formed by at least one of photolithography, etching, PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, dual damascene process, or other suitable techniques.

[0026] In some embodiments, the semiconductor configuration 100 includes a passivation layer 110 formed over at least one of a first dielectric layer 108a or a second dielectric layer 108b. The passivation layer 110 protects at least some of the first dielectric layers 108a, at least some of the second dielectric layers 108b, at least some of one or more interface VIAs 111, at least some of one or more metal layers 126, and / or at least some of one or more VIAs 124 from corrosion or other alterations during subsequent formation processes of the semiconductor configuration 100. In some embodiments, the passivation layer 110 comprises at least one of aluminum nitride (AlN), aluminum oxide (Al2O3), SiO2, silicon nitride (Si3N4), a chemically inert, corrosion-resistant dielectric material, or an organic compound having at least one of N-group, P-group, or S-group molecular structures, or other suitable materials. Other configurations and / or compositions of the passivation layer 110 are within the scope of this disclosure.

[0027] In some embodiments, the passivation layer 110 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, passivation, or other suitable techniques. The passivation process includes at least one of oxidation of the surface of the underlying material or complexation of the surface of the underlying material with an organic compound. The passivation layer 110 comprises one or more film layers covering the underlying material, such as one or more of a first dielectric layer 108a and / or a second dielectric layer 108b. A chemically stable material is used to form one or more layers of the film. During or after at least one of subsequent processes or treatments of the semiconductor configuration 100, at least one of the one or more layers of the film inhibits dissolution with respect to the underlying material or reduces at least one of the electrochemical or chemical reactivity with respect to the underlying material. Other processes for forming the passivation layer 110 are within the scope of this disclosure.

[0028] At least one of the passivation layers 110 inhibits the diffusion of at least one charge, atom, or ion into the underlying material, mitigates oxidation of the underlying material, protects the underlying material from environmental conditions, or acts as a diffusion barrier with respect to the underlying material. Other purposes or functions of the passivation layer 110 are within the scope of this disclosure.

[0029] Semiconductor configuration 100 includes a second wafer 103, sometimes referred to as a carrier wafer. The second wafer 103 comprises Si or other suitable material. The second wafer 103 has a boundary portion 128 and a second wafer interface region 130. A SiO2 layer is formed in the second wafer interface region 130 by exposing the second wafer interface region 130 to O2.

[0030] refer to Figure 2The process for bonding the second wafer 103 to the first wafer 102 includes forming an oxide protective layer 131 over the top surface 113 of the passivation layer 110 and the interface VIA 111. The oxide protective layer 131 is formed to protect the passivation layer 110 and the interface VIA 111 from the bonding forces / pressures applied to the first wafer 102 to bond the second wafer 103 to the first wafer 102, as described below. Figure 7 As described.

[0031] According to some embodiments, an oxide protective layer 131 is conformally formed over and across the passivation layer 110 and interface VIA 111. In some embodiments, the oxide protective layer 131 comprises at least one of SiO2, Si3N4, silicon oxynitride (SiON), a dielectric material having a high dielectric constant (high k), or other suitable materials. The oxide protective layer 131 can be formed by at least one of CVD, PVD, ALD, high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), or other suitable techniques. In some embodiments, the oxide protective layer 131 has a thickness between 0.5 nanometers (nm) and 3 nanometers. If the oxide protective layer 131 is too thick (e.g., greater than 3 nanometers), it may be difficult to remove in subsequent processes. If the oxide protective layer 131 is too thin (e.g., less than 0.5 nanometers), the underlying structure may be damaged when the second wafer 103 is bonded to the first wafer 102.

[0032] Figure 2 A first wafer 102 and a second wafer 103 undergoing plasma treatment are shown. In some embodiments, the first wafer 102 is plasma-treated in a first plasma chamber (not shown), and the second wafer 103 is plasma-treated in a second plasma chamber (not shown). In some embodiments, the first wafer 102 and the second wafer 103 are each plasma-treated in the same plasma chamber (not shown). Plasma treatment includes implanting material into the first plasma chamber, the second plasma chamber, or the same plasma chamber, and applying a voltage to the implanted material to generate plasma from the implanted material. The implanted material may be argon (Ar) or other suitable materials, and the plasma may be Ar plasma or other suitable plasma.

[0033] refer to Figure 3The diagram illustrates plasma treatment to activate the first wafer interface region 107 and the second wafer interface region 130. Activation involves altering the lattice structure of SiO2 molecules at the first wafer interface region 107 and the second wafer interface region 130 by breaking the bonds between each of the Si and O atoms. Breaking the bonds between each of the Si and O atoms creates dangling Si-O bonds 300 at the first wafer interface region 107 and the second wafer interface region 130. The dangling Si-O bonds 300 replace the previously existing Si-O2 bonds and are weaker than the previously existing Si-O2 bonds. The first wafer interface region 107 and the second wafer interface region 130 are each treated to form a molecular ion layer in the first wafer interface region 107 and the second wafer interface region 130. In some embodiments, the first wafer interface region 107 and the second wafer interface region 130 are each treated to form hydroxide ions (OH) from the dangling Si-O bonds 300.

[0034] Figure 3 The process is illustrated by treating the first wafer interface region 107 and the second wafer interface region 130 by applying deionized water (H2O) molecules to the first wafer interface region 107 and the second wafer interface region 130 to form OH ions from the suspended Si-O bonds 300. The deionized H2O molecules clean the first wafer interface region 107 and the second wafer interface region 130 by separating the suspended O atoms from the Si atoms according to the following formula:

[0035] Equation 1: Si + O + H₂O → Si + (OH)₂

[0036] like Figure 4 As shown, a first OH layer 400 is formed in the first wafer interface region 107 and a second OH layer is formed in the second wafer interface region 130 by treatment with deionized water. The first wafer interface region 107 and the second wafer interface region 130 may be treated with deionized H2O in the same chamber or in different chambers.

[0037] Figure 5 and Figure 6 Two different processes are shown for forming an oxide layer in at least some of the boundary portions 128 of the second wafer 103. Figure 5 The formation of the oxide layer (SiO2) is shown throughout the boundary portion 128. Figure 6 This illustrates the formation of an oxide layer primarily in the boundary portion 128 adjacent to the second wafer interface region 130. The formation of the oxide layer in the boundary portion 128 of the second wafer 103 can be achieved by means of… Figure 5 The process shown or Figure 6 The process shown in the figure occurs.

[0038] Figure 5The diagram illustrates a thermal process 500 (heat treatment) for forming a thermal oxide layer in the boundary portion 128 of the second wafer 103. The thermal oxide layer is formed inside a heated chamber, boiler, or other suitable temperature-controlled environment. The layer is formed by subjecting the second wafer 103 to an oxygen (O2) environment and a temperature of 1000 degrees Celsius for one hour. A thermal oxide layer of considerable depth. According to some embodiments, the thermal oxide layer is SiO2 and is formed by a molecular reaction between the Si of the second wafer 103 and the O2 experienced by the second wafer 103.

[0039] Equation 2: Si + O2 + heat → SiO2

[0040] At a thickness of 1000 angstroms, the thermal oxide layer of the second wafer 103 reacts well with the interface region 107 of the first wafer, as will be discussed below. Figure 10 During the subsequent annealing process described, covalent bonds are formed between the first wafer 102 and the second wafer 103.

[0041] Figure 6 A plasma treatment 600 is shown for forming an oxide layer in the boundary portion 128 of the second wafer 103 by applying plasma directed to the second wafer interface region 130. Compared with the thermal process 500 in which a thermal oxide layer is formed around the entire boundary portion 128 of the second wafer 103, the SiO2 oxide layer is mainly formed in the boundary portion 128 adjacent to the second wafer interface region 130 by means of the plasma treatment 600.

[0042] Plasma processing 600 includes subjecting the second wafer 103 to a high-density plasma (HDP) environment within a chamber. Plasma processing 600 also includes subjecting the second wafer 103 to an environment of silane (SiH4) and nitrous oxide (N2O), and applying a bias voltage directed at the interface region 130 of the second wafer.

[0043] Equation 3: SiH4 + N2O + voltage → SiO2 + (H2 + N2)

[0044] A 1000 angstrom-sized wafer is formed by subjecting the second wafer 103 to an environment of SiH4 and N2O at 300 degrees Celsius for one hour and guiding a voltage toward the interface region of the second wafer. A SiO2 oxide layer of a certain depth. At a thickness of 1000 angstroms, the oxide layer of the second wafer 103, formed by plasma treatment 600, reacts well with the interface region 107 of the first wafer, as described below. Figure 10 During the subsequent annealing process described, covalent bonds are formed between the first wafer 102 and the second wafer 103.

[0045] refer to Figure 7Regardless of whether the SiO2 oxide layer is formed via thermal process 500 or plasma treatment 600, the first wafer interface region 107 and the second wafer interface region 130 are aligned, for example, overlapping or vertically coinciding with each other, and pressed together by applying at least one of a first pressure P1 to the oxide protective layer 131 in the direction toward the second wafer interface region 130 or a second pressure P2 to the boundary portion 128 in the direction toward the first wafer interface region 107. Due to the force of at least one of the first pressure P1 or the second pressure P2, the SiO2 molecules at the second wafer interface region 130 combine with the Si atoms at the first wafer interface region 107 by means of van der Waals interactions to form Si-SiO2 surface bonds. Figure 8 As shown, Si-SiO2 surface bonding bonds the first wafer 102 to the second wafer 103.

[0046] refer to Figure 9 and Figure 10 For clarity of presentation, the Si-SiO2 surface bonding between the first wafer 102 and the second wafer 103 is not shown. Figure 9 and Figure 10 An annealing process 900 is shown for forming Si-O-Si covalent bonds at the interface 902 of the first wafer interface region 107 and the second wafer interface region 130. In some embodiments, the annealing process 900 includes subjecting the interface 902 of the first wafer interface region 107 and the second wafer interface region 130 to 350 degrees Celsius for three hours. Because Si-O-Si covalent bonds are formed at the interface 902 of the first wafer interface region 107 and the second wafer interface region 130, H atoms combine with O atoms to form H₂O as a byproduct. Other temperatures and / or annealing times for forming Si-O-Si covalent bonds between the first wafer 102 and the second wafer 103 are within the range of this disclosure.

[0047] refer to Figure 11 and Figure 12 In this embodiment, the semiconductor configuration 100 is inverted to reduce the thickness "t2" 1100 of the second wafer 103 by removing the base portion 1102. According to some embodiments, the semiconductor configuration 100 is rotated 180 degrees or inverted to facilitate the removal of the base portion 1102. The base portion 1102 is removed by at least one of wafer backside grinding, liquid etching, dry etching, plasma etching, chemical mechanical polishing, planarization, or other suitable techniques. The thickness of the base portion 1102 is "t3" 1104. Other processes for removing the base portion 1102 are within the scope of this disclosure.

[0048] Removing the base portion 1102 of the second wafer 103 reduces the thickness of the second wafer 103 from "t2" 1100 to "t4" 1200, thereby reducing the combined thickness "t5" 1202 of the first wafer 102 and the second wafer 103. According to some embodiments, after removing the base portion 1102 of the second wafer 103, the combined thickness "t5" 1202 of the first wafer 102 and the second wafer 103 is between 775 micrometers (μm) and 1,300 micrometers. The combined thickness "t5" 1202 between 775 micrometers and 1,300 micrometers reduces the weight of the semiconductor configuration 100, but enhances structural integrity due to the addition of the second wafer 103. As explained below, enhancing the structural integrity of the semiconductor configuration 100 reduces the warpage of the first wafer 102, thereby reducing or eliminating performance constraints on the semiconductor configuration 100 that would otherwise result from undesirable warpage of the first wafer 102.

[0049] As illustrated, the thickness "t1" 101 of the first wafer 102 is 775 micrometers, resulting in a warpage of 1,306 micrometers for the first wafer 102, and the combined thickness "t5" 1202 of the first wafer 102 and the second wafer 103 is 950 micrometers, resulting in a warpage of 1,086 micrometers for the first wafer 102. The combined thickness "t5" 1202 of 950 micrometers advantageously reduces the warpage of the first wafer 102 by 17% compared to the thickness of 775 micrometers. Furthermore, the combined thickness "t5" 1202 of the first wafer 102 and the second wafer 103, which is less than 1,300 micrometers, does not excessively increase the weight of the semiconductor configuration 100.

[0050] As illustrated, the thickness "t1" 101 of the first wafer 102 is 775 micrometers, resulting in a warpage of 185 micrometers for the first wafer 102, and the combined thickness "t5" 1202 of the first wafer 102 and the second wafer 103 is 958 micrometers, resulting in a warpage of 160 micrometers for the first wafer 102. The combined thickness "t5" 1202 of 958 micrometers advantageously reduces the warpage of the first wafer 102 by 23% compared to the thickness of 775 micrometers. Other combined thicknesses of the first wafer 102 and the second wafer 103 are within the scope of this disclosure.

[0051] According to some embodiments, the combined thickness “t5” 1202 is determined based on the Stoney Equation. The Stoney Equation determines the stress (σ) imposed on the film formed over the wafer, for example, by referring to... Figure 14 The layered basis discussed is the membrane and the layer. The Stony equation is:

[0052] σ=(E / (6·(1-v)))·(ts / tf)·(1 / Rσ)

[0053] Where E is Young's modulus, v is Poisson's ratio, ts is wafer thickness, tf is the thickness of the film or layer formed on the wafer, and Rσ is the radius of curvature of the wafer. According to the Stony equation, as the wafer thickness increases, the radius of curvature of the film or layer formed on the wafer increases. Therefore, increasing the wafer thickness provides a larger radius of curvature and lower stress on the film or layer formed on the wafer.

[0054] refer to Figure 13 After removing the base portion 1102 of the second wafer 103, the semiconductor configuration 100 is (again) rotated 180 degrees or reversed, and the oxide protective layer 131 is removed. The oxide protective layer 131 is removed by at least one of liquid etching, dry etching, plasma etching, chemical mechanical polishing, planarization, or other suitable techniques.

[0055] refer to Figure 14 A layered base 132 is formed over the passivation layer 110. In some embodiments, the layered base 132 includes at least one of the following: a silicon layer 134 over the passivation layer 110, a colloidal layer 136 over the silicon layer 134, a first insulating layer 138 over the colloidal layer 136, a first passivation layer 140 over the first insulating layer 138, a second insulating layer 142 over the first passivation layer 140, a second passivation layer 144 over the second insulating layer 142, or a polyimide layer 146 over the second passivation layer 144. Other configurations and / or compositions of the layered base 132 are within the scope of this disclosure.

[0056] Each layer in the layered base 132 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, oxidation, passivation processes, or other suitable techniques. Other techniques for forming each layer in the layered base 132 are within the scope of this disclosure.

[0057] refer to Figure 15 The semiconductor configuration 100 includes an etch stop layer 147 above a layered base 132. The etch stop layer 147 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, LPE, or other suitable techniques. The etch stop layer 147 comprises at least one of silicon oxynitride (SiON), SiN, SiC, carbon-doped silicon oxide, or other suitable materials. Other compositions and / or techniques for forming the etch stop layer 147 are within the scope of this disclosure.

[0058] In some embodiments, the semiconductor configuration 100 includes a first magnetic material layer 148 above an etch-stop layer 147. The composition of the first magnetic material layer 148 comprises at least one of a metallic magnetic material or a soft ferrite magnetic material. The metallic magnetic material is at least one of Fe, oriented FeSi, unoriented FeSi, FeNi, FeCo, FeSiBNbCu, CoZrTa, or other suitable materials. The soft ferrite magnetic material is at least one of MnZn, NiZn, Fe2O3, or other suitable materials. Other compositions of the first magnetic material layer 148 are within the scope of this disclosure.

[0059] Semiconductor configuration 100 includes electronic components above a first magnetic material layer 148. In some embodiments, semiconductor configuration 100 includes a low-noise amplifier, a voltage-controlled oscillator, an impedance matching circuit, or an integrated voltage regulator including electronic components 150 (e.g., on-chip inductors or a plurality of densely packed on-chip inductors) above the first magnetic material layer 148. Electronic components 150 are electrically coupled to interconnects 152. According to some embodiments, interconnects 152 are post-passivated interconnects. Other electronic components and / or interconnects are within the scope of this disclosure.

[0060] In some semiconductor configurations 100, the mass of on-chip electronic components 150 (e.g., on-chip inductors or a plurality of densely packed on-chip inductors) causes the device wafer (e.g., first wafer 102) to warp to an undesirable degree. For example, in some embodiments, the mass of the on-chip inductor or a plurality of densely packed on-chip inductors causes the device wafer to warp by more than 1,300 micrometers. Warping of the device wafer can impose an undesirable degree of pressure on one or more films or layers formed over the device wafer. Such films or layers may include the references above. Figure 14 The film or layer of the layered base 132 discussed. Depending on the degree of stress imposed on one or more of the films or layers due to the mass of the electronic component 150, the structure, composition, or function of one or more of the films or layers may be adversely affected. Adverse effects may include undesirable thin or "soft" regions forming the film or layer. Thin or "soft" regions of the film or layer may constrain or impair functional purposes, such as constraining or impairing the adhesive function of the colloidal layer 136. Furthermore, constraining or impairing the functional purpose of the film or layer may consequently constrain or impair the intended functional or performance level of the semiconductor configuration 100.

[0061] As explained above, the addition of a carrier wafer (e.g., second wafer 103) bonded to the underside of the device wafer provides at least one of the rigidity or structural integrity of the semiconductor configuration 100 and reduces or eliminates device wafer warpage, thereby reducing or eliminating the degree of stress imposed on one or more films or layers. In some embodiments, the addition of the carrier wafer reduces wafer warpage from more than 1,300 micrometers to less than 1,100 micrometers.

[0062] refer to Figure 16 The semiconductor configuration 100 includes a polyimide layer 154 above at least one of the electronic components 150 or interconnects 152. The polyimide layer 154 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, oxidation, passivation processes, or other suitable techniques. The polyimide layer 154 improves the stability of at least one of the electronic components 150 or interconnects 152.

[0063] refer to Figure 17 The semiconductor configuration 100 includes a colloidal layer 156 above a polyimide layer 154 and an etch stop layer 158 above the colloidal layer 156. The colloidal layer 156 adheres the etch stop layer 158 to the polyimide layer 154.

[0064] At least one of the etch stop layer 158 or the colloidal layer 156 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, LPE, or other suitable techniques. The colloidal layer 156 comprises one or more of polymeric materials, silica materials, epoxy resin materials, phenolic materials, acrylic materials, photoresist materials, or other suitable materials. The etch stop layer 158 comprises at least one of silicon oxynitride (SiON), SiN, SiC, carbon-doped silicon oxide, or other suitable materials. Other compositions and / or techniques for forming at least one of the colloidal layer 156 or the etch stop layer 158 are within the scope of this disclosure.

[0065] Semiconductor configuration 100 includes a second magnetic material layer 160 above an etch-stop layer 158. The composition of the second magnetic material layer 160 comprises at least one of a metallic magnetic material or a soft ferrite magnetic material. The metallic magnetic material is at least one of Fe, oriented FeSi, unoriented FeSi, FeNi, FeCo, FeSiBNbCu, CoZrTa, or other suitable materials. The soft ferrite magnetic material is at least one of MnZn, NiZn, Fe2O3, or other suitable materials. Other compositions of the second magnetic material layer 160 are within the scope of this disclosure.

[0066] Semiconductor configuration 100 includes a magnetic VIA 162 coupling a second magnetic material layer 160 to a first magnetic material layer 148. Magnetic VIA 162 completes a path for magnetic flux. Magnetic flux significantly increases the inductance of electronic component 150. Other structures that increase the inductance of electronic component 150 are within the scope of this disclosure.

[0067] refer to Figure 18 The semiconductor configuration 100 includes a reinforcing structure 164 for reinforcing and protecting the electronic component 150 from environmental conditions. The reinforcing structure 164 is at least one of the following: above the electronic component 150; directly above and completely covering the electronic component 150; indirectly above and completely covering the electronic component 150; directly above and partially covering the electronic component 150; or indirectly above and partially covering the electronic component 150.

[0068] The reinforcing structure 164 comprises at least one of a polymer layer, a polyimide layer, or other suitable materials. The reinforcing structure 164 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, oxidation, passivation processes, or other suitable techniques. Other configurations and / or compositions of the reinforcing structure 164 are within the scope of this disclosure.

[0069] Figure 19 This is an illustration of a method 1900 for manufacturing a semiconductor configuration according to some embodiments. At step 1902, the method 1900 for manufacturing a semiconductor configuration includes exposing a first silicon wafer to oxygen to form a first silicon dioxide layer in a first wafer interface region of the first wafer, and exposing a second silicon wafer to oxygen to form a second silicon dioxide layer in a second wafer interface region of the second wafer. At step 1904, the first and second wafers are treated with plasma to form suspended Si-O bonds in the first and second wafer interface regions. At step 1906, the method includes treating the first and second wafer interface regions with deionized water molecules to form hydroxide ions in the first and second wafer interface regions. At step 1908, the second wafer is subjected to heat treatment in an oxygen and heated environment, or subjected to a high-density plasma environment to form an oxide layer in the second wafer interface region. At step 1910, the method includes applying pressure to at least one of the first or second wafers in a direction toward the first and second wafer interface regions to bond the first wafer to the second wafer. At step 1912, the method includes subjecting the first wafer and the second wafer to an annealing process to covalently bond the first wafer to the second wafer. At step 1914, the thickness of the semiconductor configuration can be reduced by removing a portion of the second wafer from the semiconductor configuration.

[0070] Figure 20 Exemplary computer-readable media according to some embodiments are shown. One or more embodiments relate to computer-readable media including processor-executable instructions configured to implement one or more technologies presented herein. Figure 20 Exemplary computer-readable media are illustrated herein, wherein embodiment 2000 includes a computer-readable medium 2006 (e.g., a CD-R, DVD-R, flash drive, hard disk, etc.) on which computer-readable data 2004 is encoded. This computer-readable data 2004 then includes a set of processor-executable computer instructions 2002, which, when executed, are configured to facilitate one or more operations according to the principles set forth herein. In some embodiments 2000, the processor-executable computer instructions 2002 are configured to facilitate the performance of a method 2001 (e.g., at least some of the foregoing methods). In some embodiments, the processor-executable computer instructions 2002 are configured to facilitate the implementation of a system (e.g., at least some of the foregoing systems). Those skilled in the art can design numerous configurations to operate according to the techniques presented herein for such computer-readable media.

[0071] As disclosed, resistance to warpage of the semiconductor configuration is increased by covalently bonding a carrier wafer to a device wafer to increase the rigidity or structural integrity of the semiconductor configuration. Covalent bonds are formed at the interface region between the carrier wafer and the device wafer. The method for forming covalent bonds includes first forming van der Waals bonds at the interface region between the device wafer and the carrier wafer by applying pressure / force toward the interface region. The bonded device wafer and carrier wafer are then subjected to an annealing process to form Si-O-Si covalent bonds at the interface region. The thickness of the semiconductor configuration is reduced by removing a substrate portion of the carrier wafer. Reducing the thickness of the carrier wafer reduces the weight of the semiconductor configuration while maintaining a sufficient increase in the rigidity of the semiconductor configuration to suppress device wafer warpage. Due to the heavy and / or densely distributed electronic components in and / or on the device wafer, the degree of warpage of the semiconductor configuration is less than that of a semiconductor configuration that does not include a carrier wafer bonded to the device wafer.

[0072] A method of manufacturing a semiconductor configuration includes: forming a first molecular ion layer in a first wafer interface region of a first wafer; forming a second molecular ion layer in a second wafer interface region of a second wafer; forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region; and annealing the first wafer and the second wafer to form the second molecular bond connecting the first wafer interface region to the second wafer interface region.

[0073] In some embodiments, forming the first molecular ion layer includes forming a first hydroxide layer in the first wafer interface region; and forming the second molecular ion layer includes forming a second hydroxide layer in the second wafer interface region. In some embodiments, forming the second molecular bond includes: forming a first silicon dioxide layer in the first wafer interface region by exposing the first wafer interface region to oxygen before annealing the first wafer and the second wafer; and forming a second silicon dioxide layer in the second wafer interface region by exposing the second wafer interface region to oxygen before annealing the first wafer and the second wafer. In some embodiments, forming the first molecular ion layer includes treating the first wafer interface region with argon plasma after forming the first silicon dioxide layer in the first wafer interface region; and forming the second molecular ion layer includes treating the second wafer interface region with argon plasma after forming the second silicon dioxide layer in the second wafer interface region. In some embodiments, forming the first molecular ion layer includes treating the first wafer interface region with deionized water after treating it with argon plasma; and forming the second molecular ion layer includes treating the second wafer interface region with deionized water after treating it with argon plasma. In some embodiments, the second molecular bond is a silicon-oxygen-silicon covalent bond. In some embodiments, forming the first molecular bond connecting the first wafer interface region to the second wafer interface region includes forming a silicon dioxide layer in the second wafer interface region. In some embodiments, forming the silicon dioxide layer in the second wafer interface region includes thermally treating the second wafer to grow a thermal oxide layer in the second wafer interface region. In some embodiments, forming the silicon dioxide layer in the second wafer interface region includes subjecting the second wafer interface region to a high-density plasma environment. In some embodiments, the method includes reducing the thickness of the second wafer.

[0074] A method for manufacturing a semiconductor configuration includes: performing plasma treatment on a first wafer interface region of a first wafer; performing plasma treatment on a second wafer interface region of a second wafer; treating the first wafer interface region with deionized water after performing plasma treatment on the first wafer interface region of the first wafer; treating the second wafer interface region with deionized water after performing plasma treatment on the second wafer interface region of the second wafer; forming a silicon dioxide layer in the second wafer interface region after treating the second wafer interface region with deionized water; aligning a first surface of the first wafer interface region with a second surface of the second wafer interface region; applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region after aligning the first surface of the first wafer interface region with the second surface of the second wafer interface region; and annealing the first wafer and the second wafer to form molecular bonds connecting the first wafer interface region to the second wafer interface region.

[0075] In some embodiments, forming the molecular bonds connecting the first wafer interface region to the second wafer interface region includes forming silicon-oxygen-silicon molecules at the interface between the first and second wafer interface regions. In some embodiments, forming the silicon dioxide layer in the second wafer interface region includes thermally treating the second wafer to grow a thermal oxide layer in the second wafer interface region. In some embodiments, forming the silicon dioxide layer in the second wafer interface region includes subjecting the second wafer interface region to a high-density plasma environment. In some embodiments, the high-density plasma environment includes silane plasma and nitrous oxide plasma. In some embodiments, the method includes reducing the thickness of the second wafer.

[0076] A method for manufacturing a semiconductor configuration includes: forming a first silicon-oxygen molecular layer at a first wafer interface region of a first wafer; forming a second silicon-oxygen molecular layer at a second wafer interface region of a second wafer; treating the first silicon-oxygen molecular layer and the second silicon-oxygen molecular layer with deionized water molecules; aligning a first surface of the first wafer interface region with a second surface of the second wafer interface region; and annealing the first wafer and the second wafer to form covalent silicon-oxygen-silicon bonds at the interface between the first surface of the first wafer interface region and the second surface of the second wafer interface region to bond the first wafer to the second wafer.

[0077] In some embodiments, the method includes: forming a silicon dioxide layer in a second wafer interface region after treating the second silicon-oxygen molecular layer with the deionized water molecules; and applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region to bond the first wafer to the second wafer after aligning the first surface of the first wafer interface region with the second surface of the second wafer interface region. In some embodiments, the method includes: forming a doped region in an implantation region of the first wafer before forming the first silicon-oxygen molecular layer at the first wafer interface region of the first wafer. In some embodiments, the method includes: coupling an electronic component to a top surface of the first wafer; and reducing the combined thickness of the first wafer and the second wafer to a thickness in the range of 775 micrometers to 1,300 micrometers after annealing the first wafer and the second wafer.

[0078] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0079] Although the subject matter has been described in language specifically targeting structural features or methodological actions, it should be understood that the subject matter in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as examples of implementing at least some of the claims.

[0080] Various operations are provided in the embodiments herein. The description of some or all of the operations in order should not be construed as implying that these operations necessarily depend on the order. It will be understood that alternative orders have the benefit of this description. Furthermore, it will be understood that not all operations are necessarily present in every embodiment provided herein. In addition, it will be understood that not all operations are necessarily present in some embodiments.

[0081] It will be understood that the layers, features, elements, etc., described herein are shown with respect to each other at specific dimensions (e.g., structural dimensions or orientations). For example, for simplicity and ease of understanding, in some embodiments, the same actual dimensions may differ substantially from those shown herein. Furthermore, various techniques exist for forming the layers, regions, features, elements, etc., mentioned herein, such as at least one of etching, planarization, implantation, doping, spin coating, sputtering, growth, or deposition techniques such as CVD.

[0082] Furthermore, “exemplary” is used herein to mean serving as an example, situation, illustration, etc., and is not necessarily advantageous. As used herein, “or” is intended to mean inclusive “or” rather than exclusive “or.” Additionally, unless otherwise specified or clearly understood from the context relating to the singular form, “a” and “an” as used in this application and the appended claims are generally interpreted as meaning “one or more.” Furthermore, at least one of A and B and / or similar terms generally mean A or B or both A and B. Moreover, with regard to the use of “comprising,” “having,” “has,” “with” (or variations thereof), such terms are intended to be inclusive in a manner similar to the term “including.” Additionally, unless otherwise specified, “first,” “second,” or similar terms are not intended to imply temporal, spatial, or sequential aspects. Rather, these terms are used only as identifiers, names, etc., of features, elements, articles, etc. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0083] Furthermore, while this disclosure has been illustrated and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the foregoing components (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe these components are intended to correspond to any component that performs the specified function of the described component (e.g., functionally equivalent), even if structurally not equivalent to the disclosed structure. Additionally, while specific features of this disclosure may have been disclosed with respect to only one of several embodiments, these features may be combined with one or more other features of other embodiments, which may be desirable and advantageous for any given or particular application.

Claims

1. A method for manufacturing a semiconductor configuration, the method comprising: A first hydroxide layer is formed in the first wafer interface region of the first wafer; A second hydroxide layer is formed in the second wafer interface region of the second wafer; After the second hydroxide layer is formed, a silicon dioxide layer is formed in the second wafer interface region by heat treatment or a high-density plasma environment. By applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, silicon dioxide molecules in the silicon dioxide layer at the second wafer interface region combine with silicon atoms at the first wafer interface region to form a Si-SiO2 surface bond; and The first wafer and the second wafer are annealed to form molecular bonds that connect the interface region of the first wafer to the interface region of the second wafer.

2. The method for manufacturing a semiconductor configuration according to claim 1, comprising: Before forming the first hydroxide layer, a first silicon dioxide layer is formed in the first wafer interface region by exposing the first wafer interface region to oxygen; as well as Before forming the second hydroxide layer, a second silicon dioxide layer is formed in the second wafer interface region by exposing the second wafer interface region to oxygen.

3. The method for manufacturing a semiconductor configuration according to claim 2, wherein: Forming the first hydroxide layer includes treating the first wafer interface region with argon plasma after forming the first silicon dioxide layer in the first wafer interface region; and Forming the second hydroxide layer includes forming the second silicon dioxide layer in the second wafer interface region and then treating the second wafer interface region with argon plasma.

4. The method for manufacturing a semiconductor configuration according to claim 3, wherein: Forming the first hydroxide layer includes treating the first wafer interface region with deionized water after treating the first wafer interface region with argon plasma; and Forming the second hydroxide layer includes treating the second wafer interface region with deionized water after treating the second wafer interface region with argon plasma.

5. The method for manufacturing a semiconductor configuration according to claim 1, wherein the molecular bond is a silicon-oxygen-silicon covalent bond.

6. The method of manufacturing a semiconductor configuration according to claim 1, further comprising reducing the thickness of the second wafer.

7. A method for manufacturing a semiconductor configuration, the method comprising: Plasma treatment is performed on the first wafer interface region of the first wafer. Plasma treatment is performed on the second wafer interface region of the second wafer. After plasma treatment of the first wafer interface region of the first wafer, the first wafer interface region is treated with deionized water. After plasma treatment of the second wafer interface region of the second wafer, the second wafer interface region is treated with deionized water. After treating the second wafer interface region with the deionized water, a silicon dioxide layer is formed in the second wafer interface region; Align the first surface of the first wafer interface region with the second surface of the second wafer interface region; After aligning the first surface of the first wafer interface region with the second surface of the second wafer interface region, pressure is applied to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, causing silicon dioxide molecules in the silicon dioxide layer at the second wafer interface region to combine with silicon atoms at the first wafer interface region to form a Si-SiO2 surface bond; and The first wafer and the second wafer are annealed to form molecular bonds that connect the interface region of the first wafer to the interface region of the second wafer.

8. The method of manufacturing a semiconductor configuration according to claim 7, wherein forming the molecular bond connecting the first wafer interface region to the second wafer interface region includes forming silicon-oxygen-silicon molecules at the interface between the first wafer interface region and the second wafer interface region.

9. The method of manufacturing a semiconductor configuration according to claim 7, wherein forming the silicon dioxide layer in the second wafer interface region comprises thermally treating the second wafer to grow a thermal oxide layer in the second wafer interface region.

10. The method of manufacturing a semiconductor configuration according to claim 7, wherein forming the silicon dioxide layer in the second wafer interface region comprises subjecting the second wafer interface region to a high-density plasma environment.

11. The method of manufacturing a semiconductor configuration according to claim 10, wherein the high-density plasma environment comprises silane plasma and nitrous oxide plasma.

12. The method of manufacturing a semiconductor configuration according to claim 7, further comprising reducing the thickness of the second wafer.

13. A method of manufacturing a semiconductor configuration, the method comprising: A first silicon-oxygen molecular layer is formed at the first wafer interface region of the first wafer; A second silicon-oxygen molecular layer is formed at the second wafer interface region of the second wafer; The first silicon-oxygen molecular layer and the second silicon-oxygen molecular layer were treated with deionized water molecules; After treating the second silicon-oxygen molecular layer with the deionized water molecules, a silicon dioxide layer is formed in the second wafer interface region; Align the first surface of the first wafer interface region with the second surface of the second wafer interface region; The silicon dioxide molecules in the silicon dioxide layer at the second surface combine with the silicon atoms at the first surface to form a Si-SiO2 surface bond. as well as The first wafer and the second wafer are annealed to form covalent silicon-oxygen-silicon bonds at the interface between the first surface of the first wafer interface region and the second surface of the second wafer interface region to bond the first wafer to the second wafer.

14. The method of manufacturing a semiconductor configuration according to claim 13, comprising: After aligning the first surface of the first wafer interface region with the second surface of the second wafer interface region, pressure is applied to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region to bond the first wafer to the second wafer.

15. The method of manufacturing a semiconductor configuration according to claim 13, comprising forming a doped region in an implantation region of the first wafer before forming the first silicon-oxygen molecular layer at the first wafer interface region of the first wafer.

16. The method of manufacturing a semiconductor configuration according to claim 13, comprising: Electronic components are coupled to the upper surface of the first wafer; as well as After annealing the first wafer and the second wafer, the combined thickness of the first wafer and the second wafer is reduced to a thickness in the range of 775 micrometers to 1,300 micrometers.

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