A method for fabricating double inlay with through holes

Abstract

This application relates to the field of semiconductor manufacturing, specifically to a dual damascene method for vias, comprising the following steps: forming a via in a dielectric layer of a semiconductor substrate; forming a water-soluble polymer layer above the dielectric layer and inside the via; sequentially forming a hard mask layer, a bottom anti-reflective layer, and a photoresist pattern on the water-soluble polymer layer; performing photolithography and etching processes to form a trench above the via communicating with the via; and filling the via and the trench with Cu.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for dual damascene assembly with vias. Background Technology

[0002] In semiconductor manufacturing, dual damascene processes (also known as dual damascene processes) are frequently used to form vias and trenches. This involves depositing Cu, W, and Si in a single deposition process, followed by a planarization process. The order in which these processes are performed determines whether the vias or trenches are etched first. Currently, the dual damascene process with vias etched first is more commonly used. Figure 1-4 As shown, in the process of etching through-holes first, the through-hole pattern is formed first, specifically by etching through-hole 10' to the etching stop layer. Then, organic material 11' is filled into through-hole 10' to protect it. Next, the trench 12' is etched. However, the corrosion-resistant organic material 11' will adhere to the wall surface of through-hole 10'. When the trench 12' is formed, oxide barriers 13' are often generated. Usually, a separate etching process is required to remove the oxide barriers 13', which increases the number of process steps and causes the trench pattern to be damaged. Summary of the Invention

[0003] This application addresses, to at least part of the aforementioned technical problems in related technologies. To this end, this application proposes a pre-via dual-stacking method to solve at least one of the aforementioned technical problems.

[0004] To achieve the above objectives, the first aspect of this application provides a method for dual damascene mounting with through-holes, comprising the following steps:

[0005] Forming vias within the dielectric layer of a semiconductor substrate;

[0006] A water-soluble polymer layer is formed above the dielectric layer and inside the through-hole;

[0007] A spin-coated hard mask layer, a bottom anti-reflection layer, and a photoresist pattern are sequentially formed on the water-soluble polymer layer;

[0008] Perform photolithography and etching processes to form a trench above the through hole that communicates with the through hole;

[0009] A metal layer is filled into the through hole and the trench. Attached Figure Description

[0010] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0011] Figure 1 This diagram illustrates the structure after the through-hole is formed in the prior art.

[0012] Figure 2 This diagram illustrates the structure before etching to form trenches in the prior art.

[0013] Figure 3 It shows Figure 2 A schematic diagram of the structure after the trench is formed;

[0014] Figure 4 It shows Figure 3 Scanning electron microscope image;

[0015] Figure 5 A schematic diagram of the structure after coating a bottom anti-reflective layer and photoresist on a semiconductor substrate is shown;

[0016] Figure 6 It shows Figure 5 A schematic diagram of the structure after the photoresist pattern has been formed;

[0017] Figure 7 It shows Figure 6 A schematic diagram of the structure after the through-hole is formed;

[0018] Figure 8 It shows Figure 7 A schematic diagram of the structure after coating with a water-soluble polymer layer;

[0019] Figure 9 It shows Figure 8 A schematic diagram of the structure after the photoresist pattern has been formed;

[0020] Figure 10 The performance curves of polyvinyl alcohol are shown.

[0021] Figure 11 It shows Figure 9 A schematic diagram of the structure after etching the water-soluble polymer layer inside the through-hole;

[0022] Figure 12 It shows Figure 11 A schematic diagram of the structure after etching the remaining water-soluble polymer layer inside the through-hole;

[0023] Figure 13 It shows Figure 12 A schematic diagram of the structure after the complete trench is formed;

[0024] Figure 14 It shows Figure 13 Schematic diagram of the structure after Cu seed layer deposition;

[0025] Figure 15 It shows Figure 14 A schematic diagram of the structure after planarization. Detailed Implementation

[0026] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0027] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0028] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0029] Please refer to Figures 5 to 15 This invention provides a method for dual embellishment with through-holes, comprising the following steps:

[0030] like Figure 5 As shown, a semiconductor substrate 10 is provided, in which a conductive layer 11 is formed, and a first etch stop layer 12, a first interlayer dielectric layer 13, a second etch stop layer 14, a second interlayer dielectric layer 15 and a third etch stop layer 16 are formed sequentially from bottom to top on the semiconductor substrate 10. The first etch stop layer 12, the first interlayer dielectric layer 13, the second etch stop layer 14, the second interlayer dielectric layer 15 and the third etch stop layer 16 constitute a dielectric layer.

[0031] Specifically, the semiconductor substrate 10 may comprise any known silicon-based semiconductor material, including silicon, silicon-germanium, silicon-on-insulator, or sapphire-on-silicon substrates. Optionally, the semiconductor substrate 10 may comprise a silicon layer formed on a non-silicon-based semiconductor material, such as gallium arsenide, germanium, gallium nitride, or aluminum-phosphorus. In some embodiments, the semiconductor substrate 10 is a doped or undoped silicon substrate.

[0032] The conductive layer 11 may include a copper conductive layer, the first etch stop layer 12, the second etch stop layer 14, and the third etch stop layer 16 may be made of silicon nitride, and the first interlayer dielectric layer 13 and the second interlayer dielectric layer 15 may be made of oxide.

[0033] Next, refer to Figure 5-6 A bottom antireflective coating (BARC) 17 and a photoresist 18 are coated from bottom to top on the semiconductor substrate 10, and the photoresist 18 is patterned to form a photoresist pattern.

[0034] Next, please refer to Figure 7 Using the photoresist pattern as a mask, the bottom anti-reflection layer 17, the third etch stop layer 16, the second interlayer dielectric layer 15, the second etch stop layer 14 and the first interlayer dielectric layer 13 are etched sequentially from top to bottom until the first etch stop layer 12 is exposed. The bottom anti-reflection layer 17 and the photoresist 18 are then removed to form a via 19.

[0035] Next, please refer to Figure 8 A water-soluble polymer layer 20 is coated on the surface of the third etch stop layer 16 and inside the via 19. Specifically, in this embodiment, the water-soluble polymer layer 20 can be polyvinyl alcohol, and the thickness of the water-soluble polymer layer is [missing information].

[0036] Next, please refer to Figure 9 A spin-coated hard mask layer 21, a SiON layer, a bottom anti-reflection layer 22, and a photoresist 18 are sequentially formed on a water-soluble polymer layer 20. The photoresist 18 is patterned to form a photoresist pattern. It is worth mentioning that the opening shape of the photoresist pattern corresponds to the shape of the trench to be formed, and the via 19 is located inside the opening of the photoresist pattern.

[0037] Commonly used hard mask materials include metals, metal oxides such as iron oxide, silicon oxides, and amorphous carbon. The following examples use amorphous carbon as an example; therefore, the influence of parameters such as the given reaction gases on the amorphous carbon will be considered. The thickness of photoresist 18 is... The thickness of the SiON layer is The thickness of the spin-coated hard mask layer 21 is The process conditions for forming the spin-coated hard mask layer are as follows: after coating the spin-coated hard mask layer 21, bake at 300-400℃ for 30-120 seconds. It is worth mentioning that, since the water-soluble polymer layer 20 is polyvinyl alcohol with a low glass transition temperature (Tg), such as... Figure 10As shown, the Tg value of polyvinyl alcohol is between 200-500℃. During the baking process of spin-coated hard mask layer 21, it will not be affected by baking and will adhere to the inner wall of through hole 19, thereby avoiding the problem of gate formation during subsequent trench etching.

[0038] Next, please refer to Figure 11 The etching process removes the water-soluble polymer layer 20 on the surface of the spin-coated hard mask layer 21, SiON layer, bottom anti-reflection layer 22, and third etch stop layer 16 corresponding to the opening of the photoresist pattern, as well as a portion of the water-soluble polymer layer 20 inside the via 19. At this time, a portion of the water-soluble polymer layer 20 remains inside the via 19, and the surface of the third etch stop layer 16 is exposed. It is worth mentioning that the etching rate of the water-soluble polymer layer 20 is greater than that of the hard mask layer 21. In this way, the water-soluble polymer layer 20 can be quickly etched away during the above etching process, thereby avoiding the problem of forming a barrier.

[0039] In the above steps, a portion of the water-soluble polymer layer 20 is consumed, causing the height of the water-soluble polymer layer 20 within the via 19 to decrease, and the height of the water-soluble polymer layer 20 is, for example, lower than the second etch stop layer 14.

[0040] Next, please refer to Figure 12 Continue etching to remove the remaining water-soluble polymer layer 20 inside the via 19, and at the same time remove the water-soluble polymer layer 20 on the surface of the spin-coated hard mask layer 21, SiON layer, bottom anti-reflection layer 22 and third etch stop layer 16 until the surface of the third etch stop layer 16 is exposed.

[0041] Next, please refer to Figure 13 The etching continues to remove the portion of the second etch stop layer 14 located within the opening until the portion of the second interlayer dielectric layer 15 located within the opening is exposed, thus forming a complete trench 23. The trench 23 is located directly above the through hole 19 and communicates with the through hole 19. The through hole 19 is located at the bottom of the trench 23, and the opening size of the through hole 19 is smaller than the opening size of the trench 23.

[0042] The etching medium used in the above steps is, for example, a mixture of CF4, CHF3, Ar, and a small amount of C4F8 and O2.

[0043] Next, please refer to Figure 14 A Cu seed layer is deposited in the through-hole 19, thereby depositing a metal Cu layer 24 in the trench 23 and on the surface of the third etch stop layer 16.

[0044] Next, please refer to Figure 15The metal Cu layer 24 is planarized, and the metal Cu layer on the surface of the third etch stop layer 16 is removed, thereby forming a dual damascene structure.

[0045] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0046] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A first via dual damascene method, characterized by, The method comprises the following steps: forming a via in a dielectric layer of a semiconductor substrate; forming a water-soluble polymer layer above the dielectric layer and in the via; forming a spin-on hard mask layer, a bottom anti-reflective layer and a photoresist pattern on the water-soluble polymer layer in sequence; performing a lithography and etching process to form a trench communicating with the via above the via; filling a metal layer in the via and the trench.

2. The first via dual damascene method according to claim 1, wherein, The water-soluble polymer layer has a Tg value ranging from 200℃ to 500℃.

3. The first via dual damascene process of claim 1, wherein, The etching rate of the water-soluble polymer layer is greater than the etching rate of the hard mask layer.

4. The first via dual damascene method according to claim 2 or 3, characterized by, The water-soluble polymer layer comprises polyvinyl alcohol.

5. The first via dual damascene process of claim 4, wherein, The thickness of the water-soluble polymer layer over the medium layer is 6. The first via dual damascene process of claim 5, wherein, The thickness of the hard mask layer is 100-2000 angstroms The process condition for forming the hard mask layer is to perform baking at 300-400 degrees Celsius for 30-120 seconds after completing the coating of the hard mask layer.

7. The first via dual damascene process of claim 6, wherein, The thickness of the photoresist pattern is 8. The first via dual damascene process of claim 1, wherein, The step of forming a via comprises: forming a bottom anti-reflective layer and a photoresist pattern on the dielectric layer; performing a lithography and etching process to remove the photoresist pattern.

9. The first via dual damascene process of claim 8, wherein, The dielectric layer comprises three etching stop layers and two interlayer dielectric layers formed on the semiconductor substrate, and one interlayer dielectric layer is arranged between each two etching stop layers; The etching process is performed in three steps, comprising: first, etching to remove the spin-on hard mask layer, the bottom anti-reflective layer and part of the water-soluble polymer layer corresponding to the photoresist pattern opening; second, etching to remove the dielectric layer corresponding to the photoresist pattern opening until the middle etching stop layer is exposed; finally, etching to remove the middle etching stop layer and the bottom etching stop layer until the upper surface of the semiconductor substrate is exposed.

10. The first via dual damascene process of claim 6, wherein, Further comprising: A SiON layer is formed between the spin-on hard mask layer and the bottom anti-reflective layer, the thickness of the SiON layer is

Images