Packaging structures for semiconductor devices

Abstract

A package structure is provided, comprising an organic interposer substrate, a semiconductor die, conductive bumps, an underfill, and an insulating encapsulator. The organic interposer substrate includes stacked organic dielectric layers and conductive wiring embedded in the stacked organic dielectric layers. The semiconductor die is disposed on and electrically connected to the conductive wiring of the organic interposer substrate, and the semiconductor die includes chamfered edges. Conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate via the conductive bumps. An underfill is disposed between the semiconductor die and the organic interposer substrate, wherein the underfill encapsulates the conductive bumps and contacts the chamfered edges of the semiconductor die. An insulating encapsulator covers the organic interposer substrate and laterally encapsulates the semiconductor die and the underfill.

Description

Technical Field

[0001] The embodiments disclosed herein relate to a packaging structure for semiconductor devices. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this improvement in integration density is due to the continuous reduction in the minimum feature size, thus allowing more components to be integrated into a specific area. With the recent increase in demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and latency, the need for smaller and more innovative semiconductor die-packaging technologies has also increased. Currently, chip-on-wafer-on-substrate (CoWoS) packaging structures are increasingly favored due to their versatility and high performance. However, challenges related to the packaging process of CoWoS structures, such as warpage issues, remain. Summary of the Invention

[0003] According to some embodiments of this disclosure, a packaging structure for a semiconductor device is provided, comprising an organic interposer substrate, a semiconductor die, conductive bumps, a first underfill adhesive, and an insulating encapsulator. The organic interposer substrate includes stacked organic dielectric layers and conductive wiring embedded in the stacked organic dielectric layers. The semiconductor die is disposed on and electrically connected to the conductive wiring of the organic interposer substrate, and the semiconductor die includes chamfered edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate via the conductive bumps. The first underfill adhesive is disposed between the semiconductor die and the organic interposer substrate, wherein the first underfill adhesive encapsulates the conductive bumps and contacts the chamfered edges of at least one semiconductor die. The insulating encapsulator covers the organic interposer substrate and laterally encapsulates at least one semiconductor die and the first underfill adhesive.

[0004] According to some other embodiments of this disclosure, a packaging structure for a semiconductor device is provided, including an interposer substrate, a semiconductor die, conductive bumps, and an underfill adhesive. The interposer substrate includes stacked dielectric layers and conductive wiring embedded in the stacked dielectric layers. The semiconductor die is disposed on and electrically connected to the interposer substrate, and the coefficient of thermal expansion of the stacked dielectric layers is greater than the coefficient of thermal expansion of the semiconductor substrate of the semiconductor die. The semiconductor die includes chamfered edges, and at least one of the chamfered edges includes a beveled surface. Conductive bumps are disposed between the semiconductor die and the interposer substrate, and the semiconductor die is electrically connected to the interposer substrate via the conductive bumps. The underfill adhesive is disposed between the semiconductor die and the interposer substrate.

[0005] According to some other embodiments of this disclosure, a packaging structure for a semiconductor device is provided, comprising an organic interposer substrate, a semiconductor die, conductive bumps, and a first underfill adhesive. The organic interposer substrate includes stacked organic dielectric layers and conductive wiring embedded in the stacked organic dielectric layers. The semiconductor die is disposed on and electrically connected to the conductive wiring of the organic interposer substrate, and the semiconductor die includes rounded edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate via the conductive bumps. The first underfill adhesive is disposed between the semiconductor die and the organic interposer substrate. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure can be achieved by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 1C This is a cross-sectional view schematically illustrating the fabrication process of a semiconductor die according to some embodiments of the present disclosure.

[0008] Figures 2A to 2D This is a cross-sectional view schematically illustrating the fabrication process of a semiconductor die according to some alternative embodiments of the present disclosure.

[0009] Figures 3A to 3G This is a cross-sectional view schematically illustrating the fabrication process of a substrate-over-wafer-over-chip (CoWoS) package structure according to some embodiments of the present disclosure.

[0010] Figures 4A to 4D This is a cross-sectional view schematically illustrating various chamfered or rounded edges according to some embodiments of the present disclosure.

[0011] Figures 5A to 5D This is a cross-sectional view schematically illustrating various chamfered or rounded edges according to some alternative embodiments of the present disclosure.

[0012] Figures 6A to 6C This is a cross-sectional view schematically illustrating various chamfered edges according to some other embodiments of the present disclosure.

[0013] Figures 7A to 7E This is a bottom view schematically illustrating various chamfered edges according to some other embodiments of the present disclosure. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the purpose of brevity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0016] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packaged or three-dimensional integrated circuit (3DIC) devices. The test structures may, for example, include test pads formed in redistribution layers or on a substrate to enable testing of the 3D package or 3D IC using probes and / or probe cards. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0017] Figures 1A to 1C This is a cross-sectional view schematically illustrating the fabrication process of a semiconductor die according to some embodiments of the present disclosure.

[0018] refer to Figure 1A A semiconductor wafer W1 is provided. The semiconductor wafer W1 may include various doped regions (e.g., p-type or n-type doped regions) formed by a front-end ofline (FEOL) fabrication process of the semiconductor wafer W1. The doped regions may be doped with p-type dopants and / or n-type dopants. The doped regions may be doped with p-type dopants such as boron or BF2, n-type dopants such as phosphorus or arsenic, and / or combinations thereof. The doped regions may be configured as n-type FinFETs, p-type FinFETs, or combinations thereof. In some other embodiments, the doped regions may be configured as n-type Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs), p-type MOSFETs, or combinations thereof. The semiconductor wafer W1 may include a semiconductor substrate 110 and an interconnect structure 120, wherein the interconnect structure 120 is disposed on the semiconductor substrate 110. In some embodiments, the semiconductor substrate 110 includes a crystalline silicon substrate. In some alternative embodiments, the semiconductor substrate 110 is made of: some other suitable elemental semiconductor, such as diamond or germanium; suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide or indium phosphide; or suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide or gallium indium phosphide.

[0019] Interconnect structure 120 may include alternately stacked interconnect wirings (e.g., copper interconnect wirings) and a dielectric layer, wherein the interconnect wirings of interconnect structure 120 are electrically connected to active and / or passive components in semiconductor substrate 110. Interconnect structure 120 is formed using a back-end ofline (BEOL) fabrication process on semiconductor wafer W1. The topmost interconnect wiring of interconnect structure 120 may include conductive pads 122, which may be aluminum pads, copper pads, or other suitable metal pads. Interconnect structure 120 may also include a passivation layer (not shown) disposed on the front surface or active surface of semiconductor wafer W1, wherein conductive pads 122 are partially covered by the passivation layer. In other words, conductive pads 122 are partially exposed from openings defined in the passivation layer. The passivation layer may be a silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or dielectric layer formed using other suitable inorganic dielectric materials. The interconnect structure 120 may further include a post-passivation layer (not shown) formed over the passivation layer, wherein the post-passivation layer covers the passivation layer and the conductive pads 122, the post-passivation layer including contact openings, and the conductive pads 122 partially exposed from the contact openings defined in the post-passivation layer. The post-passivation layer may be a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable organic dielectric materials. In some alternative embodiments, the post-passivation layer is omitted.

[0020] In some embodiments, a wafer-level bumping process is performed on the interconnect structure 120 of the semiconductor wafer W1 to form conductive terminals 124 on conductive pads 122. The conductive pads 122 of the interconnect structure 120 may be bump pads, and the conductive terminals 124 may be microbumps overlapping the conductive pads 122. The wafer-level bumping process may include: forming a patterned photoresist on the front surface or active surface of the semiconductor wafer W1, wherein the patterned photoresist includes openings exposing the conductive pads 122; depositing (e.g., plating) a conductive material on the conductive pads 122 to form conductive terminals 124 in openings defined in the patterned photoresist; and removing the patterned photoresist. In some embodiments, the conductive terminals 124 may include Cu / Ni / Au bumps, Cu / Ni bumps, Cu / Ni / Au / SnAg bumps, Cu / Ni / SnAg bumps, etc.

[0021] like Figure 1AAs described, after forming the conductive terminal 124, a beveling process is performed to form a V-shaped notch G on the front surface of the semiconductor wafer W1. The V-shaped notch G can be formed by performing a wafer dicing process along the dicing path of the semiconductor wafer W1. The V-shaped notch G can be formed using a V-shaped dicing blade B1. In some embodiments, the depth of the V-shaped notch G is less than the thickness of the interconnect structure 120, wherein the depth of the V-shaped notch G is in the range of about 5 micrometers to about 20 micrometers, and the width of the V-shaped notch G is in the range of about 10 micrometers to about 100 micrometers. In some alternative embodiments, the depth of the V-shaped notch G is greater than the thickness of the interconnect structure 120, wherein the depth of the V-shaped notch G is in the range of about 20 micrometers to about 700 micrometers, and the width of the V-shaped notch G is in the range of about 100 micrometers to about 1000 micrometers.

[0022] refer to Figure 1B and Figure 1C After performing the slant cutting process, a full slant cutting process is performed along the V-shaped notch G on the front surface of the semiconductor wafer W1 to obtain a monolithic semiconductor die 100. In some embodiments, each monolithic semiconductor die 100 includes a semiconductor substrate 110a, an interconnect structure 120a disposed on the semiconductor substrate 110a, a conductive pad 122, and a conductive terminal 124.

[0023] In some embodiments, each monolithized semiconductor die 100 includes a chamfered edge CE, and the chamfered edge CE is distributed in the peripheral region of the front surface of each semiconductor die 100. In some alternative embodiments, the chamfered edge CE is distributed on the sidewall of the semiconductor die 100 facing the supporting substrate. A full dicing process can be performed by a dicing blade B2 along a first V-shaped notch G1 formed on the semiconductor wafer W1. The width of the dicing blade B2 is smaller than the width of the V-shaped notch G. In some embodiments, the semiconductor wafer W1 is attached to a dicing strip (not shown) before performing the full dicing process.

[0024] In the top view of semiconductor die 100, as shown Figures 7A to 7E As described, at least one chamfered edge CE is distributed at one or more sidewalls of the semiconductor die 100. For example... Figure 7A As described, only one chamfered edge CE is distributed along one sidewall of the semiconductor die 100. For example... Figure 7B As illustrated, the edges CE of the two adjacent chamfers are distributed along two adjacent sidewalls of the semiconductor die 100. (As stated in the original text...) Figure 7C As explained, the two chamfered edges CE are distributed along the two opposite sidewalls of the semiconductor die 100. Figure 7D As illustrated, the three adjacent chamfered edges CE are distributed along three adjacent sidewalls of the semiconductor die 100. Figure 7EAs described, the four adjacent chamfered edges CE are distributed along the four sidewalls of the semiconductor die 100.

[0025] Figures 2A to 2D This is a cross-sectional view schematically illustrating the fabrication process of a semiconductor die according to some alternative embodiments of the present disclosure.

[0026] refer to Figures 2A to 2D as well as Figures 1A to 1C , Figures 2A to 2D The manufacturing process described in the document is similar to Figures 1A to 1C The manufacturing process described herein involves two beveling processes performed before the full-cut process. For example... Figure 2A and Figure 2B As described, a first beveling process is performed to form a first V-shaped notch G1 on the front surface of the semiconductor wafer W1. After forming the first V-shaped notch, a second beveling process is performed along the first V-shaped notch G1 to form a second V-shaped notch G2 on the front surface of the semiconductor wafer W1. The first V-shaped notch G1 and the second V-shaped notch G2 can be formed by performing two wafer dicing processes along the dicing track of the semiconductor wafer W1. The first V-shaped notch G1 can be formed by a V-shaped cutting blade B1, and the second V-shaped notch G2 can be formed by another V-shaped cutting blade B1'. The depth of the second V-shaped notch G2 is greater than the depth of the first V-shaped notch G1, and the width of the first V-shaped notch G1 is greater than the width of the second V-shaped notch G2. In some embodiments, the depth of the first V-shaped notch G1 is in the range of about 5 micrometers to about 700 micrometers, the width of the first V-shaped notch G1 is in the range of about 10 micrometers to about 1000 micrometers, the depth of the second V-shaped notch G2 is in the range of about 5 micrometers to about 700 micrometers, and the width of the second V-shaped notch G2 is in the range of about 10 micrometers to about 900 micrometers.

[0027] refer to Figure 2C and Figure 2DAfter performing the first and second beveling processes, a full dicing process is performed along the first V-shaped notch G1 and the second V-shaped notch G2 distributed on the front surface of the semiconductor wafer W1 to obtain a monomerized semiconductor die 100a. In some embodiments, each monomerized semiconductor die 100a includes a semiconductor substrate 110a, an interconnect structure 120a disposed on the semiconductor substrate 110a, a conductive pad 122, and a conductive terminal 124. In some embodiments, each monomerized semiconductor die 100a includes a chamfered edge CE', and the chamfered edge CE' is distributed in the peripheral region of the front surface of each semiconductor die 100a. The full dicing process can be performed by a dicing blade B2 along the first V-shaped notch G1 and the second V-shaped notch G2 formed on the semiconductor wafer W1. The width of the dicing blade B2 is smaller than the width of the first V-shaped notch G1 and the width of the second V-shaped notch G2. In some embodiments, the semiconductor wafer W1 is attached to a dicing strip (not shown) before performing the full dicing process.

[0028] Figures 3A to 3G This is a cross-sectional view schematically illustrating the fabrication process of a substrate-over-wafer-over-chip (CoWoS) package structure according to some embodiments of the present disclosure.

[0029] refer to Figures 3A to 3C An organic interposer substrate 210 is provided on a carrier C and formed thereon. In some embodiments, the organic interposer substrate 210 is formed on a wafer-type carrier C (e.g., a silicon wafer). The organic interposer substrate 210 may include stacked organic dielectric layers 212 and conductive wiring 214 located between the stacked organic dielectric layers 212. The stacked organic dielectric layers 212 are stacked on the carrier C. The conductive wiring 214 is embedded in the stacked organic dielectric layers 212 carried by the carrier C. In some embodiments, the coefficient of thermal expansion of the stacked organic dielectric layers 212 is greater than the coefficient of thermal expansion of the semiconductor substrate 110 of the semiconductor die 100.

[0030] like Figure 3A As described, a first organic dielectric layer 212a is formed on the carrier C. The first organic dielectric layer 212a may include openings, and portions of the carrier C are exposed through openings defined in the first organic dielectric layer 212a. In some embodiments, the material of the first organic dielectric layer 212a includes polybenzoxazole (PBO), polyimide (PI), or other suitable polymer dielectric materials. In some alternative embodiments, the material of the first organic dielectric layer 212a includes a resin mixed with fillers. The first organic dielectric layer 212a can be formed using a photo-patternable material and patterned using a photolithography process.

[0031] like Figure 3B As described, a seed layer S is formed on the carrier C to cover the first organic dielectric layer 212a and the portion of the carrier C exposed through openings defined in the first organic dielectric layer 212a. The seed layer S may be a sputtered Ti / Cu seed layer that completely covers the first dielectric layer 112a. After forming the seed layer S, a patterned photoresist layer PR is formed on the seed layer S. The patterned photoresist layer PR includes trenches, and the trenches defined in the patterned photoresist layer PR expose some portions of the seed layer S. After forming the patterned photoresist layer PR on the seed layer S, the patterned photoresist layer PR can be used as a mask to perform a plating process, such that a first conductive wiring 214a is plated in the trenches and the first conductive wiring 214a covers the exposed portion of the seed layer S.

[0032] After forming the first conductive wiring 214a, the patterned photoresist layer PR is removed to expose the portion of the seed layer not covered by the first conductive wiring 214a, and a patterned seed layer S' is formed below the first conductive wiring 214a. An etching process can be performed to remove the portion of the seed layer S' not covered by the first conductive wiring 214a until some portions of the first organic dielectric layer 212a are exposed. Figure 3B As explained in the document, the first conductive wiring 214a and the patterned seed layer S' can be regarded as conductive wiring layers.

[0033] like Figure 3C As explained, after forming the first organic dielectric layer 212a and the first conductive wiring 214a, a second organic dielectric layer 212b, a second conductive wiring 214b, a third organic dielectric layer 212c, a third conductive wiring 214c, and a fourth organic dielectric layer 212d can be formed on the carrier C to form an organic interposer substrate 210. The fabrication processes of the second organic dielectric layer 212b, the third organic dielectric layer 212c, and the fourth organic dielectric layer 212d can be similar to the fabrication process of the first organic dielectric layer 212a. The fabrication processes of the second conductive wiring 214b and the third conductive wiring 214c can be similar to the fabrication process of the first conductive wiring 214a. The number of stacked organic dielectric layers 212 and conductive wiring 214 in the organic interposer substrate 210 can be modified according to the product design rules. The conductive wiring 214 may include conductive wiring 214 and vias electrically connected between the conductive wiring 214, wherein the conductive wiring can transmit signals in the horizontal direction and the vias can transmit signals in the vertical direction. The material of the conductive wiring 214 may include copper or other suitable metal materials.

[0034] refer to Figure 3D After forming an organic interposer substrate 210 on the carrier C, at least one semiconductor die 100 is provided. Figure 1CAs shown in the figure, at least one semiconductor die 100 and at least one semiconductor device 220 are mounted onto an organic interposer substrate 210 via, for example, a chip-on-wafer (CoW) bonding process. At least one semiconductor die 100 and at least one semiconductor device 220 are electrically connected to the organic interposer substrate 210 via bump connectors. Conductive terminals 124 of the semiconductor die 100 and conductive terminals 222 of the at least one semiconductor device 220 are electrically connected to a third conductive wiring 214c of the organic interposer substrate 210. In some embodiments, conductive terminals 124 include Cu / Ni / Au bumps, Cu / Ni bumps, Cu / Ni / Au / SnAg bumps, Cu / Ni / SnAg bumps, etc., and conductive terminals 222 include Cu / Ni / Au bumps, Cu / Ni bumps, Cu / Ni / Au / SnAg bumps, Cu / Ni / SnAg bumps, etc. The structure of conductive terminal 124 may be the same as or different from the structure of conductive terminal 222. The at least one semiconductor die 100 may include a logic die, and the at least one semiconductor device 220 may include a memory device. In some alternative embodiments, the at least one semiconductor die 100 includes a system-on-chip (SOC) logic die, and the at least one semiconductor device 220 includes a high bandwidth memory (HBM) cube, wherein the HBM cube includes at least stacked memory dies. In some alternative embodiments, the semiconductor die 100 may include a system-on-integrated-chip (SoIC) structure or an application-specific integrated circuit (ASIC) die.

[0035] refer to Figure 3E An underfill adhesive 230 is formed on the organic interposer substrate 210. The underfill adhesive 230 fills the space between the organic interposer substrate 210 and the semiconductor die 100, and the space between the organic interposer substrate 210 and the semiconductor device 220, thereby laterally encapsulating the conductive terminals 124 and 222. The underfill adhesive 230 can serve as a stress buffer to improve the reliability of the conductive terminals 124 and 222. Therefore, electrical connections between the organic interposer substrate 210 and the semiconductor die 100, and between the organic interposer substrate 210 and the semiconductor device 220, are ensured.

[0036] like Figure 3EAs described, an insulating encapsulation 240 is formed on the organic interposer substrate 210 to cover the semiconductor die 100, the semiconductor device 220, and the underfill adhesive 230. The insulating encapsulation 240 can be formed by an overmolding process or a film deposition process. After performing the overmolding process or film deposition process for forming the insulating encapsulation 240, as... Figure 3E As described, a polishing process can be performed to partially remove the insulating encapsulation 240. After the polishing process, the thickness of the insulating encapsulation 240 is reduced. After the polishing process, the semiconductor die 100, semiconductor device 220, and underfill 230 are exposed. In some embodiments, the polishing process includes mechanical polishing, chemical mechanical polishing (CMP), or a combination thereof. For example, the material of the insulating encapsulation 240 includes epoxy molding compounds or other suitable dielectric materials.

[0037] refer to Figure 3E and Figure 3F A removal process is performed to remove the carrier C from the organic interposer substrate 210, thereby exposing the back surface of the organic interposer substrate 210. In some embodiments, the removal process of the carrier C includes a mechanical polishing process, a CMP process, an etching process, a combination thereof, or other suitable removal processes. After performing the removal process on the carrier C, a wafer-level bump mounting process is performed on the organic interposer substrate 210 to form a conductive terminal 250 on the first conductive wiring 214a of the organic interposer substrate 210. The wafer-level bump mounting process may include: forming a patterned photoresist on the back surface of the organic interposer substrate 210, wherein the patterned photoresist includes openings for exposing the first conductive wiring 214a; depositing (e.g., plating) a conductive material on the first conductive wiring 214a to form the conductive terminal 250 in the openings defined in the patterned photoresist; and removing the patterned photoresist. In some embodiments, the conductive terminal 250 may include a controlled collapse chip connection (C4) bump, etc.

[0038] like Figure 3E and Figure 3F As explained in the text, a monomerization process is performed along the cutting path SL to monomerize the product. Figure 3E The structure obtained is described in the above description. During the monomerization process, the organic interlayer substrate 210 and the insulating encapsulator 240 are cut along the dicing path SL.

[0039] refer to Figure 3F and Figure 3GAfter performing a monomerization process, a monomerized structure is obtained and inverted onto the upper surface of a circuit substrate 270 (e.g., a printed circuit board). The monomerized structure includes an organic interposer substrate 210, a semiconductor die 100 with chamfered edges CE, a semiconductor device 220, conductive terminals (e.g., bumps) 124 and 222, an underfill adhesive 230, an insulating encapsulator 240a, and conductive terminals 250. The organic interposer substrate 210 of the monomerized structure is electrically connected to the circuit substrate 270 via the conductive terminals 250. A reflow process can be performed to reflow the conductive terminals 250 and bond the organic interposer substrate 210 of the monomerized structure to the circuit substrate 270. Then, an underfill adhesive 260 is formed on the circuit substrate 270. The underfill adhesive 260 fills the space between the organic interposer substrate 210 and the circuit substrate 270 such that the underfill adhesive 260 laterally encapsulates the conductive terminals 250. The underfill adhesive 260 can be used as a stress buffer to improve the reliability of the conductive terminal 250. Therefore, electrical connection between the organic interposer substrate 210 and the circuit substrate 270 can be ensured.

[0040] An insulating encapsulation 240a covers the organic interposer substrate 210 and laterally encapsulates the semiconductor die 100 and the underfill adhesive 230. In some embodiments, the sidewalls of the insulating encapsulation 240a are substantially aligned with the sidewalls of the organic interposer substrate 210. The top surface of the insulating encapsulation 240a may be substantially flush with the rear surface of the semiconductor die 100 and the rear surface of the semiconductor device 220. In some embodiments, the circuit substrate 270 further includes conductive terminals 272 distributed on its bottom surface. The conductive terminals 272 may be ball grid array (BGA) balls. The material of the conductive terminals 272 may include solder materials, etc.

[0041] like Figure 3G As described, the underfill 230 laterally encapsulates the conductive terminals 124 and 222, and the underfill 230 is in direct contact with the chamfered edge CE of the semiconductor die 100. Since the semiconductor die 100 includes a chamfered edge CE (e.g., a beveled surface), stress issues between the underfill 230 and the semiconductor die 100 can be mitigated. (See below for reference...) Figures 4A to 4D , Figures 5A to 5D and Figures 6A to 6C Describe the details of the chamfered edge CE.

[0042] Figures 4A to 4D This is a cross-sectional view schematically illustrating various chamfered edges or rounded (rounded) edges according to some embodiments of the present disclosure.

[0043] refer to Figure 4AThe width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge of the chamfered edge CE includes an inclined surface (e.g., a beveled surface) SS extending between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill adhesive 230 is in direct contact with a portion of the root surface RS of the semiconductor die 100, the inclined surface SS of the semiconductor die 100, and the front surface FS of the semiconductor die 100. The inclined surface SS of the chamfered edge CE is connected to the insulating encapsulation 240a through the underfill adhesive 230. Figure 3G (as shown in the diagram) are spaced apart. In other words, the beveled surface SS of the chamfered edge CE is separated from the insulating encapsulation 240a (as shown in the diagram). Figure 3G (As shown) they do not contact each other. The exterior angle θ1 between the beveled edge CE's inclined surface SS and the front surface FS of the semiconductor die 100 can be in the range of about 5 degrees to about 80 degrees.

[0044] refer to Figure 4B The width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge of the chamfered edge CE includes two connected inclined surfaces (e.g., beveled surfaces) SS1 and SS2, which extend between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill adhesive 230 is in direct contact with a portion of the root surface RS of the semiconductor die 100, the inclined surfaces SS1 and SS2 of the chamfered edge CE of the semiconductor die 100, and the front surface FS of the semiconductor die 100. The inclined surfaces SS1 and SS2 of the chamfered edge CE are connected to the insulating encapsulation 240a through the underfill adhesive 230. Figure 3G (as shown in the diagram). In other words, the beveled surfaces SS1 and SS2 of the chamfered edge CE are spaced apart from the insulating encapsulation 240a (as shown in the diagram). Figure 3G (As shown) they do not contact each other. The exterior angle θ1 between the inclined surface SS1 of the chamfered edge CE and the front surface FS of the semiconductor die 100 can be in the range of about 5 degrees to about 85 degrees, and the exterior angle θ2 between the inclined surface SS2 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP1 parallel to the front surface FS of the semiconductor die 100 can be in the range of about 5 degrees to about 85 degrees. The exterior angle θ2 is greater than the exterior angle θ1.

[0045] refer to Figure 4CThe width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge of the chamfered edge CE includes three connected inclined surfaces (e.g., beveled surfaces) SS1, SS2, and SS3, which extend between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill adhesive 230 is in direct contact with a portion of the root surface RS of the semiconductor die 100, the inclined surfaces SS1, SS2, and SS3 of the chamfered edge CE of the semiconductor die 100, and the front surface FS of the semiconductor die 100. The inclined surfaces SS1, SS2, and SS3 of the chamfered edge CE are connected to the insulating encapsulator 240a through the underfill adhesive 230. Figure 3G (as shown in the diagram) are spaced apart. In other words, the beveled surfaces SS1, SS2, and SS3 of the chamfered edge CE are separated from the insulating encapsulation 240a (as shown in the diagram). Figure 3G (As shown) they do not contact each other. The exterior angle θ1 between the inclined surface SS1 of the chamfered edge CE and the front surface FS of the semiconductor die 100 can be in the range of about 5 degrees to about 85 degrees; the exterior angle θ2 between the inclined surface SS2 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP1 parallel to the front surface FS of the semiconductor die 100 can be in the range of about 5 degrees to about 85 degrees; and the exterior angle θ3 between the inclined surface SS3 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP2 parallel to the front surface FS of the semiconductor die 100 can be in the range of about 5 degrees to about 85 degrees. The exterior angle θ3 is greater than the exterior angle θ2, and the exterior angle θ2 is greater than the exterior angle θ1.

[0046] refer to Figure 4D The semiconductor die 100 includes rounded edges RE. The width D of the rounded edge RE can range from about 5 micrometers to about 500 micrometers, and the height H of the rounded edge RE can range from about 5 micrometers to about 700 micrometers. In some embodiments, each of the rounded edges RE extends between the root surface RS (side surface of the semiconductor die 100) and the front surface FS of the semiconductor die 100. Underfill 230 is in direct contact with a portion of the root surface RS of the semiconductor die 100, the rounded edges RE of the semiconductor die 100, and the front surface FS of the semiconductor die 100. The rounded edges RE are connected to the insulating encapsulation 240a via the underfill 230. Figure 3G As shown in the diagram, the rounded corner edge RE is spaced apart from the insulating encapsulation 240a. Figure 3G(As shown) they do not contact each other. Because the semiconductor die 100 includes rounded edges RE, stress issues between the underfill adhesive 230 and the semiconductor die 100 are improved.

[0047] Figures 5A to 5D This is a cross-sectional view schematically illustrating various chamfered or rounded edges according to some alternative embodiments of the present disclosure.

[0048] refer to Figure 5A The width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge of the chamfered edge CE includes an inclined surface SS extending between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill adhesive 230 is in direct contact with the lower portion of the inclined surface SS of the semiconductor die 100 and the front surface FS of the semiconductor die 100. The insulating encapsulation 240a is in direct contact with the upper portion of the inclined surface SS of the semiconductor die 100 and the root surface RS of the semiconductor die 100. The inclined surface SS is in direct contact with both the underfill adhesive 230 and the insulating encapsulation 240a. The exterior angle θ1 between the inclined surface SS of the chamfered edge CE of the semiconductor die 100 and the front surface FS of the semiconductor die 100 can range from about 5 degrees to about 85 degrees.

[0049] refer to Figure 5B The width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge CE includes two connected inclined surfaces SS1 and SS2 extending between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill adhesive 230 is in direct contact with the lower portions of the front surface FS, inclined surface SS1, and inclined surface SS2 of the semiconductor die 100. The insulating encapsulant 240a is in direct contact with the upper portion of the inclined surface SS2 and the root surface RS of the semiconductor die 100. The inclined surface SS2 is in direct contact with both the underfill adhesive 230 and the insulating encapsulant 240a. The exterior angle θ1 between the inclined surface SS1 of the chamfered edge CE and the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees, and the exterior angle θ2 between the inclined surface SS2 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP1 parallel to the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees. The exterior angle θ2 is greater than the exterior angle θ1.

[0050] refer to Figure 5C The width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge of the chamfered edge CE includes two connected inclined surfaces SS1 and SS2, which extend between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill adhesive 230 is in direct contact with the front surface FS of the semiconductor die 100 and the lower portion of the inclined surface SS1 of the semiconductor die 100. The insulating encapsulant 240a is in direct contact with the upper portion of the inclined surface SS1 of the semiconductor die 100, the inclined surface SS2 of the semiconductor die 100, and the root surface RS of the semiconductor die 100. The inclined surface SS1 is in direct contact with both the underfill adhesive 230 and the insulating encapsulant 240a. The exterior angle θ1 between the inclined surface SS1 of the chamfered edge CE of the semiconductor die 100 and the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees, and the exterior angle θ2 between the inclined surface SS2 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP1 parallel to the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees. The exterior angle θ2 is greater than the exterior angle θ1.

[0051] refer to Figure 5D The semiconductor die 100 includes rounded edges RE. The width D of the rounded edges RE can range from about 5 micrometers to about 500 micrometers, and the height H of the rounded edges RE can range from about 5 micrometers to about 700 micrometers. In some embodiments, each of the rounded edges RE extends between the root surface RS (side surface of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill 230 is in direct contact with the lower portion of the rounded edges RE of the semiconductor die 100 and the front surface FS of the semiconductor die 100. The insulating encapsulation 240a is in direct contact with the upper portion of the rounded edges RE of the semiconductor die 100 and the root surface RS of the semiconductor die 100. The rounded edges RE are in direct contact with both the underfill 230 and the insulating encapsulation 240a.

[0052] Figures 6A to 6C This is a cross-sectional view schematically illustrating various chamfered edges according to some other embodiments of the present disclosure.

[0053] refer to Figure 6AThe width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge CE includes three connected inclined surfaces SS1, SS2, and SS3 extending between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill adhesive 230 is in direct contact with the front surface FS and the lower portion of the inclined surface SS1 of the semiconductor die 100. The insulating encapsulant 240a is in direct contact with the upper portion of the inclined surface SS1, the inclined surface SS2, the inclined surface SS3, and the root surface RS of the semiconductor die 100. The insulating encapsulant 240a completely covers the inclined surfaces SS2 and SS3. The inclined surface SS1 is in direct contact with the underfill adhesive 230 and the insulating encapsulator 240a. The exterior angle θ1 between the inclined surface SS1 of the chamfered edge CE and the front surface FS of the semiconductor die 100 can be between approximately 5 degrees and approximately 85 degrees. The exterior angle θ2 between the inclined surface SS2 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP1 parallel to the front surface FS of the semiconductor die 100 can be between approximately 5 degrees and approximately 85 degrees. The exterior angle θ3 between the inclined surface SS3 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP2 parallel to the front surface FS of the semiconductor die 100 can be between approximately 5 degrees and approximately 85 degrees. The exterior angle θ3 is greater than the exterior angle θ2, and the exterior angle θ2 is greater than the exterior angle θ1.

[0054] refer to Figure 6BThe width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge CE includes three connected inclined surfaces SS1, SS2, and SS3 extending between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. The underfill adhesive 230 is in direct contact with the lower portions of the front surface FS, inclined surfaces SS1, and inclined surfaces SS2 of the semiconductor die 100. The insulating encapsulant 240a is in direct contact with the upper portion of the inclined surface SS2, the inclined surface SS3, and the root surface RS of the semiconductor die 100. The underfill adhesive 230 may completely cover the inclined surface SS1. The inclined surface SS2 is in direct contact with both the underfill adhesive 230 and the insulating encapsulant 240a. The exterior angle θ1 between the inclined surface SS1 of the chamfered edge CE of the semiconductor die 100 and the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees. The exterior angle θ2 between the inclined surface SS2 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP1 parallel to the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees. The exterior angle θ3 between the inclined surface SS3 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP2 parallel to the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees. Exterior angle θ3 is greater than exterior angle θ2, and exterior angle θ2 is greater than exterior angle θ1.

[0055] refer to Figure 6CThe width D of the chamfered edge CE can range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edge CE can range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge CE includes three connected inclined surfaces SS1, SS2, and SS3 extending between the root surface RS (sidewall of the semiconductor die 100) and the front surface FS of the semiconductor die 100. Underfill 230 is in direct contact with the lower portions of the front surface FS, inclined surfaces SS1, SS2, and SS3 of the semiconductor die 100. Underfill 230 may completely cover inclined surfaces SS1 and SS2. Insulating encapsulation 240a is in direct contact with the upper portion of the inclined surface SS3 of the semiconductor die 100 and the root surface RS of the semiconductor die 100. Inclined surface SS3 is in direct contact with both underfill 230 and insulating encapsulation 240a. The exterior angle θ1 between the inclined surface SS1 of the chamfered edge CE of the semiconductor die 100 and the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees. The exterior angle θ2 between the inclined surface SS2 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP1 parallel to the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees. The exterior angle θ3 between the inclined surface SS3 of the chamfered edge CE of the semiconductor die 100 and the virtual plane VP2 parallel to the front surface FS of the semiconductor die 100 can be in the range of approximately 5 degrees to approximately 85 degrees. Exterior angle θ3 is greater than exterior angle θ2, and exterior angle θ2 is greater than exterior angle θ1.

[0056] According to some embodiments of this disclosure, a package structure is provided including an organic interposer substrate, a semiconductor die, conductive bumps, a first underfill adhesive, and an insulating encapsulator. The organic interposer substrate includes stacked organic dielectric layers and conductive wiring embedded in the stacked organic dielectric layers. The semiconductor die is disposed on and electrically connected to the conductive wiring of the organic interposer substrate, and the semiconductor die includes a chamfered edge. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate via the conductive bumps. The first underfill adhesive is disposed between the semiconductor die and the organic interposer substrate, wherein the first underfill adhesive encapsulates the conductive bumps and contacts the chamfered edge of at least one semiconductor die. The insulating encapsulator covers the organic interposer substrate and laterally encapsulates at least one semiconductor die and the first underfill adhesive. In some embodiments, the width of the chamfered edge is in the range of about 5 micrometers to about 500 micrometers, and the height of the chamfered edge is in the range of about 5 micrometers to about 700 micrometers. In some embodiments, at least one of the chamfered edges includes at least one inclined surface extending between the root surface of the semiconductor die and the front surface of the semiconductor die, and the first underfill adhesive contacts the inclined surface of the chamfered edge. In some embodiments, the first underfill adhesive further contacts a first portion of the root surface, and the insulating encapsulant contacts a second portion of the root surface. In some embodiments, at least one of the chamfered edges includes at least one inclined surface extending between the root surface of the semiconductor die and the front surface of the semiconductor die, the first underfill adhesive contacts a first portion of the inclined surface of the chamfered edge, and the insulating encapsulant contacts a second portion of the inclined surface of the chamfered edge. In some embodiments, at least one of the chamfered edges includes a first inclined surface and a second inclined surface, the first inclined surface extending between the front surface of the semiconductor die and the second inclined surface, the second inclined surface extending between the first inclined surface and the root surface, the first inclined surface being completely covered by the first underfill adhesive, and the second inclined surface contacting the first underfill adhesive and the insulating encapsulant. In some embodiments, the sidewalls of the insulating encapsulant are substantially aligned with the sidewalls of the organic interposer substrate. In some embodiments, the coefficient of thermal expansion of the stacked organic dielectric layer is greater than the coefficient of thermal expansion of the semiconductor substrate of the semiconductor die.In some embodiments, the encapsulation structure further includes: a circuit substrate; a first conductive terminal disposed on and electrically connected to the circuit substrate; a second conductive terminal disposed on and electrically connected to the circuit substrate; and a second underfill adhesive disposed between the organic interposer substrate and the circuit substrate. The organic interposer substrate is electrically connected to the circuit substrate via the first conductive terminal, and the first conductive terminal and the second conductive terminal are disposed on opposite sides of the circuit substrate. The second underfill adhesive encapsulates the first conductive terminal.

[0057] According to some other embodiments of this disclosure, a package structure including an interposer substrate, a semiconductor die, conductive bumps, and an underfill is provided. The interposer substrate includes stacked dielectric layers and conductive wiring embedded in the stacked dielectric layers. The semiconductor die is disposed on and electrically connected to the interposer substrate, and the coefficient of thermal expansion of the stacked dielectric layers is greater than the coefficient of thermal expansion of the semiconductor substrate of the semiconductor die. The semiconductor die includes chamfered edges, and at least one of the chamfered edges includes a beveled surface. Conductive bumps are disposed between the semiconductor die and the interposer substrate, and the semiconductor die is electrically connected to the interposer substrate via the conductive bumps. The underfill is disposed between the semiconductor die and the interposer substrate. In some embodiments, the width of the chamfered edge is in the range of about 5 micrometers to about 500 micrometers, and the height of the chamfered edge is in the range of about 5 micrometers to about 700 micrometers. In some embodiments, the underfill contacts the beveled surface and root surface of the chamfered edge. In some embodiments, the sidewalls of the insulating encapsulator are substantially aligned with the sidewalls of the interposer substrate. In some embodiments, the package structure further includes a circuit substrate, wherein the interposer substrate is electrically connected to the circuit substrate.

[0058] According to some other embodiments of this disclosure, a package structure is provided including an organic interposer substrate, a semiconductor die, conductive bumps, and a first underfill adhesive. The organic interposer substrate includes stacked organic dielectric layers and conductive wiring embedded in the stacked organic dielectric layers. The semiconductor die is disposed on and electrically connected to the conductive wiring of the organic interposer substrate, and the semiconductor die includes rounded edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate via the conductive bumps. The first underfill adhesive is disposed between the semiconductor die and the organic interposer substrate. In some embodiments, each of the rounded edges extends between a front surface and a side surface of the semiconductor die, and the first underfill adhesive contacts the rounded edge. In some embodiments, the package structure further includes an insulating encapsulator covering the organic interposer substrate and laterally encapsulating at least one semiconductor die and the first underfill adhesive, wherein the rounded edges of the semiconductor die are spaced apart from the insulating encapsulator by the first underfill adhesive. In some embodiments, the first underfill further contacts a first portion of the side surface of the semiconductor die, and the insulating encapsulant contacts a second portion of the side surface of the semiconductor die. In some embodiments, the sidewall of the insulating encapsulant is substantially aligned with the sidewall of the organic interposer substrate. In some embodiments, the package structure further includes a circuit substrate, a first conductive terminal, a second conductive terminal, and a second underfill. The first conductive terminal is disposed on and electrically connected to the circuit substrate. The second conductive terminal is disposed on and electrically connected to the circuit substrate, wherein the organic interposer substrate is electrically connected to the circuit substrate via the first conductive terminal, and the first conductive terminal and the second conductive terminal are disposed on opposite sides of the circuit substrate. The second underfill is disposed between the organic interposer substrate and the circuit substrate, wherein the second underfill encapsulates the first conductive terminal.

[0059] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0060] [Explanation of Symbols]

[0061] 100, 100a: Semiconductor die

[0062] 110, 110a: Semiconductor substrate

[0063] 120, 120a: Internal connection structure

[0064] 122: Conductive pad

[0065] 124, 222, 250, 272: Conductive terminals

[0066] 210: Organic interlayer substrate

[0067] 212: Stacked organic dielectric layers

[0068] 212a: First organic dielectric layer

[0069] 212b: Second organic dielectric layer

[0070] 212c: Third organic dielectric layer

[0071] 212d: Fourth organic dielectric layer

[0072] 214: Conductive wiring

[0073] 214a: First conductive wiring

[0074] 214b: Second conductive wiring

[0075] 214c: Third conductive wiring

[0076] 220: Semiconductor devices

[0077] 230, 260: Bottom filler adhesive

[0078] 240, 240a: Insulating Encapsulation

[0079] 270: Circuit substrate

[0080] B1, B1': V-shaped cutting blade

[0081] B2: Cutting blade

[0082] C: Carrier

[0083] CE, CE': Chamfered edge

[0084] D: Width

[0085] FS: Front Surface

[0086] G: V-shaped notch

[0087] G1: First V-shaped notch

[0088] G2: Second V-shaped notch

[0089] H: Height

[0090] PR: Patterned photoresist layer

[0091] RS: root surface

[0092] S, S': Seed layers

[0093] SS, SS1, SS2, SS3: Inclined surfaces

[0094] SL: Cutting Track

[0095] VP1, VP2: Virtual planes

[0096] W1: Semiconductor wafer

[0097] θ1, θ2, θ3: exterior angle

Claims

1. A packaging structure for a semiconductor device, comprising: An interposer substrate includes stacked dielectric layers and conductive wiring embedded in the stacked dielectric layers; A semiconductor die disposed on and electrically connected to the conductive wiring of the interposer substrate, and the semiconductor die includes chamfered edges; A conductive bump is disposed between the semiconductor die and the interposer substrate, wherein the semiconductor die is electrically connected to the interposer substrate via the conductive bump; A first underfill adhesive is disposed between the semiconductor die and the interposer substrate, wherein the first underfill adhesive encapsulates the conductive bump and covers the chamfered edge of the semiconductor die; as well as An insulating encapsulation covers the interposer substrate and laterally encapsulates the semiconductor die and the first underfill adhesive, wherein at least one of the chamfered edges includes at least one beveled surface extending between the root surface and the front surface of the semiconductor die, the first underfill adhesive contacts a first portion of the at least one beveled surface of the chamfered edge, and the insulating encapsulation contacts a second portion of the at least one beveled surface of the chamfered edge.

2. The packaging structure according to claim 1, wherein the width of the chamfered edge is in the range of 5 micrometers to 500 micrometers, and the height of the chamfered edge is in the range of 5 micrometers to 700 micrometers.

3. The packaging structure for a semiconductor device according to claim 1, wherein the chamfered edge includes a first beveled surface and a second beveled surface, the first beveled surface extending between the front surface of the semiconductor die and the second beveled surface, the second beveled surface extending between the first beveled surface and the root surface of the semiconductor die, the first underfill contacting a portion of the front surface, the first beveled surface and the second beveled surface, and the insulating encapsulant contacting the remaining portions of the root surface and the second beveled surface.

4. The packaging structure for a semiconductor device according to claim 1, wherein the chamfered edge includes a first beveled surface and a second beveled surface, the first beveled surface extending between the front surface of the semiconductor die and the second beveled surface, the second beveled surface extending between the first beveled surface and the root surface of the semiconductor die, the first underfill adhesive contacting a portion of the front surface and the first beveled surface, and the insulating encapsulant contacting the remaining portions of the root surface, the second beveled surface, and the first beveled surface.

5. The packaging structure for a semiconductor device according to claim 1, wherein at least one of the chamfered edges includes a first beveled surface and a second beveled surface, the first beveled surface extending between the front surface of the semiconductor die and the second beveled surface, the second beveled surface extending between the root surface of the semiconductor die and the first beveled surface, the second beveled surface being completely covered by the insulating encapsulant, and the first beveled surface contacting the first underfill adhesive and the insulating encapsulant.

6. The packaging structure for a semiconductor device according to claim 1, wherein at least one of the chamfered edges comprises a first beveled surface and a second beveled surface, the first beveled surface extending between the front surface of the semiconductor die and the second beveled surface, the second beveled surface extending between the root surface of the semiconductor die and the first beveled surface, the first beveled surface being completely covered by the first underfill adhesive, and the second beveled surface contacting the first underfill adhesive and the insulating encapsulant.

7. The packaging structure for a semiconductor device according to claim 1, wherein the sidewalls of the insulating encapsulant are substantially aligned with the sidewalls of the interposer substrate.

8. The packaging structure for a semiconductor device according to claim 1, wherein the stacked dielectric layer comprises a stacked organic dielectric layer, and the coefficient of thermal expansion of the stacked dielectric layer is greater than the coefficient of thermal expansion of the semiconductor substrate of the semiconductor die.

9. The packaging structure for semiconductor devices according to claim 1, further comprising: Circuit substrate; A first conductive terminal is disposed on the circuit substrate and electrically connected to the circuit substrate; A second conductive terminal is disposed on the circuit substrate and electrically connected to the circuit substrate, wherein the intermediate layer substrate is electrically connected to the circuit substrate via the first conductive terminal, and the first conductive terminal and the second conductive terminal are disposed on opposite sides of the circuit substrate. as well as A second underfill adhesive is disposed between the interposer substrate and the circuit substrate, wherein the second underfill adhesive encapsulates the first conductive terminal.

10. A packaging structure for a semiconductor device, comprising: An interposer substrate includes stacked dielectric layers and conductive wiring embedded in the stacked dielectric layers; A semiconductor die disposed on and electrically connected to the interposer substrate, wherein the coefficient of thermal expansion of the stacked dielectric layer is greater than the coefficient of thermal expansion of the semiconductor substrate of the semiconductor die, wherein the semiconductor die includes chamfered edges, and at least one of the chamfered edges includes a beveled surface. A conductive bump is disposed between the semiconductor die and the interposer substrate, wherein the semiconductor die is electrically connected to the interposer substrate via the conductive bump; An underfill adhesive is disposed between the semiconductor die and the interposer substrate; and An insulating encapsulation that covers the interposer substrate and laterally encapsulates the semiconductor die and the underfill adhesive, wherein the beveled surface contacts the underfill adhesive and the insulating encapsulation.

11. The packaging structure of claim 10, wherein the width of the chamfered edge is in the range of 5 micrometers to 500 micrometers, and the height of the chamfered edge is in the range of 5 micrometers to 700 micrometers.

12. The packaging structure for a semiconductor device according to claim 10, wherein the bottom filler contacts the beveled surface of the at least one chamfered edge and the root surface of the semiconductor die.

13. The packaging structure for a semiconductor device according to claim 10, wherein the sidewalls of the insulating encapsulant are substantially aligned with the sidewalls of the interposer substrate.

14. The packaging structure for a semiconductor device according to claim 10, further comprising a circuit substrate, wherein the interposer substrate is electrically connected to the circuit substrate.

15. A packaging structure for a semiconductor device, comprising: An interposer substrate includes stacked dielectric layers and conductive wiring embedded in the stacked dielectric layers; A semiconductor die disposed on and electrically connected to the conductive wiring of the interposer substrate, and the semiconductor die includes rounded edges. A conductive bump is disposed between the semiconductor die and the interposer substrate, wherein the semiconductor die is electrically connected to the interposer substrate via the conductive bump; A first underfill adhesive is disposed between the semiconductor die and the interposer substrate; and An insulating encapsulation covers the interposer substrate and laterally encapsulates the semiconductor die and the first underfill adhesive, wherein the rounded edges of the encapsulation contact the first underfill adhesive and the insulating encapsulation.

16. The packaging structure for a semiconductor device according to claim 15, wherein each of the edges of the rounded corners extends between the front surface of the semiconductor die and the side surface of the semiconductor die, and the first bottom filler contacts the edge of the rounded corner.

17. The packaging structure for a semiconductor device according to claim 15, wherein the first underfill adhesive is in direct contact with the lower portion of the edge of the rounded corner of the semiconductor die and the front surface of the semiconductor die.

18. The packaging structure of claim 17, wherein the insulating encapsulator is in direct contact with the upper portion of the rounded edge of the semiconductor die and the side surface of the semiconductor die.

19. The packaging structure of claim 17, wherein the sidewalls of the insulating encapsulant are substantially aligned with the sidewalls of the interposer substrate.

20. The packaging structure according to claim 15, further comprising: Circuit substrate; A first conductive terminal is disposed on the circuit substrate and electrically connected to the circuit substrate; A second conductive terminal is disposed on the circuit substrate and electrically connected to the circuit substrate, wherein the intermediate layer substrate is electrically connected to the circuit substrate via the first conductive terminal, and the first conductive terminal and the second conductive terminal are disposed on opposite sides of the circuit substrate. as well as A second underfill adhesive is disposed between the interposer substrate and the circuit substrate, wherein the second underfill adhesive encapsulates the first conductive terminal.

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