Semiconductor device and method of manufacturing semiconductor device

Abstract

This application relates to a semiconductor device and a method for manufacturing a semiconductor device. A semiconductor device includes: alternating layers of conductive layers and interlayer insulating layers; a selection conductor spaced apart from the conductive layers; an outer unit plug penetrating the conductive layers, the interlayer insulating layer, and the selection conductor; and an outer auxiliary conductor in contact with the selection conductor.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods of manufacturing semiconductor devices, and more specifically, to three-dimensional semiconductor devices and methods of manufacturing three-dimensional semiconductor devices. Background Technology

[0002] Semiconductor devices include memory cells capable of storing data. Three-dimensional semiconductor devices include memory cells arranged in three dimensions, which reduces the area occupied by the memory cells per unit area of ​​the substrate.

[0003] To improve the integration density of three-dimensional semiconductor devices, the number of memory cell stacks can be increased. However, as the number of memory cell stacks increases, the operational reliability of the three-dimensional semiconductor device may deteriorate. Summary of the Invention

[0004] In embodiments of this disclosure, a semiconductor device may be provided, comprising: alternating layers of conductive layers and interlayer insulating layers; a select conductor spaced apart from the conductive layers; an outer unit plug penetrating the conductive layers, the interlayer insulating layers, and the select conductor; and an outer auxiliary conductor surrounding the outer unit plug, the outer auxiliary conductor contacting the select conductor, wherein the outer auxiliary conductor includes a circular portion and a connecting portion, wherein the circular portions surround the outer unit plug respectively, and wherein the connecting portion connects adjacent circular portions.

[0005] In embodiments of this disclosure, a semiconductor device may be provided, comprising: alternating layers of conductive layers and interlayer insulating layers; a selector conductor spaced apart from the conductive layers; an inner cell plug penetrating the conductive layers, the interlayer insulating layers, and the selector conductor; and an inner auxiliary conductor in contact with the selector conductor, wherein the inner auxiliary conductors surround the inner cell plugs, and wherein the inner auxiliary conductors are disposed at a height higher than the height of the selector conductor.

[0006] In embodiments of this disclosure, a semiconductor device may be provided, comprising: alternating layers of conductive layers and interlayer insulating layers; a selection conductor spaced apart from the conductive layers; and a cell plug penetrating the conductive layers, the interlayer insulating layers, and the selection conductor, wherein the selection conductor includes a selection base surrounding the cell plug and a selection protrusion projecting from the selection base in the length direction of the cell plug.

[0007] In embodiments of this disclosure, a method for manufacturing a semiconductor device may be provided, the method comprising: forming a selective conductive layer on a substrate; forming a stacked structure on the selective conductive layer; forming a cell plug penetrating the selective conductive layer and the stacked structure; exposing the cell plug and the selective conductive layer by removing the substrate; isolating the selective conductive layer into a selective conductor; forming an auxiliary conductive layer covering the selective conductor; and etching the auxiliary conductive layer.

[0008] In embodiments of this disclosure, a method for manufacturing a semiconductor device may be provided, the method comprising: forming an interlayer sacrificial layer on a substrate; forming a selective sacrificial layer on the interlayer sacrificial layer; forming a preliminary stacked structure on the selective sacrificial layer; forming a cell plug penetrating the preliminary stacked structure, the selective sacrificial layer, and the interlayer sacrificial layer; removing the selective sacrificial layer; forming a selective conductive layer in a region where the selective sacrificial layer has been removed; exposing the cell plug and the selective conductive layer by removing the substrate and the interlayer sacrificial layer; forming a selective conductor surrounding the cell plug by etching the selective conductive layer; forming an auxiliary conductive layer in contact with the selective conductor; and etching the auxiliary conductive layer. Attached Figure Description

[0009] Examples of embodiments will now be described below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Similar reference numerals always refer to similar elements.

[0011] Figure 1A This is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 1B It is along Figure 1A The diagram shows a cross-sectional view of the semiconductor device taken by line A1-A1′.

[0013] Figure 1C yes Figure 1B An enlarged view of region B1 shown.

[0014] Figure 1D This is an example Figures 1A to 1C A perspective view of the external auxiliary conductor and external unit plug of the semiconductor device shown.

[0015] Figure 1E This is an example Figures 1A to 1C A perspective view of the internal auxiliary conductor and internal unit plug of the semiconductor device shown.

[0016] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 9 , Figure 10 , Figure 11 and Figure 12This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 8B It is along Figure 8A The diagram shows a cross-sectional view of the semiconductor device taken by line A2-A2′.

[0018] Figure 13A This is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 13B It is along Figure 13A The diagram shows a cross-sectional view of the semiconductor device taken by line A3-A3′.

[0020] Figure 13C yes Figure 13B An enlarged view of region B2 shown.

[0021] Figure 13D This is an example Figure 13A , Figure 13B and Figure 13C A three-dimensional view of the external auxiliary conductor and external unit plug of the semiconductor device shown.

[0022] Figure 13E This is an example Figure 13A , Figure 13B and Figure 13C A perspective view of the internal auxiliary conductor and internal unit plug of the semiconductor device shown.

[0023] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 20A and Figure 20B This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 21 , Figure 22 , Figure 23 and Figure 24 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 25 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0027] Figure 26 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0028] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0029] The implementation provides a semiconductor device with improved operational reliability.

[0030] Figure 1A This is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The diagram shows a cross-sectional view of the semiconductor device taken by line A1-A1′. Figure 1C yes Figure 1B An enlarged view of region B1 shown. Figure 1D This is an example Figures 1A to 1C A three-dimensional view of the external auxiliary conductor and external unit plug of the semiconductor device shown. Figure 1E This is an example Figures 1A to 1C A perspective view of the internal auxiliary conductor and internal unit plug of the semiconductor device shown.

[0031] Reference Figure 1A and Figure 1B The semiconductor device may include a first substrate 100. The first substrate 100 may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be directions facing axes that intersect each other. In an example, the first direction D1 and the second direction D2 may be directions facing axes that are orthogonal to each other. In an embodiment, the first substrate 100 may be a semiconductor substrate.

[0032] A first insulating layer 110 may be provided to cover the first substrate 100. The first insulating layer 110 may include an insulating material. In an embodiment, the first insulating layer 110 may include an oxide or a nitride.

[0033] A peripheral transistor TR can be disposed between the first insulating layer 110 and the first substrate 100. The peripheral transistor TR can constitute the peripheral circuitry of a semiconductor device. In one embodiment, the peripheral transistor TR can constitute the page buffer of the semiconductor device.

[0034] Each peripheral transistor TR may include an impurity region IR, a gate insulating layer GI, and a gate electrode GM. The impurity region IR may be formed by doping impurities into the first substrate 100. The gate electrode GM may be spaced from the first substrate 100 by the gate insulating layer GI. The gate insulating layer GI may include an insulating material. In an example, the gate insulating layer GI may include an oxide. The gate electrode GM may include a conductive material. In an example, the gate electrode GM may include tungsten.

[0035] An isolation layer IS may be disposed in the first substrate 100. The isolation layer IS can electrically isolate the peripheral transistors TR from each other. The isolation layer IS may include an insulating material. In an embodiment, the isolation layer IS may include an oxide.

[0036] The first contact CT1 and the first line ML1 may be disposed in the first insulating layer 110. The first contact CT1 can connect the peripheral transistor TR and the first line ML1 to each other, or connect the first lines ML1 disposed in different layers to each other. The first contact CT1 and the first line ML1 may include conductive materials. In an embodiment, the first contact CT1 and the first line ML1 may include tungsten.

[0037] A first bonding pad BP1 may be disposed in the first insulating layer 110. The first bonding pad BP1 may be connected to the first line ML1. The width of the first bonding pad BP1 may decrease as it gets closer to the first substrate 100 or the peripheral transistor TR. For example, the width of the first bonding pad BP1 in the first direction D1 may decrease as it gets closer to the first substrate 100. The first bonding pad BP1 may include a conductive material. In an embodiment, the first bonding pad BP1 may include copper.

[0038] The first insulating layer 110 may be covered by a second insulating layer 120. The second insulating layer 120 may include an insulating material. In some embodiments, the second insulating layer 120 may include an oxide or a nitride.

[0039] A second bonding pad BP2 may be disposed in the second insulating layer 120. The second bonding pad BP2 may be connected to the first bonding pad BP1. The second bonding pad BP2 may contact the first bonding pad BP1. The width of the second bonding pad BP2 may increase as it gets closer to the first bonding pad BP1. For example, the width of the second bonding pad BP2 in the first direction D1 may increase as it gets closer to the first bonding pad BP1. The width of the first bonding pad BP1 may increase as it gets closer to the second bonding pad BP2. For example, the width of the first bonding pad BP1 in the first direction D1 may increase as it gets closer to the second bonding pad BP2.

[0040] The second line ML2 and the second contact CT2 can be disposed in the second insulating layer 120. The second line ML2 can be connected to the second bonding pad BP2. The second contact CT2 can be connected to the second line ML2. The second line ML2 and the second contact CT2 can include conductive materials. In an embodiment, the second line ML2 and the second contact CT2 can include tungsten.

[0041] Bit line BL can be disposed in the second insulating layer 120. Bit line BL can be connected to the second contact CT2. Bit line BL can be electrically connected to the peripheral transistor TR through the second contact CT2, the second line ML2, the second bonding pad BP2, the first bonding pad BP1, the first line ML1, and the first contact CT1. Bit line BL can extend in the first direction D1. Bit line BL can include a conductive material. In an embodiment, bit line BL can include tungsten.

[0042] Bit line contact BCT can be formed in the second insulating layer 120. Bit line contact BCT can be connected to bit line BL. Bit line contact BCT can include a conductive material. In one embodiment, bit line contact BCT can include tungsten.

[0043] A stacked structure STA can be formed on the second insulating layer 120. The stacked structure STA may include a selective layer SL, a conductive layer COL, and an interlayer insulating layer IL. The selective layer SL and the interlayer insulating layer IL may be alternately stacked in a third direction D3. The third direction D3 may be the direction facing an axis intersecting the top surface of the first substrate 100. In an embodiment, the third direction D3 may be the direction facing an axis orthogonal to the top surface of the first substrate 100. The conductive layer COL and the interlayer insulating layer IL may be alternately stacked in the third direction D3. The selective layer SL, the conductive layer COL, and the interlayer insulating layer IL may overlap each other in the third direction D3. The selective layer SL may be disposed at a height lower than that of the conductive layer COL.

[0044] The select layer SL can be used as a select line in a semiconductor device. The select layer SL can also be used as a drain select line in a semiconductor device. The conductive layer COL can be used as a word line in a semiconductor device. The select layer SL and the conductive layer COL can comprise the same conductive material. In one embodiment, the select layer SL and the conductive layer COL can comprise tungsten. The interlayer insulating layer IL can comprise an insulating material. In one embodiment, the interlayer insulating layer IL can comprise an oxide.

[0045] The cell plug CE can penetrate the stacked structure STA. The cell plug CE can extend in the third direction D3. In an embodiment, the length direction of the cell plug CE can be defined as the third direction D3. The cell plug CE may include a fill layer FI, a channel layer CL surrounding the fill layer FI, and a memory layer ML surrounding the channel layer CL. The fill layer FI, the channel layer CL, and the memory layer ML can penetrate the stacked structure STA while extending in the third direction D3. The channel layer CL can be connected to the bit line contact BCT. The channel layer CL can be electrically connected to the bit line BL through the bit line contact BCT.

[0046] The filling layer FI may include an insulating material. In one embodiment, the filling layer FI may include an oxide. The channel layer CL may include a semiconductor material. In one embodiment, the channel layer CL may include polysilicon. The memory layer ML may include a tunnel insulating layer surrounding the channel layer CL, a data storage layer surrounding the tunnel insulating layer, and a barrier insulating layer surrounding the data storage layer. The tunnel insulating layer may include a material through which charge can tunnel. In an example, the tunnel insulating layer may include an oxide. In one embodiment, the data storage layer may include a material in which charge can be trapped. For example, the data storage layer may include a nitride. The data storage layer may include various materials depending on the data storage method. In one embodiment, the data storage layer may include silicon, a phase change material, or nanodots. The barrier layer may include a material capable of blocking the movement of charge. In one embodiment, the barrier layer may include an oxide.

[0047] An isolation structure DS can be formed in the stacked structure STA. The isolation structure DS can be formed between cell plugs CE. The isolation structure DS can extend in the second direction D2 and the third direction D3. The isolation structure DS can be disposed between selectable layers SL spaced apart in the first direction D1. The selectable layers SL spaced apart in the first direction D1 are electrically isolated from each other by the isolation structure DS. The interlayer insulating layers IL disposed below the conductive layer COL can be isolated from each other in the first direction D1 by the isolation structure DS. The isolation structure DS can be in contact with the selectable layers SL. The isolation structure DS can be spaced apart from the conductive layer COL. The isolation structure DS may include an insulating material. In an embodiment, the isolation structure DS may include an oxide.

[0048] The slit structure SLS can penetrate the stacked structure STA. The slit structure SLS can be formed between the cell plugs CE. The slit structure SLS can extend in the second direction D2 and the third direction D3. The selective layer SL, the interlayer insulating layer IL, and the conductive layer COL can be isolated from each other in the first direction D1 through the slit structure SLS. The top surface of the slit structure SLS can be disposed at a height higher than the top surface of the stacked structure STA. The slit structure SLS can protrude further than the stacked structure STA in the third direction D3. The slit structure SLS may include an insulating material. In an embodiment, the slit structure SLS may include an oxide.

[0049] Selective conductors (SECs) can be formed on the stacked structure STA. The selective conductors (SECs) can be formed on the interlayer insulating layer IL of the stacked structure STA. Two or more selective conductors (SECs) can be provided between adjacent slot structures (SLS). Each selective conductor (SEC) can surround a cell plug (CE). The selective conductor (SEC) can include a conductive material. In one embodiment, the selective conductor (SEC) can include polysilicon.

[0050] The outer auxiliary conductor OAC and the inner auxiliary conductor IAC can be in contact with the selector conductor SEC. The outer auxiliary conductor OAC can be disposed on both sides of the selector conductor SEC. The selector conductor SEC can be disposed between the outer auxiliary conductors OAC. The inner auxiliary conductor IAC can be disposed between the outer auxiliary conductors OAC. The outer auxiliary conductor OAC and the inner auxiliary conductor IAC can comprise the same conductive material. The conductive material comprised in the outer auxiliary conductor OAC and the inner auxiliary conductor IAC can be different from the conductive material comprised in the selector conductor SEC. In an embodiment, the outer auxiliary conductor OAC and the inner auxiliary conductor IAC can comprise titanium nitride.

[0051] A structure including a select conductor SEC, an outer auxiliary conductor OAC, and an inner auxiliary conductor IAC can be used as a select line in a semiconductor device. In an embodiment, a structure including a select conductor SEC, an outer auxiliary conductor OAC, and an inner auxiliary conductor IAC can be used as a source select line in a semiconductor device.

[0052] The third insulating layer 130 may cover the laminated structure STA, the slit structure SLS, the selective conductor SEC, the outer auxiliary conductor OAC, and the inner auxiliary conductor IAC. The third insulating layer 130 may include an insulating material. In some embodiments, the third insulating layer 130 may include an oxide or a nitride.

[0053] The source layer SOL can be formed on the third insulating layer 130. The source layer SOL can be connected to the channel layer CL of the cell plug CE. The source layer SOL can be in contact with the channel layer CL of the cell plug CE. The source layer SOL can be electrically connected to the channel layer CL of the cell plug CE. The source layer SOL can surround the upper portion of the channel layer CL of the cell plug CE. The uppermost portion of the channel layer CL of the cell plug CE can be disposed in the source layer SOL. The source layer SOL can include a conductive material. In an embodiment, the source layer SOL can include doped polysilicon.

[0054] A source barrier layer (SOB) can be formed on the source layer (SOL). The source barrier layer (SOB) can be in contact with the source layer (SOL). The source barrier layer (SOB) can include a conductive material. In an embodiment, the source barrier layer (SOB) can include at least one of titanium and tungsten.

[0055] Reference Figure 1A , Figure 1C , Figure 1D and Figure 1E The selector conductor SEC may include a selector base SEB and a selector protrusion SEP. The selector base SEB may surround multiple cell plugs CE. The selector base SEB may be formed on a laminated structure STA. The selector base SEB may contact the interlayer insulation layer IL disposed on the uppermost portion of the laminated structure STA. The selector base SEB may overlap with the outer auxiliary conductor OAC and the inner auxiliary conductor IAC. For example, some outer auxiliary conductors OAC and selector base SEB may be aligned in a third direction D3, and each inner auxiliary conductor IAC and selector base SEB may be aligned in a third direction D3.

[0056] The selection protrusion SEP can protrude from the selection base SEB. In an implementation, the selection protrusion SEP can extend from the selection base SEB along a third direction D3. For example, as... Figure 1C As shown, the selection protrusion SEP can extend from the top surface SEB_T of the selection base SEB on the third direction D3. The selection protrusion SEP can be positioned at a height higher than the selection base SEB. The selection protrusion SEP can each surround the portion of the cell plug CE that protrudes beyond the selection base SEB. The selection protrusion SEPs can be spaced apart from each other. The selection base SEB can be connected to the selection protrusion SEP.

[0057] The cell plug CE can penetrate the select conductor SEC. The cell plug CE can include an inner cell plug ICE and an outer cell plug OCE. The inner cell plug ICE can be surrounded by the select base SEB of the select conductor SEC. The outer cell plug OCE can be disposed on both sides of the select base SEB of the select conductor SEC.

[0058] The selector base SEB of the selector conductor SEC can contact the sidewall OCE_S of the outer cell plug OCE and the sidewall ICE_S of the inner cell plug ICE. For example, as Figure 1C As shown, the sidewall OCE_S of each outer unit plug OCE may include a portion that contacts the sidewall SEB_S of the selection base SEB of the selection conductor SEC and a portion that contacts one of the outer auxiliary conductors OAC.

[0059] like Figures 1C to 1E As shown, the Selectable Prominence (SEP) can include the External Selectable Prominence (OSEP) and the Internal Selectable Prominence (ISEP). For example... Figure 1C and Figure 1E As shown, the inner selection protrusion ISEP can extend beyond the selection base SEB around the portion of the inner unit plug ICE. For example... Figure 1C As shown, the inner selection protrusion ISEP can contact the side wall ICE_S of the inner unit plug ICE. For example... Figure 1C As shown, the outer selection protrusion OSEP can contact the side wall OCE_S of the outer unit plug OCE.

[0060] like Figure 1A , Figure 1C and Figure 1D As shown, the external auxiliary conductor OAC may include a circular portion RO and a connecting portion CO. The circular portion RO and the connecting portion CO of the external auxiliary conductor OAC may be located in... Figure 1B On the stacked structure STA shown, the circular portion RO and the connecting portion CO of the outer auxiliary conductor OAC can contact the interlayer insulation layer IL in the uppermost part of the stacked structure STA. The circular portion RO can surround the outer unit plug OCE. The circular portion RO can contact the sidewall OCE_S of the outer unit plug OCE. The circular portion RO can surround the portion of the outer unit plug OCE that protrudes beyond the selected conductor SEC.

[0061] The connecting part CO can connect adjacent circular parts RO to each other. The connecting part CO can connect to the selection base SEB of the selection conductor SEC. The sidewall CO_S of the connecting part CO can contact the sidewall SEB_S of the selection base SEB of the selection conductor SEC. The connecting part CO can be positioned at the same height as the selection base SEB of the selection conductor SEC. The connecting part CO can be positioned at a height lower than the height of the selection protrusion SEP of the selection conductor SEC.

[0062] like Figure 1C and Figure 1DAs shown, the circular portion RO may include a circular base ROB and a circular protrusion ROP. The circular base ROB may be disposed at the same height as the connecting portion CO. The circular base ROB may be connected to the connecting portion CO. The connecting portion CO may extend from the circular base ROB in the second direction D2. The circular base ROB may be disposed at the same height as the selection base SEB of the selection conductor SEC. The outer unit plug OCE may be disposed between the circular base ROB and the selection base SEB of the selection conductor SEC. The sidewall of the circular base ROB may contact the sidewall OCE_S of the outer unit plug OCE.

[0063] The circular protrusion ROP can extend from the circular base ROB on the third direction D3. The circular protrusion ROP can extend to a height higher than the height of the select base SEB of the select conductor SEC. The circular protrusion ROP can be positioned at a height higher than the height of the connector CO. The circular protrusion ROP can extend onto the outer select protrusion OSEP of the select conductor SEC. The circular protrusion ROP can surround the outer unit plug OCE. The sidewall of the circular protrusion ROP can contact the sidewall OCE_S of the outer unit plug OCE.

[0064] The circular protrusion (ROP) may include a first part ROP_1, a second part ROP_2, and a third part ROP_3.

[0065] The first portion ROP_1 of the circular protrusion ROP can be positioned at a height higher than the height of the circular base ROB. The first portion ROP_1 of the circular protrusion ROP can be positioned at a height higher than the height of the selection base SEB of the selection conductor SEC. The first portion ROP_1 of the circular protrusion ROP can be positioned at a height higher than the height of the connecting portion CO. The first portion ROP_1 of the circular protrusion ROP can be positioned at the same height as the selection protrusion SEP of the selection conductor SEC. The first portion ROP_1 of the circular protrusion ROP can be connected to the outer selection protrusion OSEP of the selection conductor SEC. The outer unit plug OCE can be positioned between the first portion ROP_1 of the circular protrusion ROP and the outer selection protrusion OSEP of the selection conductor SEC. The first portion ROP_1 of the circular protrusion ROP can extend from the circular base ROB on the third direction D3.

[0066] The second portion ROP_2 of the circular protrusion ROP can be positioned at a height higher than the first portion ROP_1 of the circular protrusion ROP. The second portion ROP_2 of the circular protrusion ROP can be positioned at a height higher than the selection protrusion SEP of the selection conductor SEC. The second portion ROP_2 of the circular protrusion ROP can extend upwards from the first portion ROP_1 of the circular protrusion ROP. The first portion ROP_1 of the circular protrusion ROP can be positioned between the second portion ROP_2 of the circular protrusion ROP and the circular base ROB.

[0067] The third portion ROP_3 of the circular protrusion ROP can be positioned at a height higher than the first portion ROP_1 of the circular protrusion ROP. The third portion ROP_3 of the circular protrusion ROP can be positioned at a height higher than the selection protrusion SEP of the selection conductor SEC. The third portion ROP_3 of the circular protrusion ROP can be positioned at the same height as the second portion ROP_2 of the circular protrusion ROP. The third portion ROP_3 of the circular protrusion ROP can be connected to the second portion ROP_2 of the circular protrusion ROP. The outer unit plug OCE can be positioned between the third portion ROP_3 of the circular protrusion ROP and the second portion ROP_2 of the circular protrusion ROP. The third portion ROP_3 of the circular protrusion ROP can overlap with the outer selection protrusion OSEP and the selection base SEB of the selection conductor SEC. In an embodiment, the third portion ROP_3 of the circular protrusion ROP can overlap with the outer selection protrusion OSEP and the selection base SEB of the selection conductor SEC on a third direction D3. Figure 1C As shown, the bottom surface ROP_3_B of the third part ROP_3 of the circular protrusion ROP can form a common surface with the top surface OSEP_T of the outer selection protrusion OSEP of the selection conductor SEC.

[0068] like Figure 1C and Figure 1E As shown, the inner auxiliary conductor IAC can be set on the inner selection protrusion ISEP of the selection conductor SEC. Figure 1C As shown, the bottom surface IAC_B of the inner auxiliary conductor IAC can form a common surface with the top surface ISEP_T of the inner selection protrusion ISEP of the selection conductor SEC. The inner auxiliary conductor IAC can surround the portion of the inner cell plug ICE that protrudes beyond the selection conductor SEC. The inner auxiliary conductor IAC can contact the sidewall ICE_S of the inner cell plug ICE. The inner auxiliary conductor IAC can be positioned at a height higher than the height of the inner selection protrusion ISEP of the selection conductor SEC. The inner auxiliary conductor IAC can be positioned at the same height as the second portion ROP_2 and the third portion ROP_3 of the circular protrusion ROP of the outer auxiliary conductor OAC.

[0069] like Figure 1C As shown, the third insulating layer 130 may include an intervening portion 131, which is inserted between the outer auxiliary conductor OAC and the inner auxiliary conductor IAC, and between the outer selection protrusion OSEP and the inner selection protrusion ISEP. The intervening portion 131 of the third insulating layer 130 may be inserted between the third portion ROP_3 of the circular protrusion ROP and the inner auxiliary conductor IAC. The intervening portion 131 of the third insulating layer 130 may contact the third portion ROP_3 of the circular protrusion ROP and the inner auxiliary conductor IAC. The intervening portion 131 of the third insulating layer 130 may contact the outer selection protrusion OSEP and the inner selection protrusion ISEP of the selection conductor SEC. The intervening portion 131 of the third insulating layer 130 may contact the top surface SEB_T of the selection base SEB of the selection conductor SEC.

[0070] In reference Figures 1A to 1E In the described semiconductor device, the select conductor SEC, outer auxiliary conductor OAC, and inner auxiliary conductor IAC, which can be used as source select lines, can be formed independently of the conductive layer COL and the select layer SL. Therefore, the number of rows of cell plugs CE controlled by the source select line can be designed independently. In an embodiment, the number of rows of cell plugs CE controlled by the source select line can be designed to be equal to the number of rows of cell plugs CE controlled by the drain select line, thereby reducing interference during read operations. However, embodiments of this disclosure are not limited to this. To reduce interference during read operations, the source select line can be designed such that the number of rows of cell plugs CE controlled by the source select line is less than the number of rows of cell plugs CE controlled by the drain select line.

[0071] In reference Figure 1A In the semiconductor device described in FIG1E, since the select conductor SEC, the outer auxiliary conductor OAC, and the inner auxiliary conductor IAC constitute the source select line, the RC delay of the source select line can be reduced. For example, the resistance of a source select line having a structure in which the outer auxiliary conductor OAC and the inner auxiliary conductor IAC are connected to the select conductor SEC is less than the resistance of a source select line having only the select conductor SEC. Therefore, according to embodiments of the present disclosure, the RC delay of the source select line can be reduced.

[0072] In reference Figures 1A to 1EIn the described semiconductor device, the length of each of the select protrusion SEP, the circular protrusion ROP, and the inner auxiliary conductor IAC in the third direction D3 can be controlled, thereby enabling control of the cutoff characteristics of the source selection transistor controlled by the source selection line. Therefore, even when no separate conductive layer for improving the cutoff characteristics of the source selection transistor is provided between the conductive layer COL used as the word line and the select conductor SEC, the cutoff characteristics of the source selection transistor can still be improved. Therefore, according to embodiments of this disclosure, it is possible to... Figure 1B The STA stack shown excludes the separate conductive layer used to improve the cutoff characteristics of the source selection transistor, thus reducing the height of the STA stack on the third direction D3.

[0073] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 8B It is along Figure 8A The diagram shows a cross-sectional view of the semiconductor device taken by line A2-A2′. Descriptions overlapping with the above description will be omitted in the following text.

[0074] Reference Figure 2 A first substrate 100 can be formed. An isolation layer IS can be formed in the first substrate 100. The gate insulating layer GI and gate electrode GM of each peripheral transistor TR can be formed on the first substrate 100. The impurity region IR of each peripheral transistor TR can be formed on both sides of the gate electrode GM in the first substrate 100. A first contact CT1, a first line ML, and a first bonding pad BP1 connected to the peripheral transistor TR can be formed. A first insulating layer 110 can be formed to cover the first substrate 100. The gate insulating layer GI and the gate electrode GM can be buried in the first insulating layer 110. The first contact CT1, the first line ML1, and the first bonding pad BP1 can be buried in the first insulating layer 110.

[0075] Reference Figure 3 A second substrate 200 can be formed. The second substrate 200 may have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. In an embodiment, the second substrate 200 may be a semiconductor substrate.

[0076] An etch stop layer (ESL) may be formed on the second substrate 200. A selective conductive layer (SEL) is formed on the etch stop layer (ESL). The selective conductive layer (SEL) may include a conductive material. The material included in the etch stop layer (ESL) may have etch selectivity relative to the material included in the selective conductive layer (SEL) and the material included in the second substrate 200. In one embodiment, the selective conductive layer (SEL) may include polysilicon, and the etch stop layer (ESL) may include a nitride.

[0077] A preliminary stacked structure PSTA can be formed on a selectively conductive layer (SEL). Forming the preliminary stacked structure PSTA may include alternately stacking an interlayer insulating layer (IL) and a sacrificial layer (FL) in a third direction (D3) on the selectively conductive layer (SEL). The interlayer insulating layer (IL) and the sacrificial layer (FL) may comprise different materials. In one embodiment, the interlayer insulating layer (IL) may comprise an oxide, and the sacrificial layer (FL) may comprise a nitride.

[0078] Reference Figure 4 A cell plug CE can be formed, which penetrates the preliminary stack-up structure PSTA and the selective conductive layer SEL. The formation of the cell plug CE may include: forming a cell plug via penetrating the preliminary stack-up structure PSTA and the selective conductive layer SEL, and forming a memory layer ML, a channel layer CL, and a fill layer FI in the cell plug via.

[0079] An isolation structure DS can be formed in the upper portion of the preliminary laminated structure PSTA. The formation of the isolation structure DS may include forming a first slit in the upper portion of the preliminary laminated structure PSTA and forming the isolation structure DS in the first slit.

[0080] Reference Figure 5 This process can form a slit structure (SLS), a selective layer (SL), and a conductive layer (COL). The formation of the slit structure (SLS), selective layer (SL), and conductive layer (COL) can include forming a through-hole structure. Figure 4 The second slit of the preliminary stacked structure PSTA shown is used to remove... Figure 4 The illustrated sacrificial layer FL forms a selector layer SL and a conductive layer COL in the empty space created by removing the sacrificial layer FL, and a slit structure SLS is formed in the second slit. Therefore, a stacked structure STA can be defined. The stacked structure may include the selector layer SL, the conductive layer COL, and the interlayer insulating layer IL.

[0081] Reference Figure 6This can form bit line contacts BCT, bit lines BL, second contacts CT2, second lines ML2, second bonding pads BP2, and a second insulating layer 120. The second insulating layer 120 can cover the stacked structure STA. Bit line contacts BCT, bit lines BL, second contacts CT2, second lines ML2, and second bonding pads BP2 can be buried in the second insulating layer 120.

[0082] Reference Figure 7 , Figure 6 The second substrate 200 shown can be aligned on the first substrate 100 such that the first bonding pad BP1 and the second bonding pad BP2 face each other.

[0083] Subsequently, the second bonding pad BP2 can be bonded to the first bonding pad BP1, and the second insulating layer 120 can be bonded to the first insulating layer 110. When the second bonding pad BP2 is bonded to the first bonding pad BP1, the channel layer CL of the cell plug CE can be electrically connected to the peripheral transistor TR through the bit line contact BCT, bit line BL, second contact CT2, second line ML2, second bonding pad BP2, first bonding pad BP1, first line ML1, and first contact CT1.

[0084] Then, it can be removed Figure 7 The second substrate 200 and etch stop layer ESL are shown. The second substrate 200 and etch stop layer ESL can be removed to expose the upper portion of the cell plug CE.

[0085] Reference Figure 8A and Figure 8B A mask layer MA can be formed on the selected conductive layer SEL and the cell plugs CE. The mask layer MA may include an opening OP. The opening OP of the mask layer MA may extend through the mask layer MA in a third direction D3. The opening OP of the mask layer MA may extend in a second direction D2. The opening OP of the mask layer MA may include sidewalls OP_S that overlap with some cell plugs CE. In an embodiment, the sidewall OP_S of each opening OP of the mask layer MA may overlap with a cell plug CE adjacent to the slit structure SLS, or with a cell plug CE adjacent to the isolation structure DS.

[0086] Etching can be performed by using a mask layer MA as an etching barrier. Figure 7 The selective conductive layer (SEL) is shown. As a result, a selective conductor (SEC) can be formed. The portions of the selective conductive layer (SEL) that are isolated from each other by etching can be defined as the selective conductor (SEC).

[0087] The selective conductive layer (SEL) can be etched to expose the slit structure (SLS).

[0088] The cell plug CE adjacent to the slit structure SLS may have a sidewall that protrudes beyond one sidewall of the select conductor SEC. The cell plug CE adjacent to the isolation structure DS may have sidewalls that protrude beyond other sidewalls of the select conductor SEC. A cell plug CE with a sidewall protruding beyond the select conductor SEC can be defined as... Figure 1A The external unit plug OCE is shown.

[0089] After etching the selective conductive layer (SEL), the mask layer (MA) can be removed.

[0090] Reference Figure 9 An auxiliary conductive layer AL can be formed. In an embodiment, the auxiliary conductive layer AL can be formed by a deposition process. The auxiliary conductive layer AL can conformally cover the cell plug CE, the selective conductor SEC, the slot structure SLS, and the stacked structure STA. The auxiliary conductive layer AL can have a uniform thickness. The auxiliary conductive layer AL can include a conductive material different from the conductive material of the selective conductive layer SEL. In an embodiment, the auxiliary conductive layer AL can include titanium nitride.

[0091] Reference Figure 10 It can be etched Figure 9 The auxiliary conductive layer AL is shown. In this embodiment, the auxiliary conductive layer AL can be etched using an etch-back process.

[0092] The auxiliary conductive layer AL can be etched to form the outer auxiliary conductor OAC and the inner auxiliary conductor IAC. The portions of the auxiliary conductive layer AL that are isolated from each other by etching can be defined as the outer auxiliary conductor OAC and the inner auxiliary conductor IAC.

[0093] The select conductor SEC can be etched together with the auxiliary conductive layer AL. The auxiliary conductive layer AL can be etched to expose the top surface of the select conductor SEC. The exposed top surface of the select conductor SEC can be etched. The select conductor SEC can be etched to form the select base SEB and the select protrusion SEP of the select conductor SEC.

[0094] When the auxiliary conductive layer AL is etched, the selective conductor SEC, cell plug CE, slit structure SLS, and stacked structure STA can be exposed again.

[0095] Reference Figure 11 A third insulating layer 130 can be formed. The third insulating layer 130 can cover the unit plug CE, the stacked structure STA, the slit structure SLS, the outer auxiliary conductor OAC, the inner auxiliary conductor IAC, and the select conductor SEC.

[0096] Reference Figure 12The upper portion of the third insulating layer 130 can be removed. In this embodiment, the upper portion of the third insulating layer 130 can be removed by a chemical mechanical polishing (CMP) process and an etching process. The upper portion of the third insulating layer 130 can be removed to expose the upper portion of the cell plug CE.

[0097] Subsequently, the memory layer ML of each cell plug CE can be etched. When the memory layer ML is etched, the upper portion of the memory layer ML can be removed. The memory layer ML can be etched to expose the upper portion of the channel layer CL.

[0098] Subsequently, as Figure 1B As shown, a source layer SOL can be formed connected to the channel layer CL. In this embodiment, the source layer SOL can be formed by a deposition process and a chemical mechanical polishing (CMP) process. Subsequently, as... Figure 1B As shown, a source barrier layer (SOB) can be formed on the source layer (SOL). In this embodiment, the source barrier layer (SOB) can be formed by a deposition process.

[0099] According to embodiments of this disclosure, the length of each of the outer auxiliary conductor OAC and the inner auxiliary conductor IAC in the third direction D3 can be varied according to the etching amount of the auxiliary conductive layer AL. By adjusting the etching amount of the auxiliary conductive layer AL, the length of each of the outer auxiliary conductor OAC and the inner auxiliary conductor IAC can meet the target. The etching amount of the auxiliary conductive layer AL can be controlled to meet the design target of the cutoff characteristics of the selected transistor.

[0100] According to embodiments of this disclosure, Figure 8A and Figure 8B The width of each opening OP in the mask layer MA shown is not limited to no more than the distance between adjacent cell plugs CE, and can be broadly configured to overlap with some cell plugs CE. Therefore, according to embodiments of this disclosure, openings OP in the mask layer MA used as a target can be formed even without using a high-resolution exposure device.

[0101] like Figure 8B As shown, it can be done through Figure 8A and Figure 8B The selected conductor SEC defined by the opening OP of the mask layer MA shown exposes some of the sidewalls of the cell plug CE. According to an embodiment of this disclosure, such as Figure 12 As shown, an outer auxiliary conductor OAC and an inner auxiliary conductor IAC can be formed on the sidewall of the cell plug CE exposed by the select conductor SEC. Select lines can be configured with the select conductor SEC, outer auxiliary conductor OAC, and inner auxiliary conductor IAC connected to each other. In embodiments of this disclosure, a gate all-around structure can be provided by the select lines surrounding the sidewall of each cell plug CE.

[0102] Figure 13A This is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 13B It is along Figure 13A The diagram shows a cross-sectional view of the semiconductor device taken by line A3-A3′. Figure 13C yes Figure 13B An enlarged view of region B2 shown. Figure 13D This is an example Figures 13A to 13C A three-dimensional view of the external auxiliary conductor and external unit plug of the semiconductor device shown. Figure 13E This is an example Figures 13A to 13C A perspective view of the internal auxiliary conductors and internal cell plugs of the semiconductor device shown. In the following text, descriptions overlapping with the above description will be omitted.

[0103] Reference Figure 13A and Figure 13B The semiconductor device may include a stacked structure STAa, a selectable layer SL, an interlayer insulating layer IL, and a conductive layer COL. The stacked structure STAa may be disposed on the first substrate 100.

[0104] An isolation layer IS and an impurity region IR of a peripheral transistor TR can be formed in the first substrate 100. A first insulating layer 110, a gate insulating layer GI and a gate electrode GM of each peripheral transistor TR, a first contact CT1, a first line ML1, a first bonding pad BP1, a second insulating layer 120, a second bonding pad BP2, a second line ML2, a second contact CT2, a bit line, and a bit line contact BCT can be disposed between the first substrate 100 and the stacked structure STAa.

[0105] The selector conductor SECa can be placed on the laminated structure STAa. The selector conductor SECa can also be placed on the interlayer insulating layer IL. The selector conductor SECa can be placed at a height higher than the height of the laminated structure STAa. The selector layer SL, the conductive layer COL, the interlayer insulating layer IL, and the selector conductor SECa can overlap each other in the third direction D3. The selector conductor SECa can be placed at a height higher than the heights of the conductive layer COL and the selector layer SL. The selector conductor SECa can be inserted around the cell plug CE.

[0106] Each selective conductor SECa can have a uniform thickness. The thickness of each selective conductor SECa can be defined as a third direction D3. The thickness of each selective conductor SECa can be equal to the thickness of each of the conductive layer COL and the selective layer SL. The selective conductor SECa can comprise the same conductive material as the conductive layer COL and the selective layer SL. In an embodiment, the selective conductor SECa can comprise tungsten.

[0107] The outer auxiliary conductor OACa and the inner auxiliary conductor IACa can contact each selector conductor SECa. The outer auxiliary conductor OACa can be positioned on both sides of the selector conductor SECa. The selector conductor SECa can be positioned between the outer auxiliary conductors OACa. The inner auxiliary conductor IACa can be positioned between the outer auxiliary conductors OACa.

[0108] The interconnected select conductor SECa, outer auxiliary conductor OACa, and inner auxiliary conductor IACa can constitute the select line of a semiconductor device. In an embodiment, the interconnected select conductor SECa, outer auxiliary conductor OACa, and inner auxiliary conductor IACa can be used as the source select line of a semiconductor device.

[0109] The third insulating layer 130a may cover the laminated structure STAa, the slit structure SLS, the selective conductor SECa, the outer auxiliary conductor OACa, and the inner auxiliary conductor IACa.

[0110] Reference Figure 13A , Figure 13C , Figure 13D and Figure 13E The element plug CE can penetrate the selector conductor SECa. The inner element plug ICE within the element plug CE can be surrounded by the selector conductor SECa. The outer element plug OCE within the element plug CE can be disposed on both sides of the selector conductor SECa. The outer element plug OCE can contact the sidewall SECa_S of the selector conductor SECa. The selector conductor SECa can contact the sidewall OCE_S of each outer element plug OCE and the sidewall ICE_S of each inner element plug ICE. The selector conductor SECa can overlap with the outer auxiliary conductor OACa and the inner auxiliary conductor IACa.

[0111] Each external auxiliary conductor OACa may include a circular portion ROa and a connecting portion COa. The circular portion ROa and the connecting portion COa of the external auxiliary conductor OACa can be provided on the laminated structure STAa. The circular portion ROa and the connecting portion COa of the external auxiliary conductor OACa can contact the interlayer insulation layer IL located at the topmost part of the laminated structure STAa. The circular portion ROa can surround the outer unit plug OCE, respectively. Each circular portion ROa can contact the sidewall OCE_S of the outer unit plug OCE.

[0112] Each connecting part COa can connect adjacent circular parts ROa to each other. Connecting part COa can connect to the selector conductor SECa. The sidewall COa_S of connecting part COa can contact the sidewall SECa_S of selector conductor SECa. Connecting part COa can be positioned at the same height as selector conductor SECa. The maximum thickness of connecting part COa in the third direction D3 can be equal to the maximum thickness of selector conductor SECa in the third direction D3.

[0113] like Figure 13C and Figure 13D As shown, the circular portion ROa may include a circular base ROBa and a circular protrusion ROPa. The circular base ROBa may be positioned at the same height as the connecting portion COa. The circular base ROBa may be connected to the connecting portion COa. The circular base ROBa may extend from the connecting portion COa. The circular base ROBa may be positioned at the same height as the selection conductor SECa. The circular base ROBa may be connected to the selection conductor SECa. The sidewall of the circular base ROBa may contact the sidewall SECa_S of the selection conductor SECa. The outer unit plug OCE may be disposed between the circular base ROBa and the selection conductor SECa. The sidewall of the circular base ROBa may contact the sidewall OCE_S of the outer unit plug OCE.

[0114] The circular protrusion ROPa can be positioned at a height higher than the circular base ROBa. The circular protrusion ROPa can be positioned at a height higher than the selector conductor SECa. The circular protrusion ROPa can be positioned at a height higher than the connector COa. The circular protrusion ROP can surround the outer unit plug OCE. The sidewall of the circular protrusion ROPa can contact the sidewall OCE_S of the outer unit plug OCE. The circular protrusion ROPa can extend from the circular base ROBa in the third direction D3. The circular protrusion ROPa can extend to overlap with the selector conductor SECa. The bottom surface ROPa_B of the circular protrusion ROPa can form a common surface with the top surface SECa_T of the selector conductor SECa.

[0115] Reference Figure 13C and Figure 13E An inner auxiliary conductor IACa can be placed on the selector conductor SECa. The bottom surface IACa_B can form a common surface with the top surface SECa_T of the selector conductor SECa. The inner auxiliary conductor IACa can surround the inner cell plug ICE. The inner auxiliary conductor IACa can contact the sidewall ICE_S of the inner cell plug ICE. The inner auxiliary conductor IACa can be positioned at a height higher than the selector conductor SECa. The inner auxiliary conductor IACa can be positioned at the same height as the circular protrusion ROPa of the outer auxiliary conductor OACa.

[0116] Reference Figure 13CThe third insulating layer 130a may include an intervening portion 131a inserted between the outer auxiliary conductor OACa and the inner auxiliary conductor IACa. The intervening portion 131a of the third insulating layer 130a may be inserted between the circular protrusion ROPa of the outer auxiliary conductor OACa and the inner auxiliary conductor IACa. The intervening portion 131a of the third insulating layer 130a may contact the circular protrusion ROPa of the outer auxiliary conductor OACa and the inner auxiliary conductor IACa. The intervening portion 131a of the third insulating layer 130a may contact the top surface SECa_T of the selective conductor SECa.

[0117] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, descriptions overlapping with the above description will be omitted.

[0118] Reference Figure 14 An etch stop layer ESLa can be formed on the second substrate 200. An interlayer sacrificial layer FIL, a selective sacrificial layer SFL, and a preliminary stack structure PSTAa can be sequentially formed on the etch stop layer ESLa. The interlayer sacrificial layer FIL can include an oxide or a material that has etch selectivity relative to the selective sacrificial layer SFL and the preliminary stack structure PSTAa. In one embodiment, the material with etch selectivity relative to the selective sacrificial layer SFL and the preliminary stack structure PSTAa can be silicon. The selective sacrificial layer SFL can include an insulating material. In one embodiment, the selective sacrificial layer SFL can include a nitride.

[0119] Reference Figure 15 It can form a unit plug CE, which penetrates through Figure 14 The preliminary stacked structure shown is PSTAa, the selected sacrificial layer SFL, and the interlayer sacrificial layer FIL. It can be... Figure 14 An isolation structure DS is formed in the upper part of the preliminary stacked structure PSTAa shown.

[0120] A selective layer SL, a conductive layer COL, a selective conductive layer SELa, and a slit structure SLS can be formed. The formation of the selective layer SL, the conductive layer COL, the selective conductive layer SELa, and the slit structure SLS may include: forming a through-hole structure. Figure 14The first slit shown depicts a stacked sacrificial layer FL, an interlayer insulating layer IL, and a selective sacrificial layer SFL. The stacked sacrificial layer FL and the selective sacrificial layer SFL are removed through the first slit. A selective layer SL and a conductive layer COL are formed in the empty space created by removing the stacked sacrificial layer FL. A selective conductive layer SELa is formed in the empty space created by removing the selective sacrificial layer SFL. A slit structure SLS is formed in the first slit. Therefore, a stacked structure STAa comprising the selective layer SL, the conductive layer COL, and the interlayer insulating layer IL can be defined. The selective layer SL, the conductive layer COL, and the selective conductive layer SELa can be formed from the same metallic material. The interlayer sacrificial layer FL may not be penetrated by the slit structure SLS.

[0121] A second insulating layer 120, bit line contact BCT, bit line BL, second contact CT2, second line ML2, and second bonding pad BP2 can be formed on the stacked structure STAa.

[0122] Reference Figure 16 , Figure 15 The second substrate 200 shown can be used by referring to Figure 2 The described process results in structural alignment. For example, Figure 15 The second substrate 200 shown can be aligned on the first substrate 100 such that the second bonding pad BP2 faces the first bonding pad BP1. The impurity region IR and gate electrode GM of each peripheral transistor TR can be connected to the second bonding pad BP2 via the first contact CT1, the first line ML1, and the first bonding pad BP1. The peripheral transistors TR can be electrically isolated from each other through the isolation layer IS in the first substrate 100. The gate insulating layer GI and gate electrode GM, the first contact CT1, the first line ML1, and the first bonding pad BP1 of each peripheral transistor TR can be buried in the first insulating layer 110. The first insulating layer 110 can cover the first substrate 100.

[0123] The second bonding pad BP2 can be bonded to the first bonding pad BP1, and the second insulating layer 120 can be bonded to the first insulating layer 110.

[0124] Then, they can be removed sequentially. Figure 15 The second substrate 200, etch stop layer ESLa, and interlayer sacrificial layer FIL are shown. The interlayer sacrificial layer FIL is removed to expose the top surface of the selective conductive layer SELa.

[0125] Reference Figure 17 , can Figure 16 A mask layer MAa is formed on the cell plug CE and the selected conductive layer SELa, as shown. The mask layer MAa may include an opening OPa.

[0126] Etching can be performed by using a mask layer MAa as an etching barrier. Figure 16 The selective conductive layer SELa is shown. As a result, a selective conductor SECa can be formed. The portions of the selective conductive layer SELa that are isolated from each other by etching can be defined as the selective conductor SECa. After etching the selective conductive layer SELa, the mask layer MAa can be removed.

[0127] Reference Figure 18 An auxiliary conductive layer ALa can be formed. The auxiliary conductive layer ALa can conformally cover the cell plug CE, the selective conductor SECa, the slit structure SLS, and the stacked structure STAa. The auxiliary conductive layer ALa can include a conductive material different from the conductive material of the selective conductive layer SELa. In an example, the auxiliary conductive layer ALa can include titanium nitride.

[0128] Reference Figure 19 It can be etched Figure 18 The auxiliary conductive layer ALa is shown. As a result, an outer auxiliary conductor OACa and an inner auxiliary conductor IACa can be formed.

[0129] Subsequently, it can form Figure 13B The third insulating layer 130a, source layer SOL, and source barrier layer SOB are shown.

[0130] Figure 20A and Figure 20B This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 20B yes Figure 20A The image shows an enlarged view of region B3. Descriptions overlapping with the above description will be omitted in the following text.

[0131] Reference Figure 20A The stacked structure STAb can be disposed on the first substrate 100. The isolation layer IS and the impurity region IR of the peripheral transistor TR can be formed in the first substrate 100. The first insulating layer 110, the gate insulating layer GI and gate electrode GM of each peripheral transistor TR, the first contact CT1, the first line ML1, the first bonding pad BP1, the second insulating layer 120, the second bonding pad BP2, the second line ML2, the second contact CT2, the bit line BL and the bit line contact BCT can be disposed between the first substrate 100 and the stacked structure STAb.

[0132] The stacked structure STAb may include a selective layer SL, an interlayer insulating layer IL, a conductive layer COL, a first barrier insulating layer BI1, and a second barrier insulating layer BI2. Each of the selective layer SL, the interlayer insulating layer IL, and the conductive layer COL may extend in a first direction D1 and a second direction D2.

[0133] Each of the interlayer insulating layer IL and the conductive layer COL may surround the cell plug CE. The cell plug CE may include an outer cell plug OCE and an inner cell plug ICE. On a plane extending along a first direction D1 and a second direction D2, the outer cell plug OCE and the inner cell plug ICE may have the following characteristics: Figure 1A or Figure 13A The same arrangement as shown.

[0134] Interlayer insulating layers IL can be spaced apart from each other in the third direction D3. Selective layer SL and conductive layer COL can be respectively disposed in the space between adjacent interlayer insulating layers IL in the third direction D3. Selective layers SL of the laminated structure STAb can be spaced apart from each other in the first direction D1 by isolation structure DS. Selective layers SL disposed at the same height can be electrically isolated from each other by isolation structure DS.

[0135] The first barrier insulating layer BI1 can contact the conductive layer COL. The first barrier insulating layer BI1 can be disposed between the conductive layer COL and the unit plug CE. The first barrier insulating layer BI1 can extend between the conductive layer COL and the interlayer insulating layer IL.

[0136] The second barrier insulating layer BI2 can contact the selector layer SL. The second barrier insulating layer BI2 can be disposed between the selector layer SL and the cell plug CE. The second barrier insulating layer BI2 can extend between the selector layer SL and the interlayer insulating layer IL. The second barrier insulating layer BI2 can extend between the selector layer SL and the isolation structure DS.

[0137] The selector conductor SECb can be disposed on the stacked structure STAb. The selector conductor SECb can surround the cell plug CE at a height higher than the conductive layer COL and the selector layer SL. The selector conductor SECb can contact the third barrier insulating layer BI3. The third barrier insulating layer BI3 can be disposed between the selector conductor SECb and the cell plug CE. The third barrier insulating layer BI3 can extend between the selector conductor SECb and the interlayer insulating layer IL disposed on the uppermost part of the stacked structure STAb.

[0138] Each cell plug CE may include a fill layer FI, a channel layer CL, and a memory layer ML. The memory layer ML may include not only a data storage layer, but also a tunnel insulation layer located between the data storage layer and the channel layer CL, and a fourth barrier insulation layer surrounding the data storage layer.

[0139] The first barrier insulating layer BI1, the second barrier insulating layer BI2, and the third barrier insulating layer BI3 may comprise the same insulating material. Alternatively, the first barrier insulating layer BI1, the second barrier insulating layer BI2, and the third barrier insulating layer BI3 may comprise an insulating material with a dielectric constant higher than that of the fourth barrier insulating layer in the memory layer ML. In an embodiment, each of the first barrier insulating layer BI1, the second barrier insulating layer BI2, and the third barrier insulating layer BI3 may comprise a metal oxide such as aluminum oxide, and the fourth barrier insulating layer of the memory layer ML may comprise silicon dioxide.

[0140] The selective conductor SECb may comprise the same conductive material as the conductive layer COL and the selective layer SL. In one embodiment, the selective conductor SECb may comprise tungsten.

[0141] The outer auxiliary conductor OACb and the inner auxiliary conductor IACb can contact each select conductor SECb. The outer auxiliary conductor OACb can be located on both sides of the select conductor SECb. The select conductor SECb can be located between the outer auxiliary conductors OACb. The select conductors SECb, outer auxiliary conductors OACb, and inner auxiliary conductors IACb connected to each other can form the select line of the semiconductor device.

[0142] The third insulating layer 130a may cover the stacked structure STAb, the slit structure SLS, the selector conductor SECb, the outer auxiliary conductor OACb, and the inner auxiliary conductor IACb. The third insulating layer 130a may contact the selector conductor SECb. The source layer SOL may contact the channel layer CL, which protrudes further from the third insulating layer 130a in the third direction D3 of each cell plug CE. The source barrier layer SOB may be connected to the channel layer CL via the source layer SOL.

[0143] Reference Figure 20B The external auxiliary conductor OACb can be disposed on both sides of the selected conductor SECb. Each external auxiliary conductor OACb can include a circular portion ROb and a connecting portion COb. The circular portion ROb and the connecting portion COb of each external auxiliary conductor OACb can contact the interlayer insulation layer IL.

[0144] The three-dimensional structure of the circular portion ROb and the connecting portion COb of each external auxiliary conductor OACb can be compared with... Figure 13D The circular portion ROa and the connecting portion COa shown have the same three-dimensional structure. For example, with Figure 13D The circular part ROa and the connecting part COa shown are similar, and each connecting part COb can be connected to the circular parts ROb that are adjacent to each other in the second direction D2.

[0145] Each circular portion ROb can surround an outer unit plug OCE corresponding to the circular portion ROb. Each circular portion ROb can include a circular base ROBb and a circular protrusion ROPb. The three-dimensional structure of the circular base ROBb and the circular protrusion ROPb can be... Figure 13D The circular base ROBa and the circular protrusion ROPa shown have the same three-dimensional structure. For example, with Figure 13D Similar to the circular base ROBb and circular protrusion ROPb shown, the circular base ROBb and circular protrusion ROPb can surround the outer cell plug OCE. The circular base ROBb can be positioned at the same height as the connector COb. The circular protrusion ROPb can extend from the circular base ROBb toward the source layer SOL. The circular protrusion ROPb can overlap with the selector conductor SECb.

[0146] The inner auxiliary conductor IACb can overlap with the selective conductor SECb. The three-dimensional structure of the inner auxiliary conductor IACb can be... Figure 13E The auxiliary conductor IACa shown has the same three-dimensional structure. For example, with Figure 13E Similar to the auxiliary conductor IACa shown, the inner auxiliary conductor IACb can be inserted around the inner unit ICE respectively.

[0147] The selector conductor SECb may include a top surface SECb_T facing the source layer SOL. The selector conductor SECb may include a sidewall SECb_S facing each of the connection portions COb of the outer auxiliary conductors OACb. The top surface SECb_T and sidewall SECb_S of the selector conductor SECb are not covered by the third barrier insulation layer BI3 and may be open. The top surface SECb_T of the selector conductor SECb may contact each circular protrusion ROPb of each outer auxiliary conductor OACb and the inner auxiliary conductor IACb. The sidewall SECb_S of the selector conductor SECb may contact the connection portion COb of the outer auxiliary conductors OACb. Therefore, the selector conductor SECb, the outer auxiliary conductors OACb, and the inner auxiliary conductor IACb can be connected to each other.

[0148] The memory layer ML and channel layer CL of each cell plug CE can protrude further toward the source layer SOL than the outer auxiliary conductor OACb and inner auxiliary conductor IACb. The channel layer CL of each cell plug CE can protrude further toward the source layer SOL than the memory layer ML of each cell plug CE.

[0149] The insulating layer 130a may include an intervening portion 131a, which is inserted between the outer auxiliary conductor OACb and the inner auxiliary conductor IACb. The intervening portion 131a of the third insulating layer 130a may contact the top surface SECb_T of the selected conductor SECb. The third insulating layer 130a may surround the memory layer ML between the circular portion ROb of each outer auxiliary conductor OACb and the source layer SOL, and the memory layer ML between the inner auxiliary conductor IACb and the source layer SOL.

[0150] The channel layer CL of each plug cell CE may protrude further toward the source layer SOL than the third insulating layer 130a. The channel layer CL of each plug cell CE may contact the source layer SOL.

[0151] Figure 21 , Figure 22 , Figure 23 and Figure 24 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, descriptions overlapping with the above description will be omitted.

[0152] In execution Figure 21 Before the process shown, it is possible to... Figure 14 As shown, an etch stop layer ESLa, an interlayer sacrificial layer FIL, a selective sacrificial layer SFL, and a preliminary stacked structure PSTAb are sequentially formed on the second substrate 200.

[0153] Reference Figure 21 The unit plug CE can be formed as a through-hole. Figure 14 The preliminary stacked structure PSTAa is shown, along with the selected sacrificial layer SFL and the interlayer sacrificial layer FIL. The isolation structure DS can be formed in... Figure 14 In the upper portion of the preliminary stacked structure PSTAa shown, each cell plug CE may include a memory layer ML, a channel layer CL, and a fill layer FI.

[0154] Subsequently, the first slit SI1 can be formed to not only penetrate... Figure 14 The preliminary laminated structure PSTAa shown consists of a sacrificial layer FL and an interlayer insulating layer IL, with the selective sacrificial layer SFL extending through it. Subsequently, it can be removed through the first slit SI1. Figure 14 The stacked sacrificial layer FL and the selected sacrificial layer SFL are shown. Empty spaces 251, 252, and 253 can be defined in the regions in which the stacked sacrificial layer FL and the selected sacrificial layer SFL have been removed.

[0155] Spaces 251, 252, and 253 may include a first space 251, a second space 252, and a third space 253. The first space 251 may be confined therein and removed. Figure 14The region of the stacked sacrificial layer FL between the isolation structure DS and the etch stop layer ESLa is shown. The second space 252 can be defined therein where the sacrificial layer FL was removed. Figure 14 The region of the stacked sacrificial layer FL that contacts the isolation structure DS, as shown. The third space 253 can be confined within it, where the removed... Figure 14 The area shown is the region where the sacrifice layer SFL is selected.

[0156] Reference Figure 22 The barrier insulating layers BI1, BI2, and BI3 can be formed respectively in Figure 21 The surfaces of the first space 251, the second space 252, and the third space 253 are shown. Barrier insulating layers BI1, BI2, and BI3 may surround the sidewalls of each unit plug CE. Barrier insulating layers BI1, BI2, and BI3 may include a first barrier insulating layer BI1, a second barrier insulating layer BI2, and a third barrier insulating layer BI3. The first barrier insulating layer BI1 may be disposed on... Figure 21 The second barrier insulating layer BI2 can be disposed on the surface of the first space 251 shown. Figure 21 The surface of the second space 252 shown. A third barrier insulating layer BI3 can be disposed on... Figure 21 On the surface of the third space 253 shown.

[0157] Subsequently, a selective conductive layer SELb, a conductive layer COL, and a selective layer SL can be formed. Therefore, a stacked structure STAb can be defined. The stacked structure STAb may include an interlayer insulating layer IL, a first barrier insulating layer BI1, a second barrier insulating layer BI2, a conductive layer COL, and a selective layer SL.

[0158] Choosing the conductive layer SELb can fill... Figure 21 This is a portion of the third space 253 shown. This portion of the third space 253 can be defined as the area not filled with the third barrier insulating layer BI3. The conductive layer COL can fill it. Figure 21 This is a portion of the first space 251 shown. This portion of the first space 251 can be defined as the area not filled with the first barrier insulating layer BI1. The selective layer SL can be filled... Figure 21 This is a portion of the second space 252 shown. This portion of the second space 252 can be defined as the area not filled with the second barrier insulating layer BI2.

[0159] After forming the cascaded structure STAb, it is possible to... Figure 21 A slit structure SLS is formed in the first slit SI1 shown. Subsequently, a second insulating layer 120, bit line contact BCT, bit line BL, second contact CT2, second line ML2, and second bonding pad BP2 can be formed on the stacked structure STAb.

[0160] Reference Figure 23 , Figure 22 The second substrate 200 shown can be used by referring to Figure 2 The described process results in structural alignment. For example, Figure 22 The substrate 200 shown can be aligned on the first substrate 100 such that the second bonding pad BP2 faces the first bonding pad BP1. The impurity region IR and gate electrode GM of each peripheral transistor TR can be connected to the second bonding pad BP2 via the first contact CT1, the first line ML1, and the first bonding pad BP1. The peripheral transistors TR can be electrically isolated from each other through the isolation layer IS in the first substrate 100. The gate insulating layer GI and gate electrode, the first contact CT1, the first line ML1, and the first bonding pad BP1 of each peripheral transistor TR can be buried in the first insulating layer 110. The first insulating layer 110 can cover the first substrate 100.

[0161] The second bonding pad BP2 can be bonded to the first bonding pad BP1, and the second insulating layer 120 can be bonded to the first insulating layer 110.

[0162] Then, they can be removed sequentially. Figure 22 The second substrate 200, etch stop layer ESLa, and interlayer sacrificial layer FIL are shown. The interlayer sacrificial layer FIL is removed to expose a portion of the third barrier insulating layer BI3. The exposed portion of the third barrier insulating layer BI3 is removed to expose the top surface of the selective conductive layer SELb.

[0163] The third barrier insulating layer BI3 may be retained between each cell plug CE and the selective conductive layer SELb. The third barrier insulating layer BI3 may also be retained between adjacent selective conductive layers SELb and interlayer insulating layers IL.

[0164] Reference Figure 24 The mask layer MAa can be formed on Figure 23 The cell plug CE and the selected conductive layer SELb are shown. The mask layer MAa may include an opening OPa.

[0165] Etching can be performed by using a mask layer MAa as an etching barrier. Figure 23 The diagram shows the selective conductive layer SELb and the third barrier insulating layer BI3. Therefore, selective conductors SECb, which are isolated from each other, can be defined, and the sidewalls of each selective conductor SECb can be exposed. After forming the selective conductors SECb, the mask layer MAa can be removed.

[0166] Then, the reference can be executed. Figure 18 and Figure 19 The described process.

[0167] Figure 25 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0168] Reference Figure 25 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0169] The memory device 1120 may include the semiconductor device described above. The memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

[0170] Memory controller 1110 is configured to control memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction code (ECC) circuitry 1114, and memory interface 1115. SRAM 1111 serves as operating memory for CPU 1112, which performs overall control operations for data exchange with memory controller 1110. Host interface 1113 includes a data exchange protocol for a host connected to memory system 1100. ECC circuitry 1114 detects and corrects errors contained in data read from memory device 1120, and memory interface 1115 interfaces with memory device 1120. Additionally, memory controller 1110 may also include read-only memory (ROM) for storing code data for connection to the host interface.

[0171] The memory system 1100 configured as described above can be a memory card or solid-state drive (SSD) in which the memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external (e.g., a host) via one of a variety of interface protocols such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Rapid (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronic Devices (IDE) protocol.

[0172] Figure 26 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0173] Reference Figure 26The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing operating voltage to the computing system 1200, and may also include an application chipset, a camera image processor, mobile DRAM, etc.

[0174] The memory system 1210 can be configured with reference to Figure 25 The memory device 1120 and memory controller 1110 described are similar to memory devices 1212 and memory controller 1211.

[0175] In the semiconductor device according to this disclosure, a structure in which the select conductor and the auxiliary conductor are connected to each other is used as a select line, which reduces the RC delay of the select line. Therefore, the operational reliability of the semiconductor device can be improved.

[0176] Cross-references to related applications

[0177] This application claims priority to Korean Patent Application No. 10-2020-0172729, filed with the Korean Intellectual Property Office on December 10, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A conductive layer and an interlayer insulating layer, wherein the conductive layer and the interlayer insulating layer are alternately stacked; Selected conductor, which is spaced apart from the conductive layer; A unit plug, the unit plug penetrating the conductive layer, the interlayer insulating layer and the selective conductor, the unit plug including an outer unit plug and an inner unit plug; An external auxiliary conductor surrounds the external unit plug and is in contact with the selection conductor; as well as Inner auxiliary conductors, each surrounding the inner unit plug, The external auxiliary conductor includes a circular portion and a connecting portion. The circular portions surround the outer unit plug. The connecting portion connects adjacent circular portions, and The selected conductor is in contact with the unit plug.

2. The semiconductor device according to claim 1, wherein, The circular portions surround portions of the outer unit plug, and the portions of the outer unit plug protrude beyond the selector conductor.

3. The semiconductor device according to claim 1, wherein, Each of the circular portions includes a circular base at the same height as the connecting portion and a circular protrusion at a height higher than the connecting portion.

4. The semiconductor device according to claim 3, wherein, The circular protrusion extends from the circular base.

5. The semiconductor device according to claim 3, wherein, The circular protrusion includes a first portion disposed at the same height as the selection conductor and a second portion disposed at a height higher than the selection conductor.

6. The semiconductor device according to claim 3, wherein, The circular protrusion overlaps with the selected conductor.

7. The semiconductor device according to claim 1, wherein, The selection conductor includes a selection base disposed at the same height as the connection portion and an outer selection protrusion disposed at a height higher than the height of the connection portion.

8. The semiconductor device according to claim 7, wherein, The outer protruding portion contacts the circular portion.

9. The semiconductor device according to claim 7, wherein, The sidewall of each of the connecting portions contacts the sidewall of the selected base portion.

10. The semiconductor device of claim 1, further comprising a barrier insulating layer disposed between each of the outer unit plugs and the selection conductor. in, The barrier insulation layer extends between the selected conductor and the interlayer insulation layer adjacent to the selected conductor.

11. The semiconductor device according to claim 10, wherein, The selective conductor includes sidewalls and a top surface, neither of which is covered by the barrier insulation layer. Each of the connecting portions contacts the sidewall of the selected conductor, and Each of the circular portions is in contact with the top surface of the selected conductor.

12. The semiconductor device according to claim 1, in, The external auxiliary conductor includes a first conductive material and the selected conductor includes a second conductive material. The first conductive material is different from the second conductive material.

13. The semiconductor device according to claim 12, wherein, The external auxiliary conductor includes titanium nitride.

14. The semiconductor device according to claim 13, wherein, The selected conductor includes polycrystalline silicon.

15. A semiconductor device comprising: A conductive layer and an interlayer insulating layer, wherein the conductive layer and the interlayer insulating layer are alternately stacked; Selected conductor, which is spaced apart from the conductive layer; A unit plug, the unit plug penetrating the conductive layer, the interlayer insulating layer and the selective conductor, the unit plug including an outer unit plug and an inner unit plug; An external auxiliary conductor surrounds the outer unit plug; as well as An inner auxiliary conductor, which is in contact with the selected conductor. The inner auxiliary conductors respectively surround the inner unit plug, and The inner auxiliary conductor is positioned at a height higher than that of the selected conductor.

16. The semiconductor device according to claim 15, wherein, The selection conductor includes a selection base and an inner selection protrusion extending from the selection base.

17. The semiconductor device according to claim 16, wherein, The top surface of each inner selection protrusion and the bottom surface of each inner auxiliary conductor form a common surface.

18. The semiconductor device according to claim 16, wherein, The inner selection protrusions are respectively surrounding the portion of the inner unit plug that protrudes beyond the selection base.

19. The semiconductor device according to claim 15, wherein, The inner auxiliary conductor and the outer auxiliary conductor comprise the same material, and the selected conductor comprises a material different from that of the inner auxiliary conductor.

20. The semiconductor device according to claim 15, in, The inner auxiliary conductor includes a first conductive material and the selected conductor includes a second conductive material. The first conductive material is different from the second conductive material.

21. The semiconductor device according to claim 15, wherein, The internal auxiliary conductor comprises titanium nitride.

22. The semiconductor device according to claim 15, wherein, The selected conductor includes polycrystalline silicon.

23. A semiconductor device comprising: A conductive layer and an interlayer insulating layer, wherein the conductive layer and the interlayer insulating layer are alternately stacked; Selected conductor, which is spaced apart from the conductive layer; A unit plug that penetrates the conductive layer, the interlayer insulating layer, and the selective conductor; as well as An outer auxiliary conductor and an inner auxiliary conductor, respectively surrounding the unit plug. The selection conductor includes a selection base surrounding the unit plug and a selection protrusion protruding from the selection base along the length of the unit plug.

24. The semiconductor device according to claim 23, wherein, The unit plug includes an inner unit plug surrounded by the selection base and outer unit plugs disposed on both sides of the selection base.

25. The semiconductor device according to claim 24, wherein, The selection protrusion includes an inner selection protrusion, and The inner selection protrusions surround the inner unit plug.

26. The semiconductor device of claim 25, wherein, The bottom surface of each inner auxiliary conductor and the top surface of each inner selective protrusion form a common surface.

27. The semiconductor device according to claim 24, wherein, The selection protrusion includes an outer selection protrusion surrounding the outer unit plug.

28. The semiconductor device according to claim 27, wherein, The external auxiliary conductor contacts the sidewall of the selection base and the sidewall of each of the external selection protrusions.

29. The semiconductor device according to claim 23, wherein, The selected protrusions are spaced apart from each other.

30. A method for manufacturing a semiconductor device, the method comprising the following steps: A selectively conductive layer is formed on the substrate; A stacked structure is formed on the selected conductive layer; Forming a unit plug that penetrates the selected conductive layer and the stacked structure; The cell plug and the selective conductive layer are exposed by removing the substrate; The selected conductive layer is isolated into a selected conductor; An auxiliary conductive layer is formed covering the selected conductor; as well as Etch the auxiliary conductive layer, The step of etching the auxiliary conductive layer includes forming an outer auxiliary conductor that contacts the sidewall of the selected conductor and an inner auxiliary conductor that overlaps with the selected conductor. The selected conductive layer is in contact with the unit plug.

31. The method according to claim 30, wherein, The auxiliary conductive layer comprises a material different from that of the selected conductive layer.

32. The method according to claim 30, wherein, The external auxiliary conductor surrounds the unit plug.

33. The method according to claim 30, wherein, The inner auxiliary conductors surround the unit plugs respectively.

34. The method of claim 30, further comprising the step of: An etch stop layer is formed on the substrate.

35. The method according to claim 34, wherein, The material comprising the etch stop layer is etch-selective relative to the material comprising the selective conductive layer.

36. The method according to claim 30, wherein, The step of isolating the selected conductive layer into the selected conductor includes the following steps: A mask layer including openings is formed on the selected conductive layer; and The selected conductive layer is etched by using the mask layer as an etching barrier.

37. The method of claim 36, wherein, The opening has sidewalls that overlap with some of the unit plugs.

38. The method according to claim 36, wherein, The unit plug includes an outer unit plug, the sidewall of which protrudes beyond the sidewall of the selected conductor.

39. The method according to claim 38, wherein, The auxiliary conductive layer surrounds the sidewall of the outer unit plug.

40. A method for manufacturing a semiconductor device, the method comprising the following steps: An interlayer sacrificial layer is formed on the substrate; A selective sacrifice layer is formed on the interlayer sacrificial layer; A preliminary stacked structure is formed on the selected sacrificial layer; Forming a unit plug that penetrates the initial stacked structure, the selected sacrificial layer, and the interlayer sacrificial layer; Remove the selected sacrifice layer; A selective conductive layer is formed in the region where the selective sacrificial layer has been removed; The cell plug and the selective conductive layer are exposed by removing the substrate and the interlayer sacrificial layer; A selective conductor is formed around the cell plug by etching the selective conductive layer; An auxiliary conductive layer is formed in contact with the selected conductor; as well as Etch the auxiliary conductive layer, The step of etching the auxiliary conductive layer includes forming an outer auxiliary conductor that contacts the selected conductor and an inner auxiliary conductor that overlaps with the selected conductor.

41. The method according to claim 40, wherein, The unit plug includes an outer unit plug that protrudes beyond the sidewall of the selected conductor.

42. The method according to claim 41, wherein, The external auxiliary conductor surrounds the sidewall of the external unit plug and the sidewall of the selection conductor.

43. The method of claim 40, further comprising the step of: Before forming the selective conductive layer, a barrier insulating layer is formed in the region where the selective sacrificial layer has been removed; as well as Before forming the auxiliary conductive layer, a portion of the barrier insulating layer is etched.

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