Three-dimensional memory device and method of manufacturing the same

Abstract

A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes: a plurality of electrode stacks stacked in a vertical direction on a substrate, each of the plurality of electrode stacks including a plurality of interlayer dielectric layers alternately stacked with a plurality of electrode layers in the vertical direction; and a plurality of staircase structures defined in the plurality of electrode stacks, each of the plurality of staircase structures being configured by pad regions of the electrode layers in the electrode stack, the pad regions being arranged in a staircase shape, a width of the staircase structure of a lower electrode stack of the plurality of electrode stacks being greater than a width of the staircase structure of an upper electrode stack of the plurality of electrode stacks.

Description

Technical Field

[0001] The various embodiments generally relate to a semiconductor technology, and more particularly to a three-dimensional storage device and a method for manufacturing the same. Background Technology

[0002] The advantage of three-dimensional storage devices is that by increasing the number of stacked layers by stacking storage cells in the vertical direction, a larger capacity can be achieved in the same area, thus providing high performance and excellent power efficiency.

[0003] Three-dimensional storage devices include multiple electrode layers that are connected to storage cells and arranged at different heights. To independently apply electrical signals to the electrode layers arranged at different heights, contacts should be connected to each electrode layer; various technologies are being developed for this purpose. Summary of the Invention

[0004] Various embodiments relate to a three-dimensional storage device and a method of manufacturing the same, which reduces contact connection failures.

[0005] In one embodiment, a three-dimensional storage device may include: a plurality of electrode stacks stacked vertically on a substrate, each of the plurality of electrode stacks including a plurality of interlayer dielectric layers alternately stacked with the plurality of electrode layers along the vertical direction; and a plurality of stepped structures defined in the plurality of electrode stacks, each of the plurality of stepped structures being constructed from pad regions of electrode layers in the electrode stacks, the pad regions being arranged in a stepped shape, the width of the stepped structure of the lower electrode stacks being greater than the width of the stepped structure of the higher electrode stacks.

[0006] In one embodiment, a method for manufacturing a three-dimensional storage device may include: forming a multilayer stack by stacking a plurality of thin film stacks in a vertical direction on a substrate, each of the thin film stacks including a plurality of first material layers, the plurality of first material layers being alternately stacked with a plurality of second material layers; and forming a plurality of stepped structures in the plurality of thin film stacks such that the width of the stepped structure of an upper thin film stack is smaller than the width of the stepped structure of a lower thin film stack. Attached Figure Description

[0007] Figure 1 This is a schematic top view of a three-dimensional storage device according to an embodiment of the present disclosure.

[0008] Figure 2 It is shown Figure 1 A perspective view of an embodiment of the stepped structure.

[0009] Figure 3This is a flowchart illustrating a method for manufacturing a three-dimensional storage device according to another embodiment of the present disclosure.

[0010] Figure 4 This is a flowchart illustrating a method for forming a stepped structure of a three-dimensional storage device according to another embodiment of the present disclosure.

[0011] Figures 5A to 5E This is a perspective view showing a three-dimensional storage device according to an embodiment of the present disclosure, arranged according to the process steps.

[0012] Figure 6 This is a schematic top view of a three-dimensional storage device according to another embodiment of the present disclosure.

[0013] Figure 7 It is along Figure 6 A cross-sectional view cut by line I-I'.

[0014] Figure 8 It is shown Figure 6 A perspective view of an embodiment of the stepped structure.

[0015] Figure 9 This is a flowchart illustrating a method for forming a stepped structure of a three-dimensional storage device according to yet another embodiment of the present disclosure.

[0016] Figures 10A to 10E This is a perspective view showing a three-dimensional storage device according to another embodiment of the present disclosure, arranged according to the process steps.

[0017] Figure 11 This is a perspective view showing the stepped structure of a three-dimensional storage device according to another embodiment of the present disclosure.

[0018] Figures 12A to 12C This is a perspective view showing a three-dimensional storage device according to another embodiment of the present disclosure, arranged according to the process steps.

[0019] Figure 13 This is a block diagram schematically illustrating a memory system including a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 14 This is a block diagram schematically illustrating a computing system including a three-dimensional storage device according to an embodiment of the present disclosure. Detailed Implementation

[0021] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of this disclosure convey the scope of this disclosure to those skilled in the art.

[0022] Because the figures, dimensions, ratios, angles, and quantities of elements given in the accompanying drawings to describe embodiments of this disclosure are merely illustrative, this disclosure is not limited to the matters described. Throughout the specification, similar reference numerals refer to similar components. In describing this disclosure, detailed descriptions of the prior art will be omitted where it is determined that such detailed descriptions might obscure the gist or clarity of this disclosure. It should be understood that the terms “comprising,” “having,” “including,” etc., used in the description and claims should not be construed as limited to what follows, unless otherwise specified. When an indefinite or definite article (e.g., “a” or “this”) is used when referring to a singular noun, the article may include the plural of the noun, unless otherwise specified.

[0023] In interpreting the elements in the embodiments of this disclosure, these elements should be interpreted as including tolerance ranges, even if not explicitly stated otherwise.

[0024] Furthermore, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are merely for distinguishing one component from another and do not limit the substance, order, sequence, or number of components. Additionally, the components in embodiments of this disclosure are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, as used herein, in the spirit of this disclosure, a first component may be a second component.

[0025] If a component is described as being "connected," "linked," or "attached" to another component, it may mean that the component is not only directly "connected," "linked," or "attached," but also indirectly "connected," "linked," or "attached" via a third component. When describing positional relationships such as "component A on component B," "component A above component B," "component A below component B," and "component A next to component B," one or more other components may be arranged between components A and B, unless the terms "directly" or "adjacent" are explicitly used.

[0026] Features of the various exemplary embodiments of this disclosure can be joined, combined, or separated, in whole or in part. Various technical interactions and operations are possible. Various exemplary embodiments can be practiced individually or in combination.

[0027] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] In the accompanying drawings, the direction projected vertically from the top surface of the substrate is defined as the vertical direction VD, and two directions parallel to and intersecting each other with the top surface of the substrate are defined as the first direction FD and the second direction SD, respectively. For example, the first direction FD may correspond to the extension direction of a word line, and the second direction SD may correspond to the extension direction of a bit line. The first direction FD and the second direction SD may intersect each other substantially perpendicularly. In the drawings, the direction indicated by the arrow and the direction opposite to it represent the same direction.

[0029] Figure 1 This is a schematic top view of a three-dimensional storage device according to an embodiment of the present disclosure, and Figure 2 It is shown Figure 1 A perspective view of an embodiment of the stepped structure. For the sake of simplicity, in Figure 1 In the middle, the following was omitted. Figure 2 The diagram shows the contacts CNT1 and CNT2.

[0030] Reference Figure 1 and Figure 2 A three-dimensional storage device according to an embodiment of the present disclosure includes a plurality of electrode stacks 10-1 to 10-4 stacked on a substrate 1. Each of the plurality of electrode stacks 10-1 to 10-4 includes a plurality of alternately stacked electrode layers 10a to 10c and a plurality of interlayer dielectric layers 40. A plurality of stepped structures STa to STd are defined in the plurality of electrode layers 10-1 to 10-4 and are constructed by pad regions of the plurality of electrode layers 10a to 10c, these pad regions being arranged in a stepped shape in each electrode layer 10-1 to 10-4. The plurality of stepped structures STa to STd are configured such that the widths of the stepped structures STc and STd of the lower electrode stacks 10-1 and 10-2 in the second direction SD are greater than the widths of the stepped structures STa and STb of the upper electrode stacks 10-3 and 10-4 in the second direction SD.

[0031] More specifically, the substrate 1 may include: a plurality of connection regions CNR1 to CNR4 arranged along a first direction FD; and a first unit array region CAR1 and a second unit array region CAR2 arranged on both sides of the plurality of connection regions CNR1 to CNR4 along the first direction FD. Although this embodiment shows the connection regions CNR1 to CNR4 centrally arranged between the first unit array region CAR1 and the second unit array region CAR2, this disclosure is not limited thereto. For example, the connection regions CNR1 to CNR4 may be arranged at the edges of the unit array regions. For ease of explanation, the connection regions CNR1 to CNR4 are defined as the first connection region CNR1 to the fourth connection region CNR4.

[0032] Substrate 1 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and their compounds. Substrate 1 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG).

[0033] An electrode structure ES can be formed on the substrate 1. The electrode structure ES can extend along the first direction FD from the first unit array region CAR1 through the first connection region CNR1 to the fourth connection region CNR4 and then to the second unit array region CAR2.

[0034] The electrode structure ES may include multiple electrode stacks 10-1 to 10-4 stacked on the substrate 1. This embodiment shows four electrode stacks 10-1 to 10-4, and for ease of explanation, electrode stacks 10-1 to 10-4 are defined as first electrode stack 10-1 to fourth electrode stack 10-4. Other embodiments may have different numbers of electrode stacks.

[0035] Each of the plurality of electrode stacks 10-1 to 10-4 may include a plurality of electrode layers 10a to 10c and a plurality of interlayer dielectric layers 40 alternately stacked in the vertical direction VD.

[0036] Multiple electrode layers 10a to 10c may include conductive materials. For example, electrode layers 10a to 10c may include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitrides or tantalum nitrides), and transition metals (e.g., titanium or tantalum). Interlayer dielectric layer 40 may include dielectric materials. For example, interlayer dielectric layer 40 may include silicon oxide.

[0037] In the electrode layers 10a to 10c of the plurality of electrode stacks 10⁻¹ to 10⁻⁴, at least one of the bottom electrode layers can form a source select line, and at least one of the top electrode layers can form a drain select line. The electrode layers between the source select line and the drain select line can form word lines.

[0038] In the first cell array region CAR1 and the second cell array region CAR2, multiple vertical channels CH are formed to pass through multiple electrode layers 10a to 10c and interlayer dielectric layers 40 along the vertical direction VD, consisting of electrode layers 10⁻¹ to 10⁻⁴. Although not shown in detail, each vertical channel CH may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon, and may include p-type impurities such as boron (B) in certain regions therein. The gate dielectric layer may have a shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stack structure consisting of an oxide layer, a nitride layer, and an oxide layer stacked sequentially.

[0039] Source select transistors can be constructed within a region or area of ​​a vertical channel CH via source select lines. Memory cells can be constructed within a region or area of ​​a vertical channel CH via word lines. Drain select transistors can be constructed within a region or area of ​​a vertical channel CH via drain select lines. Source select transistors, multiple memory cells, and drain select transistors arranged along a vertical channel CH can form a cell string.

[0040] In the first connection region CNR1, each of the electrode layers 10a to 10c of the fourth electrode stack 10-4 may have a pad region Pa exposed by another electrode layer positioned thereon. A stepped structure STa may be formed in the first connection region CNR1 by the pad region Pa of the electrode layers 10a to 10c of the fourth electrode stack 10-4, the pad region being arranged in a stepped shape along the first direction FD.

[0041] In the second connection region CNR2, each of the electrode layers 10a to 10c of the third electrode stack 10-3 may have a pad region Pb exposed by another electrode layer positioned thereon. The pad regions Pb of the electrode layers 10a to 10c of the third electrode stack 10-3 are arranged in a stepped shape along the first direction FD, such that a stepped structure STb can be formed in the second connection region CNR2.

[0042] In the third connection region CNR3, each of the electrode layers 10a to 10c of the second electrode stack 10-2 may have a pad region Pc exposed by another electrode layer positioned thereon. A stepped structure STc may be formed in the third connection region CNR3 by the pad region Pc of the electrode layers 10a to 10c of the second electrode stack 10-2, which is arranged in a stepped shape along the first direction FD.

[0043] In the fourth interconnect region CNR4, each of the electrode layers 10a to 10c of the first electrode stack 10-1 may have a pad region Pd exposed by another electrode layer positioned thereon. The pad regions Pd of the electrode layers 10a to 10c of the first electrode stack 10-1 are arranged in a stepped shape along the first direction FD to form a stepped structure STd in the fourth interconnect region CNR4.

[0044] exist Figure 2 In this configuration, the first electrode stack 10-1 and the second electrode stack 10-2 are positioned relatively lower than the third electrode stack 10-3 and the fourth electrode stack 10-4 in the vertical direction VD. Stepped structures STa and STb are respectively defined within the fourth electrode stack 10-4 and the third electrode stack 10-3. Stepped structures STc and STd are respectively defined within the second electrode stack 10-2 and the first electrode stack 10-1. The widths of stepped structures STc and STd in the second direction SD can be larger than the widths of stepped structures STa and STb in the second direction SD. For example, stepped structures STa and STb can have a first width W1, while stepped structures STc and STd can have a second width W2 that is larger than the first width W1. The widths of the pad region Pa for constructing the stepped structure STa and the pad region Pb for constructing the stepped structure STb can be a first width W1, and the widths of the pad region Pc for constructing the stepped structure STc and the pad region Pd for constructing the stepped structure STd can be a second width W2.

[0045] Step structures STa and STb with a first width W1 can be defined as belonging to the first group, and step structures STc and STd with a second width W2 can be defined as belonging to the second group. Step structures belonging to a single group can have the same width. Furthermore, step structures STa to STd can be grouped into multiple numbered groups. The width of the step structure can increase as the group number increases. For example, the step structures in the second group can have a larger width than the step structures in the first group.

[0046] although Figure 1 and Figure 2 The stepped structures STa to STd are shown with increasing widths in numbered groups, but this disclosure is not limited thereto. The stepped structures STa to STd can be configured to have different widths within a group.

[0047] A hard mask pattern HM can be formed on the electrode structure ES. The hard mask pattern HM serves as an etching mask in the etching process used to form the stepped structures STa to STd, and can be formed from a dielectric material having an etching selectivity different from that of the interlayer dielectric layer 40 and the first material layer 30, which will be discussed later. Figures 5A to 5EThe description is as follows. For example, when the first material layer 30 is formed of silicon nitride and the interlayer dielectric layer 40 is formed of silicon oxide, the hard mask pattern HM can be formed of a dielectric material having an etch selectivity different from that of silicon oxide and silicon nitride.

[0048] A dielectric layer (not shown) covering the stepped structures STa to STd can be formed on the electrode structure ES, and multiple contacts CNT1 and CNT2 can be connected to the pad regions Pa to Pd of the stepped structures STa to STd respectively through the dielectric layer. Reference numeral CNT1 indicates a contact connected to the pad regions Pa and Pb of the upper stepped structures STa and STb, and reference numeral CNT2 indicates a contact connected to the pad regions Pc and Pd of the lower stepped structures STc and STd.

[0049] When measured vertically from the top surface of the electrode structure ES, the depth of contact CNT2, which connects to the pad regions Pc and Pd of the lower stepped structures STc and STd, is greater than the depth of contact CNT1, which connects to the pad regions Pa and Pb of the upper stepped structures STa and STb. Contacts CNT1 and CNT2 can be formed by creating multiple holes in the dielectric layer that expose the pad regions Pa to Pd, and filling these holes with a conductive material. As the hole depth increases, the likelihood of contact connection failure due to insufficient overlap during hole formation also increases.

[0050] According to embodiments of this disclosure, the widths of the pad regions Pc and Pd of the lower stepped structures STc and STd, which are connected to the contact CNT2 with a greater depth, can be configured to be greater than the widths of the pad regions Pa and Pb of the upper stepped structures STa and STb, which are connected to the contact CNT1 with a smaller depth. Therefore, the stacking margin can be increased, and the occurrence of contact connection failures can be prevented or minimized.

[0051] Figure 3 This is a flowchart illustrating a method for manufacturing a three-dimensional storage device according to another embodiment of the present disclosure. Figure 4 This is a flowchart illustrating a method for forming a stepped structure of a three-dimensional storage device according to another embodiment of the present disclosure. Figures 5A to 5E This is a perspective view showing a three-dimensional storage device according to an embodiment of the present disclosure, arranged according to the process steps.

[0052] Reference Figure 3 as well as Figures 5A to 5EA method for manufacturing a three-dimensional storage device according to an embodiment of the present disclosure may include step S301 of forming a multilayer stack 110 by stacking a plurality of thin film stacks 110-1 to 110-4. Each of the plurality of thin film stacks 110-1 to 110-4 may include a plurality of first material layers 30 and a plurality of second material layers 40 alternately stacked on a substrate 1. The method may include step S302, in which stepped structures STa to STd are formed in the plurality of thin film stacks 110-1 to 110-4, such that the widths of the stepped structures STc and STd of the lower thin film stacks 110-1 and 110-2 in the second direction SD are greater than the widths of the stepped structures STa and STb of the upper thin film stacks 110-3 and 110-4 in the second direction SD.

[0053] Reference Figure 4 as well as Figures 5A to 5E The method for forming the stepped structure STa to STd may include step S401 of forming a hard mask pattern HM having multiple openings OP1 and OP2 on the uppermost thin film stack 110-4. Figure 5A As shown, each of the plurality of openings is arranged in a corresponding one of the plurality of connecting areas CNR1 to CNR4. If the plurality of connecting areas CNR1 to CNR4 are grouped into groups, then the plurality of openings OP1 and OP2 have different widths in each group. Figure 5C As shown, the method may further include step S402 of forming a stepped structure STa in the region of the uppermost thin film stack 110-4 exposed by a plurality of openings OP1 and OP2. The method may further include step S403 of forming a mask exposing at least one of the plurality of interconnecting regions CNR1 to CNR4; and step S404 of etching the multilayer stack 110 using a hard mask pattern HM and the mask as an etching mask to form a stepped structure in at least one of the plurality of thin film stacks 110-1 to 110-3. For example, as Figure 5D As shown, thin film stack 110-3 is etched, and other thin film stacks may be etched by repeating steps S403 and S404.

[0054] For details, refer to Figure 5A A multilayer laminate 110 can be formed by laminating thin film laminates 110-1 to 110-4 on substrate 1.

[0055] Each of the plurality of thin film stacks 110-1 to 110-4 may include a plurality of alternating first material layers 30 and a plurality of second material layers 40. Hereinafter, for ease of explanation, thin film stacks 110-1 to 110-4 are respectively defined as first thin film stack 110-1 to fourth thin film stack 110-4.

[0056] In one embodiment, the plurality of first material layers 30 may include sacrificial layers, and the plurality of second material layers 40 may include interlayer dielectric layers. The plurality of first material layers 30 may be formed of a dielectric material having an etch selectivity different from that of the plurality of second material layers 40. For example, the plurality of second material layers 40 may be formed of silicon oxide, while the plurality of first material layers 30 may be formed of silicon nitride. In another embodiment, the plurality of first material layers 30 may include a conductive material, while the plurality of second material layers 40 may include a dielectric material.

[0057] A hard mask pattern HM having a first opening OP1 and a second opening OP2 can be formed on a multilayer laminate 110. (See later...) Figures 5B to 5E As described, the hard mask pattern HM is used as an etching mask during the etching of the multilayer stack 110, and can be formed of a material having different etching selectivity than the plurality of first material layers 30 and the plurality of second material layers 40.

[0058] The first opening OP1 can be located in the first connection region CNR1, and the first opening OP1 can also be located in the second connection region CNR2. The width of the first opening OP1 in the second direction SD can have a dimension W1. The second opening OP2 can be located in the third connection region CNR3, and the second opening OP2 can also be located in the fourth connection region CNR4. The width of the second opening OP2 in the second direction SD can have a dimension W2, where W2 is greater than W1.

[0059] Refer again Figure 5B A first mask MP1 with an opening A1 can be formed on the hard mask pattern HM and the multilayer stack 110. This opening A1 is disposed in the first connection regions CNR1 to the fourth connection regions CNR4. The width of the opening A1 in the first direction FD can be L1. L1 can be substantially the same as described above. Figure 1 and Figure 2 Each pad region described (e.g., one of Pa to Pd) has the same width in the first direction FD.

[0060] A first etching process can be performed using a first mask MP1 and a hard mask pattern HM as etching masks to etch the fourth thin film stack 110-4 at a first etching depth. For example, the first etching depth can be substantially the same as the vertical spacing of the layers in the plurality of first material layers 30 and the plurality of second material layers 40. The vertical spacing can be defined as the sum of the thickness of one of the plurality of first material layers 30 and the thickness of one of the plurality of second material layers 40.

[0061] After the first etching process, a trimming process for the first mask MP1 can be performed. Therefore, the width of the first mask MP1 in the first direction FD can be reduced, and thus the width of the opening A1 in the first direction FD can be increased. In other words, the position of the sidewalls of the first mask MP1 in the first direction FD can be adjusted. The adjusted distance of the sidewalls of the first mask MP1 can be referenced above. Figure 1 and Figure 2 Each pad region described (e.g., one of Pa to Pd) has a substantially the same width in the first direction FD.

[0062] The first etching process and the finishing process described above can be performed alternately and repeatedly. Therefore, as... Figure 5C As shown, a stepped structure STa can be formed in the region of the fourth thin film laminate 110-4 exposed by openings OP1 and OP2.

[0063] The first mask MP1 can be formed from photoresist. The remaining first mask MP1 after the formation of the stepped structure STa can be removed by a stripping process.

[0064] Reference Figure 5D A second mask MP2 can be formed in at least one of the first connection regions CNR1 to the fourth connection regions CNR4 to expose the multilayer stack 110. For example, the second mask MP2 can expose the multilayer stack 110 in the second connection region CNR2 and the fourth connection region CNR4, and can cover the multilayer stack 110 in the first connection region CNR1 and the third connection region CNR3.

[0065] A second etching process can be performed to etch the multilayer stack 110 to a second etching depth using a second mask MP2 and a hard mask pattern HM as etching masks. The second etching depth can correspond to the thickness of a thin film stack (e.g., one of 110-1 to 110-4). For example, when a thin film stack (e.g., one of 110-1 to 110-4) is constructed of three first material layers 30 and three second material layers 40, the three first material layers 30 and the three second material layers 40 can be etched by the second etching process.

[0066] Therefore, a stepped structure STb can be formed in the second connection region CNR2 and the fourth connection region CNR4 of the third thin film laminate 110-3. The stepped structure STb of the second connection region CNR2 can be formed by removing the stepped structure STa of the second connection region CNR2 (see...) in a second etching process. Figure 5C The outline of the second connecting region CNR2 is obtained by transferring it downward along the vertical direction VD, and the stepped structure STb of the second connecting region CNR2 can be formed with the stepped structure STa of the second connecting region CNR2 (see...). Figure 5CThe same cross-sectional profile. Similarly, the stepped structure STb of the fourth connection region CNR4 can be achieved by etching the stepped structure STa of the fourth connection region CNR4 (see...) in the second etching process. Figure 5C The outline of the fourth connecting region CNR4 is obtained by transferring it downward along the vertical direction VD, and the stepped structure STb of the fourth connecting region CNR4 can be formed with the stepped structure STa of the fourth connecting region CNR4 (see...). Figure 5C They have the same cross-sectional profile.

[0067] The second mask MP2 can be formed of photoresist. The remaining second mask MP2 after the second etching process can be removed by a stripping process.

[0068] Reference Figure 5E A third mask MP3 can be formed that exposes at least one of the first connection regions CNR1 to the fourth connection regions CNR4. For example, the third mask MP3 can expose the multilayer stack 110 in the third connection region CNR3 and the fourth connection region CNR4, and can block the multilayer stack 110 in the first connection region CNR1 and the second connection region CNR2.

[0069] A third etching process can be performed to etch the multilayer stack 110 to a third etching depth using a third mask MP3 and a hard mask pattern HM as etching masks. The third etching depth can correspond to twice the height of any one of the thin film stacks 110-1 to 110-4. For example, when the thin film stack is constructed of three first material layers 30 and three second material layers 40, six first material layers 30 and six second material layers 40 can be etched in the third etching process.

[0070] Therefore, a stepped structure STc can be formed in the second thin film stack 110-2 in the third connection region CNR3, and a stepped structure STd can be formed in the first thin film stack 110-1 in the fourth connection region CNR4. The stepped structure STc of the third connection region CNR3 can be formed by etching the stepped structure STa of the third connection region CNR3 (see...) in a third etching process. Figure 5C The outline of the third connecting region CNR3 is obtained by transferring it downward along the vertical direction VD. The stepped structure STc of the third connecting region CNR3 can form a stepped structure STa that is consistent with the stepped structure STa of the third connecting region CNR3 (see...). Figure 5C The same cross-sectional profile. Similarly, the stepped structure STd of the fourth connection region CNR4 can be achieved by etching the stepped structure STb of the fourth connection region CNR4 (see...) in the third etching process. Figure 5D The outline of the fourth connecting region CNR4 is obtained by transferring it downward along the vertical direction VD. The stepped structure STd of the fourth connecting region CNR4 can form a stepped structure STb that is consistent with the stepped structure STb of the fourth connecting region CNR4 (see...). Figure 5DThey have the same cross-sectional profile.

[0071] The third mask MP3 can be formed from photoresist. The remaining third mask MP3 after the third etching process can be removed by a stripping process.

[0072] In an embodiment where the first material layer 30 is made of a sacrificial layer, an electrode layer can be formed after the third etching process by replacing the sacrificial layers in the plurality of first material layers 30 with a conductive material. In another embodiment where the first material layer 30 is made of a conductive material, the step of replacing the first material layer 30 with a conductive material can be omitted.

[0073] Below, we will refer to Figures 6 to 12C Various embodiments of this disclosure are described below. In the following description, repeated descriptions of structures substantially the same as those described above will be omitted, and only the differences will be described.

[0074] Figure 6 This is a schematic top view of a three-dimensional storage device according to another embodiment of the present disclosure. Figure 7 It is along Figure 6 A cross-sectional view cut by line I-I', and Figure 8 It is shown Figure 6 A perspective view of an embodiment of the stepped structure.

[0075] Reference Figures 6 to 8 The substrate 1 may include: a first connection region CNR1 and a second connection region CNR2 arranged along a first direction FD; and a first unit array region CAR1 and a second unit array region CAR2 arranged adjacent to the first connection region CNR1 and the second connection region CNR2 respectively along the first direction FD. Although Figures 6 to 8 The illustration shows a first connecting region CNR1 and a second connecting region CNR2 centrally located between a first cell array region CAR1 and a second cell array region CAR2, but this disclosure is not limited thereto. For example, the first connecting region CNR1 and the second connecting region CNR2 may be located at the edges of the cell array regions.

[0076] An electrode structure ES can be formed on the substrate 1. The electrode structure ES can extend along the first direction FD from the first unit array region CAR1 through the first connection region CNR1 to the second connection region CNR2, and then to the second unit array region CAR2.

[0077] The electrode structure ES may include a plurality of electrode stacks 10-1 to 10-5 stacked on the substrate 1 along the vertical direction VD. Each of the plurality of electrode stacks 10-1 to 10-5 may include a plurality of electrode layers 10a to 10c, which are stacked alternately with a plurality of interlayer dielectric layers 40. Figures 6 to 8Five electrode stacks 10-1 to 10-5 are shown, and for ease of explanation, electrode stacks 10-1 to 10-5 are defined as the first electrode stack 10-1 to the fifth electrode stack 10-5. Other embodiments may have different numbers of electrode stacks.

[0078] In the first connection region CNR1, each of the electrode layers 10a to 10c of the fifth electrode stack 10-5 may have a pad region Pa' exposed by another electrode layer positioned thereon. In the first connection region CNR1, a stepped structure STa' may be formed from the pad regions Pa' of the electrode layers 10a to 10c of the fifth electrode stack 10-5, the pad regions being arranged in a stepped shape in the first direction FD.

[0079] In the first connection region CNR1, each of the electrode layers 10a to 10c of the fourth electrode stack 10-4 may have a pad region Pb' exposed by another electrode layer positioned thereon. In the first connection region CNR1, a stepped structure STb' may be formed from the pad regions Pb' of the electrode layers 10a to 10c of the fourth electrode stack 10-4, the pad regions being arranged in a stepped shape in the first direction FD.

[0080] In the first connection region CNR1, each of the electrode layers 10a to 10c of the second electrode stack 10-2 may have a pad region Pd' exposed by another electrode layer positioned thereon. In the first connection region CNR1, a stepped structure STd' may be formed from the pad regions Pd' of the electrode layers 10a to 10c of the second electrode stack 10-2, the pad regions being arranged in a stepped shape in the first direction FD.

[0081] In the second connection region CNR2, each of the electrode layers 10a to 10c of the fifth electrode stack 10-5 may have a pad region Pa” exposed by another electrode layer positioned thereon. In the second connection region CNR2, a stepped structure STa'' may be formed from the pad regions Pa” of the electrode layers 10a to 10c of the fifth electrode stack 10-5, the pad regions being arranged in a stepped shape in the first direction FD.

[0082] In the second connection region CNR2, each of the electrode layers 10a to 10c of the third electrode stack 10-3 may have a pad region Pc' exposed by another electrode layer positioned thereon. A stepped structure STc' may be formed in the second connection region CNR2 from the pad regions Pc' of the electrode layers 10a to 10c of the third electrode stack 10-3, the pad regions being arranged in a stepped shape in the first direction FD.

[0083] In the second connection region CNR2, each of the electrode layers 10a to 10c of the first electrode stack 10-1 may have a pad region Pe' exposed by another electrode layer positioned thereon. In the second connection region CNR2, a stepped structure STe' may be formed from the pad regions Pe' of the electrode layers 10a to 10c of the first electrode stack 10-1, the pad regions being arranged in a stepped shape in the first direction FD.

[0084] For ease of explanation, the stepped structures STa', STb' and STd' arranged in the first connection area CNR1 are defined as the first stepped structures, and the stepped structures STa", STc' and STe' arranged in the second connection area CNR2 are defined as the second stepped structures.

[0085] The first stepped structures STa', STb', and STd' can be arranged along the second direction SD in the first connection region CNR1, and the second stepped structures STa", STc', and STe' can be arranged along the second direction SD in the second connection region CNR2. By arranging multiple stepped structures in the second direction SD (perpendicular to the first direction FD, which is the extension direction of the electrode structure ES) in this way, the number of connection regions required to arrange multiple stepped structures can be reduced, and the area consumed by the stepped structures can also be reduced.

[0086] The first step structures STa', STb', and STd' can be configured such that a first step structure positioned at a relatively low vertical height in the multilayer stack 110 has a larger width in the second direction SD than a first step structure positioned at a relatively high vertical height. For example, in Figure 8 In the first step structure STa', the first step structure STd' can be the highest and has the smallest first width W11, while the first step structure STd' can be the lowest and has the largest third width W13. The first step structure STb' positioned between the highest first step structure STa' and the lowest first step structure STd' can have a second width W12 in the second direction SD, which is greater than the first width W11 and less than the third width W13.

[0087] Similarly, the second step structures STa", STc' and STe' can be configured such that the second step structure positioned at a relatively low vertical position has a larger width in the second direction SD than the second step structure positioned at a higher height. The second step structure STa" at the highest position can have a first width W11, while the second step structure STc' located between the two can have a second width W12, which is greater than the first width W11, and the second step structure STe' at the lowest vertical position in the multilayer stack 110 can have a third width W13 in the second direction SD, which is greater than the second width W12.

[0088] The number of first step structures located in the first connection region CNR1 and the number of second step structures located in the second connection region CNR2 can be the same. Figures 6 to 8 Three first-step structures and three second-step structures are shown, but the number may vary in different implementations.

[0089] The second-step structures STa", STc', and STe' can correspond to the first-step structures STa', STb', and STd', respectively. In a top view (e.g., in...) Figure 6 In the first direction FD, corresponding first and second step structures can be arranged in a row and have the same width in the second direction SD. Specifically, the second step structure STa" can correspond to the first step structure STa', and when viewed from the top, the first step structure STa' and the second step structure STa" can be arranged in a row in the first direction FD, and each can have a first width W11 in the second direction SD. Similarly, the second step structure STc' can correspond to the first step structure STb', and when viewed from the top, the first step structure STb' and the second step structure STc' can be arranged in a row in the first direction FD, and each can have a second width W12 in the second direction SD. Furthermore, the second step structure STe' can correspond to the first step structure STd', and when viewed from the top, the first step structure STd' and the second step structure STe' can be arranged in a row in the first direction FD, and each can have a third width W13 in the second direction SD.

[0090] If all the stepped structures STa' to STe' and STa" are formed with a large or identical width to ensure contact overlap margin, then the overall width of the electrode structure ES in the second direction SD must also be increased. However, in the embodiments of this disclosure, by constructing the width of the lower stepped structure (for which ensuring overlap margin is relatively difficult) to be greater than the width of the upper stepped structure (for which ensuring overlap margin is relatively easy), it is possible to ensure contact overlap margin of multiple stepped structures without increasing the overall width of the electrode structure ES.

[0091] Figure 9 This is a flowchart illustrating a method for forming a stepped structure of a three-dimensional storage device according to yet another embodiment of the present disclosure. Figures 10A to 10E This is a perspective view showing a three-dimensional storage device according to another embodiment of the present disclosure, arranged according to the process steps.

[0092] Reference Figure 9 as well as Figures 10A to 10E According to another embodiment of the present disclosure, a method for forming a stepped structure of a three-dimensional storage device may include step S901 of forming stepped structures STa' and STa" in the uppermost thin film stack 110-5 by repeating a first patterning process of the uppermost thin film stack 110-5. The method may further include step S902, in which stepped structures STb' to STe' are formed in other thin film stacks 110-1 to 110-4 located below the uppermost thin film stack 110-5 by transferring the stepped structures STa' and STa" of the uppermost thin film stack 110-5 downward to the other thin film stacks 110-1 to 110-4, such that the width of the stepped structure of the lower thin film stack in the second direction SD may be greater than the width of the stepped structure of the upper thin film stack.

[0093] For details, refer to Figure 10A A multilayer stack 110 can be formed by stacking multiple thin film stacks 110-1 to 110-5 on a substrate 1. Each of the multiple thin film stacks 110-1 to 110-5 may include multiple alternating layers of first material 30 and multiple layers of second material 40. Hereinafter, for ease of explanation, thin film stacks 110-1 to 110-5 are respectively defined as the first to the fifth thin film stacks.

[0094] A first mask MP11 can be formed on the multilayer stack 110. The first mask MP11 can have openings A11 in the first connection region CNR1 and the second connection region CNR2, respectively. The width of each opening A11 in the first direction FD can be L1. L1 can be related to the above. Figures 6 to 8Each pad region described (e.g., Pa' to Pe' and one of Pa") has the same width in the first direction FD.

[0095] A first etching process can be performed using a first mask MP11 as an etching mask to etch a portion of the fifth thin film stack 110-5 at a first etching depth. For example, the first etching depth can be substantially the same as the vertical spacing between the layers in the plurality of first material layers 30 and the plurality of second material layers 40. The vertical spacing can be defined as the sum of the thickness of one of the plurality of first material layers 30 and the thickness of one of the plurality of second material layers 40.

[0096] After the first etching process, a trimming process for the first mask MP11 can be performed. Therefore, the width of the first mask MP11 in the first direction FD can be reduced, and thus the width of the opening A11 in the first direction FD can be increased. In other words, the position of the sidewalls of the first mask MP11 in the first direction FD can be adjusted. The adjusted distance of the sidewalls of the first mask MP11 can be referenced above. Figures 6 to 8 Each pad region described (e.g., Pa' to Pe' and one of Pa") has a substantially the same width in the first direction FD.

[0097] The first etching process and the finishing process described above can be performed alternately and repeatedly. Therefore, as... Figure 10B As shown, stepped structures STa' and STa" can be formed in the first connecting region CNR1 and the second connecting region CNR2 of the fifth thin film laminate 110-5, respectively.

[0098] The first mask MP11 can be formed from photoresist. The remaining first mask MP11 after the formation of the stepped structures STa' and STa" can be removed by a stripping process.

[0099] Reference Figure 10C A second mask MP12 can be formed in the first connection region CNR1 and the second connection region CNR2, having an opening A12 that exposes a portion of the multilayer laminate 110. The width of each opening A12 in the second direction SD can be D1, which can be related to the above description. Figures 6 to 8 The third width W13 described is basically the same.

[0100] A second etching process can be performed to etch the multilayer stack 110 to a second etching depth using a second mask MP12 as an etching mask. The second etching depth can correspond to twice the thickness of a thin film stack (e.g., one of 110-1 to 110-4). For example, when a thin film stack (e.g., one of 110-1 to 110-4) is constructed of three first material layers 30 and three second material layers 40, six first material layers 30 and six second material layers 40 can be etched by the second etching process.

[0101] Therefore, a stepped structure STc' can be formed in the first connecting region CNR1 and the second connecting region CNR2 of the third thin film laminate 110-3, respectively.

[0102] The second mask MP12 can be formed of photoresist. The second mask MP12 remaining after the second etching process can be removed by a stripping process.

[0103] Reference Figure 10D A third mask MP13 can be formed having an opening A13 that exposes a portion of the second connection region CNR2 of the multilayer stack 110. The width of the opening A13 in the second direction SD can be D2, which is greater than the width D1.

[0104] The difference between width D2 and width D1 can be referred to above. Figures 6 to 8 The second width W12 described is essentially the same. Furthermore, the difference between the width D3 and width D2 of the multilayer laminate 110 can be compared with the aforementioned reference. Figures 6 to 8 The first width W11 described is basically the same. The third width W13 is greater than the second width W12, and the second width W12 is greater than the one mentioned above. Figures 6 to 8 The first width W11 is described. Therefore, the width D1 is greater than the difference between width D2 and width D1, and the difference between width D2 and width D1 is greater than the difference between width D3 and width D2.

[0105] A third etching process can be performed, using a third mask MP13 as an etching mask to etch the multilayer stack 110 to a third etching depth. The third etching depth can correspond to the height of any one of the thin film stacks 110-1 to 110-5. For example, when the thin film stack is constructed of three first material layers 30 and three second material layers 40, the three first material layers 30 and three second material layers 40 can be etched by the third etching process.

[0106] Therefore, a stepped structure STb' can be formed in the second connection region CNR2 of the fourth thin film laminate 110-4, and a stepped structure STd' can be formed in the second connection region CNR2 of the second thin film laminate 110-2.

[0107] The third mask MP13 can be formed from photoresist. The third mask MP13 remaining after the third etching process can be removed by a stripping process.

[0108] Reference Figure 10E A fourth mask MP14 can be formed having openings A14 that expose portions of the first connection region CNR1 and the second connection region CNR2 of the multilayer stack 110, respectively. The width of each opening A14 in the second direction SD can be a size of width D2.

[0109] A fourth etching process can be performed, in which the multilayer stack 110 is etched to a fourth etching depth using the fourth mask MP14 as the etching mask. The fourth etching depth can be the same as the third etching depth.

[0110] Therefore, a stepped structure STb' can be formed in the first connecting region CNR1 of the fourth thin film laminate 110-4, and a stepped structure STd' can be formed in the first connecting region CNR1 of the second thin film laminate 110-2. Furthermore, a stepped structure STc' can be formed in the second connecting region CNR2 of the third thin film laminate 110-3, and a stepped structure STe' can be formed in the second connecting region CNR2 of the first thin film laminate 110-1.

[0111] The fourth mask MP14 can be formed from photoresist. The remaining fourth mask MP14 after the fourth etching process can be removed by a stripping process.

[0112] Figure 11 This is a perspective view showing the stepped structure of a three-dimensional storage device according to another embodiment of the present disclosure.

[0113] Reference Figure 11 The three-dimensional storage device according to the embodiments of this disclosure is consistent with the above reference. Figure 8 The difference in the described three-dimensional storage device may be that Figure 8 The position of the stepped structure STd' of the second electrode stack 10-2 is in Figure 11 The connection is changed to the second link region CNR2. Similarly, Figure 8 The position of the stepped structure STc' of the third electrode stack 10-3 is in Figure 11 The connection is changed to the first linked region CNR1. Because... Figure 8 The stepped structures STc' and STd' in Figure 11 The center changes to different vertical positions, so in Figure 11 In the process, the width W13 of the stepped structure STc' of the third electrode stack 10-3 is greater than the width W12 of the stepped structure STd' of the second electrode stack 10-2.

[0114] In detail, Figure 11 In this configuration, stepped structures STa', STb', and STc' can be arranged in the first connecting region CNR1, and stepped structures STa", STd', and STe' can be arranged in the second connecting region CNR2. The stepped structures STa', STb', and STc' arranged in the first connecting region CNR1 can be defined as first stepped structures, and the stepped structures STa", STd', and STe' arranged in the second connecting region CNR2 can be defined as second stepped structures.

[0115] The first step structures STa', STb' and STc' can be arranged along the second direction SD in the first connection region CNR1, and the second step structures STa", STd' and STe' can be arranged along the second direction SD in the second connection region CNR2.

[0116] In the first stepped structures STa', STb', and STc', the first stepped structure positioned at a relatively lower vertical height in the electrode structure ES can have a larger width in the second direction SD than the first stepped structure positioned at a relatively higher vertical height. That is, the first stepped structure STa', which is positioned highest, can have the smallest first width W11. The first stepped structure STb', positioned in the middle position in the vertical direction VD, can have a second width W12 that is greater than the first width W11, while the first stepped structure STc' can be the lowest and can have the largest third width W13, which is greater than the second width W12.

[0117] Similarly, in the second-tier structures STa", STd', and STe', the second-tier structure positioned at a relatively lower vertical position can have a greater width than the second-tier structure positioned at a higher height. That is, the uppermost second-tier structure STa" can have a first width W11, while the second-tier structure STd' positioned between the two can have a second width W12, which is greater than the first width W11, and the second-tier structure STe' located at the lowest vertical position can have a third width W13, which is greater than the second width W12.

[0118] The second-step structures STa", STd' and STe' can correspond to the first-step structures STa', STb' and STc', respectively. In the top view, the corresponding first-step structures and second-step structures can be arranged in a row in the first direction FD and can have the same width in the second direction SD.

[0119] Specifically, the second stepped structure STa" can correspond to the first stepped structure STa', and when viewed from the top, the first stepped structure STa' and the second stepped structure STa" can be arranged in a row in the first direction FD, and each can have the same first width W11 in the second direction SD. Similarly, the second stepped structure STd' can correspond to the first stepped structure STb', and when viewed from the top, the first stepped structure STb' and the second stepped structure STd' can be arranged in a row in the first direction FD, and each can have the same second width W12 in the second direction SD. Furthermore, the second stepped structure STe' can correspond to the first stepped structure STc', and when viewed from the top, the first stepped structure STc' and the second stepped structure STe' can be arranged in a row in the first direction FD, and each can have the same third width W13 in the second direction SD.

[0120] Figures 12A to 12C This is a perspective view showing a three-dimensional storage device according to another embodiment of the present disclosure, arranged according to the process steps.

[0121] As mentioned above Figure 10A and Figure 10B The multilayer stack 110 can be formed by stacking multiple thin film stacks 110-1 to 110-5 on the substrate 1, and by alternately repeating the first etching process using the first mask MP11 as the etching mask and the trimming process for the first mask MP11, respectively, stepped structures STa' and STa" can be formed in the first connection region CNR1 and the second connection region CNR2 of the fifth thin film stack 110-5.

[0122] Reference Figure 12A A second mask MP22 can be formed in the first connection region CNR1 and the second connection region CNR2, having an opening A22 that exposes a portion of the multilayer laminate 110. The width of each opening A22 in the second direction SD can be D1, which can be related to the width described above. Figure 11 The third width W13 described is basically the same.

[0123] A second etching process can be performed to etch the multilayer stack 110 to a second etching depth using a second mask MP22 as an etching mask. The second etching depth can be the same as the thickness of a thin film stack (e.g., one of 110-1 to 110-4). For example, when a thin film stack (e.g., one of 110-1 to 110-4) is constructed of three first material layers 30 and three second material layers 40, the three first material layers 30 and the three second material layers 40 can be etched by the second etching process.

[0124] Therefore, stepped structures STb' can be formed in the first connection region CNR1 and the second connection region CNR2 of the fourth thin film stack 110-4, respectively. The second mask MP22 can be formed of photoresist. The second mask MP22 remaining after the second etching process can be removed by a stripping process.

[0125] Reference Figure 12B A third mask MP23 can be formed having an opening A23 that exposes a portion of the first connection region CNR1 and the second connection region CNR2 of the multilayer stack 110 respectively.

[0126] The width of each opening A23 in the second direction SD can be D2. The difference between width D2 and width D1 can be referred to above. Figure 11 The second width W12 described is essentially the same. Furthermore, the difference between the width D3 and width D2 of the multilayer laminate 110 can be found in the above reference. Figure 11 The first width W11 described is basically the same. The third width W13 is greater than the second width W12, and the second width W12 is greater than the one mentioned above. Figure 11 The first width W11 is described. Therefore, the width D1 is greater than the difference between width D2 and width D1, and the difference between width D2 and width D1 is greater than the difference between width D3 and width D2.

[0127] A third etching process can be performed, in which the multilayer stack 110 is etched to a third etching depth using the third mask MP23 as an etching mask. The third etching depth can be the same as the second etching depth.

[0128] Therefore, a stepped structure STb' can be formed in the first connecting region CNR1 and the second connecting region CNR2 of the fourth thin film laminate 110-4, and a stepped structure STc' can be formed in the first connecting region CNR1 and the second connecting region CNR2 of the third thin film laminate 110-3, respectively.

[0129] The third mask MP23 can be formed from photoresist. The remaining third mask MP23 after the third etching process can be removed by a stripping process.

[0130] Reference Figure 12C A fourth mask MP24 can be formed having an opening A24 that exposes a portion of the second connection region CNR2 of the multilayer stack 110. The width of the opening A14 in the second direction SD can be D2.

[0131] A fourth etching process can be performed to etch the multilayer stack 110 to a fourth etching depth using a fourth mask MP24 as an etching mask. The fourth etching depth can correspond to twice the thickness of a thin film stack (e.g., one of 110-1 to 110-5). When the thin film stack is constructed of three first material layers 30 and three second material layers 40, six first material layers 30 and six second material layers 40 can be etched by the fourth etching process.

[0132] Therefore, a stepped structure STd' can be formed in the second connection region CNR2 of the second thin film laminate 110-2, and a stepped structure STe' can be formed in the second connection region CNR2 of the first thin film laminate 110-1.

[0133] The fourth mask MP24 can be formed from photoresist. The remaining fourth mask MP24 after the fourth etching process can be removed by a stripping process.

[0134] Figure 13 This is a block diagram schematically illustrating a memory system including a semiconductor device according to an embodiment of the present disclosure.

[0135] Reference Figure 13 The storage system 600 according to the embodiment may include a non-volatile storage device (NVMDevice) 610 and a storage controller 620.

[0136] The non-volatile storage device (NVM device) 610 can be constructed from the three-dimensional storage device described above and can operate in the manner described. The storage controller 620 can be configured to control the non-volatile storage device (NVM device) 610. The combination of the non-volatile storage device (NVM device) 610 and the storage controller 620 can provide a memory card or solid-state drive (SSD). SRAM 621 serves as the working memory for the processing unit (CPU) 622. The host interface (Host I / F) 623 includes the host data exchange protocol and is connected to the storage system 600.

[0137] Error correction code block (ECC) 624 detects and corrects errors included in data read from non-volatile storage device (NVM device) 610.

[0138] The memory interface (Memory I / F) 625 interfaces with the non-volatile memory device (NVM Device) 610 of this embodiment. The processing unit 622 performs overall control operations for data exchange with the memory controller 620.

[0139] Although not shown in the figures, it will be apparent to those skilled in the art to which this embodiment pertains that the storage system 600 according to this embodiment may additionally include a ROM storing code data for interfacing with a host. The non-volatile memory device (NVM device) 610 may be provided as a multi-chip package comprising multiple flash memory chips.

[0140] The storage system 600 according to this embodiment can provide a highly reliable storage medium with a low probability of error occurrence. In particular, the non-volatile storage device of this embodiment can be included in a storage system (e.g., a solid-state drive (SSD) which is currently under active research). In this case, the storage controller 620 can be configured to communicate with an external source (e.g., a host) via one of various interface protocols, such as USB (Universal Serial Bus), MMC (Multimedia Card), PCI-E (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attached), PATA (Parallel Advanced Technology Attached), SCSI (Small Computer System Interface), ESDI (Enhanced Small Data Center Interface), and IDE (Integrated Electronic Drive).

[0141] Figure 14 This is a block diagram schematically illustrating a computing system including a three-dimensional storage device according to an embodiment of the present disclosure.

[0142] Reference Figure 14 The computing system 700 according to an embodiment may include a storage system 710 electrically connected to a system bus 760, a microprocessor (CPU) 720, RAM 730, a user interface 740, and a modem 750 such as a baseband chipset. In the case where the computing system 700 according to this embodiment is a mobile device, a battery (not shown) may be additionally provided to supply the operating voltage of the computing system 700. Although not shown in the figures, it will be apparent to those skilled in the art that the computing system 700 according to this embodiment may additionally provide an application chipset, a camera image processor (CIS), mobile DRAM, etc. The storage system 710 may be constructed, for example, an SSD (Solid State Drive / Disk), which uses non-volatile memory to store data. Alternatively, the storage system 710 may be provided as converged flash memory (e.g., OneNAND flash memory).

[0143] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered descriptive only and not intended to limit the scope of the technology. The scope of this disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted by the appended claims and include all equivalents falling within the scope of the appended claims.

[0144] Cross-reference of related applications

[0145] This application claims priority to Korean Patent Application 10-2020-0173011, filed on December 11, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional storage device, the three-dimensional storage device comprising: Multiple electrode stacks are stacked on a substrate in a vertical direction, and each of the multiple electrode stacks includes multiple interlayer dielectric layers that are alternately stacked with the multiple electrode layers in the vertical direction. Multiple stepped structures are defined in the multiple electrode stacks, each of the multiple stepped structures being constructed from a pad region of an electrode layer in the electrode stack, the pad region being arranged in a stepped shape. as well as Multiple contacts are respectively disposed on the pad areas of the multiple stepped structures. The substrate includes a first connection region and a second connection region arranged along a first direction, wherein the first direction is perpendicular to both the vertical direction and the second direction, and the second direction is the width direction of the plurality of stepped structures. The plurality of stepped structures include a plurality of first stepped structures arranged in the first connecting region and a plurality of second stepped structures arranged in the second connecting region. The plurality of first-step structures are arranged along the second direction, and the plurality of second-step structures are also arranged along the second direction. The plurality of first stepped structures are configured such that the first stepped structure positioned at a relatively lower vertical height has a greater width in the second direction than the first stepped structure positioned at a relatively higher vertical height, and The plurality of first step structures include a highest first step structure, a lowest first step structure, and an intermediate first step structure between the highest first step structure and the lowest first step structure. The width of the intermediate first step structure in the second direction is greater than the width of the highest first step structure in the second direction, and the width of the intermediate first step structure in the second direction is less than the width of the lowest first step structure in the second direction.

2. The three-dimensional storage device according to claim 1, wherein, The multiple stepped structures are grouped, and Each of the plurality of stepped structures in a group has the same width in the second direction.

3. The three-dimensional storage device according to claim 1, wherein, Each of the plurality of second-step structures corresponds to a corresponding one of the plurality of first-step structures, and The first stepped structure and the corresponding second stepped structure have the same width in the second direction and are arranged in a row in the first direction when viewed from above.

4. The three-dimensional storage device according to claim 1, wherein the three-dimensional storage device further comprises: Vertical channels passing through the plurality of electrode stacks; as well as Multiple storage cells formed along the vertical channel.

5. The three-dimensional storage device according to claim 2, wherein, The width of the multiple stepped structures increases or decreases in groups.

6. A method for manufacturing a three-dimensional storage device, the method comprising the following steps: A multilayer stack is formed by stacking multiple thin film stacks in a vertical direction on a substrate. Each thin film stack includes multiple first material layers, and the multiple first material layers are alternately stacked with multiple second material layers. Multiple stepped structures are formed in the plurality of thin film stacks, each of the plurality of stepped structures being constructed from a pad region of an electrode layer in an electrode stack, the pad region being arranged in a stepped shape; as well as Multiple contacts are formed, each located on the pad area of ​​the plurality of stepped structures. The substrate includes a first connection region and a second connection region arranged along a first direction, wherein the first direction is the extension direction of the plurality of thin film stacks. The plurality of stepped structures formed in the first connecting region are arranged along a second direction perpendicular to both the first direction and the vertical direction when viewed from above. The plurality of stepped structures in the second connection region are arranged along the second direction when viewed from above. The plurality of stepped structures formed in the first connection region are configured such that the stepped structure positioned at a relatively lower vertical height has a greater width in the second direction than the stepped structure positioned at a relatively higher vertical height. The plurality of stepped structures formed in the first connection region include a highest stepped structure, a lowest stepped structure, and an intermediate stepped structure between the highest stepped structure and the lowest stepped structure. The width of the intermediate stepped structure in the second direction is greater than the width of the highest stepped structure in the second direction, and the width of the intermediate stepped structure in the second direction is less than the width of the lowest stepped structure in the second direction.

7. The method according to claim 6, wherein, The steps for forming the plurality of stepped structures include the following steps: By repeating the first patterning process on the uppermost thin film stack, stepped structures are formed respectively in the first connection region and the second connection region of the uppermost thin film stack; and A stepped structure is formed in the lower film stack by reproducing the stepped structure of the uppermost film stack in the lower film stack located below the uppermost film stack.

8. The method according to claim 7, wherein, The first patterning process includes: Forming a first mask having a first opening, the first opening exposing the first connection region and the second connection region respectively in the first direction with a first width; and The process of etching the uppermost thin film stack using the first mask as an etching mask at a first etching depth and the trimming process of widening the width of each of the first openings in the first direction are repeated. The first etching depth is the same as the sum of the thickness of one of the plurality of first material layers and the thickness of one of the plurality of second material layers.

9. The method according to claim 8, wherein, The step of forming the stepped structure in the lower thin film stack includes: The multilayer stack is etched at a second etch depth using a second mask having a second opening as an etch mask. The second opening exposes the first connection region and the second connection region of the multilayer stack with a first width in the second direction. The multilayer stack is etched using a third mask with a third opening as an etching mask at a third etching depth, the third opening exposing the second interconnect region in the second direction with a second width greater than the first width; and The multilayer stack is etched using a fourth mask with a fourth opening as an etching mask at a fourth etching depth. The fourth opening exposes the first interconnect region and the second interconnect region respectively in the second direction with the second width. Wherein, the first width is greater than the difference between the second width and the first width, and The difference between the second width and the first width is greater than the difference between the width of the multilayer stack and the second width.

10. The method according to claim 8, wherein, The step of forming the stepped structure in the lower thin film stack includes the following steps: The multilayer stack is etched using a second mask with a second opening as an etching mask at a second etching depth. The second opening exposes the first connection region and the second connection region respectively in the second direction with a first width. The multilayer stack is etched using a third mask with a third opening as an etching mask at a third etching depth, the third opening exposing the first connection region and the second connection region respectively in the second direction with a second width greater than the first width; and The multilayer stack is etched at a fourth etch depth using a fourth mask having a fourth opening, the fourth opening exposing the second interconnect region at the second width in the second direction. Wherein, the first width is greater than the difference between the second width and the first width, and The difference between the second width and the first width is greater than the difference between the width of the multilayer stack and the second width.

11. The method according to claim 9, wherein, The second etching depth is twice the thickness of the thin film stack.

12. The method according to claim 10, wherein, The second etching depth, the third etching depth, and the fourth etching depth are all the thicknesses of the thin film stack.

13. The method according to claim 12, wherein, The plurality of stepped structures formed in the first connection region are arranged in adjacent thin film stacks, while the plurality of stepped structures formed in the second connection region are not arranged in adjacent thin film stacks.

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