Semiconductor memory device and method for manufacturing the semiconductor memory device

Abstract

A semiconductor memory device and a method for manufacturing the semiconductor memory device are provided. The semiconductor memory device includes: a peripheral circuit structure having a page buffer group; a mesh-like first source pattern disposed on the peripheral circuit structure, the mesh-like first source pattern having a plurality of openings; a memory cell array disposed on the mesh-like first source pattern; a second source pattern disposed between the mesh-like first source pattern and the memory cell array; and a cell array side pad pattern disposed between the mesh-like first source pattern and the second source pattern, extending from the second source pattern toward the mesh-like first source pattern, the cell array side pad pattern being directly bonded to the mesh-like first source pattern.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memory devices and methods of manufacturing such semiconductor memory devices, and more specifically, to semiconductor memory devices including memory cell arrays disposed on peripheral circuitry and methods of manufacturing such semiconductor memory devices. Background Technology

[0002] A semiconductor memory device may include a memory cell array and peripheral circuitry for controlling the operation of the memory cell array, the memory cell array comprising a plurality of memory cells. The memory cell array is positioned on the peripheral circuitry, thereby enabling increased integration of the semiconductor memory device. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a semiconductor memory device includes: a peripheral circuit structure having a page buffer group; a mesh-like first source pattern disposed on the peripheral circuit structure, the mesh-like first source pattern having a plurality of openings; a memory cell array disposed on the mesh-like first source pattern; a second source pattern disposed between the mesh-like first source pattern and the memory cell array; and a cell array side pad pattern disposed between the mesh-like first source pattern and the second source pattern, extending from the second source pattern toward the mesh-like first source pattern, the cell array side pad pattern being directly bonded to the mesh-like first source pattern.

[0004] According to an embodiment of the present disclosure, a semiconductor memory device includes: a peripheral circuit structure having a page buffer group; a first source pattern disposed on the peripheral circuit structure, the first source pattern having a source contact region and a page buffer connection region; a first opening penetrating the first source pattern in the page buffer connection region; a peripheral circuit-side first pad pattern disposed in the first opening, the peripheral circuit-side first pad pattern being connected to the page buffer group; a second source pattern overlapping the first source pattern in the source contact region; a memory cell array disposed on the second source pattern; a first bit line disposed on the memory cell array, the first bit line extending to overlap the peripheral circuit-side first pad pattern; and a first contact structure extending from the peripheral circuit-side first pad pattern toward the first bit line.

[0005] According to embodiments of the present disclosure, a method for manufacturing a semiconductor memory device includes the following steps: forming a peripheral circuit structure having a page buffer group and interconnects connected to the page buffer group; forming a metal pattern group on the peripheral circuit structure having a first source pattern and a peripheral circuit-side pad pattern; forming a preliminary memory structure, a second source pattern connected to the preliminary memory structure, and a cell array-side pad pattern connected to the second source pattern on a substrate; bonding the cell array-side pad pattern to the first source pattern; removing the substrate; forming a contact structure connected to the peripheral circuit-side pad pattern; and forming a bit line overlapping the peripheral circuit structure, wherein the second source pattern is interposed between the bit line and the peripheral circuit structure, and the bit line is connected to the contact structure. Attached Figure Description

[0006] Exemplary embodiments will now be described more fully with reference to the accompanying drawings; however, other embodiments may take different forms. Therefore, the possible embodiments described in this teaching should not be construed as limited to the specific embodiments set forth herein.

[0007] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Similar reference numerals always refer to similar elements.

[0008] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0010] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 4 This is a plan view illustrating a metal pattern group according to an embodiment of the present disclosure.

[0012] Figures 5A to 5E This is an example. Figure 4 The diagram shows the peripheral circuit side pad pattern and the bit lines and contact structures connected to the peripheral circuit side pad pattern.

[0013] Figure 6 This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 7A It is along Figure 6The cross-sectional view of the semiconductor memory device shown by line II′ is as follows, and Figure 7B It is along Figure 6 The cross-sectional view of the semiconductor memory device shown is taken by line II-II′.

[0015] Figure 8 This is a cross-sectional view illustrating the process of forming a peripheral circuit structure according to an embodiment of the present disclosure.

[0016] Figure 9A and Figure 9B These are plan and cross-sectional views illustrating a process for forming a metal pattern group according to an embodiment of the present disclosure.

[0017] Figures 10A to 10D This is a cross-sectional view illustrating the process of forming a preliminary memory structure according to an embodiment of the present disclosure.

[0018] Figure 11 This is a cross-sectional view illustrating a method for forming a cell array side pad pattern according to an embodiment of the present disclosure.

[0019] Figures 12A to 12F This is a process cross-sectional view illustrating an implementation of a subsequent process following the formation of the cell array side pad pattern.

[0020] Figure 13 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0021] Figure 14 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments may be implemented in various forms, and therefore, possible embodiments should not be construed as limited to those described herein.

[0023] In the following text, the terms "first" and "second" are used to distinguish one component from another, and do not indicate the number or order of components. Therefore, components should not be limited by these terms.

[0024] The embodiments relate to a semiconductor memory device in which peripheral circuits and memory cell arrays are electrically connected to each other, and a method for manufacturing the semiconductor memory device.

[0025] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 1The semiconductor memory device 10 may include peripheral circuitry 30 and a memory cell array 20.

[0027] The peripheral circuit 30 can be configured to control programming operations for storing data in the memory cell array 20, reading operations for outputting data stored in the memory cell array 20, and erasing operations for erasing data stored in the memory cell array 20.

[0028] In an implementation, the peripheral circuitry 30 may include a voltage generator 31, a line decoder 33, a control circuit 35, and a page buffer group 37.

[0029] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 can be connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0030] Control circuit 35 can control peripheral circuit 30 in response to command CMD and address ADD.

[0031] Voltage generator 31 can generate various operating voltages based on the control of control circuit 35. Operating voltages may include pre-erase voltage, erase voltage, ground voltage, programming voltage, verification voltage, pass voltage, read voltage, etc., for programming, reading, and erasing operations.

[0032] The row decoder 33 can select a memory block based on the control of the control circuit 35. The row decoder 33 can apply an operating voltage to the word line WL connected to the selected memory block.

[0033] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. Page buffer group 37 can temporarily store data received from input / output circuitry (not shown) during programming operations based on the control of control circuitry 35. Page buffer group 37 can sense the voltage or current of bit line BL during read or verification operations based on the control of control circuitry 35. Page buffer group 37 can select bit line BL based on the control of control circuitry 35.

[0034] Structurally, the memory cell array 20 can overlap with a portion of the peripheral circuit structure constituting the peripheral circuit 30. Therefore, the two-dimensional area occupied by the semiconductor memory device can be reduced.

[0035] Figure 2 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0036] Reference Figure 2The storage block BLK may include multiple cell strings CS1 and CS2. The multiple cell strings CS1 and CS2 may be grouped into strings. Each string group may be controlled by two or more drain select lines DSL1 and DSL2 separated from each other at the same height. In an embodiment, the two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2 separated from each other at the same height. The multiple cell strings CS1 and CS2 may include a first cell string CS1 connected to the first drain select line DSL1 and a second cell string CS2 connected to the second drain select line DSL2.

[0037] The first unit string CS1 and the second unit string CS2 can be connected to the word line WL, the source select line SSL, the bit line BL, and the common source pattern CSL.

[0038] Each of the first cell string CS1 and the second cell string CS2 may include a plurality of memory cells MC connected in series, at least one source select transistor SST connected to the plurality of memory cells MC, and at least one drain select transistor DST connected to the plurality of memory cells MC. A common source pattern CSL may be connected to the plurality of memory cells MC via the source select transistor SST. A bit line BL may be connected to the plurality of memory cells MC via the drain select transistor DST.

[0039] The first drain select line DSL1 can be connected to the gate of the drain select transistor DST of the first cell string CS1, and the second drain select line DSL2 can be connected to the gate of the drain select transistor DST of the second cell string CS2. The word line WL can be connected to the gate of the memory cell MC. The source select line SSL can be connected to the gate of the source select transistor SST.

[0040] According to the above structure, the first unit string CS1 and the second unit string CS2, which are connected together to a word line and a bit line, can be independently controlled by the first drain selection line DSL1 and the second drain selection line DSL2.

[0041] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0042] Reference Figure 3 The semiconductor memory device may include a common source pattern CSL, a source select line SSL, a word line WL, a first drain select line DSL1, a second drain select line DSL2, a bit line BL, and peripheral circuit side pad patterns PP1 and PP2.

[0043] The common source pattern CSL may include a first source pattern SL1 and a second source pattern SL2.

[0044] The first source pattern SL1 may extend in a first direction D1 and a second direction D2. The first source pattern SL1 may include a source contact region SCA and a page buffer connection region PCA. The first source pattern SL1 may be a mesh with a first opening OP1 and a second opening OP2. The first opening OP1 may extend through the first source pattern SL1 in the page buffer connection region PCA. The second opening OP2 may extend through the first source pattern SL1 in the source contact region SCA.

[0045] The second source pattern SL2 can be spaced apart from the first source pattern SL1 in a third direction D3. The third direction D3 can be defined as a direction orthogonal to the first direction D1 and the second direction D2. The second source pattern SL2 can overlap with the first source pattern SL1 in the source contact area SCA. Compared to the second source pattern SL2, the first source pattern SL1 can protrude further in the first direction D1, extending from the source contact area SCA into the page buffer connection area PCA. Therefore, in the page buffer connection area PCA, the first source pattern SL1 may not overlap with the second source pattern SL2, but can be exposed due to the absence of the second source pattern SL2.

[0046] The source selection line SSL can be set on the second source pattern SL2. The source selection line SSL can be spaced apart from the second source pattern SL2 on the third direction D3.

[0047] Word lines WL can be set on the source select line SSL. Word lines WL can be spaced apart from the source select line SSL on the third-party direction D3. Word lines WL can be arranged to be spaced apart from each other on the third-party direction D3.

[0048] A source select line SSL can be positioned between the second source pattern SL2 and the lowest word line WL. However, embodiments of this disclosure are not limited thereto. In embodiments, two or more source select lines spaced apart from each other on a third direction D3 can be positioned between the second source pattern SL2 and the lowest word line WL.

[0049] The first drain selection line DSL1 and the second drain selection line DSL2 can be set at the same height on the word line WL. The first drain selection line DSL1 and the second drain selection line DSL2 can be spaced apart from the word line WL on a third direction D3. The first drain selection line DSL1 and the second drain selection line DSL2 can be arranged to be spaced apart from each other on a first direction D1.

[0050] Bit line BL can be disposed on the first drain select line DSL1 and the second drain select line DSL2. Bit line BL can be spaced apart from the first drain select line DSL1 and the second drain select line DSL2 in a third direction D3. Bit line BL can extend in a direction intersecting the first drain select line DSL1 and the second drain select line DSL2. In an embodiment, bit line BL can extend in a first direction D1.

[0051] A first drain select line DSL1 and a second drain select line DSL2 can be disposed between the uppermost word line WL and the bit line BL. However, embodiments of this disclosure are not limited thereto. In embodiments, two or more first drain select lines spaced apart from each other on the third direction D3 and two or more second drain select lines spaced apart from each other on the third direction D3 can be disposed between the bit line BL and the uppermost word line WL.

[0052] The peripheral circuit side pad patterns PP1 and PP2 can be made of the same conductive material as the first source pattern SL1. In an embodiment, the peripheral circuit side pad patterns PP1 and PP2 and the first source pattern SL1 can include aluminum.

[0053] The peripheral circuit side pad patterns PP1 and PP2 can be positioned at a height substantially the same as the height of the first source pattern SL1. The peripheral circuit side pad patterns PP1 and PP2 can be positioned within the first opening OP1, spaced apart from the first source pattern SL1. In an embodiment, the peripheral circuit side pad patterns PP1 and PP2 can include a first peripheral circuit side pad pattern PP1 and a second peripheral circuit side pad pattern PP2 spaced apart from each other within the first opening OP1. In a plan view, the first peripheral circuit side pad pattern PP1 and the second peripheral circuit side pad pattern PP2 can be offsetly positioned on a diagonal L. The diagonal L may not be parallel to orthogonal to the bit line BL. In an embodiment, the diagonal L can be positioned between an axis facing the first direction D1 and an axis facing the second direction D2. The direction facing the diagonal L can be defined as the diagonal direction.

[0054] In the following text, the term "metal pattern group" is defined as including the first source pattern SL1, the first pad pattern PP1 on the peripheral circuit side, and the second pad pattern PP2 on the peripheral circuit side.

[0055] Figure 4 This is a plan view illustrating a metal pattern group according to an embodiment of the present disclosure. For a more detailed description... Figure 3 The layout of the metal pattern group shown, Figure 4 The example shown in the comparison Figure 3 The range shown is a wider group of metal patterns.

[0056] Reference Figure 4 , as reference Figure 3 As described, the metal pattern set may include a first source pattern SL1, first pad patterns PP11, PP12, PP13, PP14 and PP15 on the peripheral circuit side, and second pad patterns PP21, PP22, PP23, PP24 and PP25 on the peripheral circuit side.

[0057] The first source pattern SL1 may extend on a plane formed by a first direction D1 and a second direction D2. The first source pattern SL1 may be a mesh having multiple first openings OP11, OP12, OP13, OP14 and OP15 and multiple second openings OP21, OP22, OP23, OP24 and OP25. The first source pattern SL1 may include page buffer connection regions PCA1, PCA2, PCA3, PCA4 and PCA5 alternately arranged on the first direction D1, and source contact regions SCA1, SCA2, SCA3, SCA4 and SCA5.

[0058] In one embodiment, the page buffer connection area may include a first page buffer connection area PCA1, a second page buffer connection area PCA2, a third page buffer connection area PCA3, a fourth page buffer connection area PCA4, and a fifth page buffer connection area PCA5, arranged spaced apart from each other in a first direction D1. In another embodiment, the source contact area may include a first source contact area SCA1, a second source contact area SCA2, a third source contact area SCA3, a fourth source contact area SCA4, and a fifth source contact area SCA5, arranged spaced apart from each other in the first direction D1. A first source pattern SL1 may extend from the first page buffer connection area PCA1 to the first source contact area SCA1, and may extend from the first source contact area SCA1 to the second page buffer connection area PCA2. The first source pattern SL1 may extend from the second page buffer connection area PCA2 to the second source contact area SCA2, and may extend from the second source contact area SCA2 to the third page buffer connection area PCA3. The first source pattern SL1 can extend from the third page buffer connection area PCA3 to the third source contact area SCA3, and from the third source contact area SCA3 to the fourth page buffer connection area PCA4. The first source pattern SL1 can extend from the fourth page buffer connection area PCA4 to the fourth source contact area SCA4, and from the fourth source contact area SCA4 to the fifth page buffer connection area PCA5. The first source pattern SL1 can extend from the fifth page buffer connection area PCA5 to the fifth source contact area SCA5.

[0059] The arrangement of the first openings OP11, OP12, OP13, OP14 and OP15 can be designed in a variety of ways based on the arrangement of the first pad patterns PP11, PP12, PP13, PP14 and PP15 on the peripheral circuit side and the second pad patterns PP21, PP22, PP23, PP24 and PP25 on the peripheral circuit side.

[0060] The first openings OP11, OP12, OP13, OP14 and OP15 may include the first opening OP11 through the first group of the first page buffer connection area PCA1, the first opening OP12 through the second group of the second page buffer connection area PCA2, the first opening OP13 through the third group of the third page buffer connection area PCA3, the first opening OP14 through the fourth group of the fourth page buffer connection area PCA4, and the first opening OP15 through the fifth group of the fifth page buffer connection area PCA5.

[0061] The first pad pattern on the peripheral circuit side may include the first pad pattern PP11 of the first group, the first pad pattern PP12 of the second group, the first pad pattern PP13 of the third group, the first pad pattern PP14 of the fourth group, and the first pad pattern PP15 of the fifth group. The second pad pattern on the peripheral circuit side may include the second pad pattern PP21 of the first group, the second pad pattern PP22 of the second group, the second pad pattern PP23 of the third group, the second pad pattern PP24 of the fourth group, and the second pad pattern PP25 of the fifth group.

[0062] Similar to a reference Figure 3 The peripheral circuit side first pad pattern PP1 and peripheral circuit side second pad pattern PP2 are described. In the plan view, the first group of peripheral circuit side first pad patterns PP11 and peripheral circuit side second pad patterns PP21 can be arranged diagonally in the first opening OP11 of the first group. The second group of peripheral circuit side first pad patterns PP12 and peripheral circuit side second pad patterns PP22 can be arranged diagonally in the first opening OP12 of the second group. The third group of peripheral circuit side first pad patterns PP13 and peripheral circuit side second pad patterns PP23 can be arranged diagonally in the first opening OP13 of the third group. The fourth group of peripheral circuit side first pad patterns PP14 and peripheral circuit side second pad patterns PP24 can be arranged diagonally in the first opening OP14 of the fourth group. The fifth group of peripheral circuit side first pad patterns PP15 and peripheral circuit side second pad patterns PP25 can be arranged diagonally in the first opening OP15 of the fifth group. From a two-dimensional viewpoint, the diagonal direction can be a direction different from the first direction D1 and the second direction D2.

[0063] The second openings OP21, OP22, OP23, OP24 and OP25 may include the second opening OP21 that penetrates the first group of the first source contact region SCA1, the second opening OP22 that penetrates the second group of the second source contact region SCA2, the second opening OP23 that penetrates the third group of the third source contact region SCA3, the second opening OP24 that penetrates the fourth group of the fourth source contact region SCA4, and the second opening OP25 that penetrates the fifth group of the fifth source contact region SCA5.

[0064] Figures 5A to 5E This is an example. Figure 4 The diagram shows the peripheral circuit side pad pattern and the bit lines and contact structures connected to the peripheral circuit side pad pattern. Figure 5A Enlarged and illustrated Figure 4 The first set of peripheral circuit side pad patterns PP11 and PP21 are shown; in Figure 5B Enlarged and illustrated Figure 4 The second set of peripheral circuit side first pad pattern PP12 and peripheral circuit side second pad pattern PP22 are shown; in Figure 5C Enlarged and illustrated Figure 4 The third group shows the first pad pattern PP13 and the second pad pattern PP23 on the peripheral circuit side; in Figure 5D Enlarged and illustrated Figure 4 The fourth group shows the first pad pattern PP14 and the second pad pattern PP24 on the peripheral circuit side; and in Figure 5E Enlarged and illustrated Figure 4 The fifth group shows the first pad pattern PP15 and the second pad pattern PP25 on the peripheral circuit side.

[0065] Reference Figures 5A to 5E The semiconductor memory device may include bit lines BL1 to BL10 that overlap with each of the following groups: a first opening OP11 of the first group, a first opening OP12 of the second group, a first opening OP13 of the third group, a first opening OP14 of the fourth group, and a first opening OP15 of the fifth group. Two or more bit lines may overlap with each of the following groups: a first pad pattern PP11 and a second pad pattern PP21 on the peripheral circuit side of the first group, a first pad pattern PP12 and a second pad pattern PP22 on the peripheral circuit side of the second group, a first pad pattern PP13 and a second pad pattern PP23 on the peripheral circuit side of the third group, a first pad pattern PP14 and a second pad pattern PP24 on the peripheral circuit side of the fourth group, and a first pad pattern PP15 and a second pad pattern PP25 on the peripheral circuit side of the fifth group.

[0066] Bit lines BL1 to BL10 can be connected via contact structures CT11, CT21, CT12, CT22, CT13, CT23, CT14, CT24, CT15, and CT25 to the first pad pattern PP11 and the second pad pattern PP21 on the peripheral circuit side of the first group, the first pad pattern PP12 and the second pad pattern PP22 on the peripheral circuit side of the second group, the first pad pattern PP13 and the second pad pattern PP23 on the peripheral circuit side of the third group, the first pad pattern PP14 and the second pad pattern PP24 on the peripheral circuit side of the fourth group, and the first pad pattern PP15 and the second pad pattern PP25 on the peripheral circuit side of the fifth group, respectively.

[0067] Contact structures CT11, CT21, CT12, CT22, CT13, CT23, CT14, CT24, CT15, and CT25 can be connected to the first pad pattern PP11 and the second pad pattern PP21 on the peripheral circuit side of the first group, the first pad pattern PP12 and the second pad pattern PP22 on the peripheral circuit side of the second group, the first pad pattern PP13 and the second pad pattern PP23 on the peripheral circuit side of the third group, the first pad pattern PP14 and the second pad pattern PP24 on the peripheral circuit side of the fourth group, and the first pad pattern PP15 and the second pad pattern PP25 on the peripheral circuit side of the fifth group, and can extend on the third direction D3. The contact structures CT11, CT21, CT12, CT22, CT13, CT23, CT14, CT24, CT15 and CT25 may include the first contact structure CT11 and the second contact structure CT21 of the first group, the first contact structure CT12 and the second contact structure CT22 of the second group, the first contact structure CT13 and the second contact structure CT23 of the third group, the first contact structure CT14 and the second contact structure CT24 of the fourth group, and the first contact structure CT15 and the second contact structure CT25 of the fifth group.

[0068] In an embodiment, the semiconductor memory device may include first bit lines BL1 to tenth bit lines BL10. The first bit lines BL1 to tenth bit lines BL10 may extend parallel to each other and may be arranged to be spaced apart from each other in a second direction D2. The first bit lines BL1 to tenth bit lines BL10 may overlap with a first opening OP11 of a first group, a first opening OP12 of a second group, a first opening OP13 of a third group, a first opening OP14 of a fourth group, and a first opening OP15 of a fifth group. The consecutively arranged bit lines may overlap with each of the following: a first pad pattern PP11 and a second pad pattern PP21 on the peripheral circuit side of the first group; a first pad pattern PP12 and a second pad pattern PP22 on the peripheral circuit side of the second group; a first pad pattern PP13 and a second pad pattern PP23 on the peripheral circuit side of the third group; a first pad pattern PP14 and a second pad pattern PP24 on the peripheral circuit side of the fourth group; and a first pad pattern PP15 and a second pad pattern PP25 on the peripheral circuit side of the fifth group.

[0069] Reference Figure 5A The first bit line BL1, the second bit line BL2, the third bit line BL3, the fourth bit line BL4, and the fifth bit line BL5, which are continuously arranged in the second direction D2, can overlap with the first pad pattern PP11 on the peripheral circuit side of the first group. The fifth bit line BL5 can be connected to the first pad pattern PP11 on the peripheral circuit side of the first group via the first contact pattern CT11 of the first group.

[0070] The sixth bit line BL6, the seventh bit line BL7, the eighth bit line BL8, the ninth bit line BL9, and the tenth bit line BL10, which are continuously arranged on the second direction D2, can overlap with the second pad pattern PP21 on the peripheral circuit side of the first group. The tenth bit line BL10 can be connected to the second pad pattern PP21 on the peripheral circuit side of the first group via the second contact pattern CT21 of the first group.

[0071] Reference Figure 5B The second bit line BL2, the third bit line BL3, the fourth bit line BL4, the fifth bit line BL5, and the sixth bit line BL6 can overlap with the first pad pattern PP12 on the peripheral circuit side of the second group. The fourth bit line BL4 can be connected to the first pad pattern PP12 on the peripheral circuit side of the second group via the first contact pattern CT12 of the second group.

[0072] The seventh bit line BL7, the eighth bit line BL8, the ninth bit line BL9, and the tenth bit line BL10 can overlap with the second pad pattern PP22 on the peripheral circuit side of the second group. The ninth bit line BL9 can be connected to the second pad pattern PP22 on the peripheral circuit side of the second group via the second contact pattern CT22 of the second group.

[0073] Reference Figure 5C The first bit line BL1, the second bit line BL2, the third bit line BL3, the fourth bit line BL4, and the fifth bit line BL5 can overlap with the first pad pattern PP13 on the peripheral circuit side of the third group. The third bit line BL3 can be connected to the first pad pattern PP13 on the peripheral circuit side of the third group via the first contact pattern CT13 of the third group.

[0074] The sixth bit line BL6, the seventh bit line BL7, the eighth bit line BL8, the ninth bit line BL9, and the tenth bit line BL10 can overlap with the second pad pattern PP23 on the peripheral circuit side of the third group. The eighth bit line BL8 can be connected to the second pad pattern PP23 on the peripheral circuit side of the third group via the second contact pattern CT23.

[0075] Reference Figure 5D The second bit line BL2, the third bit line BL3, the fourth bit line BL4, the fifth bit line BL5, and the sixth bit line BL6 can overlap with the first pad pattern PP14 on the peripheral circuit side of the fourth group. The second bit line BL2 can be connected to the first pad pattern PP14 on the peripheral circuit side of the fourth group via the first contact pattern CT14 of the fourth group.

[0076] The seventh bit line BL7, the eighth bit line BL8, the ninth bit line BL9, and the tenth bit line BL10 can overlap with the second pad pattern PP24 on the peripheral circuit side of the fourth group. The seventh bit line BL7 can be connected to the second pad pattern PP24 on the peripheral circuit side of the fourth group via the second contact pattern CT24.

[0077] Reference Figure 5E The first bit line BL1, the second bit line BL2, the third bit line BL3, the fourth bit line BL4, and the fifth bit line BL5 can overlap with the first pad pattern PP15 on the peripheral circuit side of the fifth group. The first bit line BL1 can be connected to the first pad pattern PP15 on the peripheral circuit side of the fifth group via the first contact pattern CT15 of the fifth group.

[0078] The sixth bit line BL6, the seventh bit line BL7, the eighth bit line BL8, the ninth bit line BL9, and the tenth bit line BL10 can overlap with the second pad pattern PP25 on the peripheral circuit side of the fifth group. The sixth bit line BL6 can be connected to the second pad pattern PP25 on the peripheral circuit side of the fifth group via the second contact pattern CT25.

[0079] Figure 6 This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0080] Reference Figure 6 A semiconductor memory device may include gate stack structures GST1 and GST2, channel pillars CH1 and CH2, and bit lines BL.

[0081] Gate stack structures GST1 and GST2 may include a first gate stack structure GST1 and a second gate stack structure GST2 spaced apart from each other. Each of the first gate stack structure GST1 and the second gate stack structure GST2 may extend on a plane created by a first direction D1 and a second direction D2. The first gate stack structure GST1 and the second gate stack structure GST2 may be spaced apart from each other in the first direction D1. Each of the first gate stack structure GST1 and the second gate stack structure GST2 may include a first drain select line DSL1 and a second drain select line DSL2 spaced apart from each other in the first direction D1.

[0082] Each of the first gate stack structure GST1 and the second gate stack structure GST2 can be penetrated by channel pillars CH1 and CH2 extending on the third-direction D3. Channel pillars CH1 and CH2 can be connected to bit line BL via bit line contacts BCT1 and BCT2.

[0083] Channel posts CH1 and CH2 may include a first channel post CH1 passing through the first drain select line DSL1 and a second channel post CH2 passing through the second drain select line DSL2. Bit line contacts BCT1 and BCT2 may include a first bit line contact BCT1 connected to the first channel post CH1 and a second bit line contact BCT2 connected to the second channel post CH2.

[0084] Bit lines BL can be parallel to each other. In one embodiment, each bit line BL can extend in a first direction D1. Bit lines BL can be spaced apart in a second direction D2. Bit lines BL can include a first bit line BL1 connected to a first contact structure CT1 and a second bit line BL2 connected to a second contact structure CT2. The first contact structure CT1 and the second contact structure CT2 can be disposed between a first gate stack structure GST1 and a second gate stack structure GST2. The first contact structure CT1 and the second contact structure CT2 can extend in a third direction D3.

[0085] The first bit line BL1 and the second bit line BL2 can be connected to the page buffer group via the first contact structure CT1 and the second contact structure CT2. The connection structure between the first bit line BL1 and the second bit line BL2 and the page buffer group will be described below with reference to cross-sectional views of the semiconductor memory device taken along lines II′ and II-II′.

[0086] The first line BL1 may overlap with the first channel posts CH1 and the second channel posts CH2 arranged in a row in the first direction D1. Some of the channel posts CH1 and CH2 that overlap with the first line BL1 may be connected to the first line BL1, while the other channel posts CH1 and CH2 may be connected to the other line. The second line BL2 may overlap with the first channel posts CH1 and the second channel posts CH2 arranged in a row in the first direction D1. Some of the channel posts CH1 and CH2 that overlap with the second line BL2 may be connected to the second line BL2, while the other channel posts CH1 and CH2 may be connected to the other line.

[0087] Line II′ can overlap not only with the first channel post CH1 and the second channel post CH2 connected to the first line BL1, but also with the first channel post CH1 and the second channel post CH2 connected to the other line. Line II-II′ can overlap not only with the first channel post CH1 and the second channel post CH2 connected to the second line BL2, but also with the first channel post CH1 and the second channel post CH2 connected to the other line.

[0088] Figure 7A It is along Figure 6 The cross-sectional view of the semiconductor memory device shown by line II′ is as follows, and Figure 7B It is along Figure 6 The cross-sectional view of the semiconductor memory device shown is taken by line II-II′.

[0089] Reference Figure 7A and Figure 7B The semiconductor memory device may include a peripheral circuit structure 100, a first source pattern SL1 disposed on the peripheral circuit structure 100, a memory cell array 190 disposed on the first source pattern SL1, second source patterns SL21 and SL22 disposed between the memory cell array 190 and the first source pattern SL1, a cell array side pad pattern 173 between the second source patterns SL21 and SL22 and the first source pattern SL1, a first bit line BL1 and a second bit line BL2 connected to the memory cell array 190, a first bit line contact BCT1 and a second bit line contact BCT2, and a first contact structure CT1 and a second contact structure CT2.

[0090] The peripheral circuit structure 100 may include components Figure 1The page buffer group 37 shown includes transistors 110A, 110B, 110C, 110D, 110E, and 110F, and interconnects 121 connected to transistors 110A, 110B, 110C, 110D, 110E, and 110F. Each of transistors 110A, 110B, 110C, 110D, 110E, and 110F may include a junction 111 formed in a semiconductor substrate 101, a gate insulating layer 113 formed on the semiconductor substrate 101, and a gate 115 formed on the gate insulating layer 113. The gate 115 may be disposed on an active region of the semiconductor substrate 101 separated by an isolation layer 103. The junction 111 may be defined by implanting at least one of an n-type impurity and a p-type impurity into the active regions on both sides of the gate 115.

[0091] Each of the interconnects 121 may include two or more conductive patterns connected to each other.

[0092] The interconnects 121 of transistors 110A, 110B, 110C, 110D, 110E, and 110F connected to the peripheral circuit structure 100 may be buried in the lower insulating structure 127. The lower insulating structure 127 may include two or more insulating layers.

[0093] The first source pattern SL1 may include a first source contact area SCA1′, a second source contact area SCA2′, and a page buffer connection area PCA′. The page buffer connection area PCA′ may be located between the first source contact area SCA1′ and the second source contact area SCA2′.

[0094] The first source pattern SL1 can be a mesh with a first opening OP1 and a second opening OP2. Figure 7A An example is shown: a cross-section of the first source pattern SL1 taken along line II′, which intersects the first opening OP1 and the second opening OP2. Figure 7B An example is shown: a cross-section of the first source pattern SL1 taken along line II-II′, which overlaps with the first opening OP1 but not with the second opening OP2. The first source pattern SL1 can be as follows: Figure 4 The mesh pattern is shown. The first source pattern SL1 can continuously extend from the first source contact region SCA1′ to the page buffer connection region PCA′. The first source pattern SL1 can continuously extend from the page buffer connection region PCA′ to the second source contact region SCA2′. The first source pattern SL1 can be disposed between the first opening OP1 and the second opening OP2 adjacent to the first opening OP1, and between the second openings OP2. In an embodiment, as... Figure 7A and Figure 7B The first source contact region SCA1′ and the second source contact region SCA2′ shown can correspond to Figure 4The first source contact region SCA1 and the second source contact region SCA2 are shown, and as... Figure 7A and Figure 7B The page buffer connection area PCA′ shown can correspond to Figure 4 The second page buffer connection area PCA2 is shown.

[0095] The first opening OP1 can be filled with a first pad pattern PP1 on the peripheral circuit side, a second pad pattern PP2 on the peripheral circuit side, and a first insulating pattern 129A. The first source pattern SL1, the first pad pattern PP1 on the peripheral circuit side, and the second pad pattern PP2 on the peripheral circuit side can be insulated from each other by the first insulating pattern 129A. The second opening OP2 can be filled with a second insulating pattern 129B.

[0096] The first opening OP1 and the first insulating pattern 129A can penetrate the first source pattern SL1 of the page buffer connection area PCA′. The second opening OP2 and the second insulating pattern 129B can penetrate the first source pattern SL1 in each of the first source contact areas SCA1′ and the second source contact areas SCA2′.

[0097] The first pad pattern PP1 and the second pad pattern PP2 on the peripheral circuit side can be set at substantially the same height as the first source pattern SL1. The first pad pattern PP1 and the second pad pattern PP2 on the peripheral circuit side can be made of the same conductive material as the first source pattern SL1. The first pad pattern PP1 and the second pad pattern PP2 on the peripheral circuit side can be buried in the first opening OP1 by the first insulating pattern 129A. (See reference...) Figure 3 As described, in the plan view, the first pad pattern PP1 and the second pad pattern PP2 on the peripheral circuit side can be arranged diagonally in the first opening OP1. The first pad pattern PP1 and the second pad pattern PP2 on the peripheral circuit side can be connected to some of the transistors 110A, 110B, 110C, 110D, 110E, and 110F via some of the interconnects 121. In an embodiment, the first pad pattern PP1 on the peripheral circuit side can be connected to the first transistor 110B via the interconnect 121, and the second pad pattern PP2 on the peripheral circuit side can be connected to the second transistor 110E via the interconnect 121.

[0098] The memory cell array 190 may include a first gate stack structure GST1, a second gate stack structure GST2, a first channel pillar CH1 and a second channel pillar CH2 penetrating each of the first gate stack structure GST1 and the second gate stack structure GST2, and a memory layer 140 surrounding the sidewalls of each of the first channel pillar CH1 and the second channel pillar CH2.

[0099] The first gate stack structure GST1 and the second gate stack structure GST2 can overlap with the first source contact region SCA1′ and the second source contact region SCA2′ of the first source pattern SL1, respectively. The first gate stack structure GST1 and the second gate stack structure GST2 can be disposed on the second source patterns SL21 and SL22, respectively. The first gate stack structure GST1 and the second gate stack structure GST2 can include an interlayer insulating layer 131 and conductive patterns SSL, WL, DSL1 and DSL2 alternately stacked on the second source patterns SL21 and SL22. The interlayer insulating layer 131 and the conductive patterns SSL, WL, DSL1 and DSL2 can surround the sidewall of the memory layer 140.

[0100] The first gate stack structure GST1 and the second gate stack structure GST2 can be separated from each other by the gate insulating structure 171. The gate insulating structure 171 can be disposed between the first gate stack structure GST1 and the second gate stack structure GST2. The gate insulating structure 171 can extend between the second source patterns SL21 and SL22. The gate insulating structure 171 can extend between the second source patterns SL21 and SL22 and the first source pattern SL1.

[0101] At least one upper insulating layer may be disposed on the first gate stack structure GST1 and the second gate stack structure GST2. In an embodiment, the first upper insulating layer 181 and the second upper insulating layer 187 may be stacked on the first gate stack structure GST1 and the second gate stack structure GST2.

[0102] The conductive patterns SSL, WL, DSL1, and DSL2 of the first gate stack structure GST1 and the second gate stack structure GST2 may include a source select line SSL, a word line WL, a first drain select line DSL1, and a second drain select line DSL2. The arrangement and reference of the source select line SSL, word line WL, first drain select line DSL1, and second drain select line DSL2 are as follows. Figure 3 The layouts described are the same.

[0103] The word line WL can be set between the first drain select line DSL1 and the source select line SSL, and can be extended between the second drain select line DSL2 and the source select line SSL.

[0104] The first upper insulating layer 181 may extend to fill the space between the first drain select line DSL1 and the second drain select line DSL2. The first drain select line DSL1 and the second drain select line DSL2 may be insulated from each other by the first upper insulating layer 181.

[0105] Each of the first channel pillar CH1 and the second channel pillar CH2 may extend into the first upper insulating layer 181. Each of the first channel pillar CH1 and the second channel pillar CH2 may be configured with a channel layer 151 and a core insulating layer 153. The channel layer 151 may extend in a third direction D3 to penetrate each of the first gate stack structure GST1 and the second gate stack structure GST2. The channel layer 151 may extend between each of the second source patterns SL21 and SL22 and each of the first gate stack structure GST1 and the second gate stack structure GST2. For example, the channel layer 151 may extend between the second source pattern SL21 and the first gate stack structure GST1. The channel layer 151 may be connected to the second source pattern SL21 or SL22 corresponding to the channel layer 151 and may extend toward the first bit line BL1 and the second bit line BL2. The channel layer 151 may surround the sidewall of the core insulating layer 153. The channel layer 151 may cover the surface of the core insulation layer 153 facing the first line BL1 or the second line BL2. The core insulation layer 153 may be disposed in the central region of each of the first channel post CH1 and the second channel post CH2.

[0106] Memory layer 140 may be disposed between each of the first gate stack structure GST1 and the second gate stack structure GST2 and the channel layer 151. Memory layer 140 may extend between the channel layer 151 and the first upper insulating layer 181. Memory layer 140 may include a barrier insulating layer 141, a data storage layer 143, and a tunnel insulating layer 145. Data storage layer 143 may be disposed between the barrier insulating layer 141 and the tunnel insulating layer 145, and tunnel insulating layer 145 may be disposed between the barrier insulating layer 141 and the channel layer 151. Barrier insulating layer 141 prevents charge from being introduced into each of the source select line SSL, word line WL, first drain select line DSL1, and second drain select line DSL2. Each of the local regions of data storage layer 143 surrounded by word line WL may be used as a data storage region. In an embodiment, data storage layer 143 may be configured to store a material layer capable of storing data altered by using Fowler-Nordheim tunneling. The material layer may include a nitride layer capable of trapping charges. The tunnel insulation layer 145 may include an insulating material through which charges can tunnel. In one embodiment, the tunnel insulation layer 145 may include a silicon oxide layer.

[0107] Second source patterns SL21 and SL22 may overlap with the first source contact region SCA1′ and the second source contact region SCA2′ of the first source pattern SL1, respectively. Each of the second source patterns SL21 and SL22 may include a vertical portion 161A and a horizontal portion 161B. The horizontal portion 161B may extend parallel to the first source pattern SL1, and the vertical portion 161A may extend from the horizontal portion 161B toward the central region of each of the first channel pillar CH1 and the second channel pillar CH2. The second source patterns SL21 and SL22 may include a doped semiconductor layer. In an embodiment, the second source patterns SL21 and SL22 may include n-type doped silicon.

[0108] Cell array side pad pattern 173 can extend from the second source patterns SL21 and SL22 toward the first source pattern SL1. Cell array side pad pattern 173 can be directly bonded to the first source pattern SL1 in the first source contact region SCA1′ and the second source contact region SCA2′. Cell array side pad pattern 173 and the first source pattern SL1 can include metal. The specific resistance of the first source pattern SL1 can be lower than the specific resistance of the second source patterns SL21 and SL22. Therefore, the resistance of the second source patterns SL21 and SL22 can be compensated by the first source pattern SL1, thereby improving the operational reliability of the semiconductor memory device. In an embodiment, cell array side pad pattern 173 can include copper, and the first source pattern SL1 can include aluminum. Because cell array side pad pattern 173 is directly bonded to the first source pattern SL1 that compensates for resistance, a bonding structure between the peripheral circuit structure 100 and the memory cell array 190 can be provided even if no other bonding pads are added separately to the first source pattern SL1.

[0109] The first bit line BL1 and the second bit line BL2 can be disposed on the second upper insulating layer 187. The first bit line BL1 and the second bit line BL2 can extend to overlap with the first opening OP1. The first bit line BL1 can overlap with the first pad pattern PP1 on the peripheral circuit side. The second bit line BL2 can overlap with the second pad pattern PP2 on the peripheral circuit side.

[0110] The first bit contact BCT1 connects the first bit BL1 to the channel layer 151 of the first channel post CH1. The second bit contact BCT2 connects the second bit BL2 to the channel layer 151 of the second channel post CH2. The first bit contact BCT1 and the second bit contact BCT2 extend into the first upper insulating layer 181 and the second upper insulating layer 187, and penetrate the memory layer 140 to connect to the channel layer 151.

[0111] The first opening OP1 of the first source pattern SL1 may include a region that does not overlap with the first gate stack structure GST1 and the second gate stack structure GST2. The first pad pattern PP1 and the second pad pattern PP2 on the peripheral circuit side may be disposed in the first opening OP1 to avoid overlapping with the first gate stack structure GST1 and the second gate stack structure GST2.

[0112] The first contact structure CT1 and the second contact structure CT2 can penetrate the gate insulating structure 171 between the first gate stack structure GST1 and the second gate stack structure GST2. The first contact structure CT1 and the second contact structure CT2 can penetrate the first upper insulating layer 181 and the second upper insulating layer 187. The first contact structure CT1 can extend from the first pad pattern PP1 on the peripheral circuit side toward the first bit line BL1. The second contact structure CT2 can extend from the second pad pattern PP2 on the peripheral circuit side toward the second bit line BL2.

[0113] Each of the first contact structure CT1 and the second contact structure CT2 may include a first conductive plug 185 and a second conductive plug 189. The first conductive plug 185 may penetrate the gate insulating structure 171 and the first upper insulating layer 181, and may extend in the third direction D3. The second conductive plug 189 may penetrate the second upper insulating layer 187.

[0114] The processes for forming the peripheral circuit structure 100 and the processes for forming the memory cell array 190 are not sequential but can be performed independently. Therefore, the heat generated during the process of forming the memory cell array 190 has no effect on the peripheral circuit structure 100, and thus defects in the semiconductor memory device due to heat can be reduced. A method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0115] Figure 8 This is a cross-sectional view illustrating the process of forming a peripheral circuit structure according to an embodiment of the present disclosure.

[0116] Reference Figure 8 The peripheral circuit structure 200 may include components Figure 1 The page buffer group 37 shown includes transistors 210A, 210B, and 210C, and the peripheral circuit structure 200 may include interconnects 221 connected to transistors 210A, 210B, and 210C. Each of transistors 210A, 210B, and 210C may include a junction 211, a gate insulating layer 213, and a gate 215.

[0117] The process of forming the peripheral circuit structure 200 may include forming an isolation layer 203 in a semiconductor substrate 201, forming transistors 210A, 210B and 210C, and forming interconnects 221.

[0118] Transistors 210A, 210B, and 210C can be disposed in an active region defined in a semiconductor substrate 201. The active region can be separated by an isolation layer 203. The process of forming transistors 210A, 210B, and 210C may include forming a gate insulating layer 213 and a gate 215 on the semiconductor substrate 201 and forming a junction 211 in the active region of the semiconductor substrate 201. The junction 211 can be formed by implanting at least one of n-type and p-type impurities in the active region on both sides of the gate 215.

[0119] Transistors 210A, 210B, and 210C, as well as semiconductor substrate 201, may be covered by a lower insulating structure 227. The lower insulating structure 227 may include two or more insulating layers stacked on semiconductor substrate 201.

[0120] Interconnect 221 can be connected to transistors 210A, 210B, and 210C of the page buffer group. Interconnect 221 can be buried in the lower insulating structure 227. Each of interconnects 221 may include two or more conductive patterns connected to each other.

[0121] Figure 9A and Figure 9B These are plan and cross-sectional views illustrating a process for forming a metal pattern group according to an embodiment of the present disclosure.

[0122] Reference Figure 9A and Figure 9B The metal pattern group may include peripheral circuit side pad patterns 231A1 and 231A2 and a first source pattern 231B. The peripheral circuit side pad patterns 231A1 and 231A2 and the first source pattern 231B may be formed on the peripheral circuit structure 200.

[0123] Figure 9A It is a two-dimensional diagram of a metal pattern group.

[0124] Reference Figure 9A The first source pattern 231B of the metal pattern group can be a mesh penetrated by multiple first insulating patterns 237A and multiple second insulating patterns 237B. The peripheral circuit side pad patterns 231A1 and 231A2 of the metal pattern group can include a peripheral circuit side first pad pattern 231A1 and a peripheral circuit side second pad pattern 231A2 disposed in each first insulating pattern 237A.

[0125] The first pad pattern 231A1 and the second pad pattern 231A2 on the peripheral circuit side of the metal pattern group can be formed simultaneously with the first source pattern 231B. In an embodiment, the first source pattern 231B, the first pad pattern 231A1 on the peripheral circuit side, and the second pad pattern 231A2 on the peripheral circuit side can be formed by etching the metal layer using a single mask process. The etched area of ​​the metal layer can be filled with the first insulating pattern 237A and the second insulating pattern 237B, respectively.

[0126] The first insulating pattern 237A and the second insulating pattern 237B can be planarized using a planarization process such as chemical mechanical polishing. The stress applied during the planarization process can be distributed through the mesh-like first source pattern 231B. Therefore, when the first source pattern is mesh-like, compared to the same case with a flat first source pattern, cracks in the pattern caused by stress during the planarization process can be reduced. Furthermore, when the first source pattern is mesh-like, peeling can be reduced compared to when the first source pattern is flat. Moreover, the first pad pattern 231A1 on the peripheral circuit side and the second pad pattern 231A2 on the peripheral circuit side are disposed within the opening of the first source pattern 231B, thus reducing the area occupied by the first pad pattern 231A1 on the peripheral circuit side and the second pad pattern 231A2 on the peripheral circuit side.

[0127] The first pad pattern 231A1 on the peripheral circuit side and the second pad pattern 231A2 on the peripheral circuit side can be connected to the peripheral circuit structure.

[0128] Figure 9B It is along Figure 9A The cross-sectional view taken by line III-III′ shown.

[0129] Figure 9B The second pad pattern 231A2 on the peripheral circuit side connected to the peripheral circuit structure 200 is illustrated.

[0130] Reference Figure 9B The second pad pattern 231A2 on the peripheral circuit side can be connected to one of the transistors 210A, 210B and 210C of the peripheral circuit structure 200 (e.g., 210B) via interconnect 221.

[0131] Figures 10A to 10D This is a cross-sectional view illustrating the process of forming a preliminary memory structure according to an embodiment of the present disclosure.

[0132] Reference Figure 10AAn etch stop layer 303 may be formed on a substrate 301. The substrate 301 may be made of silicon. The etch stop layer 303 may include a material that has etch selectivity relative to the substrate 301. In an embodiment, the etch stop layer 303 may include a silicon nitride layer.

[0133] Subsequently, a select gate layer 305 can be formed on the etch stop layer 303. The select gate layer 305 can be formed of various conductive materials. In one embodiment, the select gate layer 305 may include doped silicon.

[0134] Subsequently, a first material layer 311 and a second material layer 313 may be alternately stacked on the selected gate layer 305. In an embodiment, the second material layer 313 may be a sacrificial layer with etch selectivity relative to the first material layer 311. More specifically, the first material layer 311 may be configured using a silicon oxide layer, and the second material layer 313 may be configured using a silicon nitride layer. The following process is described based on an embodiment in which the first material layer 311 is configured using a silicon oxide layer and the second material layer 313 is configured using a silicon nitride layer, but the embodiments of this disclosure are not limited thereto. In another embodiment, the first material layer 311 may be configured using an insulating layer, and the second material layer 313 may be configured using a conductive layer.

[0135] Subsequently, a channel via 321 can be formed through the first material layer 311 and the second material layer 313. The channel via 321 can penetrate the select gate layer 305 and the etch stop layer 303 and extend into the substrate 301.

[0136] Reference Figure 10B , can Figure 10A A memory layer 320, a channel layer 331, and a core insulating layer 333 are formed in the shown channel hole 321.

[0137] The process for forming memory layer 320 may include in Figure 10A A barrier insulating layer 323 is formed on the surface of each channel hole 321 shown. A data storage layer 325 is formed on the barrier insulating layer 323, and a tunnel insulating layer 327 is formed on the data storage layer 325. The material layers constituting the barrier insulating layer 323, the data storage layer 325, and the tunnel insulating layer 327 can correspond to the reference. Figure 7A and Figure 7B The barrier insulation layer 141, data storage layer 143, and tunnel insulation layer 145 are described. Each of the barrier insulation layer 323, data storage layer 325, and tunnel insulation layer 327 can extend onto the stacked structure of the first material layer 311 and the second material layer 313.

[0138] The channel layer 331 may extend along the surface of the memory layer 320. The channel layer 331 may be configured as a semiconductor layer. In one embodiment, the channel layer 331 may include silicon.

[0139] The core insulating layer 333 can be formed on the channel layer 331. The core insulating layer 333 can be formed on... Figure 10A The height at which the upper end of each channel hole 321 is open, as shown.

[0140] Subsequently, a doped semiconductor layer 335 can be formed. The doped semiconductor layer 335 can be connected to a portion of the exposed core insulating layer 333 of the channel layer 331 and extend onto the stacked structure of the first material layer 311 and the second material layer 313. In an embodiment, the doped semiconductor layer 335 can be configured as an n-type doped silicon layer.

[0141] Reference Figure 10C This can form a first slit 341, which penetrates through... Figure 10B The doped semiconductor layer 335 shown and Figure 10B The diagram shows a stacked structure of a first material layer 311 and a second material layer 313. When forming the first slit 341, the gate layer 305 can be used as an etch stop layer. Figure 10B The doped semiconductor layer 335 shown can be separated into a second source pattern 335S due to the first slit 341.

[0142] Subsequently, selective removal can be achieved through the first slit 341. Figure 10B The second material layer 313 is shown. Therefore, the horizontal space 343 between the first material layers 311 can be opened. The first material layers 311 can be retained as interlayer insulation layers.

[0143] Reference Figure 10D It can be filled with conductive pattern 345. Figure 10C The horizontal space 343 is shown. Therefore, a preliminary gate stack structure 350 comprising alternating layers of first material layers 311 and conductive patterns 345 can be formed. The preliminary gate stack structure 350 can be separated from each other by the first slit 341.

[0144] Based on the above references Figures 10A to 10DThe described process-defined preliminary memory structure 300 may include a select gate layer 305 formed on a substrate 301, a preliminary gate stack structure 350 formed on the select gate layer 305, a channel layer 331, and a memory layer 320. The channel layer 331 of the preliminary memory structure 300 may penetrate the preliminary gate stack structure 350 and the select gate layer 305 and extend into the substrate 301. The memory layer 320 of the preliminary memory structure 300 may be disposed between the channel layer 331 and the preliminary gate stack structure 350, and may extend between the channel layer 331 and the substrate 301.

[0145] The channel layer 331 of the initial memory structure 300 can be connected to the second source pattern 335S.

[0146] Figure 11 This is a cross-sectional view illustrating a method for forming a cell array side pad pattern according to an embodiment of the present disclosure.

[0147] Reference Figure 11 It can be filled with gate insulating structure 351 Figure 10D The first slit 341 is shown. The gate insulating structure 351 may extend onto the second source pattern 335S.

[0148] Subsequently, a cell array-side pad pattern 353 can be formed, which is connected to each second source pattern 335S. The cell array-side pad pattern 353 can extend through the gate insulating structure 351. The cell array-side pad pattern 353 may include bonding metal. In an embodiment, the cell array-side pad pattern 353 may include copper.

[0149] Figures 12A to 12F This is a process cross-sectional view illustrating an implementation of a subsequent process following the formation of the cell array side pad pattern.

[0150] Reference Figure 12A The cell array side pad pattern 353 can be bonded to the reference. Figure 8 , Figure 9A and Figure 9B The described process provides a first source pattern 231B on the peripheral circuit structure 200. The process of bonding the cell array-side pad pattern 353 to the first source pattern 231B may include aligning the initial gate stack structure 350 and the second source pattern 335S to avoid interference with, for example... Figure 9A The first insulating pattern 237A, the second pad pattern 231A2 on the peripheral circuit side, and the first pad pattern 231A1 on the peripheral circuit side overlap.

[0151] Reference Figure 12B It can be selectively removed Figure 12AThe substrate 301 shown is used for removal. When removing the substrate 301, it can be... Figure 12A The etch stop layer 303 shown protects the selective gate layer 305. Subsequently, it can be selectively removed. Figure 12A The etch stop layer 303 is shown. Therefore, a portion of the memory layer 320 can be exposed.

[0152] Subsequently, impurity 361 can be injected into the end of the channel layer 331 that is covered by the exposed portion of the memory layer 320. In an embodiment, impurity 361 can be an n-type impurity.

[0153] Reference Figure 12C It can be achieved through etching Figure 12B The selected gate layer 305 is used to form the second slit 363. The second slit 363 can penetrate... Figure 12B The selected gate layer 305 is shown. Figure 12B The selected gate layer 305 shown can be divided into a drain selected line 305D by the second slit 363.

[0154] Two or more drain select lines 305D may overlap with each initial gate stack 350. Each drain select line 305D may be retained to surround the sidewalls of the channel layer 331 and the memory layer 320.

[0155] Subsequently, a first upper insulating layer 365 can be formed, which covers the drain select line 305D and the memory layer 320. The first upper insulating layer 365 can fill the second slit 363.

[0156] Reference Figure 12D A first conductive plug 371 can be formed that penetrates the first upper insulating layer 365 and the gate insulating structure 351. The first conductive plug 371 can be connected to the second pad pattern 231A2 on the peripheral circuit side. Although not shown in the figure, it is connected to... Figure 9A The conductive plug of the first pad pattern 231A1 on the peripheral circuit side shown can be formed simultaneously with the first conductive plug 371.

[0157] Reference Figure 12E A second upper insulating layer 373 can be formed on the first upper insulating layer 365. Subsequently, a second conductive plug 375A and a bit line contact 375B can be formed.

[0158] The second conductive plug 375A can penetrate the second upper insulating layer 373 and can be connected to the first conductive plug 371. Therefore, a contact structure 370 can be defined to connect to the second pad pattern 231A2 on the peripheral circuit side.

[0159] Each bit line contact 375B can be connected to the channel layer 331 while passing through the second upper insulating layer 373, the first upper insulating layer 365, and the memory layer 320.

[0160] Reference Figure 12F A bit line 381 can be formed, which is connected to a bit line contact 375B. The bit line 381 can be connected to the peripheral circuit structure 200 via the contact structure 370 and the second pad pattern 231A2 on the peripheral circuit side.

[0161] Figure 13 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0162] Reference Figure 13 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0163] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips. The memory device 1120 may include a first source pattern disposed between a memory cell array and a peripheral circuit structure, a second source pattern connected to the memory cell array, and a cell array-side pad pattern connected to the second source pattern, the cell array-side pad pattern being directly bonded to the first source pattern. The first source pattern may be a mesh with openings. The memory device 1120 may also include peripheral circuit-side pad patterns disposed in the openings of the first source pattern and bit lines connected to the memory cell array, the bit lines overlapping the peripheral circuit-side pad patterns. The bit lines may be connected to the peripheral circuit structure via the peripheral circuit-side pad patterns.

[0164] The memory controller 1110 controls the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 can be used as the operating memory of the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110. The host interface 1113 may include a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 can detect errors contained in data read from the memory device 1120 and correct the detected errors. The memory interface 1115 can interface with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) for storing code data, etc., for connection to the host interface.

[0165] The memory system 1100 configured as described above can be a memory card or solid-state drive (SSD) in which the memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external (e.g., a host) via one of various interface protocols such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.

[0166] Figure 14 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0167] Reference Figure 14 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing operating voltage to the computing system 1200, and may also include an application chipset, a graphics processor, mobile DRAM, etc.

[0168] The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211.

[0169] The memory device 1212 may include a first source pattern disposed between a memory cell array and a peripheral circuit structure, a second source pattern connected to the memory cell array, and a cell array-side pad pattern connected to the second source pattern, the cell array-side pad pattern being directly bonded to the first source pattern. The first source pattern may be a mesh with openings. The memory device 1212 may also include a peripheral circuit-side pad pattern disposed in the opening of the first source pattern and bit lines connected to the memory cell array, the bit lines overlapping with the peripheral circuit-side pad pattern. The bit lines may be connected to the peripheral circuit structure via the peripheral circuit-side pad pattern.

[0170] The memory controller 1211 can be configured to be consistent with the above reference. Figure 13 The memory controller 1110 described is the same.

[0171] According to this disclosure, a structure for electrical connections between peripheral circuits and memory cell arrays can be designed by utilizing openings in the source pattern disposed between the peripheral circuits and the memory cell array.

[0172] Cross-references to related applications

[0173] This application claims priority to Korean Patent Application No. 10-2020-0172452, filed with the Korean Intellectual Property Office on December 10, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: The peripheral circuit structure has a page buffer group; A mesh-like first source pattern is disposed on the peripheral circuit structure, and the mesh-like first source pattern has multiple openings; A memory cell array disposed on the first source pattern of the mesh; A second source pattern is disposed between the mesh-like first source pattern and the memory cell array; A cell array side pad pattern is disposed between the first source pattern and the second source pattern of the mesh, extending from the second source pattern toward the first source pattern of the mesh, and the cell array side pad pattern is directly bonded to the first source pattern of the mesh. as well as The peripheral circuit side pad pattern is disposed within the mesh-like first source pattern and is in contact with the peripheral circuit structure. The plurality of openings includes a plurality of first openings that do not overlap with the second source pattern and a plurality of second openings that overlap with the second source pattern; and The peripheral circuit side pad pattern is set in each of the plurality of first openings and connected to the bit line through a contact structure.

2. The semiconductor memory device according to claim 1, wherein, The resistivity of the first source pattern of the mesh is lower than that of the second source pattern.

3. The semiconductor memory device according to claim 2, wherein, The mesh-like first source pattern includes metal, and The second source pattern includes a doped semiconductor.

4. The semiconductor memory device according to claim 1, wherein, The mesh-like first source pattern includes aluminum, and The pad pattern on the unit array side includes copper.

5. The semiconductor memory device according to claim 1, wherein, The memory cell array includes: A gate stack structure having an interlayer insulating layer and a conductive pattern alternately stacked on a second source pattern; A channel layer that extends through the gate stack structure; and A memory layer is disposed between the channel layer and the gate stack structure.

6. The semiconductor memory device according to claim 5, wherein, The second source pattern includes: A horizontal portion extending parallel to the first source pattern of the mesh; and A vertical portion that extends from the horizontal portion toward the central region of the channel layer.

7. The semiconductor memory device according to claim 5, wherein, The first opening does not overlap with the gate stack structure; and The second opening overlaps with the gate stack structure.

8. The semiconductor memory device of claim 7, further comprising: An upper insulating layer is disposed on the gate stack structure; Bit line contact, which penetrates the upper insulating layer and is connected to the channel layer; as well as The bit line is disposed on the upper insulating layer and overlaps with the first opening. The peripheral circuit side pad pattern is connected to the page buffer group; and The contact structure extends through the upper insulating layer and from the pad pattern on the peripheral circuit side toward the bit line.

9. The semiconductor memory device according to claim 8, wherein, The peripheral circuit side pad pattern is made of the same conductive material as the mesh-like first source pattern.

10. The semiconductor memory device of claim 8, further comprising: A first insulating pattern is formed in the first opening to insulate the peripheral circuit side pad pattern from the mesh-like first source pattern. as well as A second insulating pattern that fills the second opening.

11. The semiconductor memory device according to claim 8, wherein, The conductive pattern includes: A source selection line is disposed on the second source pattern; Word lines, which are stacked on the source select lines and spaced apart from each other; and Drain selection lines are provided on the word lines and are spaced apart from each other at the same height. The upper insulating layer extends between the drain selection lines.

12. A semiconductor memory device, the semiconductor memory device comprising: The peripheral circuit structure has a page buffer group; A first source pattern is disposed on the peripheral circuit structure, and the first source pattern has a source contact area and a page buffer connection area; A first opening extends through the first source pattern in the page buffer connection area; A first pad pattern on the peripheral circuit side is disposed in the first opening and is connected to the page buffer group. A second source pattern, which overlaps with the first source pattern in the source contact region; A memory cell array disposed on the second source pattern; A first line, which is disposed on the memory cell array, extends to overlap with the first pad pattern on the peripheral circuit side; as well as A first contact structure extends from the first pad pattern on the peripheral circuit side toward the first bit line.

13. The semiconductor memory device of claim 12, further comprising: A second pad pattern on the peripheral circuit side, which is spaced apart from the first pad pattern on the peripheral circuit side in the first opening, is connected to the page buffer group. An insulating pattern that fills the first opening, wherein the insulating pattern insulates the first pad pattern on the peripheral circuit side, the second pad pattern on the peripheral circuit side, and the first source pattern from each other; The second bit line overlaps with the second pad pattern on the peripheral circuit side, and the second bit line extends parallel to the first bit line; as well as The second contact structure extends from the second pad pattern on the peripheral circuit side toward the second bit line.

14. The semiconductor memory device according to claim 13, wherein, In the plan view, the first pad pattern on the peripheral circuit side and the second pad pattern on the peripheral circuit side are offset and arranged diagonally, and The diagonal is neither parallel to nor perpendicular to the first bit line and the second bit line.

15. The semiconductor memory device according to claim 13, wherein, The page buffer group includes: A first transistor, the first transistor being connected to a first pad pattern on the peripheral circuit side; and The second transistor is connected to the second pad pattern on the peripheral circuit side, and The peripheral circuit structure further includes: A first interconnect, which connects the first pad pattern on the peripheral circuit side to the first transistor; and A second interconnect connects the second pad pattern on the peripheral circuit side to the second transistor.

16. The semiconductor memory device according to claim 12, wherein, The specific resistance of the first source pattern is lower than that of the second source pattern.

17. The semiconductor memory device of claim 16, wherein, The first source pattern includes metal, and The second source pattern includes a doped semiconductor.

18. The semiconductor memory device of claim 12, further comprising a cell array side pad pattern disposed between the first source pattern and the second source pattern, extending from the second source pattern toward the first source pattern, the cell array side pad pattern being directly bonded to the first source pattern in the source contact region.

19. The semiconductor memory device according to claim 18, wherein, Each of the first source pattern and the first pad pattern on the peripheral circuit side includes aluminum, and The pad pattern on the unit array side includes copper.

20. The semiconductor memory device of claim 12, further comprising a plurality of insulating patterns extending through the first source pattern in the source contact region.

21. The semiconductor memory device according to claim 12, wherein, The memory cell array includes: A channel layer connected to the second source pattern, the channel layer extending toward the bit line; A memory layer surrounding the sidewalls of the channel layer; and A gate stack structure surrounding the sidewalls of the memory layer, the gate stack structure having an interlayer insulating layer and a conductive pattern alternately stacked on the second source pattern.

22. The semiconductor memory device of claim 21, wherein, The second source pattern includes: A horizontal portion extending parallel to the first source pattern; and A vertical portion that extends from the horizontal portion toward the central region of the channel layer.

23. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A peripheral circuit structure is formed, the peripheral circuit structure having a page buffer group and interconnects connected to the page buffer group; A metal pattern group is formed on the peripheral circuit structure, the metal pattern group having a first source pattern and a peripheral circuit side pad pattern; A preliminary memory structure, a second source pattern connected to the preliminary memory structure, and a cell array side pad pattern connected to the second source pattern are formed on the substrate. The cell array side pad pattern is bonded to the first source pattern; Remove the substrate; A contact structure is formed that connects to the pad pattern on the peripheral circuit side; as well as A bit line is formed that overlaps with the peripheral circuit structure, and the second source pattern is inserted between the bit line and the peripheral circuit structure, the bit line being connected to the contact structure.

24. The method according to claim 23, wherein, The page buffer group includes transistors, and The peripheral circuit side pad pattern is connected to the transistor via the interconnect.

25. The method according to claim 23, wherein, The first source pattern is a mesh pierced by a first insulating pattern and multiple second insulating patterns, and The peripheral circuit side pad pattern is embedded in the first insulating pattern.

26. The method according to claim 23, wherein, The preliminary memory structure includes: A selective gate layer is formed on the substrate; A preliminary gate stack structure having an interlayer insulating layer and a conductive pattern alternately stacked on the selected gate layer; A channel layer that penetrates the initial gate stack and the select gate layer, extending into the substrate; and A memory layer is disposed between the channel layer and the initial gate stack structure, and extends between the channel layer and the substrate.

27. The method according to claim 26, wherein, The second source pattern is connected to the channel layer and overlaps with the initial gate stack structure.

28. The method according to claim 26, wherein, The step of bonding the cell array side pad pattern to the first source pattern includes aligning the initial gate stack structure and the second source pattern to avoid overlapping with the peripheral circuit side pad pattern.

29. The method of claim 26, further comprising the step of: After removing the substrate, the select gate layer is etched to separate the select gate layer into a drain select line; The space between the drain select lines is filled with an upper insulating layer, which covers the drain select lines and the memory layer; as well as A bit line contact is formed that extends through the upper insulating layer and the memory layer, and the bit line contact is connected to the channel layer.

30. The method according to claim 29, wherein, The bit line is connected to the bit line contact and is formed on the upper insulating layer.

31. The method according to claim 29, wherein, The contact structure penetrates the upper insulating layer.

32. The method according to claim 23, wherein, The resistivity of the metal pattern group is lower than that of the second source pattern.

33. The method according to claim 23, wherein, The metal pattern set includes aluminum, and The second source pattern includes a doped semiconductor.

34. The method according to claim 23, wherein, The metal pattern set includes aluminum, and The pad pattern on the unit array side includes copper.

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