Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate including device regions and isolation regions located between adjacent device regions; forming fins on the substrate of the device regions; forming a dummy gate layer across the fins on the substrate of the device regions, the dummy gate layer covering a portion of the top and sidewalls of the fins; the substrate of the isolation region and the dummy gate layers located on both sides of the isolation region forming a trench; forming a stress buffer layer on the sidewalls of the trench; forming a dielectric isolation structure within the trench after forming the stress buffer layer; and removing the dummy gate layer after forming the dielectric isolation structure. The stress buffer layer blocks the path for high stress generated by the dielectric isolation structure to be released into the dummy gate layer, thereby reducing the probability of grain boundaries being generated in the dummy gate layer due to stress release paths. Simultaneously, it reduces the probability of the dielectric isolation layer diffusing into the dummy gate layer and forming protrusions due to deformation, thus facilitating the subsequent clean removal of the dummy gate layer and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, semiconductor manufacturing processes continue to scale down the size of semiconductor devices. To better accommodate the reduction in feature size, semiconductor processes are gradually transitioning from planar MOSFETs to more efficient three-dimensional transistors, for example, from planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs.

[0003] In the fabrication of fin field-effect transistors, the formation of the dummy gate layer typically uses two masks. The first mask is used to form the initial dummy gate layer after the dummy gate material is deposited. The second mask is used to cut the initial dummy gate layer, thereby dividing it into multiple dummy gate layers. Compared to using a single mask to form the dummy gate layer, using a dual-mask process makes it easier to obtain a rectangular dummy gate layer profile (i.e., the ends of the cut dummy gate layer are closer to lines than arcs), thus allowing for better control over the dummy gate layer pattern. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a device region and an isolation region located between adjacent device regions; a fin located on the substrate of the device region; a gate layer located on the substrate of the device region and spanning the fin, the gate layer covering a portion of the top and a portion of the sidewalls of the fin; a dielectric isolation structure located on the substrate of the isolation region between adjacent gate layers; and a stress buffer layer located between the sidewalls of the dielectric isolation structure and the sidewalls of the gate layer.

[0006] Optionally, the substrate of the isolation region and the gate layers located on both sides of the isolation region form a trench; the stress buffer layer is located on the sidewall of the trench; the dielectric isolation structure covers the sidewall of the stress buffer layer, and the dielectric isolation structure in the trench forms an opening; the semiconductor structure further includes: a stress sharing layer located in the opening.

[0007] Optionally, the gate layer may include a dummy gate layer or a metal gate layer.

[0008] Optionally, the stress buffer layer may be made of one or more of silicon oxide, boron-doped silicon oxide, and nitrogen-doped silicon oxide.

[0009] Optionally, the thickness of the stress buffer layer is 2 nm to 5 nm.

[0010] Optionally, the material of the dielectric isolation structure includes SiN.

[0011] Optionally, the stress-sharing layer may be made of SiO2.

[0012] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including a device region and an isolation region located between adjacent device regions, wherein a fin is formed on the substrate of the device region, and a dummy gate layer spanning the fin is also formed on the substrate of the device region, the dummy gate layer covering a portion of the top and a portion of the sidewalls of the fin, and the substrate of the isolation region and the dummy gate layers located on both sides of the isolation region forming a trench; forming a stress buffer layer on the sidewalls of the trench; forming the stress buffer layer, and then forming a dielectric isolation structure within the trench; and finally removing the dummy gate layer after forming the dielectric isolation structure.

[0013] Optionally, the step of forming the dielectric isolation structure includes: forming dielectric material layers at the bottom and sidewalls of the trench, with the dielectric material layers on opposite sidewalls of the trench in contact with each other.

[0014] Optionally, the step of forming the dielectric isolation structure includes: forming a dielectric material layer at the bottom and sidewalls of the trench, wherein the dielectric material layer in the trench forms an opening; after forming the dielectric isolation structure, the forming method further includes: filling the opening with a stress-sharing layer.

[0015] Optionally, in the step of forming a stress buffer layer on the sidewall of the trench, the stress buffer layer covers the bottom and sidewall of the trench, as well as the top of the dummy gate layer; in the step of forming a dielectric isolation structure in the trench, the dielectric isolation structure covers the stress buffer layer; before removing the dummy gate layer, the forming method further includes: performing a planarization process to remove the dielectric isolation structure and stress buffer layer above the top of the dummy gate layer, exposing the top of the dummy gate layer.

[0016] Optionally, the method for removing the dummy gate layer includes: using a dry etching process to remove a portion of the dummy gate layer; and after the dry etching process, using a wet etching process to remove the remaining thickness of the dummy gate layer.

[0017] Optionally, the steps of forming the dummy gate layer and the trench include: forming an initial dummy gate layer on the substrate of the device region and the isolation region, the initial dummy gate layer spanning the fin and covering a portion of the top and a portion of the sidewalls of the fin; etching the initial dummy gate layer of the isolation region to form a trench in the initial dummy gate layer, the trench dividing the initial dummy gate layer into multiple dummy gate layers along the extending direction of the initial dummy gate layer.

[0018] Optionally, the stress buffer layer may be formed using an atomic layer deposition process.

[0019] Optionally, the stress buffer layer may be made of one or more of silicon oxide, boron-doped silicon oxide, and nitrogen-doped silicon oxide.

[0020] Optionally, the material of the pseudo-gate layer includes one or both of amorphous silicon and polycrystalline silicon.

[0021] Optionally, the dielectric isolation structure may be formed using a plasma-enhanced atomic layer deposition process.

[0022] Optionally, the material of the dielectric isolation structure includes SiN.

[0023] Optionally, the stress-sharing layer may be formed using a flowable chemical vapor deposition process.

[0024] Optionally, the stress-sharing layer may be made of SiO2.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0026] In the semiconductor structure provided by this invention, a stress buffer layer is provided between the sidewall of the dielectric isolation structure and the sidewall of the gate layer. During the formation of the semiconductor structure, a dummy gate layer is usually formed at the position of the gate layer. The stress buffer layer can alleviate the stress of the dielectric isolation structure and block the path of the high stress generated by the dielectric isolation structure to be released into the dummy gate layer, thereby reducing the probability of grain boundaries being generated in the dummy gate layer due to the stress release path of the dielectric isolation structure. This improves the local polycrystalline problem of the dummy gate layer, making it easier to remove the dummy gate layer during the formation of the semiconductor structure. At the same time, it reduces the probability that the dielectric isolation structure will diffuse into the dummy gate layer and form protrusions due to deformation, thereby reducing the probability that the protrusions will block the removal of the dummy gate layer.

[0027] In the formation method provided by this embodiment of the invention, the substrate of the isolation region and the dummy gate layers located on both sides of the isolation region form a trench. After forming a stress buffer layer on the sidewall of the trench, a dielectric isolation structure is formed in the trench. Due to the presence of the stress buffer layer, the stress buffer layer can alleviate the stress of the dielectric isolation structure, and the stress buffer layer blocks the path of the high stress generated by the dielectric isolation structure to be released into the dummy gate layer, thereby reducing the probability of grain boundaries being generated in the dummy gate layer due to the stress release path of the dielectric isolation structure. This improves the local polycrystalline problem of the dummy gate layer, making it easier to remove the dummy gate layer in the future. At the same time, it reduces the probability that the dielectric isolation structure will diffuse into the dummy gate layer due to deformation and form protrusions. This reduces the probability that the protrusions will block the removal of the dummy gate layer in the future. In summary, by forming a stress buffer layer, it is beneficial to remove the dummy gate layer cleanly in the future, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0028] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0029] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 6 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0031] refer to Figures 1 to 4 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0032] refer to Figure 1 A substrate 10 is provided, the substrate 10 including a device region (not shown) and an isolation region (not shown) located between adjacent device regions. A fin 20 is formed on the substrate of the device region, and a pseudo gate layer 21 is also formed on the substrate 10 of the device region, spanning the fin 20. The pseudo gate layer 21 covers part of the top and part of the sidewalls of the fin 20. The substrate 10 of the isolation region and the pseudo gate layer 21 located on both sides of the isolation region form a trench 40. A mask layer 30 is formed on the top of the pseudo gate layer 21. The mask layer 30 is a stack, including a silicon nitride layer 31 and a silicon oxide layer 32.

[0033] refer to Figure 2 A dielectric isolation structure 50 is formed at the bottom and sidewalls of the trench 40. The dielectric isolation structures 50 located on opposite sidewalls of the trench are in partial contact, and the bottom and sidewalls of the dielectric isolation structures 50 form an opening 51.

[0034] refer to Figure 3 A stress-sharing layer 52 is formed in the opening 51.

[0035] refer to Figure 4 Remove the pseudo-gate layer 21.

[0036] Research has revealed that when the dielectric isolation structure 50 is formed in the trench 40, the dielectric isolation structure 50 generates high stress. This stress seeks a release channel at the interface between the dielectric isolation structure 50 and the dummy gate layer 21. However, the bonding between the grain boundaries of the dummy gate layer 21 material on both sides of the dielectric isolation structure 50 is relatively weak. As a result, the stress release path generates grain boundaries in the dummy gate layer 21, leading to local polycrystalline formation of the dummy gate layer 21 material. This, in turn, makes it difficult to remove the dummy gate layer 21 in the future.

[0037] Simultaneously, due to the formation of the stress release path, the dielectric isolation structure 50 will deform, thereby forming a protrusion 23 in the dummy gate layer 21 through the interface between the dielectric isolation structure 50 and the dummy gate layer 21. When the protrusion 23 is formed in the dummy gate layer 21 between the dielectric isolation structure 50 and the fin 20, as the device feature size continues to shrink, the distance between the fin 20 and the sidewall of the trench 40 gradually decreases. The protrusion 23 between the dielectric isolation structure 50 and the fin 20 greatly hinders the removal of the dummy gate layer 21, resulting in the presence of residue 24 of the dummy gate layer 21 after removal. This has a significant impact on the performance of the semiconductor structure and, in severe cases, can affect the normal operation of the semiconductor device.

[0038] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate including a device region and an isolation region located between adjacent device regions; forming a fin on the substrate of the device region; further forming a dummy gate layer spanning the fin on the substrate of the device region; the dummy gate layer covering a portion of the top and a portion of the sidewalls of the fin; the substrate of the isolation region and the dummy gate layers located on both sides of the isolation region forming a trench; forming a stress buffer layer on the sidewalls of the trench; forming a dielectric isolation structure within the trench after forming the stress buffer layer; and removing the dummy gate layer after forming the dielectric isolation structure.

[0039] In the formation method provided by this embodiment of the invention, the substrate of the isolation region and the dummy gate layers located on both sides of the isolation region form a trench. After forming a stress buffer layer on the sidewall of the trench, a dielectric isolation structure is formed in the trench. Due to the presence of the stress buffer layer, the stress buffer layer can alleviate the stress of the dielectric isolation structure, and the stress buffer layer blocks the path for the high stress generated by the dielectric isolation structure to be released into the dummy gate layer, thereby reducing the probability of grain boundaries being generated in the dummy gate layer due to the stress release path of the dielectric isolation structure. This improves the local polycrystalline problem of the dummy gate layer, facilitating the subsequent removal of the dummy gate layer. At the same time, it reduces the probability that the dielectric isolation structure will diffuse into the dummy gate layer due to deformation and form protrusions, thereby reducing the probability that the protrusions will obstruct the removal of the dummy gate layer during subsequent removal. In summary, by forming a stress buffer layer, it is beneficial to remove the dummy gate layer cleanly, thereby improving the performance of the semiconductor structure. To make the above-mentioned objects, features and advantages of this embodiment of the invention more apparent and understandable, specific embodiments of the invention will be described in detail below with reference to the accompanying drawings.

[0040] refer to Figure 5 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0041] The semiconductor structure includes: a substrate 101 including a device region 101L and an isolation region 101M located between adjacent device regions 101L; a fin 201 located on the substrate 101 of the device region 101L; a gate layer 221 located on the substrate 101 of the device region 101L and spanning the fin 201, the gate layer 221 covering a portion of the top and a portion of the sidewalls of the fin 201; a dielectric isolation structure 511 located on the substrate 101 of the isolation region 101M between adjacent gate layers 221; and a stress buffer layer 501 located between the sidewalls of the dielectric isolation structure 511 and the sidewalls of the gate layer 221.

[0042] During the formation of the semiconductor structure, a dummy gate layer is typically formed at the location of the gate layer 221. Since a stress buffer layer 501 exists between the sidewall of the dielectric isolation structure 511 and the sidewall of the gate layer 221, the stress buffer layer 501 can alleviate the stress of the dielectric isolation structure 511. Furthermore, the stress buffer layer 501 blocks the path for the high stress generated by the dielectric isolation structure 511 to be released into the dummy gate layer, thereby reducing the probability of grain boundaries forming in the dummy gate layer due to the stress release path of the dielectric isolation structure 511. This improves the local polycrystalline problem of the dummy gate layer, facilitating its removal during the formation of the semiconductor structure. Simultaneously, it reduces the probability of the dielectric isolation structure 511 diffusing into the dummy gate layer and forming protrusions due to deformation, thus reducing the probability of these protrusions obstructing the removal of the dummy gate layer. In summary, by forming the stress buffer layer 501, it is beneficial to thoroughly remove the dummy gate layer subsequently, thereby improving the performance of the semiconductor structure.

[0043] The substrate 101 provides the basis for the process operation of forming the semiconductor structure.

[0044] In this embodiment, the substrate 101 is made of silicon. In other embodiments, the substrate 101 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate 101 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 101 may be a material suitable for process requirements or easy to integrate.

[0045] In this embodiment, the substrate 101 includes the device region 101L and the isolation region 101M.

[0046] The fin 201 is located on the device region 101L of the substrate 101 and is used to form a fin field-effect transistor.

[0047] In this embodiment, the fin 201 and the substrate 101 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate 101, thereby achieving precise control over the height of the fin 201.

[0048] In this embodiment, the material of the fin 201 is the same as the material of the substrate 101, and the material of the fin 201 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin 201 may also be different from the material of the substrate 101.

[0049] In this embodiment, the gate layer 221 is a metal gate layer formed after removing the dummy gate layer.

[0050] The gate layer 221 is made of metal, including one or more of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.

[0051] In other embodiments, the gate layer may also be a pseudo-gate layer.

[0052] In this embodiment, the substrate 101 of the isolation region and the gate layer 221 located on both sides of the isolation region form a trench (not shown).

[0053] The trench is used to provide space for the formation of the dielectric isolation structure 511.

[0054] Accordingly, in this embodiment, the stress buffer layer 501 is located on the sidewall of the trench.

[0055] Specifically, the stress buffer layer 501 is also located at the bottom of the trench.

[0056] The stress buffer layer 501 is made of one or more of silicon oxide, boron-doped silicon oxide, and nitrogen-doped silicon oxide. In this embodiment, the stress buffer layer 501 is made of silicon oxide.

[0057] The stress buffer layer 501 is made of a chemically stable material that generates relatively low stress during molding.

[0058] Silicon oxide is chemically stable and inert, and generates relatively low stress, which can effectively alleviate the stress generated by the dielectric isolation structure and inhibit the deformation of the dielectric isolation structure to form protrusions.

[0059] In this embodiment, the thickness of the stress buffer layer 501 is 2 nm to 5 nm. For example, the thickness of the stress buffer layer 501 is 3 nm or 4 nm.

[0060] The thickness of the stress buffer layer 501 should not be too small or too large. If the thickness of the stress buffer layer 501 is too small, its stress relief effect will be weakened; if the thickness of the stress buffer layer 501 is too large, it will occupy too much space in the trench 400, thereby increasing the difficulty of forming the dielectric isolation structure in the trench, and also increasing unnecessary costs and the deposition difficulty of the stress buffer layer 501.

[0061] The dielectric isolation structure 511 is used to insulate the gate layers 221 from each other and also to provide a process platform for forming the gate layers 221.

[0062] The dielectric isolation structure 511 is made of a material with high hardness and density, which reduces the probability of the dielectric isolation structure 511 being damaged during the formation of the semiconductor structure, thereby ensuring the isolation performance of the dielectric isolation structure 511.

[0063] For example, during the formation of the semiconductor structure, after the metal gate layer is formed, a portion of the metal gate layer may be removed according to process requirements. By making the material of the dielectric isolation structure 511 have high hardness and density, the probability of the dielectric isolation structure 511 being damaged during the removal of the metal gate layer can be effectively reduced, thereby improving the integrity of the dielectric isolation structure 511.

[0064] Therefore, the dielectric isolation structure 511 is made of SiN. In this embodiment, the dielectric isolation structure 511 is made of SiN. In other embodiments, the dielectric isolation structure may also be other N-containing dielectric isolation structures.

[0065] In this embodiment, the dielectric isolation structure 511 covers the sidewall of the stress buffer layer 501, and the dielectric isolation structure 511 in the trench forms an opening.

[0066] In this embodiment, the semiconductor structure further includes a stress-sharing layer 531 located in the opening.

[0067] The presence of the stress-sharing layer 531 eliminates the need for the dielectric isolation structure 511 to completely fill the trench, thereby reducing the thickness of the dielectric isolation structure 511 and alleviating the stress generated by the dielectric isolation structure 511.

[0068] The stress generated by the stress-sharing layer 531 is less than the stress generated by the dielectric isolation structure 511, and the material of the stress-sharing layer 531 includes SiO2. In this embodiment, the material of the stress-sharing layer 531 is SiO2. In other embodiments, the material of the stress-sharing layer may also be a material whose stress during molding is less than the stress during molding of the dielectric isolation structure.

[0069] It should be noted that in other embodiments, the dielectric isolation structure is filled between the adjacent gate layers, that is, the dielectric isolation structure is filled in the trench, and correspondingly, the semiconductor structure does not contain the stress sharing layer.

[0070] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure. Figures 6 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0071] refer to Figure 6A substrate 100 is provided, including a device region 100L and an isolation region 100M located between adjacent device regions. A fin 200 is formed on the substrate 100 of the device region. A pseudo gate layer 210 is also formed on the substrate 100 of the device region 100L, spanning the fin 200. The pseudo gate layer 210 covers part of the top and part of the sidewalls of the fin 200. The substrate 100 of the isolation region 100M and the pseudo gate layers 210 located on both sides of the isolation region form a trench 400.

[0072] The substrate 100 provides the basis for subsequent process operations.

[0073] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0074] In this embodiment, the substrate 100 includes the device region 100L and the isolation region 100M.

[0075] The fin 200 is located on the device region of the substrate 100 and is used in subsequent processes to form a fin field-effect transistor.

[0076] In this embodiment, the fin 200 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate 100, thereby achieving precise control over the height of the fin 200.

[0077] In this embodiment, the material of the fin 200 is the same as the material of the substrate 100, and the material of the fin 200 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin 200 may also be different from the material of the substrate 100.

[0078] The pseudo-gate layer 210 occupies space for the metal gate layer formed in subsequent processes.

[0079] In this embodiment, the pseudo-gate layer 210 is formed using a chemical vapor deposition process.

[0080] The dummy gate layer 210 can be a single-layer structure or a stacked structure, and the material of the dummy gate layer 210 includes one or both of amorphous silicon and polycrystalline silicon. In other embodiments, the material of the dummy gate layer can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or amorphous carbon.

[0081] In this embodiment, the dummy gate layer 210 is a single-layer structure, and the material of the dummy gate layer 210 is amorphous silicon. Amorphous silicon does not have a crystal orientation; therefore, the etching rate uniformity and etching effect of amorphous silicon are better, thereby improving the subsequent removal effect of the dummy gate layer 210.

[0082] It should be noted that, depending on process requirements, a gate oxide layer (not shown) may also be formed between the dummy gate layer 210 and the fin 200. The material of the gate oxide layer may be silicon oxide.

[0083] A mask layer 300 is also formed on the pseudo gate layer 210.

[0084] The mask layer 300 serves as an etching mask during the formation of the trench 400.

[0085] In this embodiment, the mask layer 300 is a non-metallic mask layer, and the material of the mask layer 300 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 300 can be a single-layer structure or a multilayer structure. As an example, the material of the mask layer 300 is silicon oxide and silicon nitride, that is, the mask layer 300 is a multilayer structure, including a silicon nitride layer 310 and a silicon oxide layer 320 covering the silicon nitride layer 310.

[0086] Specifically, the mask layer 300 is formed on the pseudo gate layer 210 using a chemical vapor deposition process.

[0087] The isolation region 100M serves as a cut region, defining the break position of the pseudo-gate layer 210 along its extension direction, thereby obtaining multiple discrete pseudo-gate layers 210. In other words, transistors formed on the same device region share the same pseudo-gate layer 210 along its extension direction.

[0088] The bottom of the trench 400 exposes the substrate 100 of the isolation region 100M, and the trench 400 also provides space for the subsequent formation of a dielectric isolation structure. Specifically, the steps of forming the dummy gate layer 210 and the trench 400 include: forming an initial dummy gate layer on the substrate of the device region 100L and the isolation region 100M, the initial dummy gate layer spanning the fin 200 and covering part of the top and part of the sidewalls of the fin 200; etching the initial dummy gate layer of the isolation region 100M, forming the trench 400 in the initial dummy gate layer, and dividing the initial dummy gate layer into a plurality of dummy gate layers 210 along the extension direction of the initial dummy gate layer.

[0089] Etching with the patterned mask layer 300 as a mask can better control the pattern morphology of the interconnect trench 400, making the sidewalls of the trench 400 smoother.

[0090] In this embodiment, the initial pseudo-gate layer is etched using an anisotropic dry etching process to form the trench 400.

[0091] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the substrate 100 at the bottom of the trench 400. At the same time, the dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the trench 400.

[0092] In this embodiment, the dry etching process is an inductively coupled plasma (ICP) etching process.

[0093] In this embodiment, the parameters of the inductively coupled plasma etching process include: high-frequency power of 300W to 800W and low-frequency power of 500W to 1000W.

[0094] It should be noted that after the groove 400 is formed, the groove 400 can also be subjected to a wet cleaning process.

[0095] The wet cleaning process helps to remove the residue generated during the formation of the trench 400, thereby providing a good interface foundation for the subsequent process to form the dielectric isolation structure, and thus improving the formation quality of the dielectric isolation structure.

[0096] In this embodiment, the solution used in the wet cleaning process includes a mixed solution of HF (hydrofluoric acid), HPM (sulfuric acid cleaning solution), and SC1 (standard cleaning solution 1).

[0097] HF solution is a mixture of hydrofluoric acid and water, with a molar ratio of water to hydrofluoric acid of 90:1 to 110:1, and a solution temperature of 23°C to 27°C. It is used to remove residual polymers and impurities. HPM solution is a mixture of sulfuric acid and hydrogen peroxide, with a ratio of sulfuric acid to hydrogen peroxide of 5:1 to 8:1, and a solution temperature of 110°C to 130°C. It is used to further remove residual organic matter and impurities. SC1 solution is a mixture of ammonia, hydrogen peroxide, and water, with a ratio of ammonia, hydrogen peroxide, and water of 1:2:40 to 1:3:60, and a solution temperature of 40°C to 70°C. It is used to remove residual particulate polymers and particulate impurities.

[0098] refer to Figure 7 A stress buffer layer 500 is formed on the sidewall of the trench 400.

[0099] After forming a stress buffer layer 500 on the sidewall of the trench 400, a dielectric isolation structure is subsequently formed within the trench 400. Due to the presence of the stress buffer layer 500, the stress buffer layer 500 can alleviate the stress of the dielectric isolation structure, and the stress buffer layer 500 blocks the path for the high stress generated by the dielectric isolation structure to be released into the dummy gate layer 210, thereby reducing the probability of grain boundaries being generated in the dummy gate layer 210 due to the stress release path of the dielectric isolation structure. This improves the local polycrystalline problem of the dummy gate layer 210, making it easier to remove the dummy gate layer 210 later. At the same time, it reduces the probability that the dielectric isolation structure will diffuse into the dummy gate layer 210 due to deformation and form protrusions, thereby reducing the probability that the protrusions will obstruct the removal of the dummy gate layer 210 later. In summary, by forming a stress buffer layer 500, it is beneficial to remove the dummy gate layer 210 cleanly, thereby improving the performance of the semiconductor structure.

[0100] In this embodiment, the stress buffer layer 500 covers the bottom and sidewalls of the trench 400 and the top of the pseudo-gate layer 210.

[0101] In this embodiment, the stress buffer layer 500 is formed using atomic layer deposition (ALD) process.

[0102] The atomic layer deposition (ALD) process is a method that achieves nanoscale ultrathin film deposition by alternately pulsed introduction of a gaseous precursor into a reactor, where it is chemically adsorbed onto the substrate and reacts to form a deposited film. Because ALD utilizes the properties of saturated chemisorption, it can ensure highly conformal and uniform deposition on large-area, porous, tubular, powder, or other complex-shaped substrates.

[0103] In this embodiment, the precursor for the atomic layer deposition process is bis(diethylamino)silane, the reaction gas is oxygen, and the inert gas is argon.

[0104] The atomic layer deposition process includes multiple cyclic deposition steps, which include: introducing a precursor bis(diethylamino)silane into a deposition chamber, followed by the introduction of a reactive gas, oxygen, and then an inert gas, argon, to stimulate the reaction between the oxygen and the precursor bis(diethylamino)silane. Both the precursor and argon are introduced in a pulsed manner.

[0105] Specifically, in this embodiment, the parameters of the atomic layer deposition process include: a precursor flow rate of 300 standard mL / min to 500 standard mL / min, an oxygen flow rate of 400 standard mL / min to 600 standard mL / min, an argon flow rate of 1 standard mL / min to 5 standard mL / min, a source power of 30 W to 50 W, a frequency of 12 MHz to 14 MHz (e.g., 13.56 MHz), a process pressure of 400 mTorr to 750 mTorr, a process temperature of 80 °C to 200 °C, a precursor bis(diethylamino)silane introduction time of 0.1 s to 0.3 s, and an argon excitation time of 0.1 s to 0.3 s after oxygen introduction.

[0106] The stress buffer layer 500 is made of one or more of silicon oxide, boron-doped silicon oxide, and nitrogen-doped silicon oxide. In this embodiment, the stress buffer layer 500 is made of silicon oxide.

[0107] The stress buffer layer 500 is made of a chemically stable material that generates relatively low stress during molding.

[0108] Silicon oxide is chemically stable and inert, and generates relatively low stress. It can effectively alleviate the stress generated by the dielectric isolation structure in subsequent processes, and inhibit the deformation of the dielectric isolation structure to form protrusions.

[0109] In this embodiment, the thickness of the stress buffer layer 500 is 2 nm to 5 nm. For example, the thickness of the stress buffer layer 500 is 3 nm or 4 nm.

[0110] The thickness of the stress buffer layer 500 should not be too small or too large. If the thickness of the stress buffer layer 500 is too small, it will weaken the stress relief effect of the stress buffer layer 500 in subsequent processes; if the thickness of the stress buffer layer 500 is too large, it will occupy too much space in the trench 400, thereby increasing the difficulty of forming the subsequent dielectric isolation structure in the trench 400, and will also increase unnecessary costs and the deposition difficulty of the stress buffer layer 500.

[0111] refer to Figure 8 After forming the stress buffer layer 500, in the trench 400 (e.g. Figure 6 A dielectric isolation structure 510 is formed inside (as shown).

[0112] The dielectric isolation structure 510 is used to insulate the metal gate layers that are subsequently formed from each other, and also to provide a process platform for the subsequent formation of metal gate layers.

[0113] In this embodiment, the step of forming the dielectric isolation structure 510 includes: forming a dielectric material layer at the bottom and sidewall of the trench 400, and the dielectric material layer in the trench 400 forming an opening 520.

[0114] Specifically, the dielectric material layer located on the sidewalls and bottom of the trench 400 forms an opening 520.

[0115] The opening 520 is used to provide space for the subsequent formation of the stress-sharing layer.

[0116] Therefore, in this embodiment, it is not necessary to completely fill the trench 400 with the dielectric isolation structure 510, thereby appropriately reducing the thickness of the dielectric isolation structure 510 and thus reducing the stress generated by the dielectric isolation structure 510.

[0117] In this embodiment, the dielectric isolation structure 510 is formed using a plasma-enhanced atomic deposition (PEALD) process.

[0118] The plasma-enhanced atomic deposition process described above is simple to prepare, has a low reaction temperature and low energy consumption, and the forming thickness is controllable. Compared with the traditional atomic deposition process, the deposition speed is faster.

[0119] In this embodiment, during the step of forming a dielectric isolation structure 510 within the trench 400, the dielectric isolation structure 510 covers the stress buffer layer 500.

[0120] The dielectric isolation structure 510 is made of a material with high hardness and density, which reduces the probability of damage to the dielectric isolation structure 510 in subsequent processes, thereby ensuring the isolation performance of the dielectric isolation structure 510.

[0121] For example, after removing the dummy gate layer 210 and forming a metal gate layer at the location of the dummy gate layer 210, depending on the process requirements, some areas of the metal gate layer may also be removed. By making the material of the dielectric isolation structure 510 have high hardness and density, the probability of the dielectric isolation structure 510 being damaged during the removal of the metal gate layer can be effectively reduced, thereby improving the integrity of the dielectric isolation structure 510.

[0122] Therefore, the dielectric isolation structure 510 is made of SiN. In this embodiment, the dielectric isolation structure 510 is made of SiN. In other embodiments, the dielectric isolation structure may also be other N-containing dielectric isolation structures.

[0123] refer to Figure 9 After forming the dielectric isolation structure 510, the method further includes: in the opening 520 (e.g. Figure 8 (As shown) is filled with a stress-sharing layer 530.

[0124] When the dielectric isolation structure 510 is formed, high stress will be generated. Since the stacked structure formed by the stress sharing layer 530 and the dielectric isolation structure 510 is used to fill the trench 400, the thickness of the dielectric isolation structure 510 can be reduced by forming the stress sharing layer 530, thereby alleviating the stress generated by the dielectric isolation structure 510.

[0125] In this embodiment, the stress-sharing layer is formed using a flowable chemical vapor deposition (FCVD) process.

[0126] Flowable chemical vapor deposition (FCVD) technology has good deposition effect, high gap filling ability, can form high-quality film structure, and can reduce the porosity in the film.

[0127] Specifically, in this embodiment, the parameters of the flowable chemical vapor deposition (FCVD) process include: a deposition temperature of 450°C to 650°C and a deposition time of 8 to 12 hours. In this embodiment, the deposition temperature is 500°C and the deposition time is 12.5 hours.

[0128] The stress generated by the stress-sharing layer 530 is less than the stress generated by the dielectric isolation structure 510, and the material of the stress-sharing layer 530 includes SiO2. In this embodiment, the material of the stress-sharing layer 530 is SiO2. In other embodiments, the material of the stress-sharing layer may also be a material whose stress during molding is less than the stress during molding of the dielectric isolation structure.

[0129] It should be noted that this embodiment is illustrated using the example where the dielectric isolation structure 510 does not completely fill the trench 400. In other embodiments, the dielectric isolation structure can also completely fill the trench, thus omitting the step of forming a stress-sharing layer. Specifically, the step of forming the dielectric isolation structure includes: forming dielectric material layers at the bottom and sidewalls of the trench, with the dielectric material layers on opposite sidewalls of the trench in contact with each other. The contact of the dielectric material layers on opposite sidewalls of the trench achieves trench filling.

[0130] refer to Figure 10 After forming the dielectric isolation structure 510 and the stress sharing layer 530, the method further includes: performing planarization processing to remove the dielectric isolation structure 510 and the stress buffer layer 500 that are higher than the top of the pseudo gate layer 210, thereby exposing the top of the pseudo gate layer 210.

[0131] By exposing the top of the pseudo-gate layer 210, preparation is made for the subsequent removal of the pseudo-gate layer 210.

[0132] In this embodiment, the planarization process is performed using a chemical mechanical polishing process.

[0133] It should be noted that a stress-sharing layer 530 is also formed in the trench 400. Therefore, during the planarization process, the stress-sharing layer 530 above the top of the pseudo-gate layer 210 is also removed.

[0134] Reference Figure 11 and Figure 12 After forming the dielectric isolation structure 510, the pseudo gate layer 210 is removed.

[0135] The dummy gate layer 210 is removed to provide space for the subsequent formation of the metal gate layer.

[0136] In this embodiment, the dummy gate layer 210 is removed through two etching steps. The steps for removing the dummy gate layer 210 are described in detail below with reference to the accompanying drawings.

[0137] Specifically, refer to Figure 11 The dummy gate layer 210 with a high thickness is removed by using a dry etching process.

[0138] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the sidewalls of the buffer layer 500. At the same time, the dry etching is more directional, which is beneficial to remove part of the pseudo gate layer 210 in a directional manner.

[0139] Specifically, removing a portion of the thickness of the pseudo-gate layer 210 means removing the pseudo-gate layer 210 that is higher than the top surface of the fin 200.

[0140] The pseudo-gate layer 210, which is higher than the top surface of the fin 200, is exposed on the fin 200 and is easy to remove in one piece, thereby increasing the rate of removing the pseudo-gate layer 210.

[0141] In this embodiment, the dry etching process is an inductively coupled plasma (ICP) etching process.

[0142] In this embodiment, the parameters of the inductively coupled plasma etching process include: high-frequency power of 300W to 800W and low-frequency power of 500W to 1000W.

[0143] refer to Figure 12 After the dry etching process, a wet etching process is used to remove the remaining thickness of the pseudo gate layer 210.

[0144] The wet etching process has the characteristics of isotropic etching, which is beneficial to remove the remaining dummy gate layer 210, thereby providing a good interface foundation for the subsequent process to form the metal gate layer, and thus improving the formation quality of the metal gate layer.

[0145] In particular, as the feature size of the device decreases, the distance between the fin 200 and the stress buffer layer 500 becomes smaller and smaller in the direction perpendicular to the extension direction of the fin 200. By utilizing the isotropic etching characteristics of the wet etching process, and the fact that the etching solution can penetrate between the fin 200 and the buffer layer 500, the remaining pseudo gate layer 210 can be completely removed.

[0146] In this embodiment, the etching solution used in the wet etching process is TMAH (tetramethylammonium hydroxide) solution. TMAH solution does not contain metal ions, is compatible with CMOS processes, and has an etching rate and selectivity similar to KOH (potassium hydroxide), resulting in good etching performance. Furthermore, TMAH solution has a lower etching rate for SiO2 and Si3N4, causing less damage to them and thus reducing damage to the stress buffer layer 500 and the dielectric isolation structure 510. Moreover, TMAH solution is non-toxic, non-polluting, and easy to operate.

[0147] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising device regions and isolation regions between adjacent device regions; a fin on the substrate of the device regions; a gate layer on the substrate of the device regions and across the fin, the gate layer conformally covering part of the top and part of the sidewall of the fin; a dielectric isolation structure on the substrate of the isolation regions between adjacent gate layers; a stress buffer layer between the sidewall of the dielectric isolation structure and the sidewall of the gate layer; the dielectric isolation structure encloses an opening; the semiconductor structure further comprises a stress sharing layer in the opening.

2. The semiconductor structure of claim 1, wherein, the substrate of the isolation region and the gate layers on both sides of the isolation region enclose a trench; the stress buffer layer is on the sidewall of the trench; the dielectric isolation structure covers the sidewall of the stress buffer layer, and the dielectric isolation structure in the trench encloses an opening.

3. The semiconductor structure of claim 1, wherein, The gate layer comprises a dummy gate layer or a metal gate layer.

4. The semiconductor structure of claim 1, wherein, The material of the stress buffer layer comprises one or more of silicon oxide, boron-doped silicon oxide, and nitrogen-doped silicon oxide.

5. The semiconductor structure of claim 1, wherein, The thickness of the stress buffer layer is 2-5 nm.

6. The semiconductor structure of claim 1, wherein, The material of the dielectric isolation structure comprises SiN.

7. The semiconductor structure of claim 1, wherein, The material of the stress sharing layer comprises SiO2.

8. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: a substrate comprising device regions and isolation regions between adjacent device regions, a fin is formed on the substrate of the device regions, a dummy gate layer is also formed on the substrate of the device regions and across the fin, the dummy gate layer conformally covers part of the top and part of the sidewall of the fin, and the substrate of the isolation region and the dummy gate layers on both sides of the isolation region enclose a trench; a stress buffer layer is formed on the sidewall of the trench; after the stress buffer layer is formed, a dielectric isolation structure is formed in the trench; after the dielectric isolation structure is formed, the dummy gate layer is removed; the step of forming the dielectric isolation structure comprises forming a dielectric material layer on the bottom and sidewall of the trench, and the dielectric material layer in the trench encloses an opening; after the dielectric isolation structure is formed, the forming method further comprises filling a stress sharing layer in the opening.

9. The method of forming a semiconductor structure of claim 8, wherein, The step of forming the dielectric isolation structure comprises forming a dielectric material layer on the bottom and sidewall of the trench, and the dielectric material layers on the opposite sidewalls of the trench are in contact.

10. The method of forming a semiconductor structure of claim 8, wherein, In the step of forming the stress buffer layer on the sidewall of the trench, the stress buffer layer covers the bottom and sidewall of the trench, and the top of the dummy gate layer; In the step of forming the dielectric isolation structure in the trench, the dielectric isolation structure covers the stress buffer layer; Before the dummy gate layer is removed, the forming method further comprises performing a planarization process to remove the dielectric isolation structure and the stress buffer layer above the top of the dummy gate layer, and expose the top of the dummy gate layer.

11. The method of forming a semiconductor structure of claim 8, wherein, The method of removing the dummy gate layer comprises using a dry etching process to remove part of the thickness of the dummy gate layer; After the dry etching process, a wet etching process is used to remove the remaining thickness of the dummy gate layer.

12. The method of forming a semiconductor structure of claim 8, wherein, The step of forming the dummy gate layer and the trench comprises forming an initial dummy gate layer on the substrate of the device regions and the isolation regions, the initial dummy gate layer crosses the fin, and covers part of the top and part of the sidewall of the fin; etching an initial dummy gate layer of the isolation region, forming a trench in the initial dummy gate layer, the trench dividing the initial dummy gate layer into a plurality of dummy gate layers along an extension direction of the initial dummy gate layer.

13. The method of forming a semiconductor structure of claim 8, wherein, forming the stress buffer layer using an atomic layer deposition process.

14. The method of forming a semiconductor structure of claim 8, wherein, a material of the stress buffer layer includes one or more of silicon oxide, boron-doped silicon oxide, and nitrogen-doped silicon oxide.

15. The method of forming a semiconductor structure of claim 8, wherein, a material of the dummy gate layer includes one or both of amorphous silicon and polysilicon.

16. The method of forming a semiconductor structure of claim 8, wherein, forming the dielectric isolation structure using a plasma-enhanced atomic layer deposition process.

17. The method of forming a semiconductor structure of claim 8, wherein, a material of the dielectric isolation structure includes SiN.

18. The method of forming a semiconductor structure of claim 8, wherein, forming the stress sharing layer using a flowable chemical vapor deposition process.

19. The method of forming a semiconductor structure of claim 8, wherein, a material of the stress sharing layer includes SiO2.

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