SiC MOSFET Devices and Manufacturing Methods

Abstract

The application discloses a SiC MOSFET device, comprising: a trench gate formed in a SiC epitaxial layer; a first bottom doped region formed under a bottom surface of the gate trench; a second deep doped region formed in the SiC epitaxial layer with a spacing from the gate trench; the first bottom doped region connected to a source; the voltage on the gate dielectric layer of the bottom surface of the gate trench determined by the gate-source voltage, thereby reducing the electric field intensity on the gate dielectric layer of the bottom surface of the gate trench; the second deep doped region extending downward from a top surface of the SiC epitaxial layer, and a bottom surface of the second deep doped region located below a bottom surface of the first bottom doped region; a top of the second deep doped region connected to the source; the first bottom doped region and the second bottom doped region increasing the depletion of the drift region between the first bottom doped region and the second bottom doped region at the bottom of the channel region, thereby reducing the short channel effect. The application discloses a manufacturing method of the SiC MOSFET device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a SiC MOSFET device; this invention also relates to a method for manufacturing a SiC MOSFET device. Background Technology

[0002] Compared to silicon, SiC has a bandgap nearly 10 times wider and a critical breakdown electric field that is also 10 times greater. This means that at the same breakdown voltage, the drift region width of a SiC device is only 1 / 10 that of a Si device, allowing for a 100-fold increase in doping concentration. The drift region resistance of SiC devices is also significantly reduced compared to Si devices. Therefore, it offers substantial advantages in high-voltage applications, such as those with breakdown voltages exceeding 600V. It is increasingly replacing Si-based superjunctions and Si-based IGBT devices in various applications.

[0003] SiC MOSFETs are currently the most likely devices to replace Si-based superjunctions and Si-based IGBTs in the 600V to 3300V range.

[0004] While SiC MOSFETs can theoretically achieve superior performance beforehand, in practice, two key issues need to be addressed: The first key issue is how to reduce the channel resistance: Channel carrier mobility. For Si-based MOSFETs and IGBTs, channel carrier mobility can easily reach 400 cm² / (V*s). However, for SiC devices, due to numerous interface defects between SiC and silicon dioxide, the mobility is only 10 cm² / (V*s) to 15 cm² / (V*s) without optimization. Annealing in a NO environment can partially reduce these interface defects, increasing the mobility to 30 cm² / (V*s) to 40 cm² / (V*s). Furthermore, by utilizing the mobility differences across different crystal orientations of SiC, and selecting an appropriate crystal orientation, the mobility in trench MOSFETs can reach over 70 cm² / (V*s). Unlike Si devices, SiC devices significantly reduce the resistance of the drift region. The channel resistance contributes more to this. The channel resistance is proportional to the channel carrier mobility and the channel length. While optimizations in device structure and manufacturing processes are continuously improving mobility, a significant gap remains compared to silicon devices. Currently, the best design approach to reduce channel resistance is to decrease channel length, which necessitates suppressing the short-channel effect. SiC MOSFETs, due to their higher doping concentration in the drift region, exhibit a more severe short-channel effect than Si-based devices. In other words, the specific on-resistance of a MOSFET device includes both channel resistance and drift region resistance. While using SiC material in the drift region can significantly reduce drift region resistance, SiC also increases channel resistance. Therefore, reducing channel resistance becomes a challenge in reducing the specific on-resistance of the device. Furthermore, overcoming the short-channel effect to further shorten the channel length is crucial for reducing channel resistance.

[0005] The second key issue is how to protect the gate dielectric layer, such as the gate oxide: According to Gauss's law, the electric field strength of the device in the semiconductor and oxide layers conforms to the following formula: .

[0006] in, It is the critical electric field strength of semiconductor devices. and These are the dielectric constants of the semiconductor material and the oxide layer material, respectively. Because the critical electric field strengths of Si and SiC differ by a factor of 10, for Si devices, in their gate dielectric layer (silicon dioxide), regardless of the specific conditions, the electric field strength is unlikely to exceed [a certain value]. For SiC devices, the critical electric field strength is reached at the interface between the SiC and the insulating layer corresponding to the gate dielectric layer, while within the insulating layer such as silicon dioxide, the electric field strength can reach as high as... This has reached or exceeded the critical electric field strength of silicon dioxide. That is, in Si devices, when the electric field strength in the Si material reaches the critical electric field strength, the gate oxide electric field strength remains at a low value; however, in SiC devices, when the electric field strength in the SiC material reaches the critical electric field strength, the gate oxide electric field strength will reach or exceed the critical electric field strength of the gate oxide, causing gate oxide breakdown and resulting in reliability issues. Therefore, for SiC MOSFETs, employing appropriate device structures and design methods to reduce the electric field strength at the gate oxide interface during device breakdown is particularly important for device reliability. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a SiC MOSFET device that can reduce the electric field strength of the gate dielectric layer and simultaneously reduce the short-channel effect. To this end, the present invention also provides a method for manufacturing a SiC MOSFET device.

[0008] To solve the above-mentioned technical problems, the device unit of the SiC MOSFET device provided by the present invention includes: A SiC epitaxial layer doped with a first conductivity type, wherein a trench gate is formed in the SiC epitaxial layer.

[0009] The trench gate includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0010] A first bottom doped region is formed in the SiC epitaxial layer below the bottom surface of the gate trench. The first bottom doped region has a second conductivity type doping. The top surface of the first bottom doped region is in contact with the bottom surface of the gate dielectric layer at the bottom surface of the gate trench.

[0011] A channel region doped with a second conductivity type is formed in the SiC epitaxial layer. The channel region extends downward from the top surface of the SiC epitaxial layer. The gate conductive material layer extends longitudinally through the channel region. The surface of the channel region is covered by the side of the gate conductive material layer to form a conductive channel.

[0012] A second deeply doped region with a second conductivity type doped is formed in the SiC epitaxial layer, and there is a gap between the second deeply doped region and the gate trench.

[0013] A source region consisting of heavily doped regions of a first conductivity type is formed on the surface of the channel region.

[0014] The top of the gate conductive material layer is connected to the gate, which is composed of a front metal layer.

[0015] The top of the source region is connected to the source electrode, which consists of a front metal layer.

[0016] The first bottom doped region is connected to the source, such that the voltage across the gate dielectric layer on the bottom surface of the gate trench is determined by the voltage difference between the source and the gate, thereby reducing the electric field strength across the gate dielectric layer on the bottom surface of the gate trench.

[0017] The second deep doped region extends downward from the top surface of the SiC epitaxial layer, and the bottom surface of the second deep doped region is located below the bottom surface of the first bottom doped region.

[0018] The top of the second deeply doped region is connected to the source electrode.

[0019] The SiC epitaxial layer at the bottom of the channel region forms a drift region.

[0020] The first bottom doped region and the second deep doped region increase the depletion of the drift region located between the first bottom doped region and the second deep doped region at the bottom of the channel region, thereby reducing the depletion between the channel region and the drift region at the bottom and thus reducing the short-channel effect.

[0021] A further improvement is that the SiC epitaxial layer is formed on a SiC substrate, the SiC substrate being heavily doped with a first conductivity type, and the drain region being composed of the thinned SiC substrate or formed by back-side ion implantation of the thinned SiC substrate.

[0022] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0023] When a SiC MOSFET device is in operation, as the drain voltage increases, the drift region at the bottom of the channel region, located between the first bottom doped region and the second deep doped region, will form a pinch-off structure.

[0024] A further improvement is that the depth of the second deep-doped region is greater than the implantation depth of the ion implantation stage.

[0025] The SiC epitaxial layer is composed of multiple SiC epitaxial sublayers stacked together, and the second deep doped region is formed by connecting multiple deep doped sub-regions formed in each of the SiC epitaxial sublayers by ion implantation through doping of the second conductivity type.

[0026] A further improvement is that the device cell region of the SiC MOSFET device is composed of multiple device cells connected in parallel.

[0027] On a top view, the device unit is a strip structure or a polygonal structure.

[0028] The polygonal structure includes squares or hexagons.

[0029] A further improvement is that the SiC epitaxial layer is composed of two SiC epitaxial sublayers stacked together, and the second deep-doped region is composed of two deep-doped sub-regions connected together.

[0030] The second SiC epitaxial sublayer is superimposed on the top surface of the first SiC epitaxial sublayer. The first deeply doped sub-region is formed in the first SiC epitaxial sublayer, and the second deeply doped sub-region is formed in the second SiC epitaxial sublayer and penetrates the second SiC epitaxial sublayer.

[0031] A further improvement is that the device unit has a strip structure, the gate trench is strip-shaped, the channel region is formed on both sides corresponding to the long side of the gate trench, and the second deep doped region is formed on both sides corresponding to the long side of the gate trench.

[0032] A further improvement is that both the first and second deeply doped sub-regions are strip-shaped structures parallel to the gate trench; the second deeply doped sub-region is superimposed on the top surface of the first deeply doped sub-region and is in contact with it.

[0033] A further improvement is that the width of the second deep-doped sub-region is equal to the width of the first deep-doped sub-region.

[0034] Alternatively, the width of the second deeply doped subregion is greater than the width of the first deeply doped subregion to reduce the specific on-resistance of the device.

[0035] Alternatively, the width of the second deep-doped sub-region may be smaller than the width of the first deep-doped sub-region to improve the pinch-off of the channel region.

[0036] A further improvement is that the second deeply doped sub-region has a strip-shaped structure parallel to the gate trench, and the first deeply doped sub-region has a strip-shaped structure perpendicular to the gate trench.

[0037] The bottoms of the first and second deep doped subregions intersect and contact each other laterally.

[0038] The first bottom doped region and the first deep doped subregion are in contact and both are connected to the source through the top of the second deep doped subregion.

[0039] A further improvement is that the arrangement step of the strip structure in the second deeply doped sub-region is independent of the arrangement step of the strip structure in the first deeply doped sub-region.

[0040] A further improvement is that the SiC epitaxial layer has a non-uniform doping concentration, with the doping concentration near the top surface being higher than that near the bottom surface, in order to reduce diffusion resistance and reduce the JFET effect.

[0041] A further improvement is that an anti-JFET injection region is also formed in the drift region between the gate trench at the bottom of the channel region and the second deeply doped region.

[0042] A further improvement is that the anti-JFET implantation region is formed by vertical implantation from the top surface of the SiC epitaxial layer to the bottom of the channel region.

[0043] Alternatively, the anti-JFET injection region is formed by angled injection after the gate trench is formed and before the gate dielectric layer is formed.

[0044] A further improvement is that the SiC MOSFET device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type.

[0045] A further improvement is that the P-type dopant includes aluminum, the N-type dopant includes nitrogen, and the material of the front metal layer includes TiNiAl.

[0046] A further improvement is that the maximum depth of the second deep-doped region is greater than 1.6 micrometers.

[0047] To solve the above-mentioned technical problems, the manufacturing method of the SiC MOSFET device provided by the present invention includes the following step in forming the second deeply doped region: Step 1: Form a first SiC epitaxial sublayer on the SiC substrate.

[0048] Step 2: Define the formation region of the first deep-doped sub-region, and perform ion implantation of the second conductivity type in the first SiC epitaxial sub-layer to form the first deep-doped sub-region.

[0049] Step 3: Form a second SiC epitaxial sublayer on the surface of the first SiC epitaxial sublayer.

[0050] Step 4: Define the formation region of the second deep doped sub-region, and perform ion implantation of the second conductivity type to form the second deep doped sub-region through the second SiC epitaxial sub-layer.

[0051] As needed, repeat the formation process of the second SiC epitaxial sublayer in step three and the formation process of the second deeply doped subregion in step four to form more SiC epitaxial sublayers and deeply doped subregions. The SiC epitaxial layer is formed by stacking the first SiC epitaxial sublayer, the second SiC epitaxial sublayer, and each SiC epitaxial sublayer on top of the second SiC epitaxial sublayer. The second deeply doped region is formed by stacking the first deeply doped subregion, the second deeply doped subregion, and the deeply doped subregion on top of the second deeply doped subregion.

[0052] A further improvement is that, in step two, a first photoresist pattern is formed using photoresist to define the formation region of the first deeply doped sub-region. The first photoresist pattern serves as a mask for ion implantation of the first deeply doped sub-region, and the first photoresist pattern is removed after ion implantation of the first deeply doped sub-region is completed.

[0053] In step four, a second photoresist pattern is formed using photoresist to define the formation region of the second deeply doped sub-region. The second photoresist pattern serves as a mask for ion implantation of the second deeply doped sub-region and is removed after ion implantation of the second deeply doped sub-region is completed.

[0054] Alternatively, in step two, a first hard mask pattern is used to define the formation region of the first deeply doped sub-region. The first hard mask pattern serves as a mask for ion implantation of the first deeply doped sub-region, and the first hard mask pattern is removed after ion implantation of the first deeply doped sub-region is completed.

[0055] In step four, a second hard mask pattern is used to define the formation region of the second deeply doped sub-region. The second hard mask pattern serves as a mask for ion implantation of the second deeply doped sub-region and is removed after ion implantation of the second deeply doped sub-region is completed.

[0056] A further improvement is that the formation process of the trench gate includes: A third hard mask pattern is formed on the surface of the SiC epitaxial layer, which opens the formation region of the gate trench and covers the outside of the formation region of the gate trench.

[0057] The gate trench is formed by etching using the third hard mask pattern as a mask.

[0058] A first bottom doped region is formed at the bottom of the gate trench by performing full ion implantation.

[0059] The gate dielectric layer is formed on the inner surface of the gate trench.

[0060] The gate conductive material layer is filled into the gate trench.

[0061] The gate structure of the SiC MOSFET device of this invention adopts a trench gate, and a first bottom doped region is set at the bottom of the gate trench. The first bottom doped region is connected to the source. Thus, the voltage of the gate dielectric layer at the bottom of the gate trench is determined by the voltage difference between the gate conductive material layer and the source, i.e., the gate-source voltage. The gate-source voltage is a small value greater than the threshold voltage when the device is turned on and is 0V when the device is turned off. Compared with the large gate-drain voltage, this invention can greatly reduce the voltage on the gate dielectric layer at the bottom of the gate trench, so it can reduce the electric field strength of the gate dielectric layer. This can provide good protection for the gate dielectric layer in the interface structure where the gate dielectric layer and the SiC epitaxial layer are in contact, thereby improving the reliability of the device.

[0062] This invention also includes a second deeply doped region in the SiC epitaxial layer, with a spacing between the second deeply doped region and the gate trench. The second deeply doped region is also connected to the source. Both the first bottom doped region and the second deeply doped region are doped with the second conductivity type. This allows the first bottom doped region and the second deeply doped region to increase the depletion of the drift region at the bottom of the channel region, thereby reducing the depletion between the channel region and the bottom drift region and thus reducing the short-channel effect. The reason is that the short-channel effect occurs because when the drift region depletes the channel region, the channel region near the drain experiences a pinch-off effect, causing the drain to be cut off. The length of the channel region is equivalent to the length of the channel region that is not controlled by the gate voltage. The length of the channel region that is pinched off is the length of the channel region that is shortened. In this invention, the first bottom doped region and the second deep doped region can increase the depletion of the drift region at the bottom of the channel region. The depletion of the channel region and the bottom drift region will be reduced. That is, the area of ​​the channel region that is depleted by the bottom drift region becomes smaller. If pinching occurs, the first bottom doped region and the second deep doped region will first pinch off the drift region at the bottom of the channel region. Therefore, the length of the pinched-off area of ​​the channel region can be reduced, thereby reducing the short-channel effect.

[0063] Because this invention can reduce the short-channel effect, it can further shorten the length of the channel region and thus reduce the channel resistance; in addition, the drift region composed of SiC epitaxial layer can greatly reduce the drift region resistance of the device, and finally further reduce the specific on-resistance of the device. Attached Figure Description

[0064] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic cross-sectional view of the device unit of the SiC MOSFET device according to the first embodiment of the present invention; Figure 2 This is the layout of the second deeply doped region of the SiC MOSFET device according to the first embodiment of the present invention; Figure 3 yes Figure 1A schematic diagram showing the location of the pinch-off structure formed by the first bottom doped region and the second deep doped region in the drift region of the structure shown. Figure 4 yes Figure 1 A schematic diagram showing the location of the JFET-resistant injection region formed in the structure shown; Figure 5 This is a layout of the first bottom doped region and the second deep doped region of the SiC MOSFET device according to the second embodiment of the present invention; Figure 6A It is along Figure 5 A cross-sectional view of the device unit of the SiC MOSFET device of the second embodiment of the present invention with the AA line in the middle. Figure 6B It is along Figure 5 A cross-sectional view of the device unit of the SiC MOSFET device of the second embodiment of the present invention with a BB line; Figures 7A-7C This is a schematic diagram of the device structure in each step of the process for forming the second deep doped region in the manufacturing method of the SiC MOSFET device according to the first embodiment of the present invention. Detailed Implementation

[0065] The first embodiment of the present invention is a SiC MOSFET device: like Figure 1 The diagram shown is a cross-sectional view of the device unit of the SiC MOSFET device according to the first embodiment of the present invention; as shown... Figure 2 The diagram shown is a layout of the second deeply doped region 3 of the SiC MOSFET device according to the first embodiment of the present invention; the device unit of the SiC MOSFET device according to the first embodiment of the present invention includes: A SiC epitaxial layer 2 with a first conductivity type doped has a trench gate formed therein.

[0066] The trench gate includes a gate trench, a gate dielectric layer 8 formed on the inner surface of the gate trench, and a gate conductive material layer 7 filled in the gate trench. The gate dielectric layer 8 is typically a gate oxide layer; the gate conductive material layer 7 is typically a polysilicon gate.

[0067] A first bottom doped region 9 is formed in the SiC epitaxial layer 2 below the bottom surface of the gate trench. The first bottom doped region 9 has a second conductivity type doping. The top surface of the first bottom doped region 9 is in contact with the bottom surface of the gate dielectric layer 8 on the bottom surface of the gate trench.

[0068] A channel region 4 doped with a second conductivity type is formed in the SiC epitaxial layer 2. The channel region 4 extends downward from the top surface of the SiC epitaxial layer 2. The gate conductive material layer 7 passes longitudinally through the channel region 4 and is covered by the side of the gate conductive material layer 7 to form a conductive channel.

[0069] A second deep-doped region 3 with a second conductivity type doped is formed in the SiC epitaxial layer 2, and there is a gap between the second deep-doped region 3 and the gate trench.

[0070] A source region 6, consisting of a heavily doped region of the first conductivity type, is formed on the surface of the channel region 4.

[0071] The top of the gate conductive material layer 7 is connected to the gate composed of the front metal layer 11.

[0072] The top of the source region 6 is connected to the source electrode, which is composed of a front metal layer 11.

[0073] The first bottom doped region 9 is connected to the source, so that the voltage borne by the gate dielectric layer 8 on the bottom surface of the gate trench is determined by the voltage difference between the source and the gate, thereby reducing the electric field strength borne by the gate dielectric layer 8 on the bottom surface of the gate trench.

[0074] The second deep doped region 3 extends downward from the top surface of the SiC epitaxial layer 2, and the bottom surface of the second deep doped region 3 is located below the bottom surface of the first bottom doped region 9.

[0075] The top of the second deeply doped region 3 is connected to the source electrode.

[0076] The SiC epitaxial layer 2 at the bottom of the channel region 4 forms a drift region.

[0077] The first bottom doped region 9 and the second deep doped region increase the depletion of the drift region located between the first bottom doped region 9 and the second deep doped region at the bottom of the channel region 4, so as to reduce the depletion between the channel region 4 and the drift region at the bottom and thereby reduce the short-channel effect.

[0078] In the first embodiment of the present invention, the SiC epitaxial layer 2 is formed on the SiC substrate 1, the SiC substrate 1 is heavily doped with a first conductivity type, and the drain region is composed of the thinned SiC substrate 1 or formed by back-side ion implantation of the thinned SiC substrate 1.

[0079] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0080] When a SiC MOSFET device is operating, as the drain voltage increases, the drift region at the bottom of the channel region 4, located between the first bottom doped region 9 and the second deep doped region, will form a pinch-off structure. For example... Figure 3 As shown, is Figure 1 The diagram shows the location of the pinch-off structure formed by the first bottom doped region 9 and the second deep doped region 3 in the drift region. The pinch-off structure is a structure in which the drift region in the region corresponding to mark 101 is completely depleted by the first bottom doped region 9 and the second deep doped region. Since the drift region and the first bottom doped region 9 and the second deep doped region of the second conductivity type deplete each other, the depletion ability of the drift region on the channel region 4 of the second conductivity type is weakened. Since the part of the channel region 4 depleted by the drift region is equivalent to no longer belonging to the part controlled by the gate voltage, i.e., no channel is formed, the length of the channel region 4 depleted by the drift region is reduced, which means that the effective length of the channel region 4 is protected, i.e., the short-channel effect is reduced.

[0081] In the first embodiment of the present invention, the depth of the second deep doped region 3 is greater than the implantation depth of the ion implantation machine.

[0082] The SiC epitaxial layer 2 is composed of multiple SiC epitaxial sublayers stacked together, and the second deep-doped region 3 is formed by connecting multiple deep-doped sub-regions formed in each of the SiC epitaxial sublayers by ion implantation through doping of the second conductivity type.

[0083] The device cell region of a SiC MOSFET device is composed of multiple device cells connected in parallel.

[0084] Typically, in the first embodiment of the present invention, the first bottom doped region 9 needs to extend to a transition region or termination region outside the device cell region, and contact the second deeply doped region 3 in the transition region or termination region, and be connected to the source electrode through a contact hole formed on the top of the second deeply doped region 3 and the source region 6. The contact hole passes through the interlayer film 10. A heavily doped ohmic contact region 5 of a second conductivity type is also formed at the bottom of the contact hole on the top of the source region 6.

[0085] On a top view, the device unit is a strip structure or a polygonal structure.

[0086] For the strip structure, although the top view of the strip structure is ultimately a rectangle, the strip structure only forms conductive channels on both sides of the length side of the trench gate of the strip structure. The width side of the trench gate of the strip structure does not form conductive channels and usually extends outside the device cell area. The strip structure is only arranged in one direction, that is, along the width direction of the strip structure.

[0087] The polygonal structure is arranged in two dimensions, horizontally and vertically.

[0088] The polygonal structure includes squares or hexagons.

[0089] The maximum depth of the second deep doped region 3 is 1.6 micrometers or more.

[0090] In a preferred embodiment, the depth of the second deep doped region 3 is 1.6 micrometers. Since the depth of the second deep doped region 3 is greater than the maximum implantation depth of the ion implantation machine, which is about 1 micrometer, the second deep doped region 3 can be achieved by superimposing secondary ion implantation. That is, the SiC epitaxial layer 2 is composed of two SiC epitaxial sublayers, and the second deep doped region 3 is composed of two deep doped subregions connected together.

[0091] Please refer to Figure 7C As shown, the second SiC epitaxial sublayer 22 is superimposed on the top surface of the first SiC epitaxial sublayer 21, the first deep-doped sub-region 31 is formed in the first SiC epitaxial sublayer 21, and the second deep-doped sub-region 32 is formed in the second SiC epitaxial sublayer 22 and passes through the second SiC epitaxial sublayer 22.

[0092] In a preferred embodiment, the device unit is a strip structure, the gate trench is strip-shaped, the channel region 4 is formed on both sides corresponding to the long side of the gate trench, and the second deep doped region 3 is formed on both sides corresponding to the long side of the gate trench.

[0093] Both the first deeply doped sub-region 31 and the second deeply doped sub-region 32 are strip-shaped structures parallel to the gate trench; the second deeply doped sub-region 32 is superimposed on the top surface of the first deeply doped sub-region 31 and is in contact with it. Figure 2 As shown, the strip structures of the first deeply doped sub-region 31 and the second deeply doped sub-region 32 are both similar to... Figure 2 The diagram shows that the second deeply doped region 3 has the same strip structure, and the width of the second deeply doped sub-region 32 is equal to the width of the first deeply doped sub-region 31. In other embodiments, the width of the second deeply doped sub-region 32 may also be greater than the width of the first deeply doped sub-region 31 to reduce the specific on-resistance of the device. Alternatively, the width of the second deeply doped sub-region 32 may be less than the width of the first deeply doped sub-region 31 to improve the pinch-off of the channel region 4.

[0094] In the first embodiment of the present invention, the SiC epitaxial layer 2 has a non-uniform doping concentration, with the doping concentration near the top surface being higher than that near the bottom surface, in order to reduce diffusion resistance and reduce JFET effect.

[0095] In other embodiments, reducing the JFET effect can also be achieved by employing an anti-JFET injection region, for example, an anti-JFET injection region is also formed in the drift region between the gate trench at the bottom of the channel region 4 and the second deeply doped region 3. Figure 4 As shown, is Figure 1 The diagram shows the location of the anti-JFET injection region formed in the structure shown; the area marked 102 is the anti-JFET injection region, which is doped with a first conductivity type to prevent JFET pinch-off, thereby reducing the resistance at the anti-JFET injection region. The anti-JFET injection region is formed by vertical implantation from the top surface of the SiC epitaxial layer 2 to the bottom of the channel region 4. Alternatively, the anti-JFET injection region is formed by angled implantation after the gate trench is formed and before the gate dielectric layer 8 is formed.

[0096] In the first embodiment of the present invention, the SiC MOSFET device is an N-type device, with N-type as the first conductivity type and P-type as the second conductivity type. The P-type dopant includes aluminum, the N-type dopant includes nitrogen, and the material of the front metal layer 11 includes TiNiAl.

[0097] In the first embodiment of the present invention, the gate structure of the SiC MOSFET device cell adopts a trench gate. On this basis, a first bottom doped region 9 is set at the bottom of the gate trench. The first bottom doped region 9 is connected to the source. Thus, the voltage of the gate dielectric layer 8 at the bottom of the gate trench is determined by the voltage difference between the gate conductive material layer 7 and the source, i.e., the gate-source voltage. The gate-source voltage is a small value greater than the threshold voltage when the device is turned on and is 0V when the device is turned off. Compared with the large gate-drain voltage, the first embodiment of the present invention can greatly reduce the voltage on the gate dielectric layer 8 at the bottom of the gate trench, so it can reduce the electric field strength of the gate dielectric layer 8. This can provide good protection for the gate dielectric layer 8 in the interface structure where the gate dielectric layer 8 and the SiC epitaxial layer 2 are in contact, thereby improving the reliability of the device.

[0098] In the first embodiment of the present invention, a second deep-doped region 3 is simultaneously provided in the SiC epitaxial layer 2. The second deep-doped region 3 has a spacing with the gate trench and is also connected to the source. Both the first bottom-doped region 9 and the second deep-doped region 3 are doped with the second conductivity type. This allows the first bottom-doped region 9 and the second deep-doped region 3 to increase the depletion of the drift region at the bottom of the channel region 4, thereby reducing the depletion between the channel region 4 and the bottom drift region and thus reducing the short-channel effect. The reason is that the short-channel effect occurs because when the drift region depletes the channel region 4, the channel region 4 near the drain experiences a pinch-off effect, and the pinched-off... The length of the channel region 4 is equivalent to being uncontrolled by the gate voltage, and the length of the pinched-off channel region 4 is the shortened length of the channel region 4. In the first embodiment of the present invention, the first bottom doped region 9 and the second deep doped region 3 can increase the depletion of the drift region at the bottom of the channel region 4, and the depletion of the channel region 4 and the bottom drift region will be reduced. That is, the area of ​​the channel region 4 that is depleted by the bottom drift region becomes smaller. If pinching occurs, the first bottom doped region 9 and the second deep doped region 3 will first pinch off the drift region at the bottom of the channel region 4, so the length of the pinched-off region of the channel region 4 can be reduced, thereby reducing the short-channel effect.

[0099] The first embodiment of the present invention can reduce the short-channel effect, thus further shortening the length of the channel region 4 and thereby reducing the channel resistance; in addition, the drift region composed of the SiC epitaxial layer 2 can greatly reduce the drift region resistance of the device, and finally further reduce the specific on-resistance of the device.

[0100] The device of the first embodiment of the present invention will be further described below with reference to specific parameters: Unlike Si substrates, SiC substrates have achieved a minimum achievable resistivity of around 0.02 Ω·cm, while Si substrates can currently achieve resistivity below 1 mΩ·cm. Furthermore, SiC substrates are more difficult to thin than Si substrates. Therefore, the substrate resistance of SiC MOSFETs is higher than that of Si-based devices.

[0101] The gate dielectric layer 8 is typically silicon dioxide, which can be oxidized at high temperatures, usually between 1150°C and 1250°C, or deposited using CVD. The thickness of this oxide layer is typically around 50 nm.

[0102] The channel region 4 is typically formed by aluminum ion implantation.

[0103] The heavily doped source region 6 is typically formed using Nitrogen ion implantation.

[0104] The thickness of the interlayer film 10 is typically around 1 μm, and it usually consists of two layers of silicon dioxide, with a typical condition being PSG+BPSG.

[0105] The most significant feature of the device in the first embodiment of the present invention is as follows: There is a second deep doped region 3, which, when p-type, can also be called a DP layer (Deep P Type Implant). It requires a very deep junction depth, typically 1.6 μm. Current ion implantation equipment typically has a maximum implantation energy of 900 keV, corresponding to a depth of 1.0 μm, which is not achievable with conventional ion implantation equipment. Therefore, the process involves ion implantation followed by epitaxy of an epitaxial layer, and then another ion implantation.

[0106] At the bottom of the gate trench is a first bottom doped region 9, which, when P-type, can also be called Bot_P (BottomP Type Implant). In the layout, it is connected to the source via the second deep doped region 3. Because the junction depth of the second deep doped region 3 is deeper than that of the first bottom doped region 9, the connection can be well implemented in the layout.

[0107] Adding a Bot_P at the bottom of the gate trench, with a potential of 0 at the bottom, can effectively reduce the electric field strength at the bottom of the gate trench, thereby effectively protecting the gate oxide.

[0108] DP and Bot_P together form a structure, both of which are connected to the source. As the drain voltage increases, they can... Figure 3 A good pinch-off is formed at the position corresponding to mark 101. This pinch-off can effectively reduce the depletion of the channel by the drift region, reduce the short channel effect, and also reduce the channel length.

[0109] The design of unit cells, or device cells, can be strip-shaped. The advantage of strip shapes is their simplicity in fabrication, but they also result in lower channel density due to their similar pitch. Therefore, polygonal unit cell structures such as squares and hexagons can also be used to increase channel density.

[0110] The following introduction will focus on strip cells.

[0111] A typical structure for this device is: The depth of the gate trench is 0.9 μm, the opening width of the gate trench is 1.0 μm, and the distance between the gate trenches is 5.0 μm.

[0112] The depth corresponding to the first bottom doped region 9 extends 0.2 μm below the trench.

[0113] The depth corresponding to the heavily doped source region 6 is 0.2 μm.

[0114] The depth corresponding to channel region 4 is 0.6 μm, and the length of channel region 4 is 0.4 μm.

[0115] The depth of the second deep doped region 3 is 1.6 μm, and the width of the second deep doped region 3 is 2.0 μm.

[0116] The following example uses a 1200V SiC MOSFET. A typical 1200V SiC MOSFET uses a 12μm thick SiC epitaxial layer 2, corresponding to a doping concentration of 8e15cm⁻¹. -3 .

[0117] In the first embodiment of this invention, to form a Deep P region, i.e., the second deep-doped region 3, it is impossible to achieve this solely through ion implantation. Therefore, this Deep P region is formed through a combination of ion implantation and epitaxy. Since the depth corresponding to Deep P in the first embodiment of this invention is 1.6 μm, it can be formed through a single ion implantation + epitaxy + another ion implantation. If a deeper Deep P region is desired, or if the maximum energy that the ion implantation equipment can implant in a single cycle is limited, then Deep P may require a second epitaxy + a third ion implantation to form.

[0118] The second embodiment of the present invention is a SiC MOSFET device: The difference between the SiC MOSFET device of the second embodiment of the present invention and the SiC MOSFET device of the first embodiment of the present invention is that the SiC MOSFET device of the second embodiment of the present invention has the following features: like Figure 5 The diagram shown is a layout of the first bottom doped region and the second deep doped region of the SiC MOSFET device according to the second embodiment of the present invention; as shown... Figure 6A As shown, it is along Figure 5 A cross-sectional structural schematic diagram of the device unit of the SiC MOSFET device of the second embodiment of the present invention with AA line; as shown. Figure 6B As shown, it is along Figure 5A cross-sectional view of the device unit of the SiC MOSFET device of the second embodiment of the present invention with a BB line is shown. The second deeply doped sub-region 32 has a strip structure parallel to the gate trench, and the first deeply doped sub-region 31 has a strip structure perpendicular to the gate trench. That is, in top view, the strip structures of the second deeply doped sub-region 32 and the first deeply doped sub-region 31 are perpendicular. The second deeply doped sub-region 32 needs to be set according to the strip structure of the gate trench. The step of the second deeply doped sub-region 32, i.e., the width and spacing of the strip structure, is consistent with the step of the gate trench. However, the arrangement step of the strip structure of the second deeply doped sub-region 32 is independent of the arrangement step of the strip structure of the first deeply doped sub-region 31.

[0119] The bottoms of the first deeply doped subregion 31 and the second deeply doped subregion 32 intersect and contact each other laterally.

[0120] The first bottom doped region 9 and the first deep doped sub-region 31 are in contact and both are connected to the source electrode through contact holes formed at the top of the second deep doped sub-region 32. That is, compared with the first embodiment of the present invention, the contact between the first bottom doped region 9 and the second deep doped region 31 can be achieved in the device cell region.

[0121] like Figures 7A-7C The diagram shown is a schematic representation of the device structure in each step of the process for forming the second deeply doped region in the manufacturing method of the SiC MOSFET device according to the first embodiment of the present invention. In the manufacturing method of the SiC MOSFET device according to the first embodiment of the present invention, the step of forming the second deeply doped region 3 includes: Step 1, such as Figure 7A As shown, a first SiC epitaxial sublayer 21 is formed on the SiC substrate 1.

[0122] Step 2, as follows Figure 7A As shown, the formation region of the first deeply doped sub-region 31 is defined, and ions of the second conductivity type corresponding to marker 202 are implanted into the first SiC epitaxial sublayer 21 to form the first deeply doped sub-region 31. The formed first deeply doped sub-region 31 is as follows: Figure 7B As shown.

[0123] In the method of the first embodiment of the present invention, in step two, a first photoresist pattern 201 formed by photoresist defines the formation area of ​​the first deeply doped sub-region 31. The first photoresist pattern 201 serves as a mask for ion implantation of the first deeply doped sub-region 31, and the first photoresist pattern 201 is removed after ion implantation of the first deeply doped sub-region 31 is completed.

[0124] In other embodiments, the method can also be as follows: In step two, a first hard mask pattern is used to define the formation region of the first deeply doped sub-region 31. The first hard mask pattern serves as a mask for ion implantation of the first deeply doped sub-region 31, and is removed after ion implantation of the first deeply doped sub-region 31 is completed. The first hard mask pattern can be formed by first forming a first hard mask layer, such as silicon oxide or silicon nitride, and then performing a photolithography definition and etching process on the first hard mask layer to form the first hard mask pattern.

[0125] Step 3, as follows Figure 7C As shown, a second SiC epitaxial sublayer 22 is formed on the surface of the first SiC epitaxial sublayer 21.

[0126] Step 4, as follows Figure 7C As shown, the formation region of the second deep doped sub-region 32 is defined, and ions of the second conductivity type corresponding to the mark 204 are implanted in the second SiC epitaxial sub-layer 22 to form the second deep doped sub-region 32 that penetrates the second SiC epitaxial sub-layer 22.

[0127] In the method of the first embodiment of the present invention, in step four, a second photoresist pattern 203 formed by photoresist defines the formation region of the second deeply doped sub-region 32. The second photoresist pattern 203 serves as a mask for ion implantation of the second deeply doped sub-region 32 and is removed after ion implantation of the second deeply doped sub-region 32 is completed.

[0128] In other embodiments, the method can also be as follows: in step four, a second hard mask pattern is used to define the formation region of the second deeply doped sub-region 32, the second hard mask pattern serves as a mask for ion implantation of the second deeply doped sub-region 32, and the second hard mask pattern is removed after ion implantation of the second deeply doped sub-region 32 is completed.

[0129] As needed, repeat the formation process of the second SiC epitaxial sublayer 22 in step three and the formation process of the second deeply doped subregion 32 in step four to form more SiC epitaxial sublayers and deeply doped subregions. The SiC epitaxial layer 2 is formed by stacking the first SiC epitaxial sublayer 21, the second SiC epitaxial sublayer 22 and each SiC epitaxial sublayer on top of the second SiC epitaxial sublayer 22. The second deeply doped region 3 is formed by stacking the first deeply doped subregion 31, the second deeply doped subregion 32 and the deeply doped subregion on top of the second deeply doped subregion 32.

[0130] In the first embodiment of the present invention, after forming the SiC epitaxial layer 2, a trench gate formation process is performed, the trench gate formation process including: A third hard mask pattern is formed on the surface of the SiC epitaxial layer 2, which opens the formation region of the gate trench and covers the outside of the formation region of the gate trench.

[0131] The gate trench is formed by etching using the third hard mask pattern as a mask.

[0132] A first bottom doped region 9 is formed at the bottom of the gate trench by performing full ion implantation.

[0133] The gate dielectric layer 8 is formed on the inner surface of the gate trench.

[0134] The gate conductive material layer 7 is filled into the gate trench.

[0135] Based on the formation of the first bottom doped region 9 and the second deep doped region 3, the subsequent formation process of the SiC MOSFET of the first embodiment of the present invention or the SiC MOSFET of the second embodiment of the present invention is the same as the existing process.

[0136] The manufacturing method of the device in the first embodiment of the present invention will be further described below with reference to specific parameters: The thickness of the first SiC epitaxial sublayer 21 is 11.2 μm, and the resistivity of the epitaxial layer is 8e15 cm⁻¹. -3 .

[0137] Depending on the temperature corresponding to ion implantation 202, if it is room temperature implantation, the patterned structure 201 is usually directly made of photoresist. If it is high-temperature implantation, which can better repair lattice defects, silicon dioxide can be used as a hard mask layer to replace the photoresist pattern 201. Then ion implantation is performed.

[0138] Subsequently, the thickness of the second SiC epitaxial sublayer 22 formed is 0.8 μm, corresponding to a doping concentration of 8e15 cm⁻¹. -3 The doping concentration is the same as that of the first layer. More preferably, to reduce the diffusion resistance of the MOSFET, the doping concentration of this epitaxial layer can be increased to 2.0e16cm. -3 .

[0139] Then a second photolithography and ion implantation 204 were performed.

[0140] Thus, DP is composed of two ion implantations and epitaxy. The formation of Bot_P is relatively simple. After the gate trench of the device is formed, while the hard mask layer of the gate trench is still present, Bot_P is formed in the plateau region (Mesa) by ion implantation through the obstruction of the hard mask layer of the gate trench.

[0141] Note that a photolithography plate is required for each of these two ion implantations.

[0142] When formed Figure 1 In the device of the first embodiment of the present invention shown, the photolithography used for the two ion implantations 203 and 204 can be exactly the same and both adopt [the following method / approach]. Figure 2 The corresponding photomask for the layout of the second deeply doped region 3. One possible approach is that the width of the second deeply doped region 3 is 2 μm, and the spacing between the second deeply doped regions 3 is 3 μm.

[0143] The photolithography used for ion implantation 203 and 204 is different. If it is desired that the second deeply doped region 3 is wider near the top of the device and narrower at the bottom, this can reduce the specific on-resistance of the device. This allows the width of the second deeply doped sub-region 32 to be greater than the width of the first deeply doped sub-region 31. Alternatively, if it is desired that the DP formation is wider near the bottom of the device and narrower at the top, this can better facilitate channel pinch-off, allowing the width of the first deeply doped sub-region 31 to be greater than the width of the second deeply doped sub-region 32.

[0144] Of course, for strip structures, the first deeply doped sub-region 31 and the second deeply doped sub-region 32 can also be in different directions, for example: when forming Figures 5-6B When using the device corresponding to the second embodiment of the present invention, it is necessary to adopt... Figure 5 The stripe structures of the first deeply doped sub-region 31 and the second deeply doped sub-region 32 shown are perpendicular to each other. This structure has the following advantages: Deep P Implant and Bot_P can be directly connected in the cell region, without needing to connect Deep P Implant and Bot_P in the transition region or terminal region of the chip as in the previous structure.

[0145] Because the first deeply doped subregion 31 is located directly at the bottom of the gate trench at certain locations, the dose injected by the Bot_P can be reduced. This can partially reduce the JFET effect caused by the Bot_P implantation.

[0146] The pitch of the photomask in the first deeply doped sub-region 31, i.e., the pitch of the strip structure of the layout, offers great flexibility and can be designed as needed. It can be smaller or larger than the pitch of the mask in the second deeply doped sub-region 32.

[0147] This structure can effectively reduce the electric field strength of the gate dielectric layer 8, and by forming a pinch-off, it reduces the depletion of the channel region, thus effectively reducing the short-channel effect.

[0148] However, the device also introduces a very serious JFET effect.

[0149] There are several ways to reduce the JFET effect: The doping concentration of the SiC epitaxial layer 2 is not uniform; rather, the doping concentration increases towards the top. For example, in a 1200V SiC MOSFET, the 12μm SiC epitaxial layer 2 may have a bottom 10.5μm layer with a doping concentration of 8e15cm. -3 The top 1.5 μm layer uses a doping concentration of 2e16cm. -3 .

[0150] Alternatively, high-energy anti-JFET ion implantation can be used, which involves implanting high-energy Nitrogen ions into the JFET. Figure 4 The area indicated by mark 102.

[0151] The anti-JFET implantation site is located below channel region 4. This can be with or without a photomask. In practice, implantation with a photomask is usually required.

[0152] Alternatively, after the gate trench is formed, a P-type implantation, such as aluminum implantation, can be performed at the bottom of the gate trench to form the first bottom doped region 9. Then, an angled N-type implantation, such as Nitrogen implantation, can be performed on the sidewalls of the gate trench to increase the doping concentration of the sidewalls and reduce the diffusion resistance.

[0153] In practice, designers can choose appropriate solutions to reduce the JFET effect based on their needs.

[0154] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A SiC MOSFET device, characterized in that, The device unit includes: A SiC epitaxial layer doped with a first conductivity type, wherein a trench gate is formed in the SiC epitaxial layer; The trench gate includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; A first bottom doped region is formed in the SiC epitaxial layer below the bottom surface of the gate trench. The first bottom doped region has a second conductivity type doping. The top surface of the first bottom doped region is in contact with the bottom surface of the gate dielectric layer at the bottom surface of the gate trench. A channel region doped with a second conductivity type is formed in the SiC epitaxial layer. The channel region extends downward from the top surface of the SiC epitaxial layer. The gate conductive material layer passes longitudinally through the channel region. The surface of the channel region is covered by the side of the gate conductive material layer to form a conductive channel. A second deep-doped region with a second conductivity type doped is formed in the SiC epitaxial layer, and there is a spacing between the second deep-doped region and the gate trench; The SiC epitaxial layer is composed of multiple SiC epitaxial sublayers stacked together, and the second deep doped region is formed by connecting multiple deep doped sub-regions formed in each of the SiC epitaxial sublayers by ion implantation through doping of the second conductivity type. A source region consisting of heavily doped regions of a first conductivity type is formed on the surface of the channel region; The top of the gate conductive material layer is connected to the gate, which is composed of a front metal layer; The top of the source region is connected to a source electrode composed of a front-side metal layer; The first bottom doped region is connected to the source, so that the voltage across the gate dielectric layer on the bottom surface of the gate trench is determined by the voltage difference between the source and the gate, thereby reducing the electric field strength across the gate dielectric layer on the bottom surface of the gate trench. The second deep-doped region extends downward from the top surface of the SiC epitaxial layer, and the bottom surface of the second deep-doped region is located below the bottom surface of the first bottom-doped region. The top of the second deeply doped region is connected to the source electrode; The SiC epitaxial layer at the bottom of the channel region constitutes a drift region; The first bottom doped region and the second deep doped region increase the depletion of the drift region located between the first bottom doped region and the second deep doped region at the bottom of the channel region, thereby reducing the depletion between the channel region and the drift region at the bottom and thus reducing the short-channel effect.

2. The SiC MOSFET device as described in claim 1, characterized in that: The SiC epitaxial layer is formed on a SiC substrate, the SiC substrate being heavily doped with a first conductivity type, and the drain region being composed of the thinned SiC substrate or formed by back-side ion implantation of the thinned SiC substrate; A drain electrode composed of a back metal layer is formed on the back side of the drain region; When a SiC MOSFET device is in operation, as the drain voltage increases, the drift region at the bottom of the channel region, located between the first bottom doped region and the second deep doped region, will form a pinch-off structure.

3. The SiC MOSFET device as described in claim 2, characterized in that: The depth of the second deep doped region is greater than the implantation depth of the ion implantation machine.

4. The SiC MOSFET device as described in claim 3, characterized in that: The device cell region of a SiC MOSFET device is composed of multiple device cells connected in parallel; On a top view, the device unit is a strip structure or a polygonal structure; The polygonal structure includes squares or hexagons.

5. The SiC MOSFET device as described in claim 4, characterized in that: The SiC epitaxial layer is composed of two SiC epitaxial sublayers stacked together, and the second deep-doped region is composed of two deep-doped sub-regions connected together; The second SiC epitaxial sublayer is superimposed on the top surface of the first SiC epitaxial sublayer. The first deeply doped sub-region is formed in the first SiC epitaxial sublayer, and the second deeply doped sub-region is formed in the second SiC epitaxial sublayer and penetrates the second SiC epitaxial sublayer.

6. The SiC MOSFET device as described in claim 5, characterized in that: The device unit has a strip-shaped structure, the gate trench is strip-shaped, the channel region is formed on both sides corresponding to the long side of the gate trench, and the second deep doped region is formed on both sides corresponding to the long side of the gate trench.

7. The SiC MOSFET device as described in claim 6, characterized in that: Both the first and second deeply doped sub-regions are strip-shaped structures parallel to the gate trench; the second deeply doped sub-region is superimposed on the top surface of the first deeply doped sub-region and is in contact with it.

8. The SiC MOSFET device as described in claim 7, characterized in that: The width of the second deep-doped sub-region is equal to the width of the first deep-doped sub-region; Alternatively, the width of the second deeply doped sub-region is greater than the width of the first deeply doped sub-region to reduce the specific on-resistance of the device; Alternatively, the width of the second deep-doped sub-region may be smaller than the width of the first deep-doped sub-region to improve the pinch-off of the channel region.

9. The SiC MOSFET device as described in claim 6, characterized in that: The second deeply doped subregion has a strip-shaped structure parallel to the gate trench, and the first deeply doped subregion has a strip-shaped structure perpendicular to the gate trench. The bottoms of the first and second deeply doped subregions intersect and contact each other laterally; The first bottom doped region and the first deep doped subregion are in contact and both are connected to the source through the top of the second deep doped subregion.

10. The SiC MOSFET device as described in claim 9, characterized in that: The arrangement step of the strip structure in the second deeply doped subregion is independent of the arrangement step of the strip structure in the first deeply doped subregion.

11. The SiC MOSFET device according to any one of claims 1 to 10, characterized in that: The SiC epitaxial layer has a non-uniform doping concentration, with the doping concentration near the top surface being higher than that near the bottom surface, in order to reduce diffusion resistance and reduce JFET effect.

12. The SiC MOSFET device according to any one of claims 1 to 10, characterized in that: An anti-JFET injection region is also formed in the drift region between the gate trench at the bottom of the channel region and the second deeply doped region.

13. The SiC MOSFET device as described in claim 12, characterized in that: The anti-JFET implantation region is formed by vertical implantation from the top surface of the SiC epitaxial layer to the bottom of the channel region; Alternatively, the anti-JFET injection region is formed by angled injection after the gate trench is formed and before the gate dielectric layer is formed.

14. The SiC MOSFET device as described in claim 1, characterized in that: SiC MOSFET devices are N-type devices, with N-type as the first conductivity type and P-type as the second conductivity type.

15. The SiC MOSFET device as described in claim 14, characterized in that: P-type doped impurities include aluminum, N-type doped impurities include nitrogen, and the material of the front metal layer includes TiNiAl.

16. The SiC MOSFET device as claimed in claim 1, characterized in that: The maximum depth of the second deep doped region is 1.6 micrometers or more.

17. The method for manufacturing a SiC MOSFET device as described in claim 3, characterized in that, The steps for forming the second deeply doped region include: Step 1: Form a first SiC epitaxial sublayer on the SiC substrate; Step 2: Define the formation region of the first deeply doped sub-region, and perform ion implantation of the second conductivity type in the first SiC epitaxial sub-layer to form the first deeply doped sub-region; Step 3: Form a second SiC epitaxial sublayer on the surface of the first SiC epitaxial sublayer; Step 4: Define the formation region of the second deep-doped sub-region, and perform ion implantation of the second conductivity type in the second SiC epitaxial sub-layer to form the second deep-doped sub-region that penetrates the second SiC epitaxial sub-layer; As needed, repeat the formation process of the second SiC epitaxial sublayer in step three and the formation process of the second deeply doped subregion in step four to form more SiC epitaxial sublayers and deeply doped subregions. The SiC epitaxial layer is formed by stacking the first SiC epitaxial sublayer, the second SiC epitaxial sublayer, and each SiC epitaxial sublayer on top of the second SiC epitaxial sublayer. The second deeply doped region is formed by stacking the first deeply doped subregion, the second deeply doped subregion, and the deeply doped subregion on top of the second deeply doped subregion.

18. The method for manufacturing a SiC MOSFET device as described in claim 17, characterized in that: In step two, the first photoresist pattern formed by photoresist defines the formation region of the first deeply doped sub-region. The first photoresist pattern serves as a mask for ion implantation of the first deeply doped sub-region, and the first photoresist pattern is removed after ion implantation of the first deeply doped sub-region is completed. In step four, a second photoresist pattern is formed using photoresist to define the formation region of the second deeply doped sub-region. The second photoresist pattern serves as a mask for ion implantation of the second deeply doped sub-region and is removed after ion implantation of the second deeply doped sub-region is completed. Alternatively, in step two, a first hard mask pattern is used to define the formation region of the first deeply doped sub-region. The first hard mask pattern serves as a mask for ion implantation of the first deeply doped sub-region, and the first hard mask pattern is removed after ion implantation of the first deeply doped sub-region is completed. In step four, a second hard mask pattern is used to define the formation region of the second deeply doped sub-region. The second hard mask pattern serves as a mask for ion implantation of the second deeply doped sub-region and is removed after ion implantation of the second deeply doped sub-region is completed.

19. The method for manufacturing a SiC MOSFET device as described in claim 17, characterized in that: The process for forming the trench gate includes: A third hard mask pattern is formed on the surface of the SiC epitaxial layer, the third hard mask pattern opening up the formation area of ​​the gate trench and covering the outside of the formation area of ​​the gate trench; The gate trench is formed by etching using the third hard mask pattern as a mask. A first bottom doped region is formed at the bottom of the gate trench by performing full ion implantation; The gate dielectric layer is formed on the inner surface of the gate trench; The gate conductive material layer is filled into the gate trench.

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