High resolution pulse width modulation signal generation circuit
By combining the control module, PWM counting module, delay module, and calibration module, the problem of limited PWM signal accuracy was solved, enabling the generation of high-resolution PWM signals and improving the signal resolution and accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 小华半导体有限公司
- Filing Date
- 2020-12-08
- Publication Date
- 2026-07-24
AI Technical Summary
In existing technologies, the accuracy of PWM signals is limited by the clock frequency, making it difficult to achieve high resolution without changing the counting clock frequency.
By combining a control module, a PWM counting module, a delay module, an output selection module, and a calibration module, and through delay calibration and delay chain design, the resolution and accuracy of the PWM signal are improved.
Without changing the counting clock frequency, the resolution and accuracy of the PWM signal are improved, the error of the delay module is reduced, and the generation of high-resolution PWM signals is achieved.
Smart Images
Figure CN114629476B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design, and in particular to a high-resolution pulse width modulation signal generation circuit. Background Technology
[0002] In switching power supplies, lighting, solar inverters, wireless chargers, and motor control, digital PWM is used to control switching power devices to regulate target voltages. With the development of SiC and GaN semiconductor technologies, the switching frequencies of switching power devices are becoming increasingly higher, which places demands on control systems to generate high-resolution PWM signals.
[0003] Generally, for a pulse width modulation (PWM) signal with a given switching frequency fswpwm, its resolution bit depth n is determined by the counter's clock frequency fck, and the formula is n = log2(fck / fswpwm). Assuming a PWM signal with a counter clock frequency of 100MHz and a switching frequency of 1MHz, its resolution is log2(100 / 1) = 6.6, meaning this PWM signal has a resolution of 6.6 bits. In many applications, the resolution of the PWM signal needs to reach 10 bits or more, in which case the clock frequency fck needs to reach fswpwm*2. 10 =1024MHz. However, the clock frequency fck is limited by the manufacturing process and cannot be increased arbitrarily. For example, to achieve 13-bit PWM accuracy at a 1MHz carrier frequency, the counting clock of the digital PWM needs to reach a frequency of over 8GHz, with a resolution of 122ps. This specification is difficult to achieve under general integrated circuit processes. Therefore, the limitation of the counter clock frequency by the manufacturing process capability creates a contradiction with the high resolution requirement of PWM.
[0004] How to further improve the accuracy of PWM signals and reduce errors has become one of the problems that urgently need to be solved by those skilled in the art. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-resolution pulse width modulation signal generation circuit to solve the problem that the accuracy of PWM signals is limited by the clock frequency in the prior art.
[0006] To achieve the above and other related objectives, the present invention provides a high-resolution pulse width modulation signal generation circuit, the high-resolution pulse width modulation signal generation circuit comprising at least:
[0007] Control module, PWM counting module, delay module, output selection module and calibration module;
[0008] The control module receives control signals and is used to generate rising edge delay, falling edge delay, output selection signal and calibration control signal;
[0009] The PWM counting module receives a counting clock and generates a PWM signal based on the counting clock.
[0010] The delay module is connected to the output of the control module and the PWM counting module, and performs a delay operation on the PWM signal based on the rising edge delay and the falling edge delay.
[0011] The output selection module is connected to the output terminals of the control module, the PWM counting module, and the delay module, and outputs the output signal of the PWM counting module or the delay module based on the output selection signal;
[0012] The calibration module is connected to the output of the control module and receives the counting clock. Based on the counting clock, it counts the frequency division signal of the ring oscillation signal of the delay module and calibrates the delay amount based on the multiple relationship between the ring oscillation signal and the counting clock. The high-level width of the ring oscillation signal is the rising edge delay amount in the delay module, and the low-level width is a preset width.
[0013] Optionally, the control module includes a delay selection register, which outputs the rising edge delay and the falling edge delay based on the delay selection register.
[0014] Optionally, the PWM counting module includes a counting unit and a comparison unit; the counting unit receives the counting clock, counts the counting clock, and outputs a count value; the comparison unit is connected to the output terminal of the counting unit, compares the count value with a preset value, and flips the level when the count value reaches the preset value to obtain the PWM signal.
[0015] Alternatively, the PWM counting module also receives a phase adjustment control signal, which is connected to the comparison unit. By changing the preset value, the phase of the PWM signal is adjusted, thereby realizing the pulse frequency modulation function.
[0016] Optionally, the delay module includes a rising edge delay unit and a falling edge delay unit;
[0017] The rising edge delay unit is connected to the output of the PWM counting module and the control module, and performs rising edge delay on the PWM signal based on the rising edge delay amount; the falling edge delay unit is connected to the rising edge delay unit and the output of the control module, and performs falling edge delay on the PWM signal after rising edge delay based on the falling edge delay amount.
[0018] Alternatively, the falling edge delay unit is connected to the output of the PWM counting module and the control module, and performs a falling edge delay on the PWM signal based on the falling edge delay amount; the rising edge delay unit is connected to the output of the falling edge delay unit and the control module, and performs a rising edge delay on the PWM signal after the falling edge delay based on the rising edge delay amount.
[0019] Alternatively, both the rising edge delay unit and the falling edge delay unit include a delay decoder, a delay chain consisting of m sequentially cascaded delay blocks, and an AND / OR logic unit.
[0020] The delay decoder decodes the delay amount to obtain the delay amount selection signal and the delay block valid signal;
[0021] The delay chain receives the PWM signal, and each delay block in the delay chain receives the delay amount selection signal and the delay block valid signal, and delays the PWM signal based on the delay amount selection signal and the delay block valid signal;
[0022] The input terminal of the AND-OR logic unit is connected to the output terminal of the delay chain and the PWM signal. The output signal of the delay chain and the PWM signal are AND-ORed to obtain the delayed signal of the PWM signal.
[0023] Where m is a natural number greater than or equal to 1.
[0024] Optionally, the delay block includes a first to an (n+1)th data selector cascaded in sequence. The first input terminal of the subsequent data selector is connected to the output terminal of the preceding data selector. The second input terminal of each data selector is connected to the PWM signal. The first and second input terminals of the first data selector are connected to the PWM signal. The control terminals of the first to the nth data selector are respectively connected to the corresponding delay amount selection signal. The control terminal of the (n+1)th data selector is connected to the corresponding delay block valid signal, where n is a natural number greater than or equal to 1.
[0025] Alternatively, the data selector is a two-to-one selector.
[0026] Alternatively, the calibration module includes a ring resonant signal generation unit and a calibration calculation unit. The ring resonant signal generation unit generates at least two ring resonant signals of different frequencies. The high-level width of each ring resonant signal is selected from different delay amounts of the delay module, and the low-level width of each ring resonant signal is a preset width. The calibration calculation unit divides the ring resonant signals by frequency and counts the divided signals of the ring resonant signals based on the counting clock to obtain the multiple relationship between the ring resonant signals and the counting clock.
[0027] Optionally, the ring vibration signal generation unit includes a delay selection subunit, a preset delay subunit, an edge detection subunit, and an RS trigger;
[0028] The delay selection subunit is connected to the output terminal of the RS flip-flop. The delay selection subunit has the same structure as the rising edge delay unit. Based on the calibration control signal, different delay amounts are selected to delay the output signal of the RS flip-flop.
[0029] The preset delay subunit is connected to the output terminal of the RS flip-flop and delays the output signal of the RS flip-flop based on a preset delay amount;
[0030] The edge detection subunit is connected to the output terminal of the preset delay unit and performs edge detection on the output signal of the preset delay subunit;
[0031] The reset terminal of the RS flip-flop is connected to the output terminal of the delay selection subunit, and the set terminal is connected to the output terminal of the edge detection subunit to generate the ring signal.
[0032] As described above, the high-resolution pulse width modulation signal generation circuit of the present invention has the following beneficial effects:
[0033] 1. The high-resolution pulse width modulation signal generation circuit of the present invention improves the resolution of the pulse width modulation signal without changing the counting clock, and can be used to adjust the period and duty cycle of the PWM signal.
[0034] 2. The high-resolution pulse width modulation signal generation circuit of the present invention measures the multiple relationship between the counting clock and the delay chain through the calibration circuit, which makes it easier to use the delay module as a lower-level extension of the PWM counting module, facilitating software control and improving the accuracy of high-resolution PWM.
[0035] 3. The high-resolution pulse width modulation signal generation circuit of the present invention uses the basic unit device MUX as the smallest delay unit of the delay chain, which also serves as the delay selection logic. This reduces the inherent delay from the input of the delay module to the output of the delay module, which is beneficial to reducing the error of the delay chain. Attached Figure Description
[0036] Figure 1 The diagram shown is a schematic representation of the high-resolution pulse width modulation signal generation circuit of the present invention.
[0037] Figure 2 The diagram shown is a structural schematic of the PWM counting module of the present invention.
[0038] Figure 3 The diagram shown is a schematic representation of the rising edge delay unit of the present invention.
[0039] Figure 4 The diagram shown is a structural schematic of the delay block of the present invention.
[0040] Figure 5 The diagram shown is a structural schematic of the calibration module of the present invention.
[0041] Component designation explanation
[0042] 1. High-resolution pulse width modulation signal generation circuit
[0043] 11 Control Module
[0044] 12 PWM counting modules
[0045] 121 Counting Units
[0046] 122 Comparison Unit
[0047] 13 Delay Module
[0048] 13a Rising Edge Delay Unit
[0049] 13b Falling edge delay unit
[0050] 131 Delay Decoder
[0051] 132 Delay Block
[0052] 1321 Data Selector
[0053] 1322 Buffer Level
[0054] 133 AND / OR logic unit
[0055] 134 Buffer
[0056] 14 Output Selection Module
[0057] 15 Calibration Modules
[0058] 151 Ring Resonance Signal Generation Unit
[0059] 1511 Delayed Selection Subunit
[0060] 1512 Preset Delay Subunit
[0061] 1513 Edge Detection Subunit
[0062] 1514 RS Trigger
[0063] 152 Calibration Unit Detailed Implementation
[0064] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0065] Please see Figures 1-5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0066] like Figure 1 As shown, the present invention provides a high-resolution pulse width modulation signal generation circuit 1, the high-resolution pulse width modulation signal generation circuit 1 comprising:
[0067] The control module 11, PWM counting module 12, delay module 13, output selection module 14, and calibration module 15 are included.
[0068] like Figure 1 As shown, the control module 11 receives control signals to generate rising edge delay up[7:0], falling edge delay down[7:0], output selection signal ctl1, and calibration control signal ctl2.
[0069] Specifically, the control module 11 includes, but is not limited to, a delay selection register, an output control unit, and a calibration control unit (not shown in the figure). Any control signal used to control the operation of each module in the high-resolution pulse width modulation signal generation circuit 1 can be generated by the control module 11. The selection of the rising edge delay up[7:0] and the falling edge delay down[7:0] is achieved by changing the delay selection register. Based on the characteristics of the register, when the edge of the PWM signal changes, the output value of the delay selection register will not change immediately, thereby avoiding competition in the output of the high-resolution PWM signal.
[0070] Specifically, in this embodiment, the control module 11 also receives a counting clock ck as its working clock. In actual use, the source of the working clock of the control module 11 can be set as needed, and is not limited to this embodiment.
[0071] It should be noted that, as an example, the rising edge delay up[7:0] and the falling edge delay down[7:0] are 8-bit bus signals. In actual use, the number of bits for the rising edge delay and the falling edge delay can be set as needed, and is not limited to this embodiment.
[0072] like Figure 1 As shown, the PWM counting module 12 receives the counting clock ck and generates a PWM signal based on the counting clock ck.
[0073] Specifically, such as Figure 2 As shown, in this embodiment, the PWM counting module 12 includes a counting unit 121 and a comparison unit 122. The counting unit 121 receives the counting clock ck, counts the counting clock ck, and outputs a count value. The comparison unit 122 is connected to the output terminal of the counting unit 121, compares the count value with a preset value (comparison threshold), and flips the level when the count value reaches the preset value to obtain the PWM signal.
[0074] It should be noted that any circuit structure capable of generating PWM waveforms is applicable to this invention and is not limited to this embodiment.
[0075] In another implementation of the present invention, the PWM counting module 11 also receives a phase adjustment control signal ctl3. As an example, the phase adjustment control signal ctl3 is provided by the control module 11. The phase adjustment control signal ctl3 is connected to the comparison unit 122, and the phase of the PWM signal is adjusted by changing the preset value, thereby realizing the Pulse Frequency Modulation (PFM) function.
[0076] like Figure 1 As shown, the delay module 13 is connected to the output terminals of the control module 11 and the PWM counting module 12, and performs a delay operation on the PWM signal based on the rising edge delay up[7:0] and the falling edge delay down[7:0].
[0077] Specifically, such as Figure 1As shown, the delay module 13 includes a rising edge delay unit 13a and a falling edge delay unit 13b. In this embodiment, the rising edge delay unit 13a is connected to the output terminals of the PWM counting module 12 and the control module 11, and performs a rising edge delay on the PWM signal based on the rising edge delay amount up[7:0]. The falling edge delay unit 13b is connected to the rising edge delay unit 13a and the output terminal of the control module 11, and performs a falling edge delay on the PWM signal after the rising edge delay based on the falling edge delay amount down[7:0]. In this embodiment, the rising edge delay unit 13a and the falling edge delay unit 13b have the same structure, both including a delay decoder 131, a delay chain composed of m sequentially cascaded delay blocks 132, and an AND / OR logic unit 133. In this embodiment, taking the rising edge delay unit 13a as an example, the difference between the falling edge delay unit 13b and the rising edge delay unit 13a is only that they receive different delay amounts (the rising edge delay unit receives the rising edge delay amount, and the falling edge delay unit receives the falling edge delay amount), and the objects of delay are different (the rising edge delay unit delays the rising edge, and the falling edge delay unit delays the falling edge), which will not be elaborated here.
[0078] More specifically, such as Figure 3 As shown, the delay decoder 131 decodes the rising edge delay up[7:0] to obtain the rising edge delay selection signal sel[255:0] and the delay block valid signal nohit[7:0]. In this embodiment, the delay decoder 131 is an 8-input 256-output decoder, which decodes the 8-bit rising edge delay into a 256-bit rising edge delay selection signal. Only one bit of the rising edge delay selection signal is valid at any given time. The delay decoder 131 also outputs an 8-bit delay block valid signal.
[0079] More specifically, such as Figure 3As shown, the delay chain includes m cascaded delay blocks 132, where m is a natural number greater than or equal to 1, and in this embodiment, m is set to 8. The delay chain receives the PWM signal and delays the rising edge of the PWM signal based on the rising edge delay selection signal sel[255:0] and the delay block valid signal nohit[7:0]. The input of the first-stage delay block is connected to the PWM signal, the input of the second-stage delay block is connected to the output of the first-stage delay block, the input of the third-stage delay block is connected to the output of the second-stage delay block, and so on, with the input of the eighth-stage delay block connected to the output of the seventh-stage delay block. The first-stage delay block receives the last eight bits (sel[255:224]) of the rising edge delay selection signal and the last bit (nohit[7]) of the delay block valid signal. The second to eighth-stage delay blocks respectively receive the eight bits of the rising edge delay selection signal and the one bit of the delay block valid signal, thereby obtaining the corresponding rising edge delay. Further, taking the eighth-stage delay block as an example, Figure 4As shown, the delay block 132 includes first to (n+1)th data selectors 1321 cascaded in sequence, where n is a natural number greater than or equal to 1; the first input terminal of the subsequent data selector is connected to the output terminal of the preceding data selector, the second input terminal of each data selector is connected to the PWM signal, the first and second input terminals of the first data selector are connected to the PWM signal, the control terminals of the first to the nth data selector are respectively connected to the corresponding bit signal in the delay amount selection signal, and the control terminal of the (n+1)th data selector is connected to the corresponding bit signal in the effective signal of the delay block; as an example, n is set to 32, and the data selector adopts a 2-to-1 multiplexer (MUX). When the delay block valid signal (nohit[0]) in the delay block 132 is low, the corresponding delay block is selected and a delay is added. When the delay block valid signal (nohit[0]) in the delay block 132 is high, the corresponding delay block is not selected and the PWM signal is directly output through the last stage 2-to-1 selector. When the delay amount selection signal (sel[0], sel[1]...sel
[30] or sel
[31] ) is low, the corresponding 2-to-1 selector is selected and a delay is added. When the delay amount selection signal (sel[0], sel[1]...sel
[30] or sel
[31] ) is high, the corresponding 2-to-1 selector is not selected and the PWM signal is directly output. As another implementation of the present invention, the delay block 132 further includes a buffer stage 1322 connected to the input terminal of the first data selector. The PWM signal is input to each data selector after passing through the buffer stage 1322. The buffer stage 1322 and the (n+1)th data selector (the last stage) have inherent delays, that is, no matter how much the delay is, these delays will exist as long as the PWM signal passes through the delay chain.
[0080] More specifically, such as Figure 3 As shown, the input terminal of the AND-OR logic unit 133 is connected to the output terminal of the delay chain and the PWM signal. An AND-OR operation is performed on the output signal of the delay chain and the PWM signal to obtain the delayed signal of the PWM signal. In this embodiment, the AND-OR logic unit 133 includes an AND gate and a NOT gate connected to the output terminal of the AND gate. In practical use, any circuit structure that can implement AND-OR logic is applicable to this invention and is not limited to this embodiment.
[0081] In another implementation of the present invention, the rising edge delay unit 13a further includes a buffer 134 connected to the input terminal of the first-stage delay block, and the PWM signal is output to the delay block 132 and the AND-OR logic unit 133 via the buffer 134. The buffer 134 and the AND-OR logic unit 133 have inherent delays.
[0082] It should be noted that, in order to reduce the error between each delay segment, the metal wire lengths at the input terminals of each data selector in this invention are equal (or approximately equal, allowing for process errors), and the metal wire lengths at the output terminals are equal (or approximately equal, allowing for process errors). The basic unit for delay in this invention, the 2-to-1 selector, simultaneously functions as a delay quantity selection and control unit. Compared to existing technologies, it has a smaller circuit size, and the inherently shorter delay caused by the selection circuit is beneficial for precise control of the PWM signal.
[0083] It should be noted that in practical use, the PWM signal can be first delayed by its falling edge, and then delayed by its rising edge. The falling edge delay unit is connected to the output of the PWM counting module and the control module, and delays the PWM signal by its falling edge based on the falling edge delay amount; the rising edge delay unit is connected to the output of the control module, and delays the PWM signal by its rising edge based on the rising edge delay amount; this is not limited to this embodiment.
[0084] like Figure 1 As shown, the output selection module 14 is connected to the output terminals of the control module 11, the PWM counting module 12 and the delay module 13. Based on the output selection signal ctl1, it outputs the output signal of the PWM counting module 11 or the delay module 12 to obtain the output signal PWM' of the high-resolution pulse width modulation signal generation circuit 1.
[0085] Specifically, when it is necessary to delay the rising edge and / or falling edge of the PWM signal, the output selection module 14 outputs the output signal of the delay module 12; when it is not necessary to delay the rising edge and / or falling edge of the PWM signal, the output selection module 14 outputs the output signal of the PWM counting module 11.
[0086] like Figure 1 As shown, the calibration module 15 is connected to the output terminal of the control module 11 and receives the counting clock ck. Based on the counting clock ck, it counts the frequency division signal of the ring oscillation signal calclk of the delay module 13, and calibrates the delay amount based on the multiple relationship between the ring oscillation signal calclk and the counting clock ck. The high-level width of the ring oscillation signal calclk is the rising edge delay amount in the delay module, and the low-level width is a preset width.
[0087] Specifically, in this embodiment, the calibration module 15 includes a ring resonant signal generation unit 151 and a calibration calculation unit 152. The ring resonant signal generation unit 151 generates at least two ring resonant signals of different frequencies. The high-level width of each ring resonant signal is selected from different delay amounts of the delay module 13, and the low-level width of each ring resonant signal is a preset value. The calibration calculation unit 152 divides the ring resonant signal calclk by frequency division, counts the divided signal of the ring resonant signal calclk based on the counting clock ck, and calculates the multiple relationship Fcal between the ring resonant signal calclk and the counting clock ck through hardware calculation, i.e., the calibration amount, and outputs a calibration completion flag comp. Based on the calibration amount Fcal, the rising edge delay amount or the falling edge delay amount is adjusted to achieve high-resolution output.
[0088] More specifically, the ring resonant signal generation unit 151 includes a delay selection subunit 1511, a preset delay subunit 1512, an edge detection subunit 1513, and an RS flip-flop 1514. The delay selection subunit 1511 is connected to the output of the RS flip-flop 1514. The delay selection subunit 1511 has the same structure as the rising edge delay unit 13a, and selects different delay amounts to delay the output signal of the RS flip-flop 1514 based on the calibration control signal ctl2. As an example, in this embodiment, the delay amounts of the delay selection subunit 1511 are set to 256 segments and 128 segments respectively, that is, all or half of the MUXs in the rising edge delay unit 13a are selected to be added to the delay chain. In actual use, the delay amount of the delay selection subunit 1511 can be set as needed, and is not limited to 256 segments and 128 segments in this embodiment. The preset delay subunit 1512 is connected to the output of the RS flip-flop 1514 and delays the output signal of the RS flip-flop 1514 based on the preset delay amount. The preset delay amount is set based on process conditions, and will not be elaborated here. The edge detection subunit 1513 is connected to the output terminal of the preset delay subunit 1512 to perform edge detection on the output signal of the preset delay subunit 1512. The reset terminal RST of the RS flip-flop 1514 is connected to the output terminal of the delay selection subunit 1511, and the set terminal SET is connected to the output terminal of the edge detection subunit 1513, thereby generating the ring oscillation signal calclk.
[0089] More specifically, the calibration module 15 uses the counting clock ck to calibrate the ring oscillator signal calclk. Using the counting clock ck as a reference, it measures the multiple relationship between the counting clock ck and the ring oscillator signal calclk (fck = Fcal * X, where X is the delay of segment 1 and Fcal is the calibration amount). Then, based on the relationship between the counting clock ck and the ring oscillator signal calclk, it compensates the output signal of the high-resolution pulse width modulation signal generation circuit 1 to generate a high-resolution PWM signal. The calibration and calculation of this invention are all implemented in hardware, eliminating the need for CPU calculations and reducing the CPU load. In the calibration module 15, the high-level width of the ring oscillator signal calclk is determined by the delay amount selected by the delay selection subunit 1511, and the low-level width is determined by the delay amount of the preset delay subunit 1512. As an example, firstly, a delay of 256 segments is selected. The calibration calculation unit 152 measures that the 512 division of the ring resonant signal calclk (the division value can be set as needed and is not limited to this embodiment) can be divided into 256 counting clocks ck (CNT). Then, a delay of 128 segments is selected. The calibration calculation unit 152 measures that the 512 division of the ring resonant signal calclk can be divided into 128 counting clocks ck (CNT).
[0090] Let the delay of each segment be X, and the inherent delay be DLY, then we get the following formula:
[0091] (256X+DLY)*512=Tck*CNT256 (1)
[0092] (128X+DLY)*512=Tck*CNT128 (2)
[0093] Where Tck is the period of the counting clock ck, and from these two formulas, we can calculate how many X's equal each ck, and obtain the calibration quantity Fcal satisfying:
[0094] Fcal=Tck / x=512*128 / (CNT256-CNT128).
[0095] In summary, this invention provides a high-resolution pulse width modulation (PWM) signal generation circuit, including a control module, a PWM counting module, a delay module, an output selection module, and a calibration module. The control module receives a control signal and generates a rising edge delay, a falling edge delay, an output selection signal, and a calibration control signal. The PWM counting module receives a counting clock and generates a PWM signal based on the counting clock. The delay module is connected to the outputs of the control module and the PWM counting module, and performs a delay operation on the PWM signal based on the rising edge delay and the falling edge delay. The output selection module is connected to the outputs of the control module, the PWM counting module, and the delay module, and outputs the output signal of either the PWM counting module or the delay module based on the output selection signal. The calibration module is connected to the output of the control module and receives the counting clock. Based on the counting clock, it counts the frequency division signal of the ring oscillation signal of the delay module and calibrates the delay based on the multiple relationship between the ring oscillation signal and the counting clock. The high-level width of the ring oscillation signal is the rising edge delay in the delay module, and the low-level width is a preset width. The high-resolution pulse width modulation (PWM) signal generation circuit of this invention improves the resolution of the PWM signal without changing the counting clock, and can be used to adjust the period and duty cycle of the PWM signal. By measuring the multiple relationship between the counting clock and the delay chain through a calibration circuit, the high-resolution PWM signal generation circuit of this invention can conveniently use the delay module as a lower-level extension of the PWM counting module, facilitating software control and improving the accuracy of high-resolution PWM. The high-resolution PWM signal generation circuit of this invention uses the basic unit device MUX as the smallest delay unit of the delay chain, which also serves as the delay selection logic, reducing the inherent delay from the delay module input to the delay module output, thus helping to reduce delay chain errors. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A high-resolution pulse width modulation signal generation circuit, characterized in that, The high-resolution pulse width modulation signal generation circuit includes at least: Control module, PWM counting module, delay module, output selection module and calibration module; The control module receives control signals and is used to generate rising edge delay, falling edge delay, output selection signal and calibration control signal; The PWM counting module receives a counting clock and generates a PWM signal based on the counting clock. The delay module is connected to the output of the control module and the PWM counting module, and performs a delay operation on the PWM signal based on the rising edge delay and the falling edge delay. The output selection module is connected to the output terminals of the control module, the PWM counting module, and the delay module, and outputs the output signal of the PWM counting module or the delay module based on the output selection signal; The calibration module is connected to the output of the control module and receives the counting clock. Based on the counting clock, it counts the frequency division signal of the ring oscillation signal of the delay module and calibrates the delay amount based on the multiple relationship between the ring oscillation signal and the counting clock. The high-level width of the ring oscillation signal is the rising edge delay in the delay module, and the low-level width is a preset width. The calibration module includes a ring oscillation signal generation unit and a calibration calculation unit. The ring oscillation signal generation unit generates at least two ring oscillation signals of different frequencies. The high-level width of each ring oscillation signal is selected from different delay amounts of the delay module, and the low-level width of each ring oscillation signal is a preset width. The calibration calculation unit divides the ring oscillation signal and counts the frequency division signal based on the counting clock to obtain the multiple relationship between the ring oscillation signal and the counting clock.
2. The high-resolution pulse width modulation signal generation circuit according to claim 1, characterized in that: The control module includes a delay selection register, which outputs the rising edge delay and the falling edge delay based on the delay selection register.
3. The high-resolution pulse width modulation signal generation circuit according to claim 1, characterized in that: The PWM counting module includes a counting unit and a comparison unit; the counting unit receives the counting clock, counts the counting clock and outputs a count value; the comparison unit is connected to the output terminal of the counting unit, compares the count value with a preset value, and flips the level when the count value reaches the preset value to obtain the PWM signal.
4. The high-resolution pulse width modulation signal generation circuit according to claim 3, characterized in that: The PWM counting module also receives a phase adjustment control signal, which is connected to the comparison unit. By changing the preset value, the phase of the PWM signal is adjusted, thereby realizing the pulse frequency modulation function.
5. The high-resolution pulse width modulation signal generation circuit according to claim 1, characterized in that: The delay module includes a rising edge delay unit and a falling edge delay unit; The rising edge delay unit is connected to the output of the PWM counting module and the control module, and performs rising edge delay on the PWM signal based on the rising edge delay amount; the falling edge delay unit is connected to the rising edge delay unit and the output of the control module, and performs falling edge delay on the PWM signal after rising edge delay based on the falling edge delay amount. Alternatively, the falling edge delay unit is connected to the output of the PWM counting module and the control module, and performs a falling edge delay on the PWM signal based on the falling edge delay amount; the rising edge delay unit is connected to the output of the falling edge delay unit and the control module, and performs a rising edge delay on the PWM signal after the falling edge delay based on the rising edge delay amount.
6. The high-resolution pulse width modulation signal generation circuit according to claim 5, characterized in that: Both the rising edge delay unit and the falling edge delay unit include a delay decoder, a delay chain consisting of m sequentially cascaded delay blocks, and an AND / OR logic unit. The delay decoder decodes the delay amount to obtain the delay amount selection signal and the delay block valid signal; The delay chain receives the PWM signal, and each delay block in the delay chain receives the delay amount selection signal and the delay block valid signal, and delays the PWM signal based on the delay amount selection signal and the delay block valid signal; The input terminal of the AND-OR logic unit is connected to the output terminal of the delay chain and the PWM signal. The output signal of the delay chain and the PWM signal are AND-ORed to obtain the delayed signal of the PWM signal. Where m is a natural number greater than or equal to 1.
7. The high-resolution pulse width modulation signal generation circuit according to claim 6, characterized in that: The delay block includes a first to an (n+1)th data selector cascaded in sequence. The first input terminal of the subsequent data selector is connected to the output terminal of the preceding data selector. The second input terminal of each data selector is connected to the PWM signal. The first and second input terminals of the first data selector are connected to the PWM signal. The control terminals of the first to the nth data selector are respectively connected to the corresponding delay amount selection signal. The control terminal of the (n+1)th data selector is connected to the corresponding delay block valid signal. Here, n is a natural number greater than or equal to 1.
8. The high-resolution pulse width modulation signal generation circuit according to claim 7, characterized in that: The data selector is a two-to-one selector.
9. The high-resolution pulse width modulation signal generation circuit according to claim 1, characterized in that: The ring vibration signal generation unit includes a delay selection subunit, a preset delay subunit, an edge detection subunit, and an RS trigger. The delay selection subunit is connected to the output terminal of the RS flip-flop. The delay selection subunit has the same structure as the rising edge delay unit. Based on the calibration control signal, different delay amounts are selected to delay the output signal of the RS flip-flop. The preset delay subunit is connected to the output terminal of the RS flip-flop and delays the output signal of the RS flip-flop based on a preset delay amount; The edge detection subunit is connected to the output terminal of the preset delay unit and performs edge detection on the output signal of the preset delay subunit; The reset terminal of the RS flip-flop is connected to the output terminal of the delay selection subunit, and the set terminal is connected to the output terminal of the edge detection subunit to generate the ring signal.