Reconfigurable ssd storage cluster

Abstract

A solid state drive (SSD) includes a first storage area classified as a byte-addressable NV storage area and a controller communicatively coupled to the first storage area over a bus. The controller detects a reduced storage capacity of the first storage area and, in response to the detection, reclassifies the first storage area as a block-addressable NV storage area. As byte-addressable NV storage areas degrade, the SSD dynamically changes the byte-addressable NV storage areas to block-addressable NV storage areas, thereby extending the useful life of the SSD.

Description

Technical Field

[0001] This invention generally relates to systems and methods for the dynamic reconfiguration of storage protocols for storage areas. Background Technology

[0002] Solid-state drives (SSDs) for storage contain various non-volatile (NV) memory areas where data can be stored. Typically, SSDs store data in addressable NV memory areas implemented using block-addressable NV memory devices such as NAND flash memory. Newer byte-addressable NV memory technologies, such as phase-change memory (PCM), magnetic random access memory (MRAM), and resistive random access memory (ReRAM), are increasingly being used as memory areas within SSDs. Byte-addressable NV memory areas can be written to and read at the single-byte or character level and can be directly overwritten without first being erased, just like block-addressable NAND flash memory. While block-addressable areas can be written to and read only in blocks and are considered highly durable, byte-addressable NV memory can have similar durability, which can be affected by manufacturing complexity and user data workload patterns.

[0003] When a write operation is performed on byte-addressable NV memory, a memory cell is reprogrammed only if a bit changes from 0 to 1 or vice versa (referred to as a "bit flip"). Memory cells degrade as the number of bit flips performed on individual cells increases, and when this number reaches a threshold, the cell may become unusable for storage purposes and may experience errors during read or write operations. As byte-addressable NV memory on an SSD degrades, the memory area may cease to function and become unusable, reducing the total user-available storage. While error-correcting code (ECC) protection bits in the memory can be used to detect and correct bit errors, the byte-addressable NV memory area may become ineffective when the number of erroneous bits in the area exceeds a threshold that limits the error-correcting capability of ECC. Because wear leveling and logic-to-physical address translation for memory cells are typically not performed on byte-addressable NV memory due to the increased read and write latency imposed by this, certain user data workload patterns can cause excessive bit flips in some memory cells, rendering the memory area unusable prematurely.

[0004] Manufacturing byte-addressable NV memory modules can be more difficult than other types of memory modules. During manufacturing, byte-addressable NV memory modules may have a large number of faulty memory cells that cannot be sold or used in products because they fail manufacturing tests, resulting in lower yields and higher overall NV memory module costs. Even if strong ECC logic can correct errors, applying strong logic in the module can increase manufacturing costs and memory access latency to unacceptable levels.

[0005] Therefore, it has long been necessary to improve the availability of byte-addressable NV memory in SSDs by addressing the aforementioned issues. Summary of the Invention

[0006] In one aspect, an SSD enabled to dynamically convert a byte-addressable NV memory area into a block-addressable NV memory area includes a first memory area classified as a byte-addressable NV memory area and a controller communicatively coupled to the first memory area via a bus. The controller detects a reduction in the storage capacity of the first memory area and, in response to the detection, reclassifies the first memory area as a block-addressable NV memory area.

[0007] In another aspect, a method for extending the lifetime of an SSD comprising a first storage area and a controller communicatively coupled to the first storage area includes: detecting, by the controller, a reduction in the storage capacity of the first storage area of ​​the SSD, wherein the first storage area is a byte-addressable NV storage area. The method further includes: in response to the detection, using the controller to reclassify the first storage area as a block-addressable NV storage area. Attached Figure Description

[0008] Figure 1 A block diagram showing an SSD system with byte-addressable NV memory and block-addressable NV memory;

[0009] Figure 2 This demonstrates the decision-making methodology used to determine whether a byte-addressable NV memory area will be reclassified as a block-addressable NV memory area.

[0010] Figure 3 A block diagram showing an SSD system that includes both external and local hosts;

[0011] Figure 4 A flowchart illustrating a method for reclassifying byte-addressable NV memory areas as block-addressable NV memory areas;

[0012] Figure 5 A flowchart illustrating a method for reclassifying byte-addressable NV memory regions as block-addressable NV memory regions based on overwrite occurrences; and

[0013] Figure 6 A flowchart illustrating a method for reclassifying byte-addressable NV memory areas as block-addressable NV memory areas based on the number of errors in the memory area. Detailed Implementation

[0014] SSD availability can be improved by enabling SSDs to dynamically reclassify byte-addressable NV storage areas to block-addressable NV storage when byte-addressable NV storage is degraded. Reclassifying storage areas that are no longer acceptable to byte-addressable NV storage allows SSDs to continue utilizing those areas by making them available to users as block-addressable NV storage areas. U.S. Patent Application No. 16 / 570,521, filed September 13, 2019, entitled "Solid State Drive Supporting Both Byte Addressable Protocol and Block Addressable Protocol," is incorporated herein by reference in its entirety.

[0015] Figure 1 A block diagram of a hybrid SSD system 100 comprising byte-addressable NV memory and block-addressable NV memory is shown. The SSD system supports both byte-addressable and block-addressable protocols, allowing the SSD to process and store data according to both protocols. The SSD system 100 includes an SSD 102 and a host 104 coupled via a bus 106. The SSD 102 includes an SSD controller 108 with ECC logic 112, a processor 113, a metadata register 114, a packet decoder 121, and block-addressable protocol controllers 115 and byte-addressable protocol controllers 116. The SSD 102 also includes an interface 111 and a memory 110 comprising first memory areas 118a to 118n and second memory areas 119a to 119n. The SSD controller 108 is coupled to the memory via one or more memory channels 117 (only a single channel is shown for simplicity). The host 104 includes a host interface 120.

[0016] Channel or bus 106 couples host 104 to SSD 102. Host 104 transmits and receives data packets at host interface 120. The data packets transmitted and received by the host include command packets and data stored in SSD 102, sometimes referred to as command payload.

[0017] SSD controller 108 includes processor 113, which can select a processor for a storage set. Processor 113 determines whether each of the first storage areas 118a to 118n and the second storage areas 119a to 119n is classified as byte-addressable or block-addressable. SSD controller 108 receives commands and data packets at interface 111, and packet decoder 121 determines the transport protocol of the received data packets. Packet decoder 121 classifies and routes incoming data packets and can be implemented in SSD controller 108 or interface 111 as shown. Packet decoder 121 can be implemented as hardware logic in SSD controller 108 or interface 111. After packet decoder 121 determines the transport protocol of the received command, SSD controller 108 and processor 113 process the command by accessing memory 110 containing the first storage areas 118a to 118n and the second storage areas 119a to 119n. For example, SSD controller 108 may receive a command to store byte-addressable data in memory 110. SSD controller 108 and processor 113 may determine that memory area 118a is a byte-addressable NV memory area and that data can be stored there. Alternatively, the data may be block-addressable data, and SSD controller 108 and processor 113 may determine that a second memory area 119a is a block-addressable NV memory and store data in the second memory area 119a. The method by which controller 108 identifies the transmission protocol of the received command and processes the command is further described below.

[0018] The SSD controller 108 maintains a metadata register 114 in the SSD 102 containing a series of byte-addressable NV memory areas (byte-addressable resource sets) and block-addressable NV memory areas (block-addressable resource sets). The metadata register 114 also contains a count of the number of times each of the first memory areas 118a to 118n and the second memory areas 119a to 119n has been overwritten, read, written, erased, and otherwise accessed. The metadata register 114 may also contain other data, such as the number of memory areas or portions of areas marked for erasure during waste collection activities or the number of previous errors in memory areas identified by the ECC logic 112. The ECC logic 112 may be used periodically by the SSD controller 108 to provide, for example, an indication of the number of bit-flipping errors in each memory area and to attempt to correct identified errors. The ECC logic 112 may be able to correct up to a specific number of errors.

[0019] If the number of errors in the memory areas 118a to 118n, classified as byte-addressable by the SSD controller 108 and processor 113, exceeds the number of errors that the ECC logic 112 can correct, then the memory areas can no longer be used as byte-addressable NV storage. Instead, the SSD controller 108 and processor 113 can reclassify the memory areas as block-addressable NV storage areas. For example, if the ECC logic 112 identifies an error count exceeding a threshold in the first memory area 118a, then the SSD controller 108 and processor 113 reclassify the first memory area 118a as block-addressable NV storage and update the memory area classification in the metadata register 114. After reclassification, block-addressable data can be stored in the first memory area 118a.

[0020] Additionally, if the number of reads, writes, erases, or overwrites of the storage area recorded in the metadata register 114 exceeds a threshold, the SSD controller 108 and processor 113 reclassify the first storage area 118a as block-addressable NV storage and update the classification of the first storage area 118a in the metadata register 114. Further reclassification factors and thresholds are discussed below. Figure 2 The threshold number of reads, writes, erases, or overwrites can be predetermined and set by the manufacturer or by the user of the SSD system 100. The threshold number of errors can also be predetermined and set by either the manufacturer or the user.

[0021] SSD controller 108 can be enabled for use with both block-addressable and byte-addressable NV storage and transport protocols. For example, in some implementations, SSD controller 108 is enabled for use with both the Gen-Z byte-addressable protocol and the NVMe Over Fabric block-addressable protocol. SSD controller 108 and host 104 can identify which protocol SSD controller 108 will use to process both block-addressable and byte-addressable transport protocols by encapsulating block-addressable commands and command payloads in byte-addressable command packets and decoding identifiers in the packet header. Packet decoder 121 located in SSD controller 108 or interface 111 can identify and route incoming data packets according to the protocol to be used. In some implementations, vendor-defined operator classes (OpClasses) and operator codes (OpCodes) are used as unique identifiers to indicate whether a packet will be decoded using the Gen-Z type-addressable protocol or the NVMe Over Fabric block-addressable protocol.

[0022] In some implementations, the first storage areas 118a to 118n and the second storage areas 119a to 119n are hybrid memory, such as storage class memory (SCM). In some implementations, the first storage areas 118a to 118n and the second storage areas 119a to 119n are magnetic random access memory (MRAM), resistive random access memory (ReRAM), or phase-change memory (PCM). In some implementations, the SSD 102 may include one or more embedded central processing unit (CPU) cores. The SSD controller 108 may be instantiated as a field-programmable gate array (FPGA), instantiated on a printed circuit board (PCB), or instantiated as an application-specific integrated circuit (ASIC). For example, the SSD controller 108 instantiated on a configurable PCB may include high-endurance SCM controller logic interconnected to the SCM die, as well as reconfigurable FPGA-based block storage protocol features and priority-based storage application acceleration hardware logic, such as copy and ECC and / or erase code logic. In some implementations, the SSD controller 108 and / or processor 113 are implemented as firmware. The SSD controller 108 includes block-addressable protocol encoding and decoding logic, such as NVMe Over Fabric protocol encoding and decoding logic within an ASIC or FPGA. In some implementations, the block-addressable protocol encoding and decoding, such as NVMe Over Fabric protocol encoding and decoding, is performed within the SSD controller 108 in an encoding / decoding acceleration engine that intercepts or receives transmitted commands identified as containing block-addressable protocols. The host 104 also includes embedded CPU resources that enable the host 104 to communicate with the SSD 102 and to encode, decode, and process block-addressable and byte-addressable protocols. In some implementations, a Gen-Z switch facilitates communication between the host 104 and the SSD 102.

[0023] In some implementations, SSD 102 is a member of a storage cluster of multiple SSDs with a direct interface connection to host 104. Host 104 requests access to block-addressable or byte-addressable resources on SSD 102 and other SSDs in the storage cluster based on user application latency priorities. For example, the FPGA-based hardware accelerator and CPU firmware in SSD controller 108 can use byte-addressable resources for data mirroring and copying operations with higher priority and lower latency, but can handle other time-consuming operations such as erasing code logic in block-addressable NV storage resources with lower priority. This capability can be configured via a software API at host interface 120 of host 104. In some implementations, the FPGA-based hardware accelerator can be statically configured during manufacturing or during a scheduled upgrade cycle and can be kept from being reconfigured during user application runtime.

[0024] In some implementations, bus 106 may be configured as a serializer / deserializer (SerDes) link communicatively coupling interface 111 of SSD 102 to host interface 120 of host 104. The SerDes link or interconnect at bus 106 coupling SSD 102 to host 104 is enabled to transmit data packets using byte-addressable and block-addressable transport protocols. For example, in some implementations, the SerDes link is enabled to transmit data packets using the Gen-Z byte-addressable transport protocol and the NVMe Over Fabric block-addressable protocol. SSD controller 108 supports storing data packets using either byte-addressable or block-addressable protocols by allowing byte-addressable commands and block-addressable NVMe Over Fabric protocols to run on the same high-speed SerDes link. SSD controller 108 handles both byte-addressable and block-addressable commands running on the SerDes link channel by enabling dynamic reconfiguration of SSD resources (e.g., reclassification of one or more of the first storage areas 118a to 118n from byte-addressable to block-addressable NV storage areas). SSD controller 108 extends the lifespan of SSD 102 by reconfiguring the byte-addressable resource set area and the block-addressable resource set area by reclassifying the byte-addressable NV storage to block-addressable. As will be discussed below... Figure 2 The description further states that the SSD controller 108 reclassifies byte-addressable NV storage as block-addressable based on manufacturing test data, field estimates based on write counts, number of hard errors, or lifespan / durability conditions of the storage module, or user application resource requirements.

[0025] Enabling dynamic reconfiguration of storage resources can reduce the manufacturing cost of SSDs with this capability. This is because if storage resources in an SSD are manufactured with too many faulty memory cells to be used as byte-addressable NV memory, these resources can be used as block-addressable NV memory, thereby reducing waste and simplifying the manufacturing process. For example, during the final testing phase of multiple storage dies, such as SCM dies, if a particular die is classified as high quality and high durability, the SSD controller 108 classifies the die as a byte-addressable NV memory resource and uses it as such. Alternatively, if a particular die is classified as having lower quality and more memory errors than the number of memory errors recoverable using ECC logic 112, the SSD controller 108 classifies the die as a block-addressable NV memory resource and uses it as such. The SSD controller 108 may record the classification in metadata register 114, in another register, or within the firmware of the SSD controller 108. When classifying dies into portions of byte-addressable or block-addressable resource sets, the durability rating and manufacturing quality of dies during the final manufacturing testing phase utilize all available resources while reducing manufacturing costs.

[0026] During the operational lifetime of SSD 102, byte-addressable NV storage areas that can no longer be used as byte-addressable NV storage can be reclassified as block-addressable NV storage by SSD controller 108. For example, if a particular storage area or die exceeds its endurance cycle or exhibits too many memory errors to be used as byte-addressable NV storage, but can still be corrected to block storage with strong ECC, it can be reclassified as block-addressable NV storage. SSD controller 108 can remove the die in question from the byte-addressable resource set in metadata register 114, but can reuse the same die in the block-addressable resource set. Finally, user applications running on host 104 can dynamically reconfigure the byte-addressable resource set and the block-addressable resource set according to the user application's requirements. For example, a user application may require a larger allocation of fast, low-latency short-term storage compared to slower, longer-term storage. In this case, for that application, the SSD controller can allocate more storage areas classified as byte-addressable NV storage compared to storage areas classified as block-addressable NV storage.

[0027] The controller 108 determines whether to reconfigure or reclassify the byte-addressable NV memory area as block-addressable through its method. Figure 2 Further description is provided below. Figure 2 This paper presents a decision-making method for determining whether a byte-addressable NV memory area will be reclassified as a block-addressable NV memory area.

[0028] In step 202, the method selects processor 113 within the storage set area of ​​the SSD controller 108 to begin processing a specific byte-addressable SSD die or region (e.g., Figure 1 The process begins when one of the first storage areas 118a to 118n or one of the second storage areas 119a to 119n is active. In step 204, it is determined whether the maximum number of write cycles for a specific area, such as storage area 118a, has been reached. The number of write cycles for that area is recorded in a register (e.g., ...). Figure 1 The metadata register 114 is accessed. The number of write cycles for a specific storage region 118a is accessed and compared with the maximum number of write cycles, which can be set by the manufacturer or by the user or user application. If the maximum number of write cycles for a specific SSD storage region 118a has been reached, then in step 206, region 118a is assigned to a block-addressable NV storage set. In step 208, the target metadata is updated in, for example, register 114 to indicate that region 118a will be classified as a block-addressable NV storage set. The method ends in step 210, at which point the storage set selection processor 113 terminates.

[0029] If, instead, the maximum number of write cycles is not reached in step 204, the method continues to step 212. In step 212, it is determined whether the ECC error count threshold has been reached. The number of ECC error counts for a specific region can be stored in register 114, or can be determined by ECC logic (e.g., ...). Figure 1 ECC logic 112 in the controller (e.g., the controller) Figure 1 Other housekeeping logic calculations or tabulations are performed in the SSD controller 108. In some implementations, different byte-addressable NV storage areas may have different assigned ECC error count thresholds. The ECC error count threshold indicates the number of errors that cannot be corrected by the ECC of the byte-addressable NV storage and may be predetermined and set by the manufacturer or by the user or user application. While the ECC error threshold indicates the point in time when the byte-addressable NV storage cannot be corrected by the ECC logic 112, in many block storage applications, errors can be corrected using stronger ECC firmware or hardware logic because much more bits are consumed by block storage application I / O compared to byte-addressable protocols. The increased latency caused by using stronger ECC logic is acceptable in block storage applications because the storage applications have a relatively small amount of frequently accessed "hot" data and a larger amount of infrequently accessed "cold" or "warm" data. If the ECC error count threshold is met, the method continues to steps 206, 208, and 210 to reclassify area 118a as a block-addressable NV storage resource.

[0030] If the ECC error count threshold is not met, the method proceeds instead to step 214. In step 214, controller 108 determines whether the read / write latency threshold for storage area 118a has been reached. The read / write latency of the storage area can be measured by the controller. The read / write latency threshold can be predetermined and set by the manufacturer or by the user or user application. If it is determined that the read / write latency threshold for the storage area has been reached, the method continues with steps 206, 208, and 210 to reclassify area 118a as a block-addressable NV storage resource.

[0031] If the read / write latency threshold is not met, the method proceeds to step 216, where controller 108 determines whether the metadata threshold for storage area 118a has been reached. The metadata threshold can be predetermined and set by the manufacturer or by the user or user application. If the metadata threshold for storage area 118a has been reached, the method continues with steps 206, 208, and 210 to reclassify area 118a as a block-addressable NV storage resource. If the metadata threshold for storage area 118a has not been reached, the method proceeds to step 218.

[0032] In step 218, controller 108 determines whether storage region 118a has been assigned as block storage by a user application. Some user applications may need to utilize block-addressable NV storage, and user applications on the host can pass this requirement to SSD 102 by assigning a storage region or die as block-addressable NV storage. If the user application has already assigned storage region 118a as block storage, the method continues with steps 206, 208, and 210 to reconfigure or reclassify region 118a as block-addressable NV storage. If the user application has not yet assigned storage region 118a as block-addressable, then in step 220, the controller assigns storage region 118a to a byte-addressable NV storage resource set. The controller then updates the target metadata in register 114 accordingly in step 208 and ends in step 210. The updated target metadata from step 208 can be provided to the method as feedback so that the current assignment of storage region 118a is known when method 200 subsequently runs.

[0033] By using various metrics to determine whether storage region 118a or a module has degraded, and if region 118a is degraded, then region 118a is reconfigured as a block-addressable resource. This extends the lifespan of SSD 102 and optimizes resource usage on SSD 102. In most user environments, byte-addressable NV storage will degrade over time and with the number of overwrite cycles, causing portions of the storage module to cease functioning as byte-addressable NV storage after meeting specific usage or lifespan thresholds. This is achieved by... Figure 2The method described in the paper reclassifies storage as block addressable once these thresholds are met, which extends the availability of storage on the SSD 102, even as the availability of byte addressable NV storage decreases.

[0034] Figure 3 The diagram shows an SSD system 300 that includes external and local hosts for long-distance data communication or data replication on additional servers. Figure 3 The SSD 302 in the middle is largely related to Figure 1 The same as described above, and includes an SSD controller 308 with ECC logic 312, a processor 313 such as a memory set selector, a metadata register 314, a packet decoder 321, and a block addressable protocol controller 315 and a byte addressable protocol controller 316. The SSD 302 also includes an interface 311 and a memory 310 including first memory areas 318a to 318n and second memory areas 319a to 319n. The SSD controller 308 is coupled to the memory via one or more memory channels 317. The SSD system 300 supports both byte addressable protocols and block addressable protocols, thereby allowing the SSD 302 to process and store data according to both block and byte addressable protocols, and as described above, the SSD system 300 includes reconfigurable first memory areas 318a to 318n and second memory areas 319a to 319n. As shown, the packet decoder 321, located in the SSD controller 308 or interface 311, can identify and route incoming data packets based on whether the payload will be used to implement or store commands according to block-addressable or byte-addressable protocols. The SSD controller 308 includes a processor 313, which can reassign or reconfigure the first storage areas 318a to 318n and the second storage areas 319a to 319n from byte-addressable NV storage to block-addressable NV storage sets based on wear or degradation characteristics, manufacturing defects, or user application requirements.

[0035] Figure 1 In the diagram, SSD 102 is shown coupled to a single local host 104; however, here, SSD 302 is coupled to local host 330 via a first channel 334 and to external host 328 via a second channel 332. SSD 302 coupled to external host 328 can be used for long-distance data communication or for saving copied data to an external server for later recovery. Although for simplicity... Figure 3 Not shown in the diagram, but local host 330 and external host 328 may contain host interfaces. (See also: Regarding...) Figure 3The first channel 334, communicatively coupling the local host 330 and the SSD 302, can be configured as a high-speed SerDes link running both byte-addressable commands and block-addressable commands. The external host 328 can also be coupled to the SSD 302 via a SerDes link, for example, an Ethernet link running the NVMe / TCP protocol, enabling the SSD controller 308 to support legacy Ethernet-based data center environments. The configurable block and byte-addressable NV storage SSD 302, with byte-addressable and block-addressable commands running on both the SerDes link and the Ethernet link, allows for enhanced remote or replicated storage and efficient communication with multi-data disaster recovery center environments. In another embodiment, the local host 330 and the external host 328 can be connected to the SSD 302 via a high-speed networking structure employing networking switches and routers (not shown for simplicity).

[0036] Typical Ethernet connections supporting NVMe Over Fabric block storage solutions do not include an integrated Ethernet connection with the SSD. Instead, the local host facilitates the switching of NVMe Over Fabric protocols, introducing latency. However, SSDs 302 capable of handling both block-addressable and byte-addressable protocols can include an integrated Ethernet SerDes link 332 within the hybrid SSD 302.

[0037] SSD 302 can be a cluster member of a storage cluster that has a direct connection to the local host 330 via other SerDes links (e.g., via Ethernet) to support existing legacy multi-site data center disaster recovery requirements for other SSDs. For example, user applications can configure byte-addressable resource sets to prioritize high-performance, low-latency burst buffer applications within the data center. User applications can also use block storage resource sets containing storage areas classified as block storage to perform zero-memory replication RDMA operations at another data center via an external SERDES link 332 (e.g., Ethernet) running the NVMe Over Fabric Transmission Control Protocol (NVMe / TCP).

[0038] Figure 4 A flowchart illustrating method 400 for reclassifying byte-addressable NV memory areas as block-addressable NV memory areas is provided. In step 402, the SSD (e.g., Figure 1 SSD 102, Figure 3 The controller in the SSD 302) (e.g., Figure 1 SSD controller 108 in Figure 3 The SSD controller 308 in the SSD detects the first storage area of ​​the SSD (e.g., Figure 1 The first storage area 118a in Figure 3 The reduced storage capacity of the first storage area 318a) in the above text. Figure 1 and 2 The controller 108 may include a processor 113 that acts as a memory set selection processor. A first memory set 118a is initially configured as a byte-addressable NV memory set. The classification of the first memory set 118A may be recorded in registers within the controller 108 (e.g., ...). Figure 1 Metadata register 114 in Figure 3 The metadata register 314 in the SSD 102 contains data that can be shared by one or more hosts (e.g., ...). Figure 1 Host 104 in Figure 3 The local host 330 or external host 328 in the system accesses multiple storage areas (e.g., for storing data) for data storage. Figure 1 First storage area 118a to 118n or second storage area 119a to 119n Figure 3 The first storage area 318a to 318n or the second storage area 319a to 319n in the above text). Figure 2 As will be further described below, the reduced storage capacity may be determined based on a variety of factors, such as write counts to the storage area, the number of errors in the storage area, reclassification of the storage area by user applications, or other factors.

[0039] In step 404, in response to the detection of reduced storage capacity, controller 108 reclassifies the first storage area 118a as a block-addressable NV storage area. In step 406, the controller updates register 114 with the metadata associated with the reclassification of the first storage area 118a as a block-addressable NV storage area. The first storage area 118a then becomes accessible only by block storage. By reconfiguring the storage area as block-addressable NV storage when it becomes unsuitable for use as a byte-addressable NV storage area, the lifetime of storage area 118a and SSD 102 is extended compared to a conventional SSD, in which a storage area unusable as byte-addressable NV storage is simply unusable for any type of storage.

[0040] SSD controller 108 may prioritize data of the aforementioned type, storing it in the remaining byte-addressable NV memory and in the block-addressable NV memory, depending on the intended use of the data from host 104. For example, data requiring low latency and fast processing may be stored in the byte-addressable area, while data tolerating high latency or infrequent access may be stored in the block storage area. For example, data copied for archiving or other "cold" data may be stored in the block-addressable NV memory area of ​​the SSD.

[0041] Figure 5A flowchart illustrates method 500 for reclassifying byte-addressable NV memory areas as block-addressable NV memory areas based on read, write, erase, or overwrite occurrences. For example, some types of SCM storage devices may be prone to read interference errors, while other types of storage devices may have or require erase cycles with separate write or programming cycles. In step 502, the SSD (e.g., Figure 1 SSD 102, Figure 3 The controller in the SSD 302) (e.g., Figure 1 SSD controller 108 in Figure 3 The SSD controller 308 in the SSD detects the first storage area of ​​the SSD (e.g., Figure 1 The first storage area 118a in Figure 3 The first memory area 118a is counted for reads, writes, erases, or overwrites. The first memory area 118a is initially configured as a byte-addressable NV memory area. The classification of the first memory area 118a can be recorded in a register within the controller 108 (e.g., ...). Figure 1 Metadata register 114 in Figure 3 The SSD 102 contains multiple storage areas (e.g., metadata register 314) that can be accessed by one or more hosts 104 for data storage. Figure 1 First storage area 118a to 118n or second storage area 119a to 119n, or Figure 3 The first storage area 318a to 318n or the second storage area 319a to 319n in the memory.

[0042] The occurrence of reads, writes, erases, or overwrites can be stored in register 114 and can be accessed periodically by controller 108 or when another read / write / erase / overwrite event occurs in the first memory area 118a. In some embodiments, other event counts indicating the number of times the first memory area 118a has been accessed can also be recorded and used for reclassification purposes.

[0043] In step 504, controller 108 compares the overwrite occurrence count with a threshold. The threshold may be a predetermined number set by the manufacturer, or it may be a threshold set by the user or a user application. The threshold may be dynamically configurable and may be based on the total number of times SSD 102 has been accessed by host 104.

[0044] In step 506, controller 108 determines the reduced storage capacity of the first storage area 118a of SSD 102 based on a comparison with a threshold. In some embodiments, if the threshold is met, controller 108 determines that the storage capacity has been reduced and needs to be reclassified. In some embodiments, if the threshold is exceeded, controller 108 determines that reclassification is required. In step 508, controller 108 reclassifies the first storage area 118a as a block-addressable NV storage area in response to the determination in step 506. In step 510, controller 108 updates the metadata related to the reclassification of the first storage area 118a as a block-addressable NV storage area in register 114. In step 512, controller 108 then stores the block-addressable data in the first storage area 118a.

[0045] Other indicators can be used by the controller to determine whether a reclassification of the storage area is necessary. For example, Figure 6 A flowchart illustrates method 600 for reclassifying byte-addressable NV memory areas as block-addressable NV memory areas based on the number of errors in the memory area. Errors may be encountered during read, write, erase, overwrite, or other types of access cycles of a memory module that includes byte-addressable NV memory areas. In step 602, the SSD (e.g., Figure 1 SSD 102, Figure 3 The controller in the SSD 302) (e.g., Figure 1 SSD controller 108 in Figure 3 The SSD controller 308 in the SSD 102 detects the first storage area of ​​the SSD 102 (e.g., Figure 1 The first storage area 118a in Figure 3 The number of errors in the first storage area 318a). The first storage area (e.g., storage area 118a) is initially configured as a byte-addressable NV storage area. The classification of the first storage area 118s can be recorded in a register within the controller 108 (e.g., Figure 1 Metadata register 114 in Figure 3 The metadata register 314 in the SSD 102 contains data that can be shared by one or more hosts (e.g., ...). Figure 1 Host 104 in Figure 3 The local host 330 or external host 328 in the system accesses multiple storage areas (e.g., for storing data) for data storage. Figure 1 First storage area 118a to 118n or second storage area 119a to 119n, or Figure 3The first storage area 318a to 318n or the second storage area 319a to 319n in the SSD 102. The number of errors in storage area 118a may be recorded and accessed in register 114 of controller 108, or may be counted during scrap collection or other routine maintenance of SSD 102. The number of errors in storage area 118a may be the number of bit flips or bits stuck at 0 or 1 detected by ECC logic 114. In some embodiments, the number of errors in storage area 118a may be determined periodically or in response to events in storage area 118a, such as requests to access storage area 118a.

[0046] In step 604, controller 108 compares the number of errors in the first storage area 118a with a threshold. The threshold may be a predetermined threshold set by the manufacturer and dependent on the ECC logic 114 available in the SSD 102. The threshold may be the number of errors in storage area 118a at which the ECC logic 114 cannot correct the errors without introducing unacceptable latency into the system. In some embodiments, the threshold is set by the user or a user application. In step 606, controller 108 determines the reduced storage capacity of the first storage area 118a of the SSD 102 as a byte-addressable NV storage area based on the comparison. In some embodiments, controller 108 determines the reduced storage capacity if the number of errors in storage area 118a meets the threshold. In some embodiments, controller 108 determines the reduced storage capacity if the number of errors in storage area 118a exceeds the threshold.

[0047] In step 608, in response to the determination of the reduced storage capacity in step 606, controller 108 reclassifies the first storage area 118a as a block-addressable NV storage area. In step 610, controller 108 updates the metadata related to the reclassification of the first storage area 118a as a block-addressable NV storage area in register 114 of SSD 102. In step 612, controller 108 stores the block-addressable data in the first storage area 118a.

[0048] Dynamic reconfiguration of storage area protocols throughout the lifespan of SSD 102 increases its lifespan by making byte-addressable NV storage areas, which are typically unavailable due to degradation, available as block-addressable high-endurance storage areas. As described above, the reclassification or reconfiguration of available storage areas on SSD 102 can occur during or after manufacturing, or dynamically during the operational lifespan of SSD 102, such as in response to degradation or based on user application resource requirements. Reallocating storage areas throughout the SSD's operational lifespan allows the SSD 102 controller to determine whether storage area 118a is classified as byte storage or block storage based on various factors related to storage area usage and availability, thereby extending storage lifespan and availability.

[0049] Those skilled in the art will appreciate other objects, advantages, and embodiments of the various aspects of the invention, which are within the scope of the description and drawings. For example (but not limitingly), structural or functional elements can be rearranged according to the invention. Similarly, the principles of the invention can be applied to other instances, which, even if not explicitly described in detail herein, will still be within the scope of the invention.

Claims

1. A solid-state drive (SSD) enabled to dynamically convert byte-addressable NV memory into block-addressable NV memory, the SSD comprising: The first storage area is classified as a byte-addressable (NV) storage area; A controller, which is communicatively coupled to the first storage area via a bus, is configured to: Detect the decrease in storage capacity of the first storage area; and In response to the detection, the first storage area is reclassified as a block-addressable NV storage area.

2. The SSD of claim 1, wherein the controller is further configured to update metadata in the controller's registers related to the reclassification of the first storage area as the block-addressable NV storage area.

3. The SSD according to claim 1, further comprising: The second storage area is classified as a byte-addressable (NV) storage area.

4. The SSD of claim 3, wherein the controller is further configured to: Before reclassifying the first storage area as the block-addressable NV storage area, the byte-addressable data in the first storage area is stored in the second storage area.

5. The SSD of claim 4, wherein the controller is further configured to: prior to reclassifying the first storage area as the block-addressable NV storage area. Receive the first byte of addressable data from the host; and The first byte of addressable data is stored in the first storage area.

6. The SSD of claim 5, wherein after reclassifying the first storage area as the block-addressable NV storage area, the controller is further configured to: Receive the first block of addressable data from the host; and The first addressable data is stored in the first storage area.

7. The SSD of claim 1, wherein the controller is further configured to: Determine the overwrite occurrence count at the first storage area; and Compare the overwrite occurrence count with the threshold.

8. The SSD of claim 7, wherein the threshold is a predetermined threshold.

9. The SSD of claim 7, wherein the threshold is set by the host.

10. The SSD of claim 1, wherein the controller is further configured to: Initiate the error correction sequence; Determine the number of errors in the first storage area; and Compare the number of errors with the threshold.

11. The SSD of claim 1, wherein the first storage area is implemented as a phase-change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (ReRAM).

12. A method for extending the lifespan of a solid-state drive (SSD), the SSD including a first storage area and a controller communicatively coupled to the first storage area, the method comprising: The controller detects a decrease in the storage capacity of the first storage area of ​​the SSD, wherein the first storage area is a byte-addressable (NV) storage area; and In response to the detection, the controller reclassifies the first storage area as a block-addressable NV storage area.

13. The method according to claim 12, wherein the method further comprises: Update the metadata related to reclassifying the first storage area as the block-addressable NV storage area in the register of the controller.

14. The method according to claim 12, wherein the method further comprises: Before reclassifying the first storage area as the block-addressable NV storage area, the byte-addressable data in the first storage area is stored in the second storage area of ​​the SSD.

15. The method of claim 14, further comprising: Before the first storage area is reclassified as the block-addressable NV storage area: Receive the first byte of addressable data from the host; and The first byte of addressable data is stored in the first storage area.

16. The method of claim 15, further comprising: After the first storage area is reclassified as the block-addressable NV storage area: Receive the first block of addressable data from the host; and The first addressable data is stored in the first storage area.

17. The method of claim 12, further comprising: The controller determines the overwrite count at the first storage area; and Compare the overwrite occurrence count with the threshold.

18. The method of claim 17, wherein comparing the overwrite occurrence count with the threshold comprises comparing the overwrite occurrence count with a predetermined threshold.

19. The method of claim 17, wherein comparing the overwrite occurrence count with the threshold includes comparing the overwrite occurrence count with a threshold set by the host.

20. The method of claim 12, further comprising: Initiate the error correction sequence; Determine the number of errors in the first storage area; and Compare the number of errors with the threshold.

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