Storage devices and storage systems including storage devices

Abstract

A storage device and a storage system including the same are provided. The storage device includes a nonvolatile memory having a valid page and a free page, a temperature sensor configured to sense a temperature of the nonvolatile memory, and a storage controller configured to implement a patrol reading module configured to read valid data stored in the valid page and identify a number of errors in the read valid data according to a set time period, and a reservation module configured to read the valid data stored in the valid page based on the temperature or the number of errors, and write the valid data to the free page while controlling a threshold voltage distribution width corresponding to a value of the valid data written to the free page.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0175534, filed with the Korean Intellectual Property Office on December 15, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to methods, apparatus, and systems consistent with exemplary embodiments of storage devices. Background Technology

[0004] Flash memory is a type of non-volatile memory that retains stored data even during power outages. Recently, storage devices including flash memory (such as solid-state drives (SSDs) and memory cards) have been widely used. Flash memory stores data by changing the threshold voltage of memory cells and reads data using predetermined read levels. However, due to the degradation of memory cells, the threshold voltage of the memory cells may change over time, potentially leading to read errors. Summary of the Invention

[0005] One or more example embodiments provide a storage device with improved retention performance.

[0006] One or more example embodiments provide a storage system with improved retention performance.

[0007] According to one aspect of an example embodiment, a storage device includes: a non-volatile memory having valid pages and free pages; a temperature sensor configured to sense the temperature of the non-volatile memory; and a storage controller configured to implement: a read-through module configured to read valid data stored in valid pages and identify the number of errors in the read valid data according to a set time period; and a retention module configured to read valid data stored in valid pages based on temperature or the number of errors, and write the valid data to free pages, while controlling a threshold voltage distribution width corresponding to the value of the valid data written to the free pages.

[0008] According to one aspect of an example embodiment, a storage system includes: a host controller configured to receive a reservation level and a reservation mode activation command, and in response to the reservation mode activation command to generate a reservation mode command indicating a reservation level; and a storage controller having a non-volatile memory device having valid pages and free pages, wherein the storage controller is configured to implement a reservation module configured to, in response to the reservation mode command, read valid data stored in a valid page, write the valid data to a free page according to the reservation level, and control a threshold voltage distribution width corresponding to the value of the valid data written to the free page.

[0009] According to one aspect of an example embodiment, a storage system includes: a storage device; a controller configured to monitor a power-off period during which the storage device remains in a power-off state, and to provide a retention mode command to the storage device based on a power-off period being greater than or equal to a set power-off period; and a power supply device configured to supply power to the storage device and the controller. The storage device includes: non-volatile memory including valid pages and free pages; and a storage controller configured to, in response to a retention mode command, read valid data stored in a valid page and write the valid data to a free page.

[0010] The aspects of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art from the following description. Attached Figure Description

[0011] The above and other aspects will become clearer from the following description of exemplary embodiments in conjunction with the accompanying drawings, wherein:

[0012] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment;

[0013] Figure 2 The diagram is based on Figure 1 A block diagram of a non-volatile memory in an example embodiment;

[0014] Figure 3 This is a diagram of a 3D V-NAND structure according to an example embodiment;

[0015] Figure 4 This is a flowchart illustrating the operation of a storage system according to an example embodiment;

[0016] Figure 5 This is a flowchart illustrating the operation of a storage system according to an example embodiment;

[0017] Figures 6 to 8 This is a diagram illustrating the retention operation according to an example embodiment;

[0018] Figure 9 and Figure 10 This is a diagram illustrating the operation of a storage system according to an exemplary embodiment;

[0019] Figure 11 This is a block diagram illustrating a storage system according to an example embodiment;

[0020] Figure 12 This is a block diagram illustrating a storage system according to an example embodiment;

[0021] Figure 13 , Figure 15 and Figure 17 This is a flowchart illustrating the operation of a storage system according to an example embodiment;

[0022] Figure 14 and Figure 16 This is a block diagram illustrating the registers according to an example embodiment;

[0023] Figure 18 This is a block diagram illustrating a storage system according to an example embodiment;

[0024] Figure 19 and Figure 20 This is a flowchart illustrating the operation of a storage system according to an example embodiment;

[0025] Figure 21 This is a diagram illustrating a system that applies a storage system according to an example embodiment;

[0026] Figure 22 This is a diagram illustrating a UFS system according to an example embodiment;

[0027] Figure 23 This is a diagram illustrating a data center using a storage system according to an example embodiment. Detailed Implementation

[0028] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment.

[0029] refer to Figure 1 The storage system 1 according to the example embodiment may include a host 100 and a storage device 200.

[0030] Storage device 200 may include a storage medium for storing data in response to a request from host 100. As an example, storage device 200 may include any or any combination of solid-state drives (SSDs), embedded memory, or removable external memory. When an SSD is provided in storage device 200, storage device 200 may be a standard-compliant device (such as Non-Volatile Memory High Speed ​​(NVMe), SATA, or SAS). When embedded memory or external memory is provided in storage device 200, storage device 200 may be a standard-compliant device (such as Universal Flash Memory (UFS), Embedded Multimedia Card (eMMC), Secure Digital (SD), or other protocols). Host 100 and storage device 200 may each generate and transmit packets according to the standard protocols employed.

[0031] When the non-volatile memory 220 of storage device 200 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 200 may include a variety of other types of non-volatile memory. For example, magnetic RAM (MRAM), spin-torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive memory (resistive RAM), or various other types of memory may be used in storage device 200.

[0032] According to an example embodiment, host 100 may include host controller 110, host memory 120, and host interface 111.

[0033] According to an example embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in an example embodiment, the host controller 110 and the host memory 120 may be integrated into the same semiconductor chip. As an example, the host controller 110 may be any of a plurality of modules provided in an application processor, and the application processor may be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 120 may be embedded memory provided in the application processor or non-volatile memory or memory module disposed outside the application processor.

[0034] The host controller 110 may be equipped with an operating system (OS) and may control the overall operation of the host 100 through the operating system (OS). The operating system (OS) may be any of the following: Windows, Unix, Linux, etc. The host controller 110 may manage operations of storing data (e.g., writing data) from the buffer area 121 into the non-volatile memory 220 or storing data (e.g., reading data) from the non-volatile memory 220 into the buffer area 121.

[0035] Host interface 111 provides a physical connection between host 100 and storage device 200. Host interface 21 can be implemented using various types of interfaces, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI High Speed ​​(PCIe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), and Compact Flash (CF) card.

[0036] The host memory 120 can be used as a buffer memory, working memory, etc., for temporarily storing data to be transferred to or from the storage device 200. For example, the host memory 120 can be implemented as volatile memory (such as DRAM or SRAM) or non-volatile memory (such as PRAM or flash memory).

[0037] Application 122 and storage driver 124 can be implemented in firmware or software and can be loaded into host memory 120. Alternatively, application 122 and / or storage driver 124 can be implemented in hardware.

[0038] Application 122 can correspond to various types of applications installed on host 100 and capable of accessing storage device 200. Application 122 can be an application that provides a reservation mode activation request to storage device 200 to cause storage device 200 to perform a reservation operation. Application 122 can provide a reservation mode activation request to storage device 200 including a reservation level. For example, application 122 can receive input from a user and provide a reservation mode activation request to storage device 200 including a reservation level. The reservation level can be set by the user.

[0039] Storage drive 124 can access storage device 200 upon request from the operating system or application 122. Storage drive 124 can translate the request from application 122 into a command corresponding to storage device 200 to access storage device 200.

[0040] Storage drive 124 may provide storage device 200 with a reservation mode command R_M_CMD, including a reservation level, upon a reservation mode activation request provided from application 122. The reservation mode command R_M_CMD may be a command conforming to host interface 111 and device interface 211. The reservation mode command R_M_CMD may, for example, be one of an input / output command (such as a read command and a write command). As another example, the reservation mode command R_M_CMD may be one of a vendor-specific command through which the manufacturer can define operations. According to an example embodiment, the reservation mode command R_M_CMD may be a vendor command that defines reservation operations based on reservation levels.

[0041] Storage device 200 may include storage controller 210 and non-volatile memory 220.

[0042] The storage controller 210 may include a device interface 211, a memory interface 212, and a central processing unit (CPU) 213. Additionally, the storage controller 210 may also include working memory 214, a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an Advanced Encryption Standard (AES) engine 218.

[0043] Device interface 211 can transmit packets to and receive packets from host 100. Packets transmitted from host 100 to device interface 211 may include commands, data to be written to non-volatile memory 220, etc. Packets transmitted from device interface 211 to host 100 may include responses to commands, data read from non-volatile memory 220, etc. Memory interface 212 can transmit data to non-volatile memory 220 for writing to non-volatile memory 220, or can receive data read from non-volatile memory 220. Memory interface 212 may be implemented in accordance with standards conventions such as Toggle or ONFI.

[0044] Working memory 214 can operate under the control of CPU 213 and can be used as working memory, buffer memory, cache memory, etc. For example, working memory 214 can be implemented as volatile memory (such as DRAM or SRAM) or non-volatile memory, such as PRAM or flash memory.

[0045] A flash transition layer (FTL) 214a can be loaded into working memory 214. Data write and read operations of non-volatile memory 220 can be controlled by CPU 213 executing flash transition layer 214a. Flash transition layer 214a can perform various functions such as address mapping, wear leveling, and garbage collection. Address mapping is the operation of translating logical addresses received from the host into physical addresses used to actually store data in non-volatile memory 220. Wear leveling is a technique that prevents excessive degradation of specific blocks by allowing blocks in non-volatile memory 220 to be used uniformly. For example, wear leveling can be achieved through firmware techniques that balance the erase counts of physical blocks. Garbage collection is a technique used to ensure available capacity in non-volatile memory 220 by copying valid data from blocks to new blocks and erasing existing blocks.

[0046] The reservation module 214b can be implemented in firmware or software and can be loaded into the working memory 214. Alternatively, the reservation module 214b can be implemented in hardware. The reservation module 214b can perform a reservation operation in response to the reservation mode command R_M_CMD. The reservation module 214b can perform the reservation operation based on the reservation level included in the reservation mode command R_M_CMD. Therefore, the reservation module 214b can control the width of the threshold voltage distribution corresponding to the data.

[0047] In other words, in the storage system according to the example embodiment, a retention operation can be performed upon user request. The user can request a retention operation. For example, a retention operation can be requested based on a retention level or according to the conditions of the storage system (such as the storage system being unattended for an extended period).

[0048] The packet manager 215 can generate packets according to the protocol of the interface negotiated with the host 100, or parse various types of information from packets received from the host 100. Furthermore, the buffer memory 216 can temporarily store data to be written to or read from the non-volatile memory 220. The buffer memory 216 can be provided internally to the storage controller 210, or alternatively, externally to the storage controller 210.

[0049] ECC engine 217 can perform error detection and correction functions on read data read from non-volatile memory 220. More specifically, ECC engine 217 can generate parity bits for write data to be written to non-volatile memory 220, and the generated parity bits can be stored in non-volatile memory 220 along with the write data. When reading data from non-volatile memory 220, ECC engine 217 can use the parity bits read from non-volatile memory 220 along with the read data to correct errors in the read data, and can output the error-corrected read data.

[0050] The AES engine 218 can use a symmetric key algorithm to perform either encryption or decryption operations or any combination thereof on the data input to the storage controller 210.

[0051] Figure 2 This is an exemplary block diagram illustrating a non-volatile memory according to an example embodiment.

[0052] refer to Figure 2 The non-volatile memory 220 may include a controller 222, a memory cell array 223, a page buffer unit 224, a voltage generator 225, and a line decoder 226. The non-volatile memory 220 may also include... Figure 1 The memory interface 212 shown may also include column logic, pre-decoder, temperature sensor, command decoder, address decoder, etc.

[0053] The controller 222 can control various operations of the non-volatile memory 220. The controller 222 can output various control signals in response to commands CMD and / or addresses ADDR from the memory interface 212. For example, the controller 222 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0054] The memory cell array 223 may include multiple memory blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 223 can be connected to the page buffer unit 224 via the bit line BL, and can be connected to the line decoder 226 via the word line WL, the serial select line SSL, and the ground select line GSL.

[0055] In an example embodiment, memory cell array 223 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an example embodiment, memory cell array 223 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0056] Page buffer unit 224 may include multiple page buffers PB1 to PBn (where n is an integer equal to or greater than 3), and the multiple page buffers PB1 to PBn may be connected to memory cells via multiple bit lines BL. Page buffer unit 224 may select at least one of the bit lines BL based on the column address Y-ADDR. Depending on the operating mode, page buffer unit 224 may be used as a write driver or a sense amplifier. For example, during a programming operation, page buffer unit 224 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer unit 224 may sense the data stored in the memory cell by sensing the current or voltage of the selected bit line.

[0057] Voltage generator 225 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 225 can generate programming voltage, reading voltage, programming verification voltage, erasing voltage, etc., as word line voltage VWL.

[0058] The line decoder 226 can select one of a plurality of word lines WL and one of a plurality of string select lines SSL based on the line address X-ADDR. For example, during a programming operation, the line decoder 226 can apply a programming voltage and a programming verification voltage to the selected word line, and during a read operation, the line decoder 226 can apply a read voltage to the selected word line.

[0059] Figure 3 This is a diagram illustrating a 3D V-NAND structure according to an example embodiment. When Figure 1 When the non-volatile memory 220 is implemented as a 3D V-NAND type flash memory, the memory cell array 223 constituting the non-volatile memory 220 (see...) Figure 2 Multiple memory blocks BLK1 to BLKz can be freely configured as follows: Figure 3 The equivalent circuit shown is illustrated.

[0060] Figure 3 The memory block BLK1 shown represents a 3D memory block formed in a 3D structure on a substrate. For example, multiple NAND strings included in memory block BLK1 can be formed in a direction perpendicular to the substrate.

[0061] refer to Figure 3 The memory block BLK1 may include multiple memory NAND strings NS11 to NS33 connected between the common source line CSL and bit lines BL1, BL2, and BL3. Each of the multiple memory NAND strings NS11 to NS33 may each include a string select transistor SST, multiple memory cells MC1 to MC8, and a ground select transistor GST. Figure 3 The diagram illustrates that each of the multiple memory NAND strings NS11 to NS33 includes eight memory cells MC1 to MC8, but this disclosure is not necessarily limited thereto.

[0062] The serial select transistor SST can be connected to its corresponding serial select lines SSL1, SSL2, and SSL3. Multiple memory cells MC1 to MC8 can be connected to their corresponding gate lines GTL1 to GTL8. Gate lines GTL1 to GTL8 can correspond to word lines, and some of them can correspond to pseudo-word lines. The ground select transistor GST can be connected to its corresponding ground select lines GSL1, GSL2, and GSL3. The serial select transistor SST can be connected to its corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0063] Word lines at the same height (e.g., WL1) can be connected together, and ground select lines GSL1, GSL2, and GSL3 can be separated from string select lines SSL1, SSL2, and SSL3. Figure 3 In the diagram, memory block BLK1 is shown as connected to eight gate lines GTL1 to GTL8 and three bit lines BL1, BL2, BL3, but is not necessarily limited to this.

[0064] Figure 4 This is a flowchart illustrating the operation of a storage system according to an example embodiment.

[0065] refer to Figure 1 and Figure 4The storage driver 124 can receive a reservation mode activation request including a reservation level (operation S110). A reservation mode activation request including a reservation level can be provided from application 122. The reservation level can be a period of time guaranteeing data stored in the non-volatile memory 220. For example, a first reservation level can indicate a first period of time, and a second reservation level can indicate a second period of time longer than the first period of time. The period of time guaranteeing data can vary depending on the width of the threshold voltage distribution of valid data. In other words, the width of the threshold voltage distribution of valid data can vary depending on the reservation level.

[0066] The storage drive 124 may issue a reservation mode command R_M_CMD, including a reservation level, in response to a reservation mode activation request (operation S120). The storage drive 124 may provide the reservation mode command R_M_CMD to the storage device 200.

[0067] Storage device 200 can perform a reservation operation (operation S130) in response to the reservation mode command R_M_CMD. The reservation operation can be performed based on the reservation level.

[0068] Figure 5 This is a flowchart illustrating the retention operation according to an example embodiment. For example, Figure 4 The hold operation S130 may include Figure 5 The operation shown is illustrated.

[0069] refer to Figure 1 and Figure 5 The non-volatile memory 220 may include at least one active page and at least one free page. The reservation module 214b may perform a reservation operation in response to the reservation mode command R_M_CMD.

[0070] The reserved module 214b can read valid data from the valid pages of the non-volatile memory 220 (operation S132).

[0071] The reservation module 214b can store valid data read from valid pages of non-volatile memory 220 in buffer memory 216 (operation S134).

[0072] The reservation module 214b can program valid data into a free page of the non-volatile memory 220 based on the reservation level included in the reservation mode command R_M_CMD (operation S136). For example, valid data read from a valid page of the first memory block can be written to a free page of a free block different from the first memory block.

[0073] When the number of free pages is less than the number of valid pages in the non-volatile memory 220, the reservation module 214b can generate a free block by performing an erase operation on at least one memory block, and can program valid data into the free pages. Therefore, free pages may be erased, thus causing a garbage collection effect.

[0074] In the non-volatile memory 220, as programming time increases, the width of the threshold voltage distribution can be reduced and retention performance can be improved. Therefore, the retention module 214b can improve retention performance by controlling the width of the threshold voltage distribution, for example, based on the retention level, by controlling the programming time.

[0075] The reservation module 214b can determine whether the valid page in operation S132 is the last valid page (operation S138). If the valid page in operation S132 is the last valid page, the reservation operation can be terminated. On the other hand, if the valid page in operation S132 is not the last valid page, the reservation module 214b can perform operation S132 on the next valid page (operation S139).

[0076] Figures 6 to 8 This is a diagram illustrating the reserved operation according to an example embodiment. Figure 6 This is a diagram illustrating the threshold voltage distribution of memory cells before a hold operation is performed. Figure 7 This is a diagram illustrating the threshold voltage distribution of a memory cell that has performed a retention operation based on a second retention level. Figure 8 This is a graph illustrating the threshold voltage distribution of memory cells that have performed a retention operation based on a first retention level. Figures 6 to 8 In the diagram, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0077] refer to Figure 6 Non-volatile memory 220 (see Figure 1 The memory cells included in the example can be multi-level cells (MLCs) storing 2 bits. However, the example embodiments are not limited to this, and the memory cells can be three-level cells (TLCs) or single-level cells (SLCs). Figure 6 In the diagram, dashed line 10 represents the initial programming threshold voltage distribution of the memory cell, and solid line 20 represents the threshold voltage distribution that changes over time.

[0078] A memory cell can have four states: E, P1, P2, and P3. Each of the four states can be defined as a range of threshold voltage Vth. Each memory cell can be programmed to have a threshold voltage Vth belonging to one of the four states: E, P1, P2, and P3, based on two bits written to it. The four states E, P1, P2, and P3 can be identified using, for example, three read voltages with levels between the four threshold voltage Vth ranges.

[0079] As time passes after a memory cell has been programmed, the threshold voltage distribution of that cell may change due to the cell's physical characteristics or external factors. Specifically, charge loss may occur as time passes after programming, where electrons trapped in the floating gate or tunnel oxide are emitted, leading to a change in the threshold voltage distribution. Furthermore, the tunnel oxide may degrade during repeated operations on the memory cell (such as programming and erasing), further increasing charge loss. This charge loss can lower the threshold voltage. Therefore, the threshold voltage distribution 20 may shift to the left compared to the initial programmed threshold voltage distribution 10.

[0080] refer to Figure 7 and Figure 8 Compared to the threshold voltage distribution 20 of the memory cell before the retention operation, the threshold voltage distributions 30 and 40 of the memory cell after the retention operation can be shifted to the right.

[0081] The widths of the threshold voltage distributions 30 and 40 of the memory cells that have already undergone the hold operation can be smaller than the width of the threshold voltage distribution 20 of the memory cells before the hold operation was performed. Specifically, when the hold operation is performed based on the first hold level, as... Figure 8 As shown, the width of the threshold voltage distribution of the memory cell can be controlled to a second width W2. Furthermore, when a reservation operation is performed based on the second reservation level, as... Figure 7 As shown, the width of the threshold voltage distribution of the memory cell can be controlled to a first width W1.

[0082] A reservation level indicates the period for which the user wishes to guarantee the reliability of data stored in non-volatile memory. A first reservation level can be a first time period, and a second reservation level can be a second time period longer than the first. The second width W2 of the threshold voltage distribution 40 of the memory cell that has performed a reservation operation based on the first reservation level can be greater than the first width W1 of the threshold voltage distribution 30 of the memory cell that has performed a reservation operation based on the second reservation level. Therefore, valid data can be guaranteed for a longer period in the memory cell that has performed a reservation operation based on the second reservation level than in the memory cell that has performed a reservation operation based on the first reservation level.

[0083] In other words, as the hold level increases, the width of the threshold voltage distribution of memory cells that have already performed hold operations based on the hold level can decrease. Conversely, as the hold level increases, the threshold voltage distribution of memory cells that have already performed hold operations based on the hold level can become sharper.

[0084] Figure 9 and Figure 10 It is a diagram. Figure 5 The diagram for operation S136. Figure 9 This diagram illustrates a method for programming valid data in an idle page based on a second reserved level. Figure 10 This diagram illustrates a method for programming valid data in an idle page based on a first reserved level. Figure 9 and Figure 10 In the diagram, the horizontal axis represents time, and the vertical axis represents the programming voltage used during the hold operation.

[0085] refer to Figure 1 , Figure 9 and Figure 10 The reservation module 214b can program valid data in an idle page using, for example, a programming voltage whose voltage level is gradually changed based on the reservation level. For example, the programming voltage could be an incremental step pulse programming (ISPP) voltage with the voltage level increasing gradually.

[0086] refer to Figure 1 and Figure 9 The reservation module 214b can program valid data in an idle page using multiple first programming voltages Vpgm1 to VpgmN. Each increment of the voltage level of the first programming voltages Vpgm1 to VpgmN can be changed by altering the first voltage level ΔVpgm1. The reservation module 214b can apply each of the first programming voltages Vpgm1 to VpgmN and the verification voltage Vvfy1.

[0087] refer to Figure 1 and Figure 10 The reservation module 214b can program valid data in an idle page using multiple second programming voltages Vpgm1 to VpgmM. Each increment of the voltage level of the second programming voltages Vpgm1 to VpgmM can be changed by altering the second voltage level ΔVpgm2. The reservation module 214b can apply each of the second programming voltages Vpgm1 to VpgmM and the verification voltage Vvfy2.

[0088] The first retention level can be a first time period, and the second retention level can be a second time period longer than the first time period. For example, the second voltage level ΔVpgm2 can be greater than the first voltage level ΔVpgm1, and the number of second programming voltages Vpgm1 to VpgmM can be the same as the number of first programming voltages Vpgm1 to VpgmN. M can be the same as N. For example, the second voltage level ΔVpgm2 can be the same as the first voltage level ΔVpgm1, and the number of second programming voltages Vpgm1 to VpgmM can be less than the number of first programming voltages Vpgm1 to VpgmN. M can be less than N.

[0089] Therefore, a memory cell that has already performed a retention operation based on the first retention level can have, for example... Figure 8 The threshold voltage distribution 40, and the memory cell that has already performed a retention operation based on the second retention level can have, for example, Figure 7 The threshold voltage distribution 30. That is, the first width W1 of the threshold voltage distribution of the memory cell that has performed a retention operation based on the second retention level (see Figure 7 The second width W2 can be smaller than the threshold voltage distribution of the memory cell that has already performed a reservation operation based on the first reservation level (see...). Figure 8 Therefore, the retention performance of a memory cell that has already performed a retention operation based on the second retention level can be higher than that of a memory cell that has already performed a retention operation based on the first retention level.

[0090] Figure 11 This is a block diagram illustrating a storage system according to an example embodiment. For simplicity of description, [the following is a simplified description]. Figure 1 The differences will be described in detail.

[0091] refer to Figure 11 In the storage system 2 according to the example embodiment, the storage controller 210 may further include a DRAM interface 241. The storage controller 210 can exchange data with the DRAM 240 through the DRAM interface 241.

[0092] The reservation module 214b can perform a reservation operation in response to the reservation mode command R_M_CMD. Specifically, the reservation module 214b can read valid data from valid pages of the non-volatile memory 220. The reservation module 214b can store the valid data read from valid pages of the non-volatile memory 220 in the DRAM 240. The reservation module 214b can program the valid data stored in the DRAM 240 to free pages of the non-volatile memory 220 based on the reservation level included in the reservation mode command R_M_CMD. Therefore, the reservation module 214b can control the width of the threshold voltage distribution corresponding to the valid data value.

[0093] Figure 12 This is a block diagram illustrating a storage system according to an example embodiment. For simplicity of description, [the following is a simplified description]. Figure 1 The differences will be described in detail. Figure 13 , Figure 15 and Figure 17 The illustration is based on an example embodiment. Figure 12 The flowchart of the operation of the storage system. Figure 14 and Figure 16 The illustration is based on an example embodiment. Figure 12 A block diagram of the registers provided in the memory system.

[0094] refer to Figure 12 and Figure 13 The storage system 3 according to the example embodiment may also include a reading module 214c, a register 219 and a temperature sensor 230.

[0095] Temperature sensor 230 can sense the temperature T of non-volatile memory 220, patrol module 214c can periodically perform patrol operation, and retention module 214b can count the number of errors that occur during patrol operation (operation S210).

[0096] Temperature sensor 230 can be connected to non-volatile memory 220 to sense the temperature T of non-volatile memory 220. Temperature sensor 230 can provide the sensed temperature T to retention module 214b.

[0097] The patrol reading module 214c can be implemented in firmware or software and can be loaded into the working memory 214. Alternatively, the patrol reading module 214c can be implemented in hardware. The patrol reading module 214c can perform patrol reading operations according to a set time period. The set time period can be, for example, a time period set by a setting command provided from the host 100.

[0098] The scan operation can instruct the scan module 214c to read valid data from all valid pages of the non-volatile memory 120 without receiving a read command from the host 100. The scan module 214c can issue a read command and address, and based on the read command and address, can read valid data from all valid pages of the non-volatile memory 120. At this time, the ECC engine 217 can perform error detection and correction functions on the valid data read from the valid pages by the scan module 214c. The retention module 214b can count the number of errors detected during the scan operation.

[0099] The retention module 214b can determine whether the temperature T of the non-volatile memory 220 is greater than or equal to the set temperature Tth or whether the counted number of errors NOE is greater than or equal to the set value Eth during the set time Pth (operation S220). The set time Pth and the set value Eth can be, for example, the time and value set by a setting command provided from the host 100.

[0100] When the temperature T of the non-volatile memory 220 is lower than the set temperature Tth during the set time Pth and the counted number of errors NOE is less than the set value Eth, the retention module 214b can return to operation S210.

[0101] When it is determined that the temperature T of the non-volatile memory 220 is greater than or equal to the set temperature Tth or the counted number of errors NOE is greater than or equal to the set value Eth during the set time Pth, the retention module 214b can determine the retention level (operation S230). The retention module 214b can determine the retention level based on the temperature T of the non-volatile memory 220 maintained within the set time Pth or the counted number of errors NOE.

[0102] refer to Figure 14 Multiple tables 219a and 219b can be stored in register 219. These multiple tables 219a and 219b can be tables stored, for example, by configuration commands provided from host 100.

[0103] The first table 219a can indicate the retention level Lr corresponding to the temperature T of the non-volatile memory 220. The second table 219b can indicate the retention level Lr corresponding to the number of errors NOE that occur during the scan operation.

[0104] The retention module 214b can read the retention level, which depends on the temperature T of the non-volatile memory 220, from the first table 219a. The retention module 214b can also read the retention level based on, for example, the average temperature T of the non-volatile memory 220 during a set time Pth. The retention module 214b can also read the retention level, which depends on the number of errors (NOE) occurring during the scan operation, from the second table 219b to determine the retention level.

[0105] The retention module 214b can perform a retention operation (operation S240) based on a determined retention level. The higher the temperature T of the non-volatile memory 220 and the greater the number of errors (NOE) occurring during the read operation, the more degradation may occur in the memory cells. Therefore, as the temperature T of the non-volatile memory 220 increases and the number of errors (NOE) occurring during the read operation increases, the retention module 214b can control the width of the threshold voltage distribution corresponding to valid data to be smaller. The retention module 214b can control the width of the threshold voltage distribution corresponding to valid data to be smaller by controlling the amount of programming voltage used in the retention operation, programming time, etc. The retention module 214b can perform a reference... Figures 6 to 10 The described retention operation.

[0106] For example, Figure 7 The diagram illustrates the threshold voltage distribution of memory cells that have performed a retention operation based on the first retention level L1 when the temperature T of the non-volatile memory 220 is a first temperature T1, or the threshold voltage distribution of memory cells that have performed a retention operation based on the first retention level L1' when the number of errors NOE occurring in the scan operation is a first value NOE1. In this case, Figure 9 The following method is shown: the reservation module 214b programs valid data in the free page based on the first reservation levels L1 and L1'. Figure 7 The diagram illustrates the threshold voltage distribution of memory cells that have performed retention operations based on the second retention level L2 when the temperature T of the non-volatile memory 220 is a second temperature T2, or the threshold voltage distribution of memory cells that have performed retention operations based on the second retention level L2' when the number of errors NOE occurring in the scan operation is a second value NOE2. In this case, Figure 9 The following method is shown: the reservation module 214b programs valid data in the free page according to the second reservation levels L2 and L2'.

[0107] refer to Figure 7 and Figure 8 The first temperature T1 can be lower than the second temperature T2, and the first value NOE1 can be less than the second value NOE2. The width W1 of the threshold voltage distribution 40 of the memory cells that have performed retention operations based on the second retention levels L2 and L2' can be less than the width W2 of the threshold voltage distribution 30 of the memory cells that have performed retention operations based on the first retention levels L1 and L1'.

[0108] In addition, refer to Figure 9 and Figure 10 As the temperature T of the non-volatile memory 220 increases and / or the number of errors (NOE) occurring during the scan operation increases, the retention module 214b can use a higher programming voltage to program valid data into the free pages.

[0109] Figure 15 This is a block diagram illustrating the operation of a storage system according to an example embodiment.

[0110] refer to Figure 12 and Figure 15 The storage device 200 can be powered by the received power (operation S310). The storage device 200 can receive a power outage period Pp from the host 100 (operation S320). That is, while the storage device 200 is powered on, the host 100 can receive a power outage period Pp, during which the storage device 200 remains in a power-off state. The reservation module 214b can determine whether the power outage period Pp of the storage device 200 is greater than or equal to a set power outage period Pp_th (operation S330). When the power outage period Pp of the storage device 200 is less than the set power outage period Pp_th, the process can return to operation S310.

[0111] When the power-off period Pp of the storage device 200 is determined to be greater than or equal to the set power-off period Pp_th, the reservation module 214b can determine the reservation level (operation S340). The reservation module 214b can determine the reservation level based on the power-off period Pp of the storage device 200. For example, if the power-off period Pp is greater than or equal to the first power-off period Ppf1, then the reservation level can be determined as the first reservation level L1". For example, if the power-off period Pp is greater than or equal to the second power-off period Ppf2, then the reservation level can be determined as the second reservation level L2".

[0112] refer to Figure 16 Register 219 may also include a third table 219c. The third table 219c may be, for example, a table stored by a setting command provided from host 100.

[0113] The third table 219c may include a reservation level Lr depending on the power-off period Pp of the storage device 200. The reservation module 214b can read the reservation level depending on the power-off period Pp of the storage device 200 to determine the reservation level.

[0114] The reservation module 214b can perform a reservation operation (operation S350) based on a determined reservation level. The longer the power-off period Pp of the storage device 200, the more degradation may occur in the memory cells. Therefore, as the power-off period Pp of the storage device 200 increases, the reservation module 214b can control the width of the threshold voltage distribution corresponding to valid data to be smaller. The reservation module 214b can control the width of the threshold voltage distribution corresponding to valid data to be smaller by controlling the amount of programming voltage used in the reservation operation, programming time, etc. The reservation module 214b can perform a reference... Figures 6 to 10 The described retention operation.

[0115] For example, Figure 8 The diagram illustrates the threshold voltage distribution of memory cells that have already performed a retention operation based on the first retention level L1" when the power-off period Pp of storage device 200 is the first power-off period Ppf1. In this case... Figure 10 The following method is shown: the reservation module 214b programs valid data in the free page based on the first reservation level L1". Figure 7 The diagram illustrates the threshold voltage distribution of memory cells that have already performed a retention operation based on the second retention level L2" when the power-off period Pp of storage device 200 is the second power-off period Ppf2. In this case... Figure 9 The following method is shown: the reservation module 214b programs valid data in the free page based on the second reservation level L2".

[0116] refer to Figure 7 and Figure 8 The width W1 of the threshold voltage distribution 40 of the memory cell that has performed a retention operation based on the second retention level L2” can be smaller than the width W2 of the threshold voltage distribution 30 of the memory cell that has performed a retention operation based on the first retention level L1”.

[0117] In addition, refer to Figure 9 and Figure 10 As the power-off period Pp of storage device 200 increases, the reservation module 214b can use more programming voltage to program valid data into the free pages.

[0118] Figure 17 This is a flowchart illustrating the operation of a storage system according to other example embodiments. For simplicity, the following description will focus on the references. Figure 15 The differences in the descriptions.

[0119] refer to Figure 12 and Figure 17 The storage device 200 can be powered by the received power (operation S1710), and can receive the power-on time and power-off time information INF_P of the storage device 200 from the host 100 (operation S1720).

[0120] Storage device 200 can calculate the power outage period Pp by using the power-on time and power-off time information INF_P of storage device 200, during which storage device 200 remains in a power-off state (operation S1725).

[0121] Storage device 200 can compare the power outage period Pp with the set power outage period Pp_th (operation S1730). If the power outage period Pp of storage device 200 is less than the set power outage period Pp_th, then the process can return to operation S1710.

[0122] When the power-off period Pp of the storage device 200 is determined to be greater than or equal to the set power-off period Pp_th, the reservation module 214b can determine the reservation level (operation S1740). The reservation module 214b can perform a reservation operation based on the determined reservation level (operation S1750).

[0123] When retention performance is determined to be degraded, the storage device 200 according to the example embodiment may rewrite the valid data itself to enhance or improve retention performance.

[0124] Figure 18 This is a block diagram illustrating a storage system according to an example embodiment. Figure 19 and Figure 20 It is a diagram. Figure 18 The flowchart of the operation.

[0125] refer to Figure 18 The storage system 4 according to the example embodiment can be a vehicle. The storage system 4 may include a storage device 310, a temperature sensor 315, a controller 320, one or more sensors 330, a communication interface 340, a user interface 350, a first functional block 360, a second functional block 370, and a power supply device 380.

[0126] Storage device 310 can be referenced above. Figures 1 to 17 One of the described storage devices 200.

[0127] Temperature sensor 315 can sense the temperature of storage device 310. The temperature of storage device 310 sensed by temperature sensor 315 can be provided to controller 320.

[0128] Controller 320 can control the overall operation of storage device 4. Controller 320 can control power supply device 380 to supply power to storage device 310, temperature sensor 315, controller 320, one or more sensors 330, communication interface 340, user interface 350, first function block 360, second function block 370, and power supply device 380. Controller 320 can provide hold-up mode commands to storage device 310 based on the temperature of storage device 310 sensed by temperature sensor 315 or the power-off period during which storage device 310 remains in a power-off state.

[0129] Sensor 330 may include one or more camera devices, one or more LiDAR sensors, one or more active scanning devices (such as ultrasonic sensors), and one or more geospatial positioning devices. Sensor 1150 can generate sensing signals by monitoring at least a portion of the external environment surrounding the vehicle.

[0130] The communication interface 340 may include a wireless transceiver and / or a global positioning system (GPS).

[0131] User interface 350 may include a display unit that indicates the vehicle's dashboard. The display unit may display the above reference. Figures 1 to 11 Application 122 as described. (See reference...) Figures 1 to 11 As described, a user can provide a reservation mode activation request, including a reservation level, through the displayed application 122, causing the storage device 310 to perform a reservation operation. Therefore, the controller 320 can provide a reservation mode command, including a reservation level, to the storage device 310.

[0132] The first functional block 360 can execute the first process. The second functional block 370 can execute the second process. The first process and the second process can be different from each other. The first and second processes can refer to, for example, the operation of a vehicle steering device configured to control the direction of the vehicle, a throttle device configured to control acceleration and / or deceleration by controlling the vehicle's motor or engine, a braking device configured to control the braking of the vehicle, external lighting devices, etc.

[0133] refer to Figure 18 and Figure 19 Temperature sensor 315 can sense the temperature T of storage device 310 (operation S410). Controller 320 can determine whether the temperature T of storage device 310 is higher than or equal to the set temperature Tth during a set time Pth (operation S420). When the temperature T of storage device 310 is lower than the set temperature Tth during the set time Pth, the process can return to operation S410.

[0134] When it is determined that the temperature T of storage device 310 is higher than or equal to the set temperature Tth during a set time Pth, controller 320 may determine a hold-in level (operation S430). Controller 320 may include a register in which the hold-in level dependent on the temperature T of storage device 310 is stored. Controller 320 may read the hold-in level dependent on the temperature T of storage device 310 from the register to determine the hold-in level. Controller 320 may issue a hold-in mode command including the hold-in level (operation S440). Storage device 310 may receive the hold-in mode command and perform a hold-in operation (operation S450). The example embodiment is not limited thereto, and controller 320 may issue the hold-in mode command by receiving the temperature T of storage device 310 from a temperature sensor in storage device 310.

[0135] refer to Figure 18 and Figure 20 The controller 320 can sense the power-off period Pp during which the storage device 310 remains in a power-off state (operation S510). If the power-off period Pp of the storage device 310 is less than the set power-off period Pp_th, then the process can return to operation S510.

[0136] When the power-off period Pp of storage device 310 is determined to be greater than or equal to the set power-off period Pp_th, controller 320 can power on storage device 310 (operation S525). Controller 320 can control power supply device 380 to supply power to storage device 310. Controller 320 can determine a reservation level based on power-off period Pp (operation S530). Controller 320 may include a register that stores the reservation level depending on the power-off period Pp of storage device 310. Controller 320 can read the reservation level depending on the power-off period Pp of storage device 310 from the register to determine the reservation level. Controller 320 can issue a reservation mode command including the reservation level (operation S540). Storage device 310 can receive the reservation mode command and perform a reservation operation (operation S550).

[0137] When the vehicle is parked for an extended period, the storage device 310 may be in a power-off state for a prolonged period. Therefore, the retention performance of the storage device 310 may deteriorate. Furthermore, the temperature of the storage device 310 may rise due to the vehicle's environmental conditions, and thus, the retention performance of the storage device 310 may also deteriorate.

[0138] However, in the storage system according to the example embodiment, the retention operation can be performed based on the temperature of the storage device 310 and / or the power outage period of the storage device 310. Furthermore, the retention operation can be performed upon user request. Therefore, the retention performance of the storage device 310 can be improved or enhanced.

[0139] Figure 21 This is a diagram illustrating a system that applies a storage system according to an example embodiment.

[0140] Figure 21 System 1000 can be a mobile system, such as a portable communication terminal (mobile phone), smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. However, the example embodiments are not necessarily limited to mobile systems, and Figure 21 The system 1000 can also be a personal computer, laptop computer, server, media player, automotive equipment (such as navigation system), etc.

[0141] refer to Figure 21 The system 1000 may include a main processor 1100, memories 1200a and 1200b and storage devices 1300a and 1300b, and may also include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470 and a connection interface 1480.

[0142] The main processor 1100 can control the overall operation of the system 1000, and more specifically, the operation of other components constituting the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, an application processor, etc.

[0143] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an example embodiment, the main processor 1100 may also include an accelerator block 1130, which is dedicated circuitry for high-speed data operations, such as artificial intelligence (AI) data operations. The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), etc., and may be implemented as a separate chip physically independent of other components of the main processor 1100.

[0144] Memory 1200a and 1200b can be used as the main memory device of system 1000 and may include volatile memory, such as SRAM and / or DRAM, or may include non-volatile memory, such as flash memory, PRAM and / or RRAM. Memory 1200a and 1200b can be implemented in the same package as main processor 1100.

[0145] Storage devices 1300a and 1300b can be referenced above. Figures 1 to 17 The storage device 200 described.

[0146] Storage devices 1300a and 1300b can be used as non-volatile storage devices for storing data regardless of power supply, and can have a relatively larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b can be used as references. Figures 1 to 17 The storage device 200 described.

[0147] Image capture device 1410 can capture still images or moving pictures (e.g., a series of still images) and can be a camera, camcorder, webcam, etc.

[0148] User input device 1420 can receive various types of data input from the user in system 1000, and can be a touchpad, keypad, keyboard, mouse, microphone, etc.

[0149] Sensor 1430 can sense various types of physical quantities that can be obtained from outside the system 1000, and can convert the sensed physical quantities into electrical signals. Sensor 1430 can be a temperature sensor, pressure sensor, illuminance sensor, position sensor, acceleration sensor, biosensor, gyroscope, etc.

[0150] Communication device 1440 can transmit signals to and receive signals from other devices outside system 1000 according to various communication protocols. Communication device 1440 can be implemented by including antennas, transceivers, modems, etc.

[0151] The display 1450 and the speaker 1460 can be used as output devices to output visual and auditory information to the user of the system 1000, respectively.

[0152] The power supply device 1470 can appropriately convert power supplied from the battery built into the system 1000 and / or an external power source to supply power to each component of the system 1000.

[0153] The connection interface 1480 can provide a connection between the system 1000 and an external device connected to the system 1000 and capable of exchanging data with the system 1000.

[0154] Figure 22 This is a diagram illustrating a UFS system according to an example embodiment. The UFS system 2000 is a system conforming to the UFS standard published by the Joint Electronic Equipment Committee (JEDEC) and may include a UFS host 2100, a UFS device 2200, and a UFS interface 2300. Figure 21 The above description of System 1000 is in relation to Figure 22 The following descriptions may also be applied within the scope of non-conflict. Figure 22 The UFS system 2000.

[0155] refer to Figure 22 UFS host 2100 and UFS device 2200 can interconnect via UFS interface 2300. When Figure 21 When the main processor 1100 is an application processor, the UFS host 2100 can be implemented as part of the corresponding application processor. The UFS host controller 2110 and host memory 2140 can respectively correspond to… Figure 21 The main processor 1100 includes a controller 1120 and memory 1200a and 1200b. The UFS device 2200 can correspond to... Figure 21 Storage devices 1300a and 1300b, and the UFS device controller 2210 and non-volatile memory 2220 can respectively correspond to Figure 21 The storage controllers 1310a and 1310b and the non-volatile memories 1320a and 1320b.

[0156] UFS host 2100 may include UFS host controller 2110, application 2120, UFS driver 2130, host memory 2140, and UFS interconnect (UIC) layer 2150. UFS device 2200 may include UFS device controller 2210, non-volatile memory 2220, storage interface 2230, device memory 2240, UIC layer 2250, and regulator 2260. Non-volatile memory 2220 may be composed of multiple memory cells 2221, and memory cells 2221 may be reference cells. Figure 2 and Figure 3 The described non-volatile memory 220. The UFS device controller 2210 and the non-volatile memory 2220 can be connected to each other via the storage interface 2230.

[0157] Application 2120 may refer to a program that wishes to communicate with UFS device 2200 in order to use the functions of UFS device 2200. Application 2120 may transmit input / output requests (IORs) to UFS drive 2130 for input / output to UFS device 2200.

[0158] UFS drive 2130 can manage UFS host controller 2110 via UFS-HCI (Host Controller Interface). UFS drive 2130 can translate input / output requests generated by application 2120 into UFS commands defined by the UFS standard and transmit the translated UFS commands to UFS host controller 2110. One input / output request can be translated into multiple UFS commands. UFS commands can be defined by the SCSI standard, or they can be UFS-only commands.

[0159] The UFS host controller 2110 can transmit UFS commands translated by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 via the UIC layer 2150 and the UFS interface 2300. In this process, the UFS host register 2111 of the UFS host controller 2110 can be used as a command queue (CQ).

[0160] The UIC layer 2150 of the UFS host 2100 may include MIPI M-PHY 2151 and MIPI UniPro 2152, and the UIC layer 2250 of the UFS device 2200 may include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0161] The UFS interface 2300 may include a line for transmitting a reference clock REF_CLK, a line for transmitting a hardware reset signal RESET_n for the UFS device 2200, a pair of lines for transmitting differential input signal pairs DIN_t and DIN_c, and a pair of lines for transmitting differential output signal pairs DOUT_t and DOUT_c.

[0162] The UFS device controller 2210 of the UFS device 2200 can control the overall operation of the UFS device 2200. The UFS device controller 2210 can manage the non-volatile memory 2220 through logic units (LUs) 2211, which are logical data storage units. The number of LUs 2211 can be eight, but is not limited to this.

[0163] The UFS device controller 2210 may include working memory 2212, in which the reservation module 2212a is driven. The reservation module 2212a and the non-volatile memory 2220 may be as described above. Figures 1 to 17 The described reserved module 214a and non-volatile memory 220.

[0164] The UFS host 2100 can sequentially store commands to be transmitted to the UFS device 2200 in a UFS host register 2111 that can be used as a command queue, and transmit the commands to the UFS device 2200 in the above order. At this time, even while a previously transmitted command is still being processed by the UFS device 2200, that is, even before receiving notification that a previously transmitted command has been processed by the UFS device 2200, the UFS host 2100 can transmit the next command waiting in the command queue to the UFS device 2200. Therefore, even while processing a previously transmitted command, the UFS device 2200 can receive the next command from the UFS host 2100. Multiple memory units 2221 can be referenced above. Figure 2 and Figure 3 The non-volatile memory 220 is described.

[0165] Figure 23 This is a diagram illustrating a data center using a storage system according to an example embodiment.

[0166] refer to Figure 23Data center 3000 is a facility that collects and provides services for various types of data, and may be referred to as a data storage center. Data center 3000 may be a system for operating search engines and databases, or it may be a computing system used in government agencies or companies (such as banks). Data center 3000 may include application servers 3100 to 3100n, storage servers 3200 to 3200m, and archive storage servers 3300. The number of application servers 3100 to 3100n, the number of storage servers 3200 to 3200m, and the number of archive storage servers 3300 may be varied according to exemplary embodiments, and the number of application servers 3100 to 3100n, the number of storage servers 3200 to 3200m, and the number of archive storage servers 3300 may differ from each other.

[0167] Application server 3100, storage server 3200, and file storage server 3300 may include at least one of processors 3110, 3210, 3310, or memory 3120, 3220, 3320. When storage server 3200 is described by way of example, processor 3210 may control the overall operation of storage server 3200 and access memory 3220 to execute instructions and / or data loaded in memory 3220. Memory 3220 may be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVMDIMM). According to example embodiments, the number of processors 3210 and the number of memory 3220 included in storage server 3200 may be selected differently. In example embodiments, processors 3210 and memory 3220 may be provided as a processor-memory pair. In example embodiments, the number of processors 3210 and the number of memory 3220 may be different. Processor 3210 may include a single-core processor or a multi-core processor. The above description of storage server 3200 can be similarly applied to application server 3100. According to an example embodiment, application server 3100 may not include storage device 3150. Storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 included in storage server 3200 may be selected differently depending on the example embodiment. Controllers 3251, 3351, NAND 3252, 3352, DRAM 3253, 3353, and interfaces 3254, 3354 may be referenced above. Figures 1 to 17 The described storage controller 210, non-volatile memory 220, buffer memory 216, and device interface 211.

[0168] Application servers 3100 to 3100n, storage servers 3200 to 3200m, and archive storage server 3300 can communicate with each other via network 1300. Network 1300 can be implemented using Fibre Channel (FC), Ethernet, etc. In this case, FC can be a medium for relatively high-speed data transmission, and an optical switch providing high performance / high availability can be used. Depending on the access method of network 1300, storage servers 3200 to 3200m can be provided as file storage devices, block storage devices, or object storage devices.

[0169] In an example embodiment, network 1300 may be a storage-only network, such as a storage area network (SAN). As an example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In yet another example embodiment, network 1300 may be a general-purpose network, such as a TCP / IP network. For example, network 1300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), NVMe on a fabric (NVMe-oF), etc.

[0170] The following text will focus on describing application server 3100 and storage server 3200. The description of application server 3100 can also be applied to another application server 3100n, and the description of storage server 3200 can also be applied to another storage server 3200m.

[0171] Application server 3100 can store data requested by users or clients in one of storage servers 3200 to 3200m via network 1300. Furthermore, application server 3100 can retrieve data requested by users or clients from one of storage servers 3200 to 3200m via network 1300. For example, application server 3100 can be implemented as a web server, a database management system (DBMS), etc.

[0172] Application server 3100 can access the memory 3120n or storage device 3150n included in another application server 3100n via network 1300, or access the memory 3220 to 3220m or storage device 3250 to 3250m included in storage servers 3200 to 3200m via network 1300. Therefore, application server 3100 can perform various operations on the data stored in application servers 3100 to 3100n and / or storage servers 3200 to 3200m. For example, application server 3100 can execute commands for moving or copying data between application servers 3100 to 3100n and / or storage servers 3200 to 3200m. At this time, data can be transferred directly from storage devices 3250 to 3250m of storage servers 3200 to 3200m or via storage devices 3220 to 3220m of storage servers 3200 to 3200m to storage devices 3120 to 3120n of application servers 3100 to 3100n. Data moved via network 1300 can be encrypted data for security or privacy purposes.

[0173] The archive storage server 3300 can be used as a secondary storage server for cold storage. Therefore, compared to storage servers 3200 to 3200m, the access frequency can be lower and the power outage period can be longer.

[0174] Switches 3230 and 3330 can selectively connect processors 3210 and 3310 to storage devices 3250 and 3350 under the control of processors 3210 and 3310, or selectively connect NICs 3240 and 3340 to storage devices 3250 and 3350.

[0175] The power supply device 3400 can supply power to application servers 3100 to 3100n, storage servers 3200 to 3200m, and archive storage server 3300.

[0176] The data center 3000 may also include an archive storage server 3300 and a power supply unit 3400. The archive storage server 3300 can be used as a secondary storage server for cold storage. In addition, the archive storage server 3300 can store data that requires permanent or long-term storage, such as raw data.

[0177] In the data center 3000 according to the example embodiment, the file storage server 3300 can perform the operations described in the above reference. Figures 1 to 17 The retention operation described herein can therefore enhance or improve the retention performance of the file storage server 3300.

[0178] According to an example embodiment, at least one of the components, elements, modules, or units (collectively referred to as "components" in this paragraph) indicated by the blocks in the drawings can be specifically implemented as various numbers of hardware, software, and / or firmware structures that perform the corresponding functions described above. These components may include, for example... Figure 2 , Figure 12 and Figure 18 The FTL 214a, reservation module 214b, patrol module 214c, group manager 215, ECC 217, AES 218, controller 222, controller 320, first function block 360, and second function block 370 shown are illustrated, but are not limited thereto. At least one of these components may use a direct circuit structure, such as a memory, processor, logic circuit, lookup table, etc., which can perform a corresponding function under the control of one or more microprocessors or other control devices. Furthermore, at least one of these components may be specifically implemented as a module, program, or part of code containing one or more executable instructions for performing a specified logical function, and executed by one or more microprocessors or other control devices. Additionally, at least one of these components may include or be implemented by a processor, such as a central processing unit (CPU), microprocessor, etc., that performs the corresponding function. Two or more of these components may be combined into a single component, which performs all the operations or functions of the combined two or more components. Furthermore, at least a portion of the function of at least one of these components may be performed by another of these components.

[0179] It will also be understood that, although in example embodiments related to a method or flowchart a step or operation is described after another step or operation, a step or operation may be performed before the other step or operation unless the other step or operation is described as being performed before the step or operation.

[0180] Although exemplary embodiments have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure.

Claims

1. A storage device, comprising: Non-volatile memory, which includes valid pages and free pages; A temperature sensor configured to sense the temperature of the non-volatile memory; as well as A storage controller includes at least one processor configured to control: The patrol reading module reads valid data stored in the valid page and identifies the number of errors in the read valid data according to a set time period. as well as The retention module reads the valid data stored in the valid page based on the temperature or the number of errors, and writes the valid data into the free page while controlling the threshold voltage distribution width corresponding to the value of the valid data written to the free page. The at least one processor is further configured to control the reservation module to: Based on the condition that the temperature is higher than or equal to a first temperature and lower than or equal to a second temperature within a set time period, the read valid data is written to the free page while the threshold voltage distribution width corresponding to the value of the valid data written to the free page is controlled to a first width. Based on the count of errors as a first value, the valid data read is written to the free page while the threshold voltage distribution width corresponding to the value of the valid data written to the free page is controlled to the first width. Based on the fact that the temperature is higher than the second temperature within the set time, while controlling the threshold voltage distribution width corresponding to the value of the valid data written to the free page to the second width, the read valid data is written to the free page, and Based on the number of errors being a second value, while controlling the threshold voltage distribution width corresponding to the value of the valid data written to the free page to the second width, the read valid data is written to the free page. Wherein, the first value is less than the second value, and Wherein, the first width is greater than the second width.

2. The storage device according to claim 1, wherein, The storage controller includes a buffer memory, and The at least one processor is further configured to control the reservation module to store the valid data read from the valid page in the buffer memory, and to write the valid data stored in the buffer memory into the free page.

3. The storage device according to claim 2, wherein, The non-volatile memory includes a first memory block and a second memory block separate from the first memory block, and The valid pages are provided in the first memory block and the free pages are provided in the second memory block.

4. The storage device according to claim 1, wherein, The storage device is also configured to receive a power outage period corresponding to the storage device, and The at least one processor is further configured to control the reservation module to read the valid data stored in the valid page based on the power outage period, and to write the read valid data into the free page while controlling the threshold voltage distribution width corresponding to the value of the valid data written into the free page.

5. The storage device according to claim 4, wherein, The at least one processor is further configured to control the reservation module to read the valid data stored in the valid page and write the valid data into the free page, based on the power outage period being greater than or equal to a set power outage period.

6. The storage device according to claim 1, wherein, The at least one processor is further configured to control the reservation module to read the valid data stored in the valid page, and to write the read valid data into the free page while controlling the threshold voltage distribution width corresponding to the value of the valid data written into the free page, based on the temperature being higher than or equal to a set temperature within a set time or the number of errors being greater than or equal to a set value.

7. The storage device according to claim 1, wherein, The at least one processor is also configured to control the reservation module to control the threshold voltage distribution width by writing the read valid data to the free page using a programming voltage whose voltage level is changed in a stepwise manner.

8. The storage device according to claim 7, wherein, The at least one processor is also configured to control the reservation module to: Based on the condition that the temperature is higher than or equal to a first temperature and lower than or equal to a second temperature within a set time period, a first programming voltage whose voltage level is gradually changed is used to write the read valid data into the free page, so that the threshold voltage distribution width corresponding to the value of the valid data written into the free page is controlled to a first width. Based on the number of errors as a first value, the read valid data is written to the free page using a first programming voltage whose voltage level is gradually changed, so that the threshold voltage distribution width corresponding to the value of the valid data written to the free page is controlled to the first width. Based on the fact that the temperature is higher than the second temperature within the set time, the read valid data is written to the free page using a second programming voltage whose voltage level is gradually changed, so as to control the threshold voltage distribution width corresponding to the value of the valid data written to the free page to a second width, and Based on the number of errors as a second value, the valid data read is written to the free page using a second programming voltage whose voltage level is gradually changed, so that the threshold voltage distribution width corresponding to the value of the valid data written to the free page is controlled to the second width. Wherein, the first value is less than the second value, and The first programming voltage includes fewer steps than the second programming voltage.

9. The storage device according to claim 7, wherein, The at least one processor is also configured to control the reservation module to: Based on the temperature being a first temperature, a first programming voltage, whose voltage level is gradually changed, is used to write the read valid data into the free page, so that the threshold voltage distribution width corresponding to the value of the valid data written into the free page is controlled to a first width. Based on the number of errors as a first value, the first programming voltage, whose voltage level is gradually changed by the first voltage level, is used to write the read valid data into the free page, so that the threshold voltage distribution width corresponding to the value of the valid data written into the free page is controlled to the first width. Based on the temperature being a second temperature, a second programming voltage, whose voltage level is gradually changed, is used to write the read valid data into the free page, so that the threshold voltage distribution width corresponding to the value of the valid data written into the free page is controlled to a second width, and Based on the number of errors as a second value, the second programming voltage, whose voltage level is gradually changed, is used to write the read valid data into the free page, so that the threshold voltage distribution width corresponding to the value of the valid data written into the free page is controlled to the second width. Wherein, the first temperature is lower than the second temperature. Wherein, the first value is less than the second value, and Wherein, the first voltage level is greater than the second voltage level.

10. A storage system, comprising: The host controller is configured to receive a hold level and a hold mode activation command, and in response to the hold mode activation command generate a hold mode command indicating the hold level; as well as A storage controller includes at least one processor and a non-volatile memory device, the non-volatile memory device including valid pages and free pages, wherein the at least one processor is configured to control a reservation module to read valid data stored in the valid pages in response to a reservation mode command, and to write the valid data into the free pages according to the reservation level while controlling a threshold voltage distribution width corresponding to the value of the valid data written into the free pages. The retention mode command includes a first retention mode command indicating a first retention level and a second retention mode command indicating a second retention level. The first retention mode command is generated based on the power-off period of the non-volatile memory device being a first preset power-off period, and the second retention mode command is generated based on the power-off period being a second preset power-off period. The first preset power-off period is shorter than the second preset power-off period. The at least one processor is further configured to write the valid data into the free page according to a first reserved level while controlling the threshold voltage distribution width corresponding to the value of the valid data written into the free page to a first width, and to write the valid data into the free page according to a second reserved level while controlling the threshold voltage distribution width corresponding to the value of the valid data written into the free page to a second width, wherein the first width is greater than the second width.

11. The storage system according to claim 10, wherein, The at least one processor is further configured to control the reservation module to write read valid data into the free page using a programming voltage whose voltage level is changed in a stepwise manner according to the reservation level, thereby controlling the threshold voltage distribution width corresponding to the value of the valid data written into the free page.

12. The storage system according to claim 10, wherein, The storage controller also includes a buffer memory, and The at least one processor is further configured to control the reservation module to store the valid data read from the valid page in the buffer memory, and to write the valid data stored in the buffer memory into the free page.

13. The storage system according to claim 10, wherein, The threshold voltage distribution width corresponding to the value of the valid data stored in the valid page is wider than the threshold voltage distribution width corresponding to the value of the valid data written to the free page.

14. A storage system, comprising: Storage devices; A controller is configured to monitor the power outage period during which the storage device remains in a power-off state, and to provide a retention mode command to the storage device based on the power outage period being greater than or equal to a set power outage period. Specifically, a first retention mode command is provided to the storage device based on the power outage period being a first set power outage period, and a second retention mode command is provided to the storage device based on the power outage period being a second set power outage period. The first retention mode command indicates a first retention level, and the second retention mode command indicates a second retention level. The first set power outage period is shorter than the second set power outage period. A power supply device is configured to supply power to the storage device and the controller. The storage device includes: Non-volatile memory, including valid pages and free pages; and The storage controller is configured to, in response to the reservation mode command, read valid data stored in the valid pages, and, while controlling the threshold voltage distribution width corresponding to the value of the valid data written to the free pages, write the valid data to the free pages according to the reservation level. The storage controller is further configured to write the valid data into the free page according to the first reservation level, so as to control the threshold voltage distribution width corresponding to the value of the valid data written into the free page to a first width, and to write the valid data into the free page according to the second reservation level, so as to control the threshold voltage distribution width corresponding to the value of the valid data written into the free page to a second width, wherein the first width is greater than the second width.

15. The storage system according to claim 14, wherein, The controller is also configured to control the power supply device to supply power to the storage device and provide the retention mode command to the storage device based on the power outage period being greater than or equal to the set power outage period.

16. The storage system of claim 14, further comprising a temperature sensor configured to sense the temperature of the storage device. in, The controller is also configured to provide the retention mode command to the storage device based on the temperature being higher than or equal to a set temperature within a set time period.

17. The storage system according to claim 16, wherein, The controller is also configured to identify a retention level based on the temperature and to provide the storage device with a retention mode command indicating the retention level. The storage controller is further configured to write the valid page to the free page according to the reservation level, thereby controlling the threshold voltage distribution width corresponding to the value of the valid data written to the free page.

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