Data driver circuit

Abstract

The present disclosure relates to a data driver circuit capable of overcoming a frequency limitation by correcting a skew between a clock and data even if the number of frequencies and channels increases, and the data driver circuit according to an aspect can include a shift register configured to output a sampling signal in response to a clock, a first latch part configured to sample and latch data for each channel in response to each sampling signal, and a bidirectional skew buffer part provided between a stage of a first channel and a stage of a second channel belonging to the shift register and between a first latch of the first channel and a first latch of the second channel belonging to the first latch part, and configured to buffer a clock input from the stage of the first channel to output the buffered clock to the stage of the second channel, and to buffer and latch data of the second channel input after data of the first channel latched by the first latch of the first channel in synchronization with the buffered clock to output the latched data to the first latch of the second channel.

Description

Technical Field

[0001] This disclosure relates to a data driver circuit that can correct the skew between clock and data even as the frequency and number of channels increase. Background Technology

[0002] The display device includes a panel configured to display an image via a pixel matrix, a gating driver circuit configured to drive gating lines of the panel, a data driver circuit configured to provide data signals to data lines of the panel, and a timing controller configured to control the gating driver circuit and the data driver circuit.

[0003] The data driver circuit can sequentially latch the image data provided by the timing controller for each horizontal time period, simultaneously convert the latched data segments of each horizontal line into analog data signals, and output the converted data signals to the data lines on the panel respectively.

[0004] As display devices evolve towards higher resolutions, there is a need to increase the driving frequency of data driver circuits and the number of output channels.

[0005] However, when the length of the chip increases due to the increase in the number of output channels, the increased length of the data path in the channel region can cause a deviation between the clock and the data, resulting in data sampling errors and thus limiting the ability to increase the frequency. Summary of the Invention

[0006] This disclosure aims to provide a data driver circuit that can overcome frequency limitations by correcting the deviation between the clock and data, even as the frequency and number of channels increase.

[0007] According to one aspect of this disclosure, a data driver circuit is provided, comprising: a shift register configured to output a sampling signal in response to a clock; a first latch configured to sample and latch data for each channel in response to each of the sampling signals; and a bidirectional de-skew buffer disposed between a stage of a first channel belonging to the shift register and a stage of a second channel, and between a first latch of the first channel belonging to the first latch and a first latch of the second channel, and configured to buffer a clock input from a stage of the first channel to output a buffered clock to a stage of the second channel, and to buffer and latch data input to the second channel synchronously with the buffered clock after the data of the first channel latched by the first latch of the first channel, to output latched data to the first latch of the second channel.

[0008] The bidirectional de-skew buffer section may include: a clock buffer configured to buffer the clock provided from the first channel stage of the shift register and output the buffered clock to the second channel stage; and a data buffer section configured to buffer and latch the data of the second channel input through the first latch of the first channel of the first latch section in sync with the clock output from the clock buffer, and output the latched data to the first latch of the second channel.

[0009] Each of the multiple bits of data buffers and clock buffers constituting the data buffer section may include: an input switch section including a first switch and a second switch connected in series between the first supply line and the second supply line and configured to determine an input direction or a latching operation; an output switch section including a third switch and a fourth switch connected in series between the first supply line and the second supply line and configured to determine an output direction or a latching operation; and a buffer section connected between a first connection node between the first switch and the second switch and a second connection node between the third switch and the fourth switch.

[0010] The shift register and the first latch can be divided into multiple channel blocks, and a bidirectional de-bias buffer can be disposed between the multiple channel blocks. The multiple channel blocks of the shift register and the first latch, as well as the bidirectional de-bias buffer between the multiple channel blocks, can be sequentially activated from an inactive state. When the first latch latches all data segments of the multiple channel blocks, the multiple channel blocks and the bidirectional de-bias buffer can be deactivated.

[0011] The data driver circuit may further include: a second latch, which is configured to simultaneously receive and latch data segments of multiple channels latched in the first latch, and output the latched data segments in response to a load signal, wherein the clock buffer of the bidirectional deflection buffer can be enabled in response to a carry signal received from the first channel stage of the shift register, and can be disabled in response to a load signal of the second latch, and the data buffer of the bidirectional deflection buffer can be enabled or disabled according to the output of the clock buffer.

[0012] The clock buffer may include: an input switch section comprising a first A switch and a second A switch connected in series between a first clock supply line connected to a first channel stage of the shift register and a second clock supply line connected to a second channel stage of the shift register; an output switch section comprising a third A switch and a fourth A switch connected in series between the first clock supply line and the second clock supply line; a buffer section connected between a first A connection node between the first A switch and the second A switch and a second A connection node between the third A switch and the fourth A switch; and an SR latch circuit configured to receive and latch a carry signal and a load signal received from the first channel stage as a set signal and a reset signal, respectively, and output the set signal and the reset signal to the buffer section.

[0013] The buffer section of the clock buffer may include a first inverter (1A) connected to a first connection node (1A); and a NAND gate circuit configured to receive the output of the first inverter (1A) and the output of the SR latch circuit, perform NAND gate logic operations, and output the operation result to a second connection node (2A). The buffer section of the clock buffer may also include a second inverter (2A) configured to receive the output of the second connection node (2A), generate a data enable signal, and output the data enable signal to the data buffer.

[0014] Each of the multiple bits of the data buffer constituting the data buffer section may include: an input switch section including a 1B switch and a 2B switch connected in series between a first data supply line connected to a first latch of a first channel and a second data supply line connected to a first latch of a second channel; an output switch section including a 3B switch and a 4B switch connected in series between the first data supply line and the second data supply line; and a buffer section including a 1B inverter and a 2B inverter connected in series between a 1B connection node between the 1B switch and the 2B switch and a 2B connection node between the 3B switch and the 4B switch.

[0015] The data driver circuit may include: a channel region, in which a shift register, a first latch, a bidirectional de-skew buffer, a second latch, a digital-to-analog converter, and an output buffer are disposed; an output pad region configured to output data signals provided from the channel region to multiple output channels; an input pad region configured to receive transmission signals; a receiver disposed adjacent to the input pad region and configured to receive transmission signals through the input pad region, and recover clock, data, and control signals from the received transmission signals to output the recovered clock, data, and control signals; and a logic controller disposed adjacent to the receiver and the channel region and located between the receiver and the channel region, and configured to send clock and control signals provided from the receiver to the channel region, and rearrange data for each channel to provide data to the channel region.

[0016] The logic controller may include a first logic controller and a second logic controller respectively disposed adjacent to two side surface portions of the channel region, with the channel region located therebetween. The receiver may include a first receiver and a second receiver respectively disposed adjacent to the first and second logic controllers. The input pad region may include a first input pad region and a second input pad region disposed on two side surface portions of the data driver circuitry, adjacent to the first and second receivers respectively. The output pad region may be disposed at the lower end portion of each of the input pad region, receiver, logic controller, and channel region.

[0017] According to another aspect of this disclosure, a data driver circuit including a bidirectional de-skew buffer is provided. The bidirectional de-skew buffer is disposed between a stage of a first channel and a stage of a second channel belonging to a shift register, and between a first latch of a first channel and a first latch of a second channel belonging to a first latch. The bidirectional de-skew buffer may include: a clock buffer configured to buffer a clock input from a stage of the first channel and output the buffered clock to a stage of the second channel; and a data buffer configured to buffer and latch data input to the second channel after the data of the first channel latched by the first latch of the first channel is latched, synchronously with the clock output from the clock buffer, and output the latched data to the first latch of the second channel. Attached Figure Description

[0018] The accompanying drawings, included to provide a further understanding of the present disclosure and incorporated into and constituting a part of this application, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings: Figure 1This is a block diagram that schematically illustrates the configuration of a display device according to one embodiment; Figure 2 This is a block diagram illustrating a display device having a data driver integrated circuit (IC) according to one embodiment; Figure 3 This is a block diagram illustrating the internal configuration of a data driver IC according to one implementation. Figure 4 This is a block diagram illustrating the arrangement of a data driver IC according to one embodiment; Figure 5 This is an equivalent circuit diagram illustrating the internal configuration of a bidirectional debiasing buffer according to one embodiment; Figure 6A and Figure 6B This is a diagram illustrating the bidirectional buffering operation of a bidirectional debiasing buffer according to one embodiment; Figure 7A and Figure 7B This is a diagram illustrating the bidirectional latching operation of a bidirectional debias buffer (BDB) according to one embodiment; Figure 8 This is a block diagram illustrating a partial configuration of the shift register and latch section of a data driver IC having a BDB component according to one embodiment; Figure 9 This is a timing diagram illustrating the input / output signals of a clock buffer and a data buffer according to one embodiment; Figure 10 This is a diagram illustrating the principle of reducing the power consumption of a data driver IC according to one embodiment; Figure 11 This is a block diagram illustrating a partial configuration of the shift register and latch section of a data driver IC according to one embodiment; Figure 12 This is a timing diagram illustrating the input / output signals of a BDB component in an inactive and active state in a data driver IC according to one embodiment; and Figure 13 This is an equivalent circuit diagram illustrating the internal configuration of a clock buffer and a data buffer according to one embodiment. Detailed Implementation

[0019] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following description of embodiments in conjunction with the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0020] The shapes, dimensions, scales, angles, and quantities disclosed in the drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the illustrated details. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the essential points of this disclosure.

[0021] When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Unless otherwise stated, singular terms may include plural forms.

[0022] When interpreting a component, even if there is no explicit description, the component should be interpreted as including the tolerance range.

[0023] When describing positional relationships, for example, when the positional relationship between two components is described as “above,” “over,” “below,” and “adjacent,” one or more other components may be positioned between the two components unless more restrictive terms are used (e.g., “only” or “directly”).

[0024] When describing temporal relationships, such as when time sequence is described as "after", "following", "next" and "before", discontinuous situations may be included unless more restrictive terms (e.g., "just", "immediately" or "directly") are used.

[0025] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0026] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify corresponding elements from other elements, and the basis, order, or number of corresponding elements shall not be limited by these terms. Unless otherwise stated, the expression that an element is “connected,” “joined,” or “adheded” to another element or layer means that the element or layer may be directly connected or adhered to another element or layer, or indirectly connected or adhered to another element or layer, and that one or more intermediate elements or layers are “disposed” between these elements or layers.

[0027] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, "at least one or more of the first element, the second element, and the third element" means a combination of all elements listed from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0028] Features of the various embodiments of this disclosure may be connected or combined with each other in part or in whole, and may interoperate with each other and be technically driven in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other or together in a mutually dependent manner.

[0029] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 This is a block diagram schematically illustrating the configuration of a display device according to one embodiment. Figure 2 This is a diagram illustrating a display device having multiple data driver integrated circuits (ICs) according to one embodiment. Figure 3 This is a block diagram illustrating the internal configuration of a data driver IC according to one embodiment, and Figure 4 This is a block diagram illustrating the arrangement of a data driver IC according to one embodiment.

[0031] According to one embodiment, the display device can be any of various display devices, including liquid crystal display devices, electroluminescent display devices, and micro light-emitting diode (LED) display devices. The electroluminescent display device can be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0032] Reference Figure 1 The display device may include a display panel 100, a gating driver 200, a data driver 300, a gamma voltage generator 500, a timing controller 400, etc. The gating driver 200 and the data driver 300 can be defined as panel drivers. The gating driver 200, the data driver 300, and the timing controller 400 can be defined as display drivers.

[0033] The display panel 100 displays images through a display area DA in which subpixels P are arranged in a matrix. Each of the subpixels P is one of a red subpixel that emits red light, a green subpixel that emits green light, a blue subpixel that emits blue light, and a white subpixel that emits white light, and is independently driven by at least one thin-film transistor (TFT). A unit pixel can be composed of a combination of two, three, or four subpixels with different colors.

[0034] The gate electrode of each TFT belonging to sub-pixel P is connected to the gate driver 200 through a gate line provided on the display panel 100, and the input electrode of either the source electrode or the drain electrode of each TFT is connected to the data driver 300 through a data line provided on the display panel 100.

[0035] In other words, in each of the sub-pixels P, when the TFT is turned on in response to a scan pulse of the gate-on voltage provided from the gate driver 200 via the corresponding gate line, the pixel voltage (driving voltage) corresponding to the data signal is charged by receiving the data signal provided from the data driver 300 via the corresponding data line through the turned-on TFT, and light corresponding to the charged voltage is emitted, thereby representing the grayscale corresponding to the data signal.

[0036] The display panel 100 may also include a touch sensor screen that completely overlaps with the display area and is configured to sense the user's touch, and the touch sensor screen may be embedded in the display panel 100 or disposed in the display area of ​​the display panel 100.

[0037] The timing controller 400 can receive image data and synchronization signals from a host system (not shown). For example, the host system can be any of a computer, television system, set-top box, or portable terminal system such as a tablet computer or mobile phone. Synchronization signals can include a dot clock, data enable signal, vertical synchronization signal, horizontal synchronization signal, etc.

[0038] The timing controller 400 can use the received synchronization signal and the timing setting information (start time, pulse width, etc.) stored in the internal register to generate multiple data control signals to provide multiple data control signals to the data driver 300, and generate multiple gating control signals to provide multiple gating control signals to the gating driver 200.

[0039] The timing controller 400 can perform various types of image processing on the provided image data, such as brightness correction for reducing power consumption and image quality correction, and provide the image-processed data to the data driver 300.

[0040] The gamma voltage generator 500 can generate a reference gamma voltage set including multiple reference gamma voltages with different voltage levels, and provide the reference gamma voltage set to the data driver 300. Under the control of the timing controller 400, the gamma voltage generator 500 can generate multiple reference gamma voltages corresponding to the gamma characteristics of the display device, and provide the reference gamma voltages to the data driver 300. The gamma voltage generator 500 may include a programmable gamma IC, and can receive gamma data from the timing controller 400, generate or adjust the reference gamma voltage level according to the gamma data, and output the reference gamma voltage level to the data driver 300.

[0041] The gating driver 200 is controlled according to multiple gating control signals provided by the timing controller 400 to drive the gating lines of the display panel 100 respectively. The gating driver 200 can drive multiple gating lines sequentially. The gating driver 200 can provide a scan signal of gate on voltage to the corresponding gating line during the driving period of each gating line, and provide a scan signal of gate off voltage to the corresponding gating line during the non-driving period of each gating line.

[0042] The gate driver 200 may include at least one gate driver IC and may be mounted on a circuit film such as tape-on-film (TCP), chip-on-film (COF), or flexible printed circuit (FPC) for attachment to the display panel 100 via tape auto-bonding (TAB), or may be mounted on the display panel 100 via chip-on-glass (COG). Alternatively, the gate driver 200 may be formed on a TFT substrate together with a TFT belonging to each of the sub-pixels P of the display panel 100 and embedded in the bezel region of the display panel 100.

[0043] The data driver 300 can be controlled according to the data control signal provided from the timing controller 400, and can convert the digital image data provided from the timing controller 400 into analog data signals and provide the analog data signals to each data line of the display panel 100. The data driver 300 can convert digital image data into analog data signals using grayscale voltages obtained by subdividing multiple reference gamma voltages provided from the gamma voltage generator 500.

[0044] The data driver 300 may include at least one data driver IC and may be mounted on a circuit film such as TCP, COF, FPC, etc. to be attached to the display panel 100 in a TAB manner, or may be mounted in the bezel area of ​​the display panel 100 in a COG manner.

[0045] Reference Figure 2The data driver 300 may include multiple data driver ICs (D-ICs) 600, and a timing controller 400 may be mounted on it. Figure 1 ) and Gamma Voltage Generator 500 ( Figure 1 It is located between the printed circuit board (PCB) 800 and the display panel 100, and is connected to the PCB 800 and the display panel 100.

[0046] Each of the multiple data driver ICs 600 can receive a transmission signal from the PCB 800 through either of its inputs located on its left and right surface portions, respectively, and can output a data signal to the display panel 100 through its output located at its lower end portion. Furthermore, in each of the data driver ICs 600, the input may be located on one side surface portion instead of both side surface portions, or it may be located on the upper end portion.

[0047] Reference Figure 3 Each of the data driver ICs 600 may include a receiver 630, a shift register 660, a first latch 670 and a second latch 680, a grayscale voltage generator 652, a digital-to-analog converter (DAC) unit 690, and an output buffer unit 692.

[0048] Each of the data driver ICs 600 can provide the corresponding data signal to m data lines (where m is a positive integer) on the display panel 100 through m output channels CH1 to CHm.

[0049] In each of the data driver ICs 600, a shift register 660, a first latch 670 and a second latch 680, a DAC 690 and an output buffer 692 can be disposed in the channel region, and the shift register 660, the first latch 670 and the second latch 680, the DAC 690 and the output buffer 692 can include m channels equal to the number of output channels CH1 to CHm.

[0050] To reduce the number of transmission lines and electromagnetic interference (EMI), the timing controller 400 and the multiple data driver ICs 600 can use a high-speed serial interface method in which image data and control signals are converted into serial transmission signals (with embedded clocks) and sent and received in a point-to-point manner. For this purpose, the timing controller 400 includes a transmitter, and each of the multiple data driver ICs 600 includes a receiver 630. The timing controller 400 can transmit transmission signals in the form of differential signals, such as low-voltage differential signaling (LVDS), through at least one pair of transmission channels respectively connected to the multiple data driver ICs 600.

[0051] Each data driver IC 600's receiver 630 can receive the transmitted signal in the form of a differential signal provided by the timing controller 400 in a high-speed serial interface method, recover the clock from the received differential signal, and also use the recovered clock to recover digital image data and control signals, and output the recovered digital image data and control signals to the logic controller 640.

[0052] The logic controller 640 can convert image data provided from the receiver 630 into a parallel form for each sub-pixel unit, rearrange the data of each sub-pixel according to the operation options, and output the rearranged data to the first latch unit 670. The logic controller 640 can use clock and data control signals provided from the receiver 630 to output start pulses and clock signals to the shift register 660, output load signals to the second latch unit 680 and the output buffer unit 692, and can also generate and output control signals required for the operation of other components.

[0053] The shift register 660 can sequentially output multiple sampled signals to the first latch unit 670 while simultaneously shifting the start pulse according to the clock signal. The shift register 660 can include multiple channel stages and, while performing the shift operation for sequentially shifting the start pulse according to the clock signal, sequentially outputs the sampled signals of multiple channels to the first latch unit 670. The shift register 660 can include m channel stages, equal to the number of output channels CH1 to CHm, and can include fewer than m stages.

[0054] The first latch unit 670 can, for each channel of each sub-pixel unit, sequentially latch data segments of multiple channels sequentially transmitted from the receiver 630 via the data bus in response to sampling signals of multiple channels sequentially input from the shift register 660. When all channel data segments are latched, the first latch unit 670 can simultaneously output the latched data of each channel to the second latch unit 680. The first latch unit 670 may include m first latches for each of the output channels CH1 to CHm.

[0055] The second latch unit 680 can simultaneously output data from each channel (sub-pixel) received from the first latch unit 670 to the DAC unit 690 in response to a load signal provided from the logic controller 640. The second latch unit 680 may include a second latch for m channels, equal to the number of output channels CH1 to CHm.

[0056] The grayscale voltage generator 652 can divide the reference gamma voltage provided by the gamma voltage generator 500 into multiple grayscale voltages corresponding to the grayscale values ​​of the image data by dividing the reference gamma voltage via a resistor string, and then output the subdivided grayscale voltages to the DAC unit 690.

[0057] The DAC unit 690 can use the grayscale voltage provided from the grayscale voltage generator 652 to convert the data of each sub-pixel provided by the second latch unit 680 into an analog data signal for each channel, and output the analog data signal to the output buffer unit 692. The DAC unit 690 may include m channels equal to the number of channels CH1 to CHm.

[0058] The output buffer unit 692 can buffer the data signal of each sub-pixel provided from the DAC unit 690 for each channel, and output the buffered data signal to each of the plurality of output channels CH1 to CHm. The output buffer unit 692 may include m output buffers, the same number as the number of output channels CH1 to CHm.

[0059] Reference Figure 4 Since the number of output channels connected to the data lines of the display panel 100 is large, each of the data driver ICs 600 according to one embodiment may have a rectangular shape that extends in the left-right direction, and the output pad area 620 may be provided in the long area of ​​the lower part of the data driver IC 600.

[0060] For bidirectional driving, each of the data driver ICs 600 may include a first input pad region 610A and a second input pad region 610B respectively disposed on its left and right surface portions, and may include a first receiver (RX) 630A and a second receiver 630B respectively disposed adjacent to the first input pad region 610A and the second input pad region 610B, and a first logic controller 640A and a second logic controller 640B respectively disposed adjacent to the first receiver 630A and the second receiver 630B. Additionally, each of the data driver ICs 600 may include a channel region 650 disposed between the first logic controller 640A and the second logic controller 640B and thus driven in both directions, and connected at its lower end to the output pad region 620. (See also...) Figure 3 The shift register 660, the first latch 670 and the second latch 680, the DAC section 690 and the output buffer section 692 described can be set in the channel region 650.

[0061] The data driver IC 600 can receive a transmission signal from the timing controller 400 via one of the first input pad area 610A and the second input pad area 610B, depending on the operating options.

[0062] The data driver IC 600 can convert the transmission signal input through the first input pad area 610A into data for each sub-pixel, so that the data of each sub-pixel can be transmitted to the channel area 650 through the A data path (first data path) passing through the first receiver 630A and the first logic controller 640A in the first direction. The data driver IC 600 can sequentially sample and latch the data of each sub-pixel for each channel through the B data path (second data path) from the first logic controller 640A through the first channel area 650A and the second channel area 650B in the first direction, convert the latched data of each sub-pixel into a data signal, and output the data signal for each channel through the output pad area 620.

[0063] Furthermore, the data driver IC 600 can convert the transmission signal input through the second input pad area 610B into data for each sub-pixel, so that the data of each sub-pixel can be transmitted to the channel area 650 through the A data path (first data path) of the second receiver 630B and the second logic controller 640B in the second direction. The data driver IC 600 can sequentially sample and latch the data of each sub-pixel for each channel through the B data path (second data path) of the second logic controller 640B in the second direction through the second channel area 650B and the first channel area 650A, convert the latched data of each sub-pixel into a data signal, and output the data signal for each channel through the output pad area 620.

[0064] Specifically, in a data driver IC 600 according to one embodiment, in order to prevent the problem of clock and data deviation in the long channel region 650 as the number of output channels CH1 to CHm increases, a bidirectional de-skew buffer (BDB) component configured to use the clock to synchronize the data is applied to each of the multiple channels of the first latch 670 and the shift register 660 in the channel region 650, thereby compensating for the deviation generated between the clock and the data.

[0065] Therefore, the BDB component may include a clock buffer as a bidirectional de-skew buffer for clock signals and a data buffer as a bidirectional de-skew buffer for data signals. The channel region 650 may be divided into multiple channel blocks, and the clock buffer and data buffer of the BDB component may be positioned between adjacent channel blocks. The clock buffer can buffer and output clock signals in both directions, and the data buffer can buffer and latch data so that the data is synchronized with the clock provided from the clock buffer and output, thereby compensating for the deviation between the clock and the data. This will be described in detail below.

[0066] Figure 5 This is an equivalent circuit diagram illustrating the internal configuration of a BDB according to one embodiment, and Figure 6A and Figure 6B This is a diagram illustrating the bidirectional buffering operation of a BDB according to one embodiment, and Figure 7A and Figure 7B This is a diagram illustrating a bidirectional latching operation of a BDB according to one implementation.

[0067] Reference Figure 5 According to one embodiment, a BDB may include: an input switch section 710, which includes a first switch SW1 and a second switch SW2; an output switch section 730, which includes a third switch SW3 and a fourth switch SW4; and a buffer section 720, which includes a first inverter INV1 and a second inverter INV2 between the input switch section 710 and the output switch section 730. The switching operation of each of the first to fourth switches SW1, SW2, SW3 and SW4 can be controlled by logic controllers 640A and 640B (640). The internal circuit configuration of the BDB can be applied to each of the clock buffer and data buffer sections, and in this case, the input switch section 710 of the data buffer can be controlled by the output of the clock buffer. The data buffer section of a channel includes a multi-bit data buffer that buffers and latches multi-bit data segments in parallel, and the data buffer for each bit can be configured as follows: Figure 5 The internal circuit shown.

[0068] The first switch SW1 and the second switch SW2 of the input switch unit 710 can be connected in series between the first supply line IO_L and the second supply line IO_R, and can determine the input direction or latching operation.

[0069] The third switch SW3 and the fourth switch SW4 of the output switch unit 730 can be connected in series between the first supply line IO_L and the second supply line IO_R, and can determine the output direction or latch operation.

[0070] The first inverter INV1 and the second inverter INV2 of the buffer section 720 can be connected in series between the first connection node N1 between the first switch SW1 and the second switch SW2 and the second connection node N2 between the third switch SW3 and the fourth switch SW4, and can buffer and output input signals or latch and output input signals.

[0071] Reference Figure 6A When the first switch SW1 and the fourth switch SW4 are turned on, and the second switch SW2 and the third switch SW3 are turned off, the input signal provided by the left first supply line IO_L can be buffered by the first path passing through the first switch SW1, the first inverter INV1 and the second inverter INV2 and the fourth switch SW4 in the first direction, and output through the right second supply line IO_R.

[0072] Reference Figure 6B When the first switch SW1 and the fourth switch SW4 are open, and the second switch SW2 and the third switch SW3 are closed, the input signal provided by the right second supply line IO_R can be buffered by the second path in the second direction through the second switch SW2, the first inverter INV1 and the second inverter INV2 and the third switch SW3, and output through the left first supply line IO_L.

[0073] When Figure 6A The first switch SW1 and the fourth switch SW4 are connected, and the second switch SW2 and the third switch SW3 are disconnected, and then as shown... Figure 7A When the first switch SW1 and the third switch SW3 are open and the second switch SW2 and the fourth switch SW4 are closed, the input signal provided by the left first supply line IO_L can be as follows: Figure 6A The signal is buffered via a first path through a first switch SW1, a first inverter INV1, a second inverter INV2, and a fourth switch SW4 in the first direction, and then latched via a third path through a second switch SW2, a first inverter INV1, a second inverter INV2, and a fourth switch SW4. The latch signal can be output via the right second supply line IO_R.

[0074] When responding to the control of logic controllers 640A and 640B (640), such as Figure 6B The first switch SW1 and the fourth switch SW4 are open, and the second switch SW2 and the third switch SW3 are closed, and then as shown... Figure 7B When the second switch SW2 and the fourth switch SW4 are open and the first switch SW1 and the third switch SW3 are closed, the input signal provided by the right second supply line IO_R can be as follows: Figure 6BThe path shown is buffered in the second direction via the second switch SW2, the first inverter INV1, the second inverter INV2, and the third switch SW3, and then as... Figure 7B The signal is latched via a fourth path that passes through the first switch SW1, the first inverter INV1, the second inverter INV2, and the third switch SW3, and the latch signal can be output through the left first supply line IO_L.

[0075] Figure 8 This is a block diagram illustrating a partial configuration of the shift register and latch section of a data driver IC with BDB components according to one embodiment. Figure 9 This is a timing diagram illustrating the input / output signals of a clock buffer and a data buffer according to one embodiment.

[0076] Reference Figure 8 According to one embodiment, the BDB component may include: a clock buffer 662 disposed on the clock line between level STn-1 of the (n-1)th channel (n is an integer greater than or equal to 2) and level STn of the nth channel in the shift register 660; and a data buffer 672 disposed on the data bus between the first latch LA1(n-1) of the (n-1)th channel and the first latch LA1n of the nth channel in the first latch 670.

[0077] The clock buffer 662 of the BDB component can buffer the input clock CLK_L provided by stage STn-1 of the (n-1)th channel, and provide the buffered output clock CLK_R as a clock signal to stage STn of the nth channel.

[0078] The data buffer unit 672 of the BDB component can buffer and latch the data of the (n-1)th channel in sync with the buffer output clock CLK_R of the clock buffer 662, and then transmit the data of the nth channel through the data bus via the first latch LA1(n-1) of the (n-1)th channel. It also provides the data of the nth channel, synchronized with the buffer output clock CLK_R of the clock buffer 662, to the first latch LA1n of the nth channel. The data buffer unit 672 of the BDB component may include a k-bit data buffer unit 672 (k is a positive integer) that buffers and latches k bits of the corresponding channel (sub-pixel) data and outputs the latched k bits.

[0079] In shift register 660, stage STn-1 of channel (n-1) can output the sampled signal of channel (n-1) to the first latch LA1(n-1) of channel (n-1) in response to input clock CLK_L, and stage STn of channel n can output the sampled signal to the first latch LA1n of channel n in response to buffered output clock CLK_R buffered by clock buffer 662.

[0080] The first latch LA1(n-1) of the (n-1)th channel can sample and latch the data of the (n-1)th channel in response to the sampling signal provided from the stage STn-1 of the (n-1)th channel. The first latch LA1n of the nth channel can sample and latch the data DATA_R of the nth channel provided by the data buffer unit 672 in response to the sampling signal provided from the stage STn of the nth channel. The first latch LA1n of each channel may include a k-bit first latch for latching k bits of each sub-pixel respectively.

[0081] The second latches LA2(n-1) and LA2n of the second latch unit 680 for the (n-1)th and nth channels can simultaneously receive and latch data signals from the first latches LA1(n-1) and LA1n of the (n-1)th and nth channels in response to the load signal LOAD, which serves as the second latch enable signal, and simultaneously output the latched data signals. The second latch LA2n for each channel may include a k-bit second latch for latching k bits of each sub-pixel respectively.

[0082] Reference Figure 9 The data DATA, which is input to the first latch unit 670 as the original signal, and the clock CLK, which is input to the shift register 660, are provided to enable the timing T of the clock CLK to be pulled down. pdCLK The pull-down timing T of each of the data segments D(n-1), D(n), D(n+1), and D(n+2) pdDATA synchronous.

[0083] Because the B data path is longer in channel region 650, a pull-down timing T may occur in the input clock CLK_L to the shift register 660 input to the corresponding channel and the data DATA_L input to the first latch unit 670. pdCLK The pull-down timing T of each of the data segments D(n-1), D(n), D(n+1), and D(n+2) pdDATA Mismatch deviation (T) skew = T pdCLK - T pdDATA ).

[0084] However, by using the clock buffer 662 and data buffer 672 of the BDB component according to one embodiment, the data buffer 672 can buffer and latch the input data DATA_L of the corresponding channel, and provide the latched data DATA_R of the corresponding channel to the corresponding channel of the first latch 670, so as to synchronize with the buffered output clock CLK_R of the clock buffer 662. Therefore, the clock buffer 662 and data buffer 672 of the BDB component can be synchronized by correcting the pull-down timing T of the clock CLK. pdCLK The pull-down timing T of each of the data segments D(n-1), D(n), D(n+1), and D(n+2) pdDATA The deviation caused by the difference between them is used to compensate for the timing mismatch.

[0085] As described above, in the data driver IC 600 according to one embodiment, the BDB can be used as a bidirectional buffer and simultaneously as a latch to compensate for deviations (i.e., timing mismatch) that may occur between the clock and data due to the high-frequency drive of the B data path through the logic controllers 640A and 640B and the channel region 650.

[0086] Furthermore, in the data driver IC 600 according to one embodiment, since the BDB component is used as a bidirectional buffer, an optimized arrangement can be achieved to shorten the A data path with the highest driving frequency (i.e., the adjacent arrangement of receivers 630A and 630B with logic controllers 640A and 640B). Figure 4 This overcomes frequency limitations.

[0087] Furthermore, according to one embodiment, the data driver IC 600 can sequentially enable and activate the channels of the shift register, the first latch, and the BDB component in a channel block manner using the output of the BDB component. When all channels are enabled and activated, the data driver IC 600 can disable and deactivate the channels, thereby reducing power consumption and electromagnetic interference (EMI). This will be described in detail below.

[0088] Figure 10 This is a diagram illustrating the principle of reducing the power consumption of a data driver IC according to one embodiment.

[0089] Reference Figure 10 In the data driver IC 600, the channel region 650 can be divided into multiple channel blocks B1 to B7 based on multiple BDB components.

[0090] For example, within each active period of a horizontal time period, data segments of multiple channels sequentially provided from the first logic controller 640A to the channel region 650 can be sequentially latched in the first latch unit 670 for each channel via the B data path in the shift direction (first direction) of the shift register 660.

[0091] First, when the first channel block B1 becomes active, the first latch of the first channel block B1 can sequentially latch the data of the first channel block B1 for each channel in response to the sampling signals sequentially output from the shift register of the first channel block B1. At this time, the shift registers and first latches of each of the second channel blocks B2 to the seventh channel blocks B7 are inactive.

[0092] When the BDB component between the first channel block B1 and the second channel block B2 is activated to output the clock and data for the corresponding channel, the second channel block B2 is activated after the first channel block B1. Furthermore, the first latch of the second channel block B2 can sequentially latch the data of the second channel block B2 for each channel in response to the sampling signals sequentially output from the shift register of the second channel block B2. At this time, the shift registers and first latches of each of the third to seventh channel blocks B7 following the second channel block B2 remain inactive.

[0093] When the BDB component between the second channel block B2 and the third channel block B3 is activated to output clock and data, the third channel block B3 is activated after the first channel block B1 and the second channel block B2, and the first latch of the third channel block B3 can sequentially latch the data of the third channel block B3 for each channel in response to the sampled signals sequentially output from the shift register of the third channel block B3. At this time, the shift registers and first latches of each of the fourth channel blocks B4 to the seventh channel blocks B7 after the third channel block B3 remain inactive.

[0094] When the BDB component between the third channel block B3 and the fourth channel block B4 is activated to output clock and data, the fourth channel block B4 is activated after the first channel blocks B1 to the third channel blocks B3, and the first latch of the fourth channel block B4 can sequentially latch the data of the fourth channel block B4 for each channel in response to the sampled signals sequentially output from the shift register of the fourth channel block B4. At this time, the shift registers and first latches of each of the fifth channel blocks B5 to the seventh channel blocks B7 are inactive.

[0095] When the BDB component between the fourth channel block B4 and the fifth channel block B5 is activated to output clock and data, the fifth channel block B5 is activated after the first channel blocks B1 to the fourth channel blocks B4, and the first latch of the fifth channel block B5 can sequentially latch the data of the fifth channel block B5 for each channel in response to the sampled signals sequentially output from the shift register of the fifth channel block B5. At this time, the shift registers and first latches of each of the sixth channel blocks B6 to the seventh channel blocks B7 are inactive.

[0096] When the BDB component between the fifth channel block B5 and the sixth channel block B6 is activated to output clock and data, the sixth channel block B6 is activated after the first channel blocks B1 to the fifth channel blocks B5, and the first latch of the sixth channel block B6 can sequentially latch the data of the sixth channel block B6 for each channel in response to the sampling signals sequentially output from the shift register of the sixth channel block B6. At this time, the shift register and the first latch of the seventh channel block B7 are inactive.

[0097] When the BDB component between the sixth channel block B6 and the seventh channel block B7 is activated to output clock and data, all of the first channel blocks B1 to the seventh channel block B7 are activated, and the first latch of the seventh channel block B7 can latch the data of the seventh channel block B7 sequentially for each channel in response to the sampling signals sequentially output from the shift register of the seventh channel block B7.

[0098] As described above, the first latch of each of the first channel blocks B1 to the seventh channel blocks B7 can sequentially latch the data of the corresponding channel and output all segments of the latched data to the second latch. Then, in response to the load signal of the second latch, all BDB components are activated, and the shift register and the first latch of each of the first channel blocks B1 to the seventh channel blocks B7 are deactivated.

[0099] As described above, according to one embodiment, the B data path provided to the channel region 650 by the logic controllers 640A and 640B of the data driver IC is activated sequentially in response to the control of multiple BDB components in a channel block manner, and remains inactive until the corresponding channel block is activated, thereby reducing power consumption and EMI.

[0100] Figure 11 This is a block diagram illustrating a partial configuration of the shift register and latch section of a data driver IC according to one embodiment, and Figure 12 This is a timing diagram illustrating the input / output signals of a BDB component in an inactive and active state in a data driver IC according to one embodiment.

[0101] Figure 11 The BDB component shown is... Figure 8 The difference in the BDB components shown is that the clock buffer 662 also receives the carry signal SHR from the previous stage STn-1 and the load signal LOAD from the second latch 680 to control the data buffer 672. Therefore, these differences will be described in detail, and descriptions of the data buffer 672 will be omitted or simplified. Figure 8 Description of overlapping components.

[0102] Reference Figure 11 and Figure 12 Clock buffer 662 can be enabled in response to the carry signal SHR from the previous stage STn-1, and can buffer the input clock CLK_L provided from the previous stage STn-1, and then output the buffered output clock CLK_R to the next stage STn. Clock buffer 662 can be disabled in response to the load signal LOAD generated by the second latch 680 after the first latch 670 outputs all segments of latched data to the second latch 680, and then waits for the next enable state.

[0103] The clock buffer 662 can generate a data enable signal D_EN by inverting the buffer output clock CLK_R and output the generated data enable signal D_EN to the data buffer section 672.

[0104] The data buffer unit 672 can be enabled and activated, or disabled and deactivated, according to the data enable signal D_EN received from the clock buffer 662. When the data enable signal D_EN is enabled in response to the carry signal SHR of the previous stage STn-1, the data buffer unit 672 can be activated to buffer and latch the data of the nth channel provided through the data bus via the first latch LA1(n-1) of the (n-1)th channel, and output the latched data to the first latch LA1n of the nth channel. When the data enable signal D_EN is disabled in response to the load signal LOAD of the second latch unit 680, the data buffer unit 672 can be deactivated.

[0105] Figure 13 This is an equivalent circuit diagram illustrating the internal configuration of the clock buffer and data buffer of a BDB component according to one embodiment.

[0106] Reference Figure 13 According to one embodiment, the BDB component includes a clock buffer 662 and a data buffer 672.

[0107] Clock buffer 662 may include an input switch section 710A including a first switch SW1A and a second switch SW2A, an output switch section 730A including a third switch SW3A and a fourth switch SW4A, and a buffer section 720A including a first inverter INV1A and a NAND gate circuit NG connected between a first connection node N1A of the input switch section 710A and a second connection node N2A of the output switch section 730A. Clock buffer 662 also includes an SR latch circuit SR and a second inverter INV2A. The SR latch circuit SR receives data from the previous stage STn-1 of the shift register (see...). Figure 11 The carry signal SHR provided by ) and the carry signal provided by the second latch 680 ( Figure 11 The load signal LOAD is used as the set signal S and the reset signal R, respectively. The second inverter INV2A inverts the output of the NAND gate circuit NG of the second connection node N2A of the output switch section 730A to generate the data enable signal D_EN and provides the data enable signal D_EN to the input switch section 710B of the data buffer section 672.

[0108] In the clock buffer 662, the first switch SW1A and the second switch SW2A of the input switch section 710A can be connected in series between the first supply line IO_L and the second supply line IO_R, and the input direction can be determined in response to the control of the logic controllers 640A and 640B (640).

[0109] The third switch SW3A and the fourth switch SW4A of the output switch section 730A in the clock buffer 662 are connected in series between the first supply line IO_L and the second supply line IO_R, and the output direction can be determined in response to the control of the logic controllers 640A and 640B (640).

[0110] When the first switch SW1A and the fourth switch SW4A are turned on, the clock buffer 662 can perform a clock buffering operation in the first direction, or when the second switch SW2A and the third switch SW3A are turned on, it can perform a clock buffering operation in the second direction opposite to the first direction.

[0111] In clock buffer 662, the SR latch circuit SR can receive data from the previous stage STn-1 of the shift register. Figure 11 The carry signal SHR provided by the second latch unit 680 is used as the set signal S and is also received by the second latch unit 680. Figure 11 The load signal LOAD serves as the reset signal R. In response to the set signal S, it outputs an enable signal to the NAND gate circuit NG through the output terminal Q, and in response to the reset signal R, it outputs a disable signal to the NAND gate circuit NG through the output terminal Q.

[0112] In clock buffer 662, the first inverter INV1A and NAND gate circuit NG of buffer section 720 can be connected in series between the first connection node N1A between the first switch SW1A and the second switch SW2A and the second connection node N2A between the third switch SW3A and the fourth switch SW4A, and can buffer and output the input clock CLK_L or disable the buffered output clock CLK_R.

[0113] In clock buffer 662, when the SR latch circuit SR responds to the previous stage STn-1 ( Figure 11 When the carry signal SHR is provided to provide an enable signal, the NAND gate circuit NG can buffer the input clock CLK_L together with the first inverter INV1A to provide a buffered output clock CLK_R through the second connection node N2A. At this time, the second inverter INV2A can invert the buffered output clock CLK_R provided through the second connection node N2A, and output the data enable signal D_EN, which alternates between the enabled and disabled states synchronously with the buffered output clock CLK_R, to the input switch section 710B of the data buffer section 672.

[0114] When the SR latch circuit SR responds to the second latch section 680 ( Figure 11 When the load signal LOAD is provided with a disable signal, the NAND gate circuit NG can disable the buffered output clock CLK_R. In this case, the second inverter INV2A can output the disabled data enable signal D_EN provided through the second connection node N2A to the input switch 710B of the data buffer section 672.

[0115] The data buffer section 672 may include an input switch section 710B including a first switch SW1B and a second switch SW2B, an output switch section 730B including a third switch SW3B and a fourth switch SW4B, and a buffer section 720B including a first inverter INV1B and a second inverter INV2B between the input switch section 710B and the output switch section 730B.

[0116] In the data buffer section 672, the first switch SW1B and the second switch SW2B of the input switch section 710B can be connected in series between the first supply line IO_L and the second supply line IO_R, and can determine the input direction or determine the latching operation in response to the data enable signal D_EN provided from the clock buffer 662. The first switch SW1B is controlled by the data enable signal D_EN, which is the output of the second inverter INV2A of the clock buffer 662, and the second switch SW2B can be controlled by the input signal of the second inverter INV2A provided from the second connection node N2A of the clock buffer 662.

[0117] In the data buffer section 672, the third switch SW3B and the fourth switch SW4B of the output switch section 730B can be connected in series between the first supply line IO_L and the second supply line IO_R, and can determine the output direction or latching operation in response to the control of the logic controllers 640A and 640B (640).

[0118] In the data buffer section 672, the first inverter INV1B and the second inverter INV2B of the buffer section 720B can be connected in series between the first connection node N1B between the first switch SW1B and the second switch SW2B and the second connection node N2B between the third switch SW3B and the fourth switch SW4B, and can buffer and output input data DATA_L.

[0119] In the data buffer section 672, when the first switch SW1B and the fourth switch SW4B are turned on, and then the second switch SW2B and the fourth switch SW4B are turned on, the input data provided by the left first supply line IO_L can be buffered through a first path in the first direction through the first switch SW1B, inverters INV1B and INV2B and the fourth switch SW4B, and then latched through a third path through the second switch SW2B, inverters INV1B and INV2B and the fourth switch SW4B, and output through the right second supply line IO_R.

[0120] In the data buffer section 672, when the second switch SW2B and the third switch SW3B are turned on, and then the first switch SW1B and the third switch SW3B are turned on, the input data supplied through the right second supply line IO_R can be buffered through a second path in the second direction via the second switch SW2B, inverters INV1B and INV2B and the third switch SW3B, and then latched through a fourth path via the first switch SW1B, inverters INV1B and INV2B and the third switch SW3B, and output through the left first supply line IO_L.

[0121] As described above, in the data driver IC 600 according to one embodiment, the BDB component can be used as a bidirectional buffer and simultaneously as a latch to compensate for the deviation between the clock and the data (i.e., timing mismatch), which may be caused by the high-frequency drive of the B data path through the logic controllers 640A and 640B and the channel region 650.

[0122] Furthermore, in the data driver IC 600 according to one embodiment, since the BDB component is used as a bidirectional buffer, an optimized arrangement of the A data path with the highest driving frequency can be achieved (i.e., the adjacent arrangement of receivers 630A and 630B with logic controllers 640A and 640B), thereby overcoming frequency limitations.

[0123] Furthermore, according to one embodiment, the data driver IC 600 can reduce power consumption and EMI by partially enabling and activating or disabling and deactivating the channel of the first latch using the output of the BDB component.

[0124] As described above, the data driver circuit according to one embodiment corrects the deviation between clock and data by using clock buffers and data buffers of BDB components disposed between adjacent channel blocks for each of the multiple channel blocks, thereby preventing timing mismatch between clock and data even when the frequency and number of channels increase, thus overcoming frequency limitations and ensuring degrees of freedom to overcome design constraints.

[0125] According to one embodiment, the data driver circuit can be configured as a minimal circuit by using clock and data buffers of BDB components disposed between adjacent channel blocks, thus without increasing chip area, and can reduce current consumption and minimize EMI by activating channels only when necessary.

[0126] The data driver circuit and display device including the data driver circuit according to the embodiments can be applied to various electronic devices. For example, the data driver circuit and display device including the data driver circuit according to the embodiments can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MPEG audio layer 3 players, mobile medical devices, desktop personal computers (PCs), laptops, netbooks, workstations, navigation devices, in-vehicle navigation devices, in-vehicle display devices, televisions, wallpaper display devices, signage devices, game consoles, laptops, monitors, cameras, camcorders, home appliances, etc.

[0127] The features, structures, effects, etc., described above in the various examples of this disclosure are included in at least one example of this disclosure, and are not necessarily limited to one example. Furthermore, the features, structures, effects, etc., shown in at least one example of this disclosure can be combined or modified by those skilled in the art to which the technical concept of this disclosure pertains for use in other examples. Therefore, the content related to such combinations and modifications should be interpreted as being included within the technical spirit or scope of this disclosure.

[0128] Although this disclosure is not limited to the embodiments and drawings described above, it will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope, and equivalents of the claims should be understood to be included within the scope of this disclosure.

[0129] Cross-references to related applications

[0130] This application claims the benefit of Korean Patent Application No. 10-2020-0175283, filed on December 15, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A data driver circuit, the data driver circuit comprising: A shift register configured to output a sampled signal in response to a clock; A first latch unit is configured to sample and latch data for each channel in response to each of the sampled signals; as well as A bidirectional de-skew buffer is disposed between the stages of the first and second channels of the shift register and between the first latches of the first channel and the first latches of the second channel of the first latch unit. It is configured to buffer the clock input from the stage of the first channel to output the buffered clock to the stage of the second channel, and to synchronously buffer and latch the data of the second channel input after the data of the first channel latched by the first latch of the first channel is stored, so as to output the latched data to the first latch of the second channel. The shift register and the first latch are divided into multiple channel blocks. The bidirectional de-biasing buffer is disposed between the plurality of channel blocks. The shift register and the plurality of channel blocks of the first latch, as well as the bidirectional de-bias buffer between the plurality of channel blocks, are sequentially activated from the deactivated state, and When the first latch latch latches all data segments of the plurality of channel blocks, the plurality of channel blocks and the bidirectional de-bias buffer are deactivated.

2. The data driver circuit according to claim 1, wherein, The bidirectional deflection buffer section includes: A clock buffer, configured to buffer the clock supplied from the stage of the first channel of the shift register and output the buffered clock to the stage of the second channel; and A data buffer section is configured to buffer and latch data of the second channel input through the first latch of the first channel of the first latch section in synchronization with the clock output from the clock buffer, and to output the latched data to the first latch of the second channel.

3. The data driver circuit according to claim 2, wherein, Each of the plurality of bit data buffers constituting the data buffer section and the clock buffer includes: An input switch section, the input switch section including a first switch and a second switch connected in series between a first supply line and a second supply line and configured to determine an input direction or a latching operation; An output switching section, comprising a third switch and a fourth switch connected in series between the first supply line and the second supply line and configured to determine the output direction or the latching operation; and A buffer section is connected between a first connection node between the first switch and the second switch and a second connection node between the third switch and the fourth switch. The first supply line of the clock buffer is connected to the stage of the first channel. The second supply line of the clock buffer is connected to the stage of the second channel. The first supply line of the data buffer is connected to the first latch of the first channel, and The second supply line of the data buffer is connected to the first latch of the second channel.

4. The data driver circuit according to claim 3, wherein, The clock buffer is configured as follows: A clock buffering operation is performed in the first direction passing through the first supply line, the first switch that is turned on, the buffer section, the fourth switch that is turned on, and the second supply line; or A clock buffering operation is performed in the second direction, passing through the second supply line, the second switch that is turned on, the buffer section, the third switch that is turned on, and the first supply line.

5. The data driver circuit according to claim 3, wherein, Each of the plurality of bit data buffers is configured to: A data buffering operation is performed in the first direction passing through the first supply line, the first switch that is turned on, the buffer section, the fourth switch that is turned on, and the second supply line, and a latching operation is performed in the first path passing through the second switch that is turned on, the buffer section, the fourth switch that is turned on, and the second supply line; or A data buffering operation is performed in the second direction passing through the second supply line, the second switch that is turned on, the buffer section, the third switch that is turned on, and the first supply line, and a latching operation is performed in the second path passing through the first switch that is turned on, the buffer section, the third switch that is turned on, and the first supply line.

6. The data driver circuit of claim 2, further comprising a second latch, the second latch being configured to simultaneously receive and latch data segments of a plurality of channels latched in the first latch, and to output the latched data segments in response to a load signal. in, The clock buffer of the bidirectional de-skew buffer section is enabled in response to a carry signal received from the first channel stage of the shift register, and is disabled in response to the load signal of the second latch section. The data buffer section of the bidirectional debiasing buffer is enabled or disabled based on the output of the clock buffer.

7. The data driver circuit according to claim 6, wherein, The clock buffer includes: The input switch section includes a first A switch and a second A switch connected in series between a first-1 supply line of the stage connected to the first channel of the shift register and a second-1 supply line of the stage connected to the second channel of the shift register; The output switch section includes a 3A switch and a 4A switch connected in series between the first-1 supply line and the second-1 supply line; A buffer section, the buffer section being connected between a first A connection node between the first A switch and the second A switch and a second A connection node between the third A switch and the fourth A switch; and An SR latch circuit is configured to receive and latch the carry signal and the load signal received from the first channel as a set signal and a reset signal, respectively, and output the set signal and the reset signal to the buffer section.

8. The data driver circuit according to claim 7, wherein, The buffer section of the clock buffer includes: Inverter 1A, the inverter 1A being connected to the connection node 1A; and The NAND gate circuit is configured to receive the output of the first A inverter and the output of the SR latch circuit, perform NAND gate logic operations, and output the operation result to the second A connection node.

9. The data driver circuit according to claim 8, wherein, The clock buffer also includes a second inverter, which is configured to receive the output of the second connection node, generate a data enable signal, and output the data enable signal to the data buffer.

10. The data driver circuit according to claim 9, wherein, Each of the multiple bits of the data buffer constituting the data buffer section includes: The input switch section includes a first B switch and a second B switch connected in series between a first-2 supply line of a data bus connected to the first latch via the first channel and a second-2 supply line of the first latch connected to the second channel. The output switching section includes a 3B switch and a 4B switch connected in series between the first-2 supply line and the second-2 supply line; and The buffer section includes a first inverter and a second inverter connected in series between a first connection node between the first B switch and the second B switch and a second connection node between the third B switch and the fourth B switch.

11. The data driver circuit according to claim 10, wherein, The data enable signal output from the clock buffer controls the first B switch of the data buffer, and The signal output from the first B connection node of the clock buffer controls the second B switch of the data buffer.

12. The data driver circuit according to claim 1, wherein the data driver circuit comprises: A channel region is provided with the shift register, the first latch, the bidirectional de-biasing buffer, a second latch connected to the first latch, a digital-to-analog converter connected to the second latch, and an output buffer connected to the digital-to-analog converter. An output pad area, the output pad area being configured to output data signals provided from the channel area to multiple output channels; An input pad area is configured to receive transmission signals; A receiver is configured to be adjacent to the input pad area and to receive the transmission signal through the input pad area, and to recover the clock, data and control signals from the received transmission signal to output the recovered clock, data and control signals; as well as A logic controller is configured to be adjacent to and between the receiver and the channel region, and to transmit the clock and control signals provided from the receiver to the channel region, and to rearrange the data for each channel to provide the data to the channel region.

13. The data driver circuit according to claim 12, wherein, The logic controller includes a first logic controller and a second logic controller respectively disposed adjacent to two side surface portions of the channel region, and the channel region is located between the first logic controller and the second logic controller. The receiver includes a first receiver and a second receiver respectively disposed adjacent to the first logic controller and the second logic controller. The input pad region includes a first input pad region and a second input pad region disposed on two side surface portions of the data driver circuit, respectively adjacent to the first receiver and the second receiver, and The output pad area is located at the lower portion of each of the input pad area, the receiver, the logic controller, and the channel area.

14. The data driver circuit according to claim 13, wherein, Depending on the driving option, a signal is transmitted in a first direction in the channel region via a first input pad area, a first receiver, and a first logic controller, or According to the driving option, a signal is transmitted in a second direction in the channel region via a second input pad area, a second receiver, and a second logic controller.

15. A data driver circuit including a bidirectional de-skew buffer, the bidirectional de-skew buffer being disposed between a stage belonging to a first channel and a second channel of a shift register, and between a first latch belonging to a first latch of a first channel and a first latch belonging to a first latch of a second channel. in, The bidirectional deflection buffer section includes: A clock buffer, configured to buffer the clock input from the stage of the first channel and output the buffered clock to the stage of the second channel; and A data buffer section is configured to buffer and latch data of the second channel that is input after the data of the first channel, which is latched by the first latch of the first channel, is stored in sync with a clock output from the clock buffer, and to output the latched data to the first latch of the second channel. Each of the multiple bit data buffers constituting the data buffer section and the clock buffer includes: An input switch section, the input switch section including a first switch and a second switch connected in series between a first supply line and a second supply line and configured to determine an input direction or a latching operation; An output switching section, comprising a third switch and a fourth switch connected in series between the first supply line and the second supply line and configured to determine the output direction or the latching operation; and A buffer section is connected between a first connection node between the first switch and the second switch and a second connection node between the third switch and the fourth switch. The first supply line of the clock buffer is connected to the stage of the first channel. The second supply line of the clock buffer is connected to the stage of the second channel. The first supply line of the data buffer is connected to the first latch of the first channel, and The second supply line of the data buffer is connected to the first latch of the second channel.

16. A data driver circuit, the data driver circuit comprising: A bidirectional de-biasing buffer section is disposed between the stage of the first channel and the stage of the second channel of the shift register, and between the first latch of the first channel and the first latch of the second channel of the first latch section. as well as A second latch is configured to simultaneously receive and latch data segments from multiple channels latched in the first latch, and to output the latched data segments in response to a load signal. The bidirectional deflection buffer section includes: A clock buffer, configured to buffer the clock input from the stage of the first channel and output the buffered clock to the stage of the second channel; and A data buffer section is configured to buffer and latch data of the second channel that is input after the data of the first channel, which is latched by the first latch of the first channel, is stored in sync with a clock output from the clock buffer, and to output the latched data to the first latch of the second channel. The clock buffer is enabled in response to a carry signal received from the first channel stage of the shift register, and disabled in response to a load signal from the second latch. The data buffer is enabled or disabled based on the output of the clock buffer.

17. The data driver circuit according to claim 16, wherein, The clock buffer includes: The input switch section includes a first A switch and a second A switch connected in series between a first-1 supply line of the stage connected to the first channel of the shift register and a second-1 supply line of the stage connected to the second channel of the shift register; The output switch section includes a 3A switch and a 4A switch connected in series between the first-1 supply line and the second-1 supply line; A buffer section, the buffer section being connected between a first A connection node between the first A switch and the second A switch and a second A connection node between the third A switch and the fourth A switch; and An SR latch circuit is configured to receive and latch the carry signal and the load signal received from the first channel as a set signal and a reset signal, respectively, and output the set signal and the reset signal to the buffer section. Each of the multiple bits of the data buffer constituting the data buffer section includes: The input switch section includes a first B switch and a second B switch connected in series between a first-2 supply line of a data bus connected to the first latch via the first channel and a second-2 supply line of the first latch connected to the second channel. The output switching section includes a 3B switch and a 4B switch connected in series between the first-2 supply line and the second-2 supply line; and The buffer section includes a first inverter and a second inverter connected in series between a first connection node between the first B switch and the second B switch and a second connection node between the third B switch and the fourth B switch.

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