Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate; a gate structure on the substrate; a source-drain structure in the substrate on both sides of the gate structure; a source-drain contact layer on the source-drain structure between the gate structures; a protective layer between the source-drain contact layer and the gate structure; and a gate cap layer on the gate structure between the source-drain contact layers. In the embodiment, the protective layer is between the source-drain contact layer and the gate structure, the source-drain contact layer is on the source-drain structure between the protective layer, and the protective layer can well electrically isolate the source-drain contact layer and the gate structure, so that the source-drain contact layer and the gate structure are not easy to bridge, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and a substrate. These interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit.

[0004] The semiconductor structure includes a substrate, a gate structure on the substrate, and source / drain structures located on both sides of the gate structure within the substrate, used to improve the carrier migration rate in the channel during operation of the semiconductor structure. In the back end, the semiconductor structure also includes a source / drain contact layer located on the surface of the source / drain structures, used to connect the source / drain structures to external circuitry. The insulation performance between the source / drain contact layer and the gate structure is crucial to the electrical performance of the semiconductor structure.

[0005] Furthermore, to further improve the integration of semiconductor structures, the Contact Over Active Gate (COAG) process was introduced. Compared to traditional gate contact plugs located above the gate structure in the isolation region, the COAG process can place the gate contact plug above the gate structure in the active area (AA), resulting in a higher integration of the semiconductor structure. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which makes it less likely for the source-drain contact layer connecting the source-drain structure to bridge with the gate structure, thereby optimizing the electrical performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, forming a gate structure on the substrate, forming source / drain structures within the substrate on both sides of the gate structure, forming an interlayer dielectric layer on the exposed portion of the substrate of the gate structure, the interlayer dielectric layer covering the sidewalls of the source / drain structures and the gate structure, with the top of the interlayer dielectric layer being higher than the top of the gate structure, the interlayer dielectric layer and the gate structure forming a groove; forming a first gate capping layer in the groove, the first gate capping layer having a higher etch resistance than the interlayer dielectric layer; forming a first opening penetrating the interlayer dielectric layer and exposing the source / drain structures; forming a source / drain contact layer in the first opening; after forming the source / drain contact layer, removing the first gate capping layer, forming a second opening on the top of the gate structure; and forming a second gate capping layer in the second opening.

[0008] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; a source / drain structure located within the substrate on both sides of the gate structure; a source / drain contact layer located on the source / drain structure between the gate structures; a protective layer located between the source / drain contact layer and the gate structure; and a gate cap layer located on the gate structure between the source / drain contact layers.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure formation method provided by this invention, the interlayer dielectric layer and the gate structure form a groove, and a first gate capping layer is formed in the groove. Because the etching resistance of the first gate capping layer is greater than that of the interlayer dielectric layer, as the integration density of the semiconductor structure increases, the damage to the first gate capping layer is smaller during the formation of the first opening, resulting in a larger process window for the formation of the first opening. This allows for a high-density first opening and optimizes the formation process of the first opening. Furthermore, because the damage to the first gate capping layer is smaller during the formation of the first opening exposing the source / drain structure, the first opening is less likely to expose the gate structure. Consequently, the source / drain contact layer formed in the first opening is less likely to bridge with the gate structure, achieving self-aligned contact between the source / drain contact layer and the source / drain structure. This is beneficial for improving the formation quality of the semiconductor structure and optimizing its electrical performance. In addition, because the damage to the first gate capping layer is smaller during the formation of the first opening, the space occupied by the first gate capping layer meets the process requirements. Removing the first gate capping layer forms a second opening, the morphology of which meets the process requirements. This ensures that the morphology of the second gate capping layer formed in the second opening meets the process requirements, further improving the electrical performance of the semiconductor structure.

[0011] In the semiconductor structure provided by the embodiments of the present invention, a protective layer is located between the source / drain contact layer and the gate structure; a gate cap layer is located on the gate structure between the source / drain contact layers. The protective layer can effectively isolate the source / drain contact layer and the gate structure, making it less prone to bridging between the source / drain contact layer and the gate structure, which is beneficial to improving the electrical performance of the semiconductor structure. Attached Figure Description

[0012] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] Figures 8 to 10 This is a schematic diagram of the structure corresponding to each step in another method of forming a semiconductor structure;

[0014] Figure 11 This is a schematic diagram of the semiconductor structure according to the first embodiment of the present invention;

[0015] Figure 12 This is a schematic diagram of the semiconductor structure according to the second embodiment of the present invention;

[0016] Figures 13 to 21 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to the first embodiment of the present invention;

[0017] Figures 22 to 27 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to the second embodiment of the present invention. Detailed Implementation

[0018] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0019] refer to Figures 1 to 7 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0020] like Figure 1 As shown, a substrate is provided, the substrate including a substrate (not shown), a fin 1 discrete on the substrate, an initial gate structure 2 spanning the fin 1, and source / drain structures 3 located in the fin 1 on both sides of the initial gate structure 2, a contact etch stop layer 5 (CESL) conformally covering the top of the source / drain structures 3 and the sidewalls of the initial gate structure 2, and an interlayer dielectric layer 4 covering the contact hole etch stop layer 5.

[0021] like Figure 2 As shown, the initial gate structure 2 is etched back to a portion of its thickness to form a gate structure 6 and the first groove 7 located on the side of the interlayer dielectric layer 4.

[0022] like Figure 3 As shown, a gate cap layer 8 is formed in the first groove 7; a dielectric layer 9 is formed covering the gate cap layer 8 and the interlayer dielectric layer 4; after the dielectric layer 9 is formed, a mask layer 10 is formed on the dielectric layer 9 directly above a portion of the gate cap layer 8.

[0023] like Figure 4 As shown, the dielectric layer 9 is etched using the mask layer 10 as a mask to remove the interlayer dielectric layer 4 on the source / drain structure 3, forming a second groove 11. During the formation of the second groove 11, the mask layer 10 is consumed.

[0024] like Figure 5 As shown, the contact hole etching stop layer 5 at the bottom of the second groove 11 is removed to form a source / drain opening 13 that exposes the source / drain structure 3.

[0025] like Figure 6 As shown, a conductive material layer (not shown) is formed in the source / drain opening 13, and the conductive material layer covers the gate cap layer 8; the conductive material layer is planarized to form the source / drain contact layer 14.

[0026] During the formation of the source / drain opening 13, in order to maximize the area of ​​the top of the source / drain structure 3 exposed by the opening 13, excessive etching is performed. Consequently, the gate cap layer 8 on the gate structure 6 is further damaged. Furthermore, during the formation of the source / drain opening 13, the original mask layer 10 (such as...) is also etched excessively. Figure 3 The damage to the gate cap layer 8 between the two layers (as shown) is greater than the damage to the gate cap layer 8 directly below the original mask layer 10. The original mask layer 10 (as shown) Figure 3 The remaining thickness of the gate cap layer 8 between the two (as shown) is less than the thickness of the gate cap layer 8 directly below the original mask layer 10; after the conductive material layer is formed and the conductive material layer is planarized, the source-drain contact layer 14 is also formed on the top of part of the source-drain contact layer 14, and the source-drain contact layer 14 and the top of the gate structure 6 are easily bridged (CT-MG Short), resulting in poor electrical performance of the semiconductor structure.

[0027] In another case, such as Figure 7 As shown, in order to prevent the top of the source / drain contact layer 14 from bridging with the top of the gate structure 6, excessive etching is not performed during the formation of the source / drain opening 13. Consequently, the area of ​​the top of the source / drain structure 3 exposed by the source / drain opening 13 is small, resulting in a large contact resistance between the source / drain contact layer 14 and the source / drain structure 3, and poor electrical performance of the semiconductor structure.

[0028] refer to Figures 8 to 10 This shows a schematic diagram of the structure corresponding to each step in another method for forming a semiconductor structure.

[0029] like Figure 8 As shown, a substrate is provided, the substrate including a substrate (not shown), fins 1a discretely disposed on the substrate, a gate structure 6a spanning the fins 1a, source / drain structures 3a located in the fins 1a on both sides of the gate structure 6a, a contact etch stop layer 5a (CESL) conformally covering the top of the source / drain structures 3a and the sidewalls of the gate structure 6a, and an interlayer dielectric layer 4a covering the contact etch stop layer 5a. The substrate also includes a gate cap layer 8a formed on the top of the gate structure 6a; a dielectric layer 9a formed covering the gate cap layer 8a and the interlayer dielectric layer 4a; and a mask layer 10a formed on the dielectric layer 9a, the mask layer 10a being discretely formed on the dielectric layer 9a directly above each gate cap layer 8a.

[0030] like Figure 9 As shown, the dielectric layer 9a is etched using the mask layer 10a as a mask to remove the interlayer dielectric layer 4a on the source-drain structure 3a, forming a second groove (not shown in the figure). During the formation of the second groove, the mask layer 10a is consumed. The contact hole etching stop layer 5a at the bottom of the second groove is removed to form a source-drain opening 13a that exposes the source-drain structure 3a.

[0031] like Figure 10 As shown, a conductive material layer (not shown) is formed in the source / drain opening 13a, and the conductive material layer covers the gate cap layer 8a; the conductive material layer is planarized to form a source / drain contact layer 14a.

[0032] During the formation of the second groove and the formation of the source / drain opening 13a based on the second groove, because the mask layer 10a is formed on the dielectric layer 9a directly above each gate cap layer 8a, the damage to the gate cap layer 8a is relatively small during the formation of the source / drain opening 13a. Consequently, the angle between the sidewall of the source / drain opening 13a and the normal to the substrate surface is relatively large, and the area of ​​the top of the source / drain structure 3a exposed by the source / drain opening 13a is relatively small. This results in a large contact resistance between the source / drain contact layer 14a and the source / drain structure 3a, and poor electrical performance of the semiconductor structure.

[0033] To address the aforementioned technical problem, the method for forming the semiconductor structure includes forming a groove with the interlayer dielectric layer and the gate structure, and forming a first gate capping layer in the groove. Because the etching resistance of the first gate capping layer is greater than that of the interlayer dielectric layer, with increasingly higher integration density in semiconductor structures, the damage to the first gate capping layer is less during the formation of the first opening. This results in a larger process window for forming the first opening, enabling high-density first openings and optimizing the formation process of the first opening. Furthermore, because the damage to the first gate capping layer is less during the formation of the first opening exposing the source / drain structure, the first opening is less likely to expose the gate structure. Consequently, the source / drain contact layer formed in the first opening is less likely to bridge with the gate structure, achieving self-aligned contact between the source / drain contact layer and the source / drain structure. This improves the formation quality of the semiconductor structure and optimizes its electrical performance. Furthermore, because the damage to the first gate cap layer is minimal during the formation of the first opening, the space occupied by the first gate cap layer meets the process requirements. Removing the first gate cap layer forms the second opening, and the morphology of the second opening meets the process requirements. This ensures that the morphology of the second gate cap layer formed in the second opening meets the process requirements, which is beneficial to improving the electrical performance of the semiconductor structure.

[0034] The provided semiconductor structure includes: a substrate; a gate structure located on the substrate; a source / drain structure located within the substrate on both sides of the gate structure; a source / drain contact layer located on the source / drain structure between the gate structures; a protective layer located between the source / drain contact layer and the gate structure; and a gate capping layer located on the gate structure between the source / drain contact layers. The protective layer effectively isolates the source / drain contact layer and the gate structure, making it less prone to bridging and thus improving the electrical performance of the semiconductor structure.

[0035] This invention provides a semiconductor structure. Figure 11 A schematic diagram of the first embodiment of the semiconductor structure of the present invention is shown.

[0036] The semiconductor structure includes: a substrate; a gate structure 301 located on the substrate; a source / drain structure 302 located within the substrate on both sides of the gate structure 301; a source / drain contact layer 315 located on the source / drain structure 302 between the gate structures 301; a protective layer 310 located between the source / drain contact layer 315 and the gate structure 301; and a gate cap layer 316 located on the gate structure 301 between the source / drain contact layers 315.

[0037] In the semiconductor structure provided by this embodiment of the invention, a protective layer 310 is located between the source / drain contact layer 315 and the gate structure 301; a gate cap layer 316 is located on the gate structure 301 between the source / drain contact layers 315. The protective layer 310 can effectively isolate the source / drain contact layer 315 and the gate structure 301, making it less likely for the source / drain contact layer 315 and the gate structure 301 to bridge, which is beneficial to improving the electrical performance of the semiconductor structure.

[0038] The substrate includes a substrate 300 and fins 304 located on the substrate 300. Accordingly, the semiconductor structure is exemplified by a FinFET (Fin Field-Effect Transistor). In other embodiments, the substrate may also be a planar substrate, and the semiconductor structure is a planar transistor (MOSFET). In still other embodiments, the substrate further includes a plurality of suspended channel layers located on the fins, the channel layers being spaced apart in the normal direction of the substrate surface; accordingly, the semiconductor structure is a gate-all-around (GAA) transistor.

[0039] In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0040] In this embodiment, the material of the fin 304 is the same as the material of the substrate 300, including silicon.

[0041] The semiconductor structure further includes an isolation layer (not shown in the figure) located on the substrate 300 exposed by the fin 304, and the isolation layer covers a portion of the sidewall of the fin 304.

[0042] The isolation layer is used to isolate the gate structure 301 and the substrate 300. In this embodiment, the material of the isolation layer includes silicon oxide.

[0043] The gate structure 301 spans the fin 304 and covers part of the top wall and part of the side wall of the fin 304. In this embodiment, the direction of extension parallel to the surface of the substrate 300 and perpendicular to the extension direction of the gate structure 301 is defined as lateral.

[0044] When the semiconductor structure is in operation, the gate structure 301 is used to turn the channel on or off.

[0045] Specifically, the gate structure 301 includes a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer.

[0046] The semiconductor structure further includes a sidewall layer 306 located on the sidewall of the gate structure 301.

[0047] The sidewall layer 306 is used to electrically isolate the source / drain structure 302 and the gate structure 301, making it less likely for the source / drain structure 302 and the gate structure 301 to bridge. In addition, the sidewall layer 306 is also used to electrically isolate the source / drain contact layer 315 and the gate structure 301, making it less likely for the source / drain contact layer 315 to bridge with the gate structure 301, which is beneficial to improving the electrical performance of the semiconductor structure.

[0048] The sidewall layer 306 is made of a low-k dielectric material, which helps to reduce the capacitive coupling effect between the gate structure 301 and the source / drain structure 302 and the source / drain contact layer 315, thereby improving the electrical performance of the semiconductor structure.

[0049] In this embodiment, the material of the sidewall layer 306 includes SiOC.

[0050] The source / drain contact layer 315 is used to connect the source / drain structure 302 to the subsequent interconnect structure.

[0051] In this embodiment, the source / drain contact layer 315 is made of a conductive material. Specifically, the material of the source / drain contact layer 315 includes one or more of W, Co, and Ru. In this embodiment, the material of the source / drain contact layer 315 is W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0052] A protective layer 310 is located between the source / drain contact layer 315 and the gate structure 301. Specifically, the protective layer 310 is located on the sidewall of the source / drain contact layer 315, occupying the lateral space between the gate structures 301. This results in a smaller lateral dimension of the source / drain contact layer 315 located between the protective layers 310, which is beneficial for improving the integration density of the semiconductor structure. The protective layer 310 also works in conjunction with the sidewall layer 306 to electrically isolate the gate structure 301 from the source / drain structure 302 and the source / drain contact layer 315.

[0053] Specifically, the material of the protective layer 310 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and silicon hydroxide. In this embodiment, the material of the protective layer 310 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the protective layer 310.

[0054] It should be noted that the protective layer 310 should not be too thick or too thin. If the protective layer 310 is too thick, it will occupy too much lateral space between the gate structures 301, resulting in an excessively small lateral dimension of the source / drain contact layer 315 between the protective layers 310. Consequently, the contact area between the source / drain contact layer 315 and the source / drain structure 302 will be too small, leading to excessively high contact resistance and poor current characteristics of the semiconductor structure. If the protective layer 310 is too thin, it cannot effectively electrically isolate the gate structure 301 and the source / drain contact layer 315, making them prone to bridging and resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the protective layer 310 is 1 nanometer to 5 nanometers.

[0055] When the semiconductor structure is in operation, the source-drain structure 302 is used to provide stress to the channel and improve the migration rate of charge carriers in the channel.

[0056] In this embodiment, the semiconductor structure is used to form an NMOS (Negative channel Metal Oxide Semiconductor), and the source / drain structure 302 is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, the N-type ions include phosphorus, arsenic, or antimony.

[0057] In other embodiments, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source / drain structure is silicon germanide doped with P-type ions. In this embodiment, the P-type ions include boron, gallium, or indium.

[0058] During the formation of the semiconductor structure, the gate cap layer 316 is used to protect the top of the gate structure 301 from damage. When the semiconductor structure is working, it helps to improve the gate structure 301's control over the channel.

[0059] In this embodiment, the gate cap layer 316 is made of a dielectric material. Specifically, the material of the gate cap layer 316 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the gate cap layer 316 includes silicon nitride.

[0060] It should be noted that the gate cap layer 316 should not be too thick or too thin. If the gate cap layer 316 is too thick, the source / drain contact layer 315 is formed in the first opening (not shown in the figure). The first opening is formed by etching the interlayer dielectric layer. If the gate cap layer 316 is too thick, during the etching process of the interlayer dielectric layer and the formation of the first opening, the depth-to-width ratio of the first opening is large, and the generated reaction byproducts are not easily removed quickly, which hinders the etching process. This results in an excessively large angle between the sidewall of the first opening and the normal of the substrate 300 surface. In other words, the lateral dimension of the bottom of the first opening is smaller than the lateral dimension of the top of the first opening. The area of ​​the top of the source / drain structure 302 exposed by the first opening is small, and the corresponding contact area between the source / drain contact layer 315 and the source / drain structure 102 is small, resulting in a large contact resistance between the source / drain contact layer 315 and the source / drain structure 102. It should be noted that in extreme cases, during the formation of the first opening, because the reaction byproducts cannot be removed in time, the etching process of the first opening may even stop. The source / drain contact layer 315 formed in the first opening cannot connect with the source / drain structure 302, forming an open circuit. If the gate capping layer 316 is too thin, even if its etch resistance is greater than that of the interlayer dielectric layer, it is easily removed during the etching process to form the first opening exposing the source / drain structure 302. This results in the first opening easily exposing the gate structure 301, and the subsequent source / drain contact layer 315 formed in the first opening is prone to bridging with the gate structure 301, leading to poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the gate capping layer 316 is 5 nanometers to 30 nanometers.

[0061] It should be noted that the semiconductor structure further includes: a contact hole etch stop layer 308, located between the protective layer 310 and the gate structure 301, and between the protective layer 310 and the source / drain structure 302.

[0062] Specifically, the contact hole etch stop layer 308, located between the protective layer 310 and the gate structure 301, refers to the layer between the protective layer 310 and the sidewall layer 306.

[0063] During the formation of the semiconductor structure, in the process of etching the interlayer dielectric layer 303 to form the first opening exposing the source / drain structure 302, the contact hole etching stop layer 308 at the bottom of the interlayer dielectric layer 303 is etched. The etching rate of the contact hole etching stop layer 308 is less than the etching rate of the interlayer dielectric layer 303. The top of the contact hole etching stop layer 308 plays a role in temporarily stopping the etching, so that the problem of over-etching or under-etching in different areas is not likely to occur due to inconsistent etching rates. This is beneficial to improving the uniformity of the first opening formed subsequently. Correspondingly, it improves the morphological uniformity of the source / drain contact layer 315 and improves the electrical performance of the semiconductor structure.

[0064] In this embodiment, the material of the contact hole etching stop layer 308 includes silicon nitride.

[0065] refer to Figure 12 The diagram shows a schematic representation of a second embodiment of the semiconductor structure of the present invention.

[0066] The similarities between this embodiment and the first embodiment will not be repeated here. The differences between this embodiment and the first embodiment are as follows:

[0067] The semiconductor structure further includes a source / drain capping layer 418 located on the source / drain contact layer 416.

[0068] During the formation of the semiconductor structure, the source / drain capping layer 418 is used to protect the top of the source / drain contact layer 416 from damage, so that the source / drain contact layer 416 can better connect the source / drain structure 402 to the subsequent interconnect structure.

[0069] Specifically, the source / drain capping layer 418 is made of one or more of silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and silicon hydroxide. In this embodiment, the source / drain capping layer 418 is made of silicon nitride.

[0070] The semiconductor structure further includes: a first contact layer 422, which penetrates the source / drain cap layer 418 and contacts the source / drain contact layer 416; and a second contact layer 423, which penetrates the gate cap layer 420 and contacts the gate structure 401.

[0071] The first contact layer 422 is used to connect the source / drain contact layer 416 to the subsequent interconnect structure.

[0072] The second contact layer 423 is used to connect the gate structure 401 to the subsequent interconnect structure. The second contact layer 423 is located in the active area (AA), and correspondingly, the second contact layer 423 is an active gate contact hole plug (COAG), which can improve the integration of the semiconductor structure and optimize the electrical performance of the semiconductor structure.

[0073] In this embodiment, the first contact layer 422 and the second contact layer 423 are made of the same material, which is a conductive material. Specifically, the conductive material layer includes one or more of W, Co, and Ru. In this embodiment, the conductive material layer is made of W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0074] The semiconductor structure further includes a dielectric layer 421 located on the gate cap layer 420 and the source / drain cap layer 418 between the first contact layer 422 and the second contact layer 423.

[0075] The dielectric layer 421 is used to electrically isolate the first contact layer 422 and the second contact layer 423.

[0076] In this embodiment, the dielectric layer 421 is made of silicon oxide.

[0077] refer to Figures 13 to 21 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0078] refer to Figure 13 A substrate is provided, on which a gate structure 101 is formed. Source and drain structures 102 are formed in the substrate on both sides of the gate structure 101. An interlayer dielectric layer 103 is formed on the exposed portion of the substrate of the gate structure 101. The interlayer dielectric layer 103 covers the sidewalls of the source and drain structures 102 and the gate structure 101, and the top of the interlayer dielectric layer 103 is higher than the top of the gate structure 101. The interlayer dielectric layer 103 and the gate structure 101 form a groove 105.

[0079] The substrate provides the technological basis for the subsequent formation of the semiconductor structure. With the development of semiconductor technology, the integration density of semiconductor structures is increasing. Due to the limitations of photolithography, it is impossible to expose fine and excessively small patterns, such as those smaller than 20nm. In this embodiment, a mask layer is subsequently formed only directly above a portion of the gate structure 101.

[0080] In this embodiment, the step of providing the substrate includes a substrate 100 and a fin 104 located on the substrate 100. Accordingly, the subsequently formed semiconductor structure is a fin field-effect transistor (FinFET). In other embodiments, the substrate may also be a planar substrate, and the corresponding semiconductor structure is a planar transistor (MOSFET). In some other embodiments, the substrate further includes a channel stack located on the fin, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, and the corresponding subsequent semiconductor structure is a gate-all-around transistor (GAA).

[0081] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0082] In this embodiment, the material of the fin 104 is the same as the material of the substrate 100, including silicon.

[0083] The semiconductor structure further includes an isolation layer (not shown) located on the substrate 100 exposed by the fin 104, and the isolation layer covers a portion of the sidewall of the fin 104.

[0084] The isolation layer is used to isolate the gate structure 101 and the substrate 100. In this embodiment, the material of the isolation layer includes silicon oxide.

[0085] The gate structure 101 spans the fin 104 and covers part of the top wall and part of the sidewall of the fin 104. In this embodiment, the extending direction is parallel to the surface of the substrate 100 and perpendicular to the extending direction of the gate structure 101.

[0086] When the semiconductor structure is in operation, the gate structure 101 is used to turn the channel on or off.

[0087] Specifically, the gate structure 101 includes a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer.

[0088] The sidewall layer 106 is used to electrically isolate the source / drain structure 102 and the gate structure 101. Furthermore, during the subsequent etching of the interlayer dielectric layer 103 on top of the source / drain structure 102 to form a first opening exposing the source / drain structure 102, the sidewall layer 106 defines the formation position of the first opening, making it less likely for the source / drain contact layer subsequently formed at the first opening to bridge with the gate structure 101, thus improving the electrical performance of the semiconductor structure. Additionally, after a first gate capping layer is formed in the groove 105 and the source / drain contact layer is formed, the first gate capping layer is removed, forming a second opening on top of the gate structure. The sidewall layer 106 defines the formation position of the second opening, resulting in higher morphological uniformity of the second openings in each region, which further improves the electrical performance of the semiconductor structure.

[0089] The sidewall layer 106 is made of a low-k dielectric material, which helps to reduce the capacitive coupling effect between the gate structure 101 and the source / drain contact layer 103 and improve the electrical performance of the semiconductor structure.

[0090] The material of the sidewall layer 106 includes SiOC.

[0091] When the semiconductor structure is in operation, the source-drain structure 102 is used to provide stress to the channel and improve the migration rate of charge carriers in the channel.

[0092] In this embodiment, the semiconductor structure is used to form an NMOS (Negative channel Metal Oxide Semiconductor), and the source / drain structure 102 is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, the N-type ions include phosphorus, arsenic, or antimony.

[0093] In other embodiments, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain structures are doped with silicon germanide containing P-type ions. In this embodiment, the P-type ions include boron, gallium, or indium.

[0094] The interlayer dielectric layer 103 is used for electrical isolation of adjacent devices. In this embodiment, the material of the interlayer dielectric layer 103 is an insulating material. Specifically, the material of the interlayer dielectric layer 103 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 103.

[0095] In this embodiment, the groove 105 provides process space for the subsequent formation of the first gate cap layer.

[0096] In the step of providing the substrate, contact hole etch stop layers 108 are formed on the bottom and sides of the interlayer dielectric layer 103.

[0097] During the subsequent etching of the interlayer dielectric layer 103 to form the first opening exposing the source / drain structure 102, the etching rate of the contact hole etching stop layer 108 is less than the etching rate of the interlayer dielectric layer 103. The top of the contact hole etching stop layer 108 serves as a temporary etching stop, making it less likely for different areas to experience over-etching or under-etching due to inconsistent etching rates, which helps improve the uniformity of the first opening.

[0098] In this embodiment, the material of the contact hole etching stop layer 108 includes silicon nitride.

[0099] It should be noted that in the step of providing the substrate, the groove 105 should not be too deep or too shallow. If the groove 105 is too deep, and the first gate cap layer subsequently formed in the groove 105 is too thick, the interlayer dielectric layer 103 will also be too thick. Subsequently, removing the interlayer dielectric layer 103 will result in an excessively deep first opening, leading to an excessively large aspect ratio. During the formation of the first opening, reaction byproducts will be difficult to remove quickly, hindering the etching process. This results in an excessively large angle between the sidewall of the first opening and the normal to the surface of the substrate 100. In other words, the lateral dimension of the bottom of the first opening is smaller than the lateral dimension of the top of the first opening. The area of ​​the top of the source / drain structure 102 exposed by the first opening is small, resulting in a small contact area between the source / drain contact layer and the source / drain structure 102 subsequently formed in the first opening. This leads to a larger contact resistance between the source / drain contact layer and the source / drain structure 102. It should be noted that, in extreme cases, during the formation of the first opening, the etching process of the first opening may even stop because the reaction byproducts cannot be eliminated in time. This would prevent the source / drain contact layer formed in the first opening from connecting with the source / drain structure 102, resulting in an open circuit. If the groove 105 is too shallow, the thickness of the first gate capping layer subsequently formed in the groove 105 will be small. Even if the etching resistance of the first gate capping layer is greater than that of the interlayer dielectric layer, the gate capping layer is easily removed during the etching of the interlayer dielectric layer 103 to form the first opening exposing the source / drain structure 102. This would cause the first opening to easily expose the gate structure 101, and consequently, the source / drain contact layer subsequently formed in the first opening would easily bridge with the gate structure 101, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the depth of the groove 105 in the step of providing the substrate is 5 nanometers to 30 nanometers.

[0100] refer to Figure 14A first gate cap layer 107 is formed in the groove 105, and the etching resistance of the first gate cap layer 107 is greater than that of the interlayer dielectric layer 103.

[0101] Because the etching resistance of the first gate capping layer 107 is greater than that of the interlayer dielectric layer 103, with the increasing integration of semiconductor structures, the damage to the first gate capping layer 107 during the formation of the first opening is smaller. This results in a larger process window for the formation of the first opening, enabling the acquisition of a high-density first opening and optimizing the formation process of the first opening. Furthermore, because the etching resistance of the first gate capping layer 107 is greater than that of the interlayer dielectric layer 103, the damage to the first gate capping layer 107 is smaller during the etching of the interlayer dielectric layer 103 to form the first opening exposing the source / drain structure 102. The first opening is less likely to expose the gate structure 101, and correspondingly, the source / drain contact layer formed in the first opening is less likely to bridge with the gate structure 101. This achieves self-aligned contact between the source / drain contact layer and the source / drain structure 302, which is beneficial for improving the formation quality of the semiconductor structure and optimizing its electrical performance. Furthermore, the first gate capping layer 107 occupies space for the subsequent second gate capping layer, and because the first gate capping layer 107 suffers less damage during the formation of the first opening, the space occupied by the first gate capping layer 107 meets the process requirements. Removing the first gate capping layer 107 forms the second opening, and the morphology of the second opening meets the process requirements. This makes the morphology of the second gate capping layer formed in the second opening meet the process requirements, which is beneficial to improving the electrical performance of the semiconductor structure.

[0102] In this embodiment, the first gate capping layer 107 is located on top of the gate structure 101, and the interlayer dielectric layer 103 is located between the first gate capping layers 107. Because the etching resistance of the first gate capping layer 107 is greater than that of the interlayer dielectric layer 103, the interlayer dielectric layer 103 is etched at a faster rate. During the process of forming the first opening through the interlayer dielectric layer 103, the damage to the first gate capping layer 107 is smaller. Consequently, the gate structure 101 below the first gate capping layer 107 is less likely to be damaged, and the source / drain structure 102 can be exposed through the first opening in a self-aligned manner.

[0103] During the etching of the interlayer dielectric layer 103 to form the first opening exposing the source / drain structure 102, the first gate cap layer 107 is used to protect the top of the gate structure 101 from damage. When the semiconductor structure is working, it helps to improve the control capability of the gate structure 101 over the channel and optimize the electrical performance of the semiconductor structure.

[0104] Specifically, the material of the first gate cap layer 107 includes one or more of aluminum, aluminum oxide, aluminum nitride, titanium nitride, titanium oxide, and tungsten oxide. In this embodiment, the material of the first gate cap layer 107 includes aluminum oxide.

[0105] In this embodiment, the step of forming a first gate cap layer 107 in the groove 105 includes: forming a first cap material layer (not shown in the figure) on the groove 105 and the interlayer dielectric layer 103; removing the first cap material layer above the interlayer dielectric layer 103, and the remaining first cap material layer located in the groove 105 as the first gate cap layer 107.

[0106] In this embodiment, the first capping material layer is formed using Physical Vapor Deposition (PVD). PVD offers advantages such as low deposition temperature (typically below 550°C), fast deposition rate, controllable composition and structure of the deposited layer, simple operation, high efficiency, and low cost. Furthermore, PVD is highly compatible with existing equipment and processes. In other embodiments, the first capping material layer can also be formed using Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD).

[0107] In this embodiment, chemical mechanical planarization (CMP) is used to remove the first capping material layer above the interlayer dielectric layer 103. The remaining first capping material layer located in the groove 105 serves as the first gate capping layer 107. CMP is a global surface planarization technique. While removing the first capping material layer above the interlayer dielectric layer 103, it helps improve the flatness of the top surface of the interlayer dielectric layer 103 and the top surface of the first gate capping layer 107, providing a highly flat surface for the subsequent etching process to form the first opening and improving the formation quality of the first opening.

[0108] refer to Figures 15 to 18 A first opening 109 is formed that penetrates the interlayer dielectric layer 103 and exposes the source / drain structure 102.

[0109] The first opening 109 prepares for the subsequent formation of the source / drain contact layer.

[0110] Specifically, the step of forming a first opening 109 that penetrates the interlayer dielectric layer 103 and exposes the source / drain structure 102 includes:

[0111] like Figure 15As shown, a first dielectric layer 111 is formed on the first gate cap layer 107 and the interlayer dielectric layer 103; a mask layer 112 is formed on the first dielectric layer 111 directly above a portion of the gate structure 101.

[0112] It should be noted that, compared with the case where a mask layer is formed directly above each of the gate structures, during the formation of the mask layer 112, the mask layer 112 is only located directly above a portion of the gate structures 101, which increases the process window of the mask layer 112 and reduces the process difficulty of forming the mask layer 112.

[0113] Specifically, such as Figure 15 As shown, six gate structures 101 are illustrated. The mask layer 112 exposes two consecutive gate structures 101 and three interlayer dielectric layers 103 located between the gate structures 101. In this case, during the subsequent etching of the interlayer dielectric layers 103 to form the first opening exposing the source / drain structures 102, even if the mask layer 112 is not formed directly above part of the gate structures 101, the damage to the first gate cap layer 107 is still relatively small because the etching resistance of the first gate cap layer 107 is greater than that of the interlayer dielectric layers 103. The first opening is still not easy to expose the gate structure 101, and correspondingly, the source / drain contact layer formed in the first opening is not easy to bridge with the gate structure 101, achieving self-aligned contact between the source / drain contact layer and the source / drain structure 302. This is beneficial to improving the formation quality of the semiconductor structure and optimizing the electrical performance of the semiconductor structure.

[0114] The first dielectric layer 111 provides a flat process platform for forming the mask layer 112, which is beneficial for subsequent pattern transfer based on the mask layer 112 to form the first opening that exposes the source-drain structure 102.

[0115] In this embodiment, the material of the first dielectric layer 111 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the first dielectric layer 111.

[0116] In this embodiment, the first dielectric layer 111 is formed using a flowable chemical vapor deposition (FCVD) process, which helps to achieve a higher flatness on the surface of the first dielectric layer 111.

[0117] like Figures 16 to 18 As shown, the first dielectric layer 111 and the interlayer dielectric layer 103 are etched using the mask layer 112 as a mask to form the first opening 109 (e.g., ...). Figure 18 (As shown).

[0118] In this embodiment, the first dielectric layer 111 and the interlayer dielectric layer 103 are etched using a dry etching process with the mask layer 112 as a mask to form the first opening 109. The dry etching process has anisotropic etching characteristics, good control over the etching profile, and can obtain fairly accurate pattern transformation, which is beneficial to ensuring that the morphology of the first opening 109 meets the process requirements.

[0119] It should be noted that during the process of etching the first dielectric layer 111 and the interlayer dielectric layer 103 using a dry etching process to form the first opening 109, the mask layer 112 will be consumed and removed, and the first dielectric layer 111 will also be consumed and removed.

[0120] It should be noted that during the process of forming the first opening 109 that penetrates the interlayer dielectric layer 103 and exposes the source / drain structure 102, the top of the sidewall layer 106 and the contact hole etch stop layer 108 on the top of the sidewall of the first gate cap layer 107 are etched.

[0121] In this embodiment, during the step of forming the first opening 109, a protective layer 110 is formed on the sidewall of the first opening 109.

[0122] The first opening 109 exposes the source / drain structure 102, meaning that the first opening 109 is located between the gate structures 101. Subsequently, a source / drain contact layer is formed in the first opening 109. Because the protective layer 110 is located on the sidewall of the first opening 109, the protective layer 110 can electrically isolate the source / drain contact layer and the gate structure 101, making it less likely for the source / drain contact layer and the gate structure 101 to bridge, which is beneficial to improving the electrical performance of the semiconductor structure.

[0123] The protective layer 110 is formed on the sidewall of the first protective layer 109, that is, the protective layer 110 is formed between adjacent gate structures 101. The lateral space between the gate structures 101 is reduced, which makes the lateral size of the source and drain contact layer subsequently formed in the first opening 109 smaller, which is beneficial to improving the integration of the semiconductor structure.

[0124] Specifically, the material of the protective layer 110 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and silicon hydroxide. In this embodiment, the material of the protective layer 110 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the protective layer 110.

[0125] It should be noted that the protective layer 110 should not be too thick or too thin. If the protective layer 110 is too thick, it will occupy too much lateral space between the gate structures 301. If the lateral dimension of the first opening 109 between the protective layers 110 is too small, the lateral dimension of the source / drain contact layer subsequently formed in the first opening 109 will be too small, the contact area between the source / drain contact layer and the source / drain structure 102 will be too small, and the contact resistance between the source / drain contact layer and the source / drain structure 102 will be too large, resulting in poor current characteristics of the semiconductor structure. If the protective layer 110 is too thin, it cannot effectively electrically isolate the gate structure 101 from the subsequent source / drain contact layer formed in the first opening 109. The gate structure 101 and the source / drain contact layer are prone to bridging, resulting in poor electrical performance of the semiconductor structure. Furthermore, if the protective layer 110 is too thin, metal ions in the first gate cap layer 107 can easily diffuse to the sidewalls of the protective layer 110 facing away from the first gate cap layer 107, i.e., the sidewalls of the first opening 109. During the subsequent formation of the source / drain contact layer 115 in the first opening 109, the metal ions on the sidewalls of the first opening 109 cannot provide a good growth or deposition environment for the source / drain contact layer, leading to poor formation quality of the source / drain contact layer 115. In this embodiment, the thickness of the protective layer 110 is 1 nanometer to 5 nanometers.

[0126] Specifically, the steps for forming the protective layer 110 include:

[0127] like Figure 16 As shown, the interlayer dielectric layer 103 is etched to form a third opening 113 penetrating the interlayer dielectric layer 103.

[0128] The third opening 113 provides process space for the conformal covering protective material layer.

[0129] In this embodiment, the interlayer dielectric layer 103 is etched using a dry etching process to form the third opening 113. In other embodiments, a combination of dry and wet etching processes can also be used to form the third opening.

[0130] like Figure 17 As shown, a protective material layer 114 is formed to conformally cover the third opening 113 and the first gate cap layer 107.

[0131] The protective material layer 114 prepares for the subsequent formation of a protective layer.

[0132] In this embodiment, the protective material layer 114 is formed using a chemical vapor deposition (CVD) process. CVD is a method for generating a thin film by chemically reacting one or more gaseous compounds or elements containing thin film elements. It has good step coverage and allows for control over the deposition thickness of the protective material layer 114, thereby controlling the thickness of the subsequently formed protective layer. In other embodiments, the protective material layer can also be formed using atomic layer deposition (ALD).

[0133] like Figure 18 As shown, the protective material layer 114 at the top of the first gate cap layer 107 and the protective material layer 114 at the bottom of the third opening 113 are removed, and the remaining protective material layer 114 located on the sidewall of the third opening 113 serves as the protective layer 110.

[0134] In this embodiment, a maskless dry etching process is used to remove the protective material layer 114 on top of the first gate cap layer 107 and the protective material layer 114 at the bottom of the third opening 113. The maskless dry etching process has anisotropic etching characteristics, which helps to ensure that the protective material layers 114 on top of the first gate cap layer 107 and at the bottom of the third opening 113 are completely removed while minimizing damage to the protective material layer 114 on the sidewall of the first opening 109. This makes it less likely that the thickness of the protective material layer 114 on the side of the gate structure 101 will be reduced, allowing the formed first opening 109 to self-align and expose the source / drain structure 102. Simultaneously, the protective layer 110 has a larger lateral dimension, thus preventing bridging between the gate structure 101 and the subsequently formed source / drain contact layer. Furthermore, the process of removing the protective material layer 114 located at the top of the first gate cap layer 107 and the bottom of the third opening 113 using a maskless etching process does not require a photomask, thus reducing process costs.

[0135] It should be noted that the step of forming the first opening 109 that penetrates the interlayer dielectric layer 103 and exposes the source / drain structure 102 further includes: etching the contact hole etching stop layer 108 at the top of the source / drain structure 102 to expose the source / drain structure 102.

[0136] Accordingly, the first opening 109 is formed by the source / drain structure 102, the contact hole etch stop layer 108, and the protective layer 110.

[0137] In this embodiment, a dry etching process is used to etch the contact hole etching stop layer 108 at the top of the source / drain structure 102, exposing the source / drain structure 102. Furthermore, during the etching of the contact hole etching stop layer 108 at the top of the source / drain structure 102, using the top of the source / drain structure 102 as the etching stop position helps reduce damage to other film layers.

[0138] refer to Figure 19 A source / drain contact layer 115 is formed in the first opening 109.

[0139] The source / drain contact layer 115 is used to connect the source / drain structure 102 to the subsequent interconnect structure.

[0140] Specifically, the material of the source / drain contact layer 115 includes one or more of W, Co, and Ru. In this embodiment, the material of the source / drain contact layer 115 is W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0141] The step of forming the source / drain contact layer 115 in the first opening 109 includes: forming a source / drain conductive material layer in the first opening 109 and on the first gate cap layer 107; removing the source / drain conductive material layer above the first gate cap layer 107 using a planarization process, and the remaining source / drain conductive material layer located in the first opening 109 as the source / drain contact layer 115.

[0142] In this embodiment, chemical mechanical planarization (CMP) is used to remove the source / drain conductive material layer above the first gate cap layer 107. CMP is a global surface planarization technique that, while removing the source / drain conductive material layer above the first gate cap layer 107, also ensures a high degree of flatness on the top surfaces of the first gate cap layer 107, sidewall layer 106, contact hole etch stop layer 108, and protective layer 110.

[0143] In this embodiment, an electrochemical plating (ECP) process is used to form a source / drain conductive material layer in the first opening 109. The electrochemical plating process has advantages such as simple operation, fast deposition speed, and low cost.

[0144] It should be noted that after removing the source and drain conductive material layers above the first gate cap layer 107 using a planarization process, the top of the first gate cap layer 107, sidewall layer 106, contact hole etch stop layer 108, and protective layer 110 are further planarized to provide a flat platform for subsequent semiconductor processes, which is beneficial to improving the uniformity of the semiconductor structure.

[0145] refer to Figure 20 After forming the source / drain contact layer 115, the first gate cap layer 107 is removed, and a second opening 116 is formed on the top of the gate structure 101.

[0146] The first gate capping layer 107 is removed to form a second opening 116, which prepares for the subsequent formation of a second gate capping layer in the second opening 116.

[0147] Specifically, the second opening 116 is formed by the sidewall layer 106 and the gate structure 101.

[0148] The first gate capping layer 107 is made of the metal element Al. Removing the first gate capping layer 107 makes it difficult for the metal ions Al in the first gate capping layer 107 to diffuse into the bottom gate structure 101 and source / drain structure 102. During the operation of the semiconductor structure, the gate structure 101 can better control the opening and closing of the channel, and the source / drain structure 102 can provide sufficient stress to the channel, improving the migration rate of charge carriers in the channel. In addition, the first gate capping layer 107 includes the metal element Al, resulting in poor insulation performance of the first gate capping layer 107. If the first gate capping layer 107 is retained, a gate contact layer is subsequently formed that penetrates the first gate capping layer 107 and the gate structure 101. The first gate capping layer 107 cannot effectively electrically isolate the gate contact layer, resulting in poor electrical performance of the semiconductor structure.

[0149] In this embodiment, a wet etching process is used to remove the first gate capping layer 107, forming a second opening 116 on the top of the gate structure 101. In other embodiments, a combination of wet and dry etching processes can be used to remove the first gate capping layer.

[0150] Specifically, the material of the first gate cap layer 107 includes aluminum oxide. The corresponding wet etching solution includes one or both of NH4OH and KOH.

[0151] refer to Figure 21 A second gate cap layer 117 is formed in the second opening 116.

[0152] In subsequent semiconductor processes, the second gate capping layer 117 is used to protect the top of the gate structure 101 from damage, allowing the gate structure 101 to better control the opening and closing of the channel. Furthermore, compared to the first gate capping layer 107 (as in...), the second gate capping layer 117... Figure 18 The second gate capping layer 117 (as shown) has better insulation properties, and a gate contact layer is subsequently formed that penetrates the second gate capping layer 117 and contacts the gate structure 101. The second gate capping layer 117 can better electrically isolate the gate contact layer and improve the electrical performance of the semiconductor structure.

[0153] In this embodiment, the material of the second gate cap layer 117 includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and silicon hydroxide.

[0154] In this embodiment, the step of forming a second gate capping layer 117 in the second opening 116 includes: forming a second capping material layer on the second opening 116 and the source / drain contact layer 115; removing the second capping material layer above the source / drain contact layer 115, and leaving the remaining second capping material layer in the second opening 116 as the second gate capping layer 117.

[0155] In this embodiment, the second capping material layer is formed using chemical vapor deposition. In other embodiments, the second capping material layer may also be formed using atomic layer deposition.

[0156] In this embodiment, a planarization process is used to remove the second capping material layer above the source / drain contact layer 115. Specifically, the planarization process includes a chemical mechanical polishing process.

[0157] refer to Figures 22 to 27 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention.

[0158] The similarities between this embodiment and the first embodiment will not be repeated here. The difference between this embodiment and the first embodiment is that a source / drain capping layer 218 is formed on top of the source / drain contact layer 216.

[0159] During the formation of the semiconductor structure, the source / drain capping layer 218 is used to protect the top of the source / drain contact layer 216 from damage.

[0160] Specifically, the step of forming the source / drain contact layer 216 in the first opening (not shown in the figure) includes:

[0161] like Figure 22 As shown, an initial source / drain contact layer 215 is formed in the first opening.

[0162] like Figure 23 As shown, the initial source / drain contact layer 215 with a partial thickness is etched to form the source / drain contact layer 216 and a fourth opening 217 located on top of the source / drain contact layer 216.

[0163] In this embodiment, a portion of the initial source / drain contact layer 215 is etched using a dry etching process to form the source / drain contact layer 216 and a fourth opening 217 located on top of the source / drain contact layer 216. The dry etching process has anisotropic etching characteristics, providing good control over the etching profile and enabling highly accurate pattern transformation, which helps ensure the morphology of the fourth opening 217 meets process requirements. Furthermore, during the dry etching process, the removal rate of the initial source / drain contact layer 215 is greater than the removal rate of the first gate cap layer 207, resulting in less damage to the first gate cap layer 207. Moreover, the dry etching process allows for precise control of the removal thickness of the initial source / drain contact layer 215, thereby ensuring the depth of the fourth opening 217 reaches the preset target, which is beneficial for improving the electrical performance of the semiconductor structure.

[0164] like Figure 24 As shown, a source / drain cap layer 218 is formed in the fourth opening 217.

[0165] In subsequent semiconductor processes, the source / drain capping layer 218 is used to protect the top of the source / drain contact layer 216 from damage, so that the source / drain contact layer 216 can better connect the source / drain structure 202 to the subsequent interconnect structure.

[0166] In this embodiment, the material of the source / drain capping layer 218 includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and silicon hydroxide.

[0167] In this embodiment, the step of forming the source / drain capping layer 218 in the fourth opening 217 includes: forming a source / drain capping material layer on the fourth opening 217 and the source / drain contact layer 216; removing the source / drain capping material layer above the first gate capping layer 207, and leaving the remaining source / drain capping material layer in the fourth opening 217 as the source / drain capping layer 218.

[0168] In this embodiment, the source / drain capping material layer is formed using chemical vapor deposition. In other embodiments, the source / drain capping material layer can also be formed using atomic layer deposition.

[0169] In this embodiment, a planarization process is used to remove the source / drain capping material layer that is higher than the first gate capping layer 207, and the remaining source / drain capping material layer located in the fourth opening 217 serves as the source / drain capping layer 218.

[0170] Specifically, the planarization process includes chemical mechanical polishing.

[0171] like Figure 25As shown, the method for forming the semiconductor structure further includes: after forming the source / drain contact layer 216, removing the first gate cap layer 207, and forming a second opening 219 on the top of the gate structure 201.

[0172] The removal of the first gate capping layer 207 forms a second opening 219. The function of forming a second gate capping layer in the second opening is not described here.

[0173] In this embodiment, a wet etching process is used to remove the first gate cap layer 207, forming a second opening 219 on the top of the gate structure 201.

[0174] refer to Figure 26 A second gate cap layer 220 is formed in the second opening 219.

[0175] In subsequent semiconductor processes, the second gate capping layer 220 is used to protect the top of the gate structure 201 from damage, so that the gate structure 201 can better control the opening and closing of the channel.

[0176] In this embodiment, the material of the second gate cap layer 220 includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and silicon hydroxide.

[0177] refer to Figure 27 The method for forming the semiconductor structure further includes: after forming the second gate cap layer 220, forming a second dielectric layer 221 on the second gate cap layer 220 and the source / drain contact layer 216.

[0178] The second dielectric layer 221 is used to electrically isolate the first and second contact plugs subsequently formed.

[0179] The material of the second dielectric layer 221 includes silicon oxide.

[0180] In this embodiment, the second dielectric layer 221 is formed using a flowable chemical vapor deposition process, which helps to achieve a higher flatness on the surface of the second dielectric layer 221.

[0181] The second dielectric layer 221 and the source / drain cap layer 218 are etched to form a first contact hole (not shown in the figure) exposing the source / drain contact layer 216; the second dielectric layer 221 and the second gate cap layer 220 are etched to form a second contact hole (not shown in the figure) exposing the gate structure 201; a rear conductive material layer (not shown in the figure) is formed in the first contact hole and the second contact hole, wherein the rear conductive material layer in the first contact hole serves as the first contact layer 222 and the rear conductive material layer in the second contact hole serves as the second contact layer 223.

[0182] The first contact layer 222 is used to connect the source / drain contact layer 216 to the subsequent interconnect structure.

[0183] The second contact layer 223 is used to connect the gate structure 201 to the subsequent interconnect structure. The second contact layer 223 is located in the active area (AA), and correspondingly, the second contact layer 223 is an active gate contact hole plug (COAG), which can improve the integration of the semiconductor structure and optimize the electrical performance of the semiconductor structure.

[0184] Specifically, the material of the back-end conductive material layer includes one or more of W, Co, and Ru. In this embodiment, the material of the back-end conductive material layer is W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0185] In this embodiment, an electrochemical electroplating process is used to form a downstream conductive material layer in the first and second contact holes. The electrochemical electroplating process has advantages such as simple operation, fast deposition speed, and low cost.

[0186] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a gate structure is formed, and source / drain structures are formed within the substrate on both sides of the gate structure. An interlayer dielectric layer is formed on the exposed portion of the substrate of the gate structure, the interlayer dielectric layer covering the sidewalls of the source / drain structures and the gate structure, and the top of the interlayer dielectric layer being higher than the top of the gate structure. The interlayer dielectric layer and the gate structure form a groove. In the step of providing the substrate, contact hole etch stop layers are formed at the bottom and sides of the interlayer dielectric layer. A first gate capping layer is formed in the groove, located on top of the gate structure. The material of the first gate capping layer contains metal elements. The etching resistance of the first gate capping layer is greater than that of the interlayer dielectric layer. During the subsequent formation of the first opening through the interlayer dielectric layer, the interlayer dielectric layer is etched at a faster rate, and the damage to the first gate capping layer is smaller. As a result, the first opening can self-align and expose the source and drain structure. The interlayer dielectric layer is located between the first gate capping layers. A first opening is formed that penetrates the interlayer dielectric layer and exposes the source / drain structure; wherein a protective layer is formed on the sidewall of the first opening, and the protective layer occupies the lateral space between the gate structures; A source / drain contact layer is formed in the first opening, which is surrounded by a source / drain structure, a contact hole etch stop layer, and a protective layer; wherein, based on the protective layer, the gate structure is electrically isolated from the source / drain structure and the source / drain contact layer. After forming the source / drain contact layer, the first gate cap layer is removed, and a second opening is formed on the top of the gate structure; A second gate capping layer is formed in the second opening, and the material of the second gate capping layer includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and silicon hydroxide.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first gate cap layer includes one or more of aluminum, aluminum oxide, aluminum nitride, titanium nitride, titanium oxide, and tungsten oxide.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the first gate cap layer in the groove includes: A first capping material layer is formed on the groove and the interlayer dielectric layer; The first capping material layer above the interlayer dielectric layer is removed, and the remaining first capping material layer located in the groove serves as the first gate capping layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first capping material layer is formed using atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first capping material layer, which is higher than the interlayer dielectric layer, is removed using a chemical mechanical polishing process.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first opening that penetrates the interlayer dielectric layer and exposes the source / drain structure includes: A first dielectric layer is formed on the first gate cap layer and the interlayer dielectric layer; A mask layer is formed on the first dielectric layer directly above part of the gate structure; The first dielectric layer and the interlayer dielectric layer are etched using the mask layer as a mask to form the first opening.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the depth of the groove is 5 nanometers to 30 nanometers.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and silicon hydroxide.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the protective layer is 1 nanometer to 5 nanometers.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for forming the protective layer include: The interlayer dielectric layer is etched to form a third opening penetrating the interlayer dielectric layer; A protective material layer is formed to conformally cover the third opening and the first gate cap layer; Remove the protective material layer on top of the first gate cap layer and the protective material layer at the bottom of the third opening, and the remaining protective material layer located on the sidewall of the third opening serves as a protective layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The protective material layer is formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the source / drain contact layer in the first opening includes: A source / drain conductive material layer is formed in the first opening and on the first gate cap layer; The source / drain conductive material layer above the first gate cap layer is removed, and the remaining source / drain conductive material layer located in the first opening serves as the source / drain contact layer.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first gate cap layer is removed by using a wet etching process or a combination of wet and dry etching processes, and a second opening is formed on the top of the gate structure.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the second gate cap layer in the second opening includes: A second capping material layer is formed on the second opening and the source / drain contact layer; Remove the second capping material layer above the source / drain contact layer, and the remaining second capping material layer in the second opening serves as the second gate capping layer.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the source / drain contact layer in the first opening includes: An initial source / drain contact layer is formed in the first opening; The initial source / drain contact layer of a certain thickness is etched to form the source / drain contact layer and a fourth opening located on top of the source / drain contact layer; A source / drain cap layer is formed in the fourth opening.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the semiconductor structure further includes: After the second gate capping layer is formed, a second dielectric layer is formed on the second gate capping layer and the source / drain capping layer; The second dielectric layer and the source / drain cap layer are etched to form a first contact hole that exposes the source / drain contact layer; The second dielectric layer and the second gate cap layer are etched to form a second contact hole that exposes the gate structure; A first contact layer is formed in the first contact hole; A second contact layer is formed in the second contact hole.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method for forming a semiconductor structure according to any one of claims 1 to 16, wherein the semiconductor structure comprises: Base; A gate structure is located on the substrate; The source / drain structure is located within the substrate on both sides of the gate structure; A source / drain contact layer is located on the source / drain structures between the gate structures; A protective layer is located between the source / drain contact layer and the gate structure; wherein the protective layer occupies the lateral space between the gate structures, and based on the protective layer, the gate structure is electrically isolated from the source / drain structure and the source / drain contact layer; A gate cap layer is located on the gate structure between the source and drain contact layers.

18. The semiconductor structure as claimed in claim 17, characterized in that, The material of the protective layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxycarbonate, silicon carbonitride, and silicon hydroxide.

19. The semiconductor structure as claimed in claim 17, characterized in that, The thickness of the protective layer is 1 nanometer to 5 nanometers.

20. The semiconductor structure as claimed in claim 17, characterized in that, The semiconductor structure further includes: a source / drain capping layer located on the source / drain contact layer; The semiconductor structure further includes: a first contact layer that penetrates the source / drain cap layer and contacts the source / drain contact layer; and a second contact layer that penetrates the gate cap layer and contacts the gate structure.

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