Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor device capable of forming a suitable pad and a manufacturing method thereof. According to one embodiment, the semiconductor device has a first pad, which is a first pad provided in a first insulating film, including a first layer provided on a side surface and a lower surface of the first insulating film, and a second layer provided on the side surface and the lower surface of the first insulating film via the first layer. The above device further has a second pad, which is a second pad provided on the first pad in a second insulating film on the first insulating film, including a third layer provided on a side surface and an upper surface of the second insulating film, and a fourth layer provided on the side surface and the upper surface of the second insulating film via the third layer. The above device further has a first portion provided between an upper surface of the first pad and a lower surface of the second insulating film, or between a lower surface of the second pad and an upper surface of the first insulating film, including a metal element identical to a metal element contained in the first layer or the third layer.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2020-208637 (filed on December 16, 2020), which is the basic application. This application incorporates the entire contents of the basic application by reference to it. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] In the fabrication of semiconductor devices by bonding metal pads and insulating films on one substrate to metal pads and insulating films on another substrate, sometimes the surface of the metal pad on one substrate is exposed onto the surface of the insulating film on the other substrate. In this case, problems such as the diffusion of metal atoms (e.g., copper atoms) from the exposed surface of the metal pad may occur. Summary of the Invention

[0005] The embodiments provide a semiconductor device capable of forming a suitable pad and a method for manufacturing the same.

[0006] According to one embodiment, a semiconductor device includes a first insulating film and a first pad, the first pad being disposed within the first insulating film and comprising a first layer disposed on the side surface and lower surface of the first insulating film, and a second layer disposed on the side surface and lower surface of the first insulating film through the first layer. The device further comprises a second insulating film and a second pad disposed on the first insulating film, the second pad being disposed within the second insulating film on the first pad, and comprising a third layer disposed on the side surface and upper surface of the second insulating film, and a fourth layer disposed on the side surface and upper surface of the second insulating film through the third layer. The device further comprises a first portion disposed between the upper surface of the first pad and the lower surface of the second insulating film, or between the lower surface of the second pad and the upper surface of the first insulating film, comprising a metal element identical to the metal element contained in the first layer or the third layer. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a cross-sectional view showing the structure of the columnar portion CL in the first embodiment.

[0009] Figures 3-4 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0010] Figure 5 This is a cross-sectional view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0011] Figure 6 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0012] Figures 7-11 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0013] Figure 12 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0014] Figures 13-16 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment.

[0015] Figure 17 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

[0016] Figure 18 This is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment.

[0017] Figure 19 This is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment.

[0018] Figure 20 This is a cross-sectional view showing the structure of the semiconductor device according to the sixth embodiment.

[0019] Explanation of symbols

[0020] 1: Array chip; 2: Circuit chip;

[0021] 11: Memory cell array; 12: Insulating film; 13: Interlayer insulating film; 13a: Insulating film.

[0022] 13b: Insulating film, 13c: Insulating film, 13d: Insulating film, 13e: Insulating film

[0023] 14: Interlayer insulating film, 14a: Insulating film, 14b: Insulating film, 14c: Insulating film

[0024] 14d: Insulating film, 14e: Insulating film, 15: Substrate, 16: Substrate

[0025] 21: Stepped structural section; 22: Contact plug;

[0026] 23: Wiring layer; 24: Through-hole plug;

[0027] 31: Transistor, 32: Gate electrode, 33: Contact plug

[0028] 34: Routing layer, 35: Routing layer, 36: Routing layer

[0029] 37: Through-hole plug; 37a: Barrier metal layer; 37b: Plug material layer;

[0030] 38: Metal gasket; 38a: Barrier metal layer; 38b: Gasket material layer.

[0031] 41: Metal gasket; 41a: Barrier metal layer; 41b: Gasket material layer;

[0032] 42: Through-hole plug; 42a: Barrier metal layer; 42b: Plug material layer;

[0033] 43: Routing layer, 44: Routing layer

[0034] 45: Through-hole plug; 46: Metal gasket; 47: Passivation film.

[0035] 51: Insulating layer; 52: Barrier insulating film; 53: Charge storage layer; 54: Tunnel insulating film.

[0036] 55: Channel semiconductor layer, 56: Core insulating film, 61: Metal layer Detailed Implementation

[0037] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 20 In this text, identical components are marked with the same symbol, and repeated descriptions are omitted.

[0038] (First Embodiment)

[0039] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device is a three-dimensional memory formed by bonding array chip 1 and circuit chip 2.

[0040] The array chip 1 includes a memory cell array 11 containing multiple memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 under the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film, or a laminated film containing a silicon oxide film and other insulating films. The interlayer insulating film 13 is an example of a second insulating film.

[0041] Circuit chip 2 is disposed below array chip 1. The symbol S indicates the bonding surface between array chip 1 and circuit chip 2. Circuit chip 2 includes an interlayer insulating film 14 and a substrate 15 beneath the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film, or a laminate containing a silicon oxide film and other insulating films. The interlayer insulating film 14 is an example of a first insulating film. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate.

[0042] Figure 1 The X and Y directions are parallel to and perpendicular to the surface of the substrate 15, and the Z direction is perpendicular to the surface of the substrate 15. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not be aligned with the direction of gravity.

[0043] The array chip 1 has multiple word lines WL and source lines SL as multiple electrode layers within the memory cell array 11. Figure 1 The stepped structure 21 of the memory cell array 11 is shown. Each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22. Each columnar portion CL passing through multiple word lines WL is electrically connected to the bit line BL via a through-hole plug 24, and is also electrically connected to the source line SL. The source line SL comprises a first layer SL1 as a semiconductor layer and a second layer SL2 as a metal layer.

[0044] The circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 disposed on a substrate 15 through a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 15. In addition, the circuit chip 2 includes a plurality of contact plugs 33 disposed on the gate electrode 32, the source diffusion layer or the drain diffusion layer of these transistors 31, a wiring layer 34 disposed on these contact plugs 33 and including a plurality of wirings, and a wiring layer 35 disposed on the wiring layer 34 and including a plurality of wirings.

[0045] The circuit chip 2 further includes a wiring layer 36 disposed on the wiring layer 35 and containing multiple wirings, multiple via plugs 37 disposed on the wiring layer 36, and multiple metal pads 38 disposed on these via plugs 37. The metal pads 38 are, for example, metal layers containing a Cu (copper) layer. The metal pads 38 are examples of first pads, and the via plugs 37 are examples of first plugs. The circuit chip 2 functions as a control circuit (logic circuit) that controls the operation of the array chip 1. This control circuit is composed of transistors 31, etc., and is electrically connected to the metal pads 38.

[0046] The array chip 1 includes a plurality of metal pads 41 disposed on metal pads 38 and a plurality of through-hole plugs 42 disposed on the metal pads 41. Additionally, the array chip 1 includes a wiring layer 43 disposed on these through-hole plugs 42 and containing a plurality of wirings, and a wiring layer 44 disposed on the wiring layer 43 and containing a plurality of wirings. The metal pads 41 are, for example, metal layers containing Cu layers. The metal pads 41 are examples of second pads, and the through-hole plugs 42 are examples of second plugs. The bit lines BL are included in the wiring layer 44. The control circuit described above is electrically connected to the memory cell array 11 via the metal pads 41, 38, etc., and controls the operation of the memory cell array 11 via the metal pads 41, 38, etc.

[0047] The array chip 1 further includes a plurality of through-hole plugs 45 disposed on the wiring layer 44, metal pads 46 disposed on these through-hole plugs 45 or on the insulating film 12, and a passivation film 47 disposed on the metal pads 46 or on the insulating film 12. The metal pads 46 are, for example, metal layers containing a Cu layer, serving as... Figure 1 The external connection pads (solder pads) of the semiconductor device function as passivation films. The passivation film 47 is an insulating film such as a silicon oxide film, and has an opening P that exposes the upper surface of the metal pad 46. The metal pad 46 can be connected to a mounting substrate or other devices through the opening P via bonding wires, solder balls, metal bumps, etc.

[0048] Figure 2 This is a cross-sectional view showing the structure of the columnar portion CL in the first embodiment.

[0049] like Figure 2 As shown, the memory cell array 11 has alternating layers of interlayer insulating film 13 ( Figure 1 The device contains multiple word lines WL and multiple insulating layers 51. The word lines WL are, for example, a W (tungsten) layer. The insulating layers 51 are, for example, a silicon oxide film.

[0050] The columnar portion CL sequentially comprises a barrier insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53, for example, is a silicon nitride film, formed on the side of the word line WL and the insulating layer 51 via the barrier insulating film 52. The charge storage layer 53 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55, for example, is a polysilicon layer, formed on the side of the charge storage layer 53 via the tunnel insulating film 54. The barrier insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, silicon oxide films or metal insulating films.

[0051] Figure 3 and Figure 4 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0052] Figure 3 The diagram shows an array chip W1 containing multiple array chips 1 and a circuit chip W2 containing multiple circuit chips 2. The array chip W1 is also referred to as a "memory chip", and the circuit chip W2 is also referred to as a "CMOS chip".

[0053] It is worth noting that, Figure 3 The orientation of the array chip W1 and Figure 1 The array chip 1 is oriented in the opposite direction. In this embodiment, the semiconductor device is manufactured by bonding the array chip W1 to the circuit chip W2. Figure 3 This shows the array chip W1 before its orientation was reversed for bonding. Figure 1The image shows the array chip 1 after its orientation was reversed and it was bonded and cut for bonding.

[0054] exist Figure 3 In the diagram, symbol S1 represents the upper surface of array chip W1, and symbol S2 represents the upper surface of circuit chip W2. It is important to note that array chip W1 includes a substrate 16 disposed under the insulating film 12. The substrate 16 is, for example, a semiconductor substrate such as a silicon substrate.

[0055] In this embodiment, firstly, as Figure 3 As shown, a memory cell array 11, an insulating film 12, an interlayer insulating film 13, a stepped structure portion 21, and a metal pad 41 are formed on the substrate 16 of the array chip W1, and an interlayer insulating film 14, a transistor 31, and a metal pad 38 are formed on the substrate 15 of the circuit chip W2. For example, a through-hole plug 45, a wiring layer 44, a wiring layer 43, a through-hole plug 42, and a metal pad 41 are sequentially formed on the substrate 16. Similarly, a contact plug 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, a through-hole plug 37, and a metal pad 38 are sequentially formed on the substrate 15. Next, as... Figure 4 As shown, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 14. Next, the array wafer W1 and the circuit wafer W2 are annealed at 400°C. This bonds the metal pad 41 and the metal pad 38.

[0056] Next, substrate 15 is thinned using CMP (Chemical Mechanical Polishing), and substrate 16 is removed using CMP. Then, the array wafer W1 and circuit wafer W2 are diced into multiple chips. This process manufactures... Figure 1 Semiconductor devices. Figure 1 The diagram shows a circuit chip 2 comprising a metal pad 38 and an interlayer insulating film 14, and an array chip 1 comprising a metal pad 41 and an interlayer insulating film 13 respectively disposed on the metal pad 38 and the interlayer insulating film 14. It should be noted that the metal pad 46 and the passivation film 47 are formed on the insulating film 12, for example, after the thin film formation of the substrate 15 and the removal of the substrate 16.

[0057] It should be noted that in this embodiment, the array chip W1 is bonded to the circuit chip W2, but alternatively, the array chips W1 can be bonded to each other. (See reference...) Figures 1-4 The content and references mentioned above Figures 5 to 20 The content described below can also be applied to the bonding of array chips W1 to each other.

[0058] in addition, Figure 1The boundary surfaces of interlayer insulating film 13 and interlayer insulating film 14, and the boundary surfaces of metal pad 41 and metal pad 38 are shown, but these boundary surfaces generally become invisible after the annealing process described above. However, the location of these boundary surfaces can be estimated by detecting, for example, the tilt of the side surface of metal pad 41 and the side surface of metal pad 38, or the positional offset of the side surface of metal pad 41 and the side surface of metal pad 38.

[0059] Furthermore, the semiconductor device of this embodiment can be cut into multiple chips. Figure 1 The state becomes the object of the transaction, or it can be the state before it is cut into multiple chips. Figure 4 The state becomes the object of the transaction. Figure 1 A semiconductor device that indicates the state of a chip. Figure 4 A semiconductor device indicating the state of a wafer. In this embodiment, a wafer-shaped semiconductor device ( Figure 4 Manufacturing multiple chip-shaped semiconductor devices Figure 1 ).

[0060] Figure 5 This is a cross-sectional view showing the structure of the semiconductor device of the comparative example of the first embodiment. Figure 6 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 5 The semiconductor device shown is Figure 6 The difference in the semiconductor device shown is, for example, the presence or absence of metal layer 61. Metal layer 61 is an example of Part 1.

[0061] The following is for reference Figure 6 The structure of the semiconductor device in this embodiment will be described, and then refer to... Figure 5 and Figure 6 The semiconductor device of this embodiment is compared with the semiconductor device of the comparative example.

[0062] In this embodiment ( Figure 6 In this embodiment, the interlayer insulating film 14 includes insulating films 14e, 14d, 14c, 14b, and 14a sequentially disposed under the bonding surface S, and the interlayer insulating film 13 includes insulating films 13e, 13d, 13c, 13b, and 13a sequentially disposed on the bonding surface S. Furthermore, the metal pad 38 includes a barrier metal layer 38a and a padding material layer 38b sequentially disposed within the interlayer insulating film 14, and the metal pad 41 includes a barrier metal layer 41a and a padding material layer 41b sequentially disposed within the interlayer insulating film 13. The semiconductor device of this embodiment further includes the aforementioned metal layer 61.

[0063] Insulating films 14a, 14c, 14e, 13a, 13c, and 13e are, for example, SiO2 films (silicon oxide films). Insulating films 14b and 13b are, for example, SiN films (silicon nitride films). In this embodiment, insulating films 14b and 13b are used as etching stop layers, for example, when forming holes for embedding metal pads 38 and 41 within interlayer insulating films 14 and 13 by etching. Insulating films 14d and 13d are, for example, SiCN films (silicon carbon nitride films). In this embodiment, insulating films 14d and 13d are formed, for example, to prevent Cu atoms in metal pads 38 and 41 from diffusing into interlayer insulating films 14 and 13. Insulating films 14d and 13d are examples of the third and fourth films, respectively. Furthermore, insulating films 14e and 13e are examples of the first and second films, respectively.

[0064] In this embodiment, insulating films 14e and 13e are natural oxide films formed by the natural oxidation of insulating films 14d and 13d, respectively, before the array wafer W1 and the circuit wafer W2 are bonded. Therefore, in this embodiment, the lower surface of insulating film 14e is in contact with the upper surface of insulating film 14d, and the upper surface of insulating film 13e is in contact with the lower surface of insulating film 13e. Furthermore, in this embodiment, the upper surface of insulating film 14e is in contact with the lower surface of insulating film 13e. It should be noted that insulating films 14e and 13e can be formed by reasons other than natural oxidation, for example, by CMP or plasma treatment of the surfaces of interlayer insulating films 14 and 13.

[0065] A barrier metal layer 38a is formed on the side and lower surface (bottom surface) of the interlayer insulating film 14, and is in contact with the side and lower surface of the interlayer insulating film 14. A padding material layer 38b is formed on the side and lower surface of the interlayer insulating film 14 through the barrier metal layer 38a. Similarly, a barrier metal layer 41a is formed on the side and upper surface (bottom surface) of the interlayer insulating film 13, and is in contact with the side and upper surface of the interlayer insulating film 13. A padding material layer 41b is formed on the side and upper surface of the interlayer insulating film 13 through the barrier metal layer 41a. Barrier metal layers 38a and 41a are examples of the first and third layers, respectively. Padding material layers 38b and 41b are examples of the second and fourth layers, respectively.

[0066] The barrier metal layers 38a and 41a are, for example, metal layers containing Ti (titanium), Al (aluminum), or Mn (manganese), and here are Ti layers. In this embodiment, the barrier metal layers 38a and 41a are formed, for example, to prevent Cu atoms within the metal pads 38 and 41 from diffusing into the interlayer insulating films 14 and 13. The barrier metal layers 38a and 41a can also be metal compound layers containing metallic and non-metallic elements, such as metal oxide films or metal nitride films. Alternatively, the barrier metal layers 38a and 41a can also be alloy layers containing two or more metallic elements. The padding material layers 38b and 41b are, for example, metal layers containing Cu, and here are Cu layers. The padding material layers 38b and 41b can also be metal layers other than Cu layers.

[0067] In this embodiment, the metal pads 38 and 41 have the same planar shape. These planar shapes are, here, squares or rectangles having two sides extending in the X direction and two sides extending in the Y direction. Therefore, the widths of the metal pad 41 in the X direction and the Y direction in this embodiment become the same as the widths of the metal pad 38 in the X direction and the Y direction, respectively.

[0068] Therefore, if the metal pad 41 is positioned directly above the metal pad 38, the lower surface of the metal pad 41 will only be in contact with the upper surface of the metal pad 38, and will not be in contact with the upper surfaces of layers other than the metal pad 38. Similarly, the lower surface of the metal pad 38 will only be in contact with the lower surface of the metal pad 41, and will not be in contact with the lower surfaces of layers other than the metal pad 41.

[0069] However, in this embodiment, the metal pad 41 is not positioned directly above the metal pad 38. Therefore, the lower surface of the metal pad 41 in this embodiment is not only in contact with the upper surface of the metal pad 38, but is also disposed on the upper surface of the interlayer insulating film 14. Similarly, the upper surface of the metal pad 38 in this embodiment is not only in contact with the lower surface of the metal pad 38, but is also disposed below the lower surface of the interlayer insulating film 13. Furthermore, in this embodiment, the metal layer 61 is formed between the upper surface of the metal pad 38 and the lower surface of the interlayer insulating film 13, and between the lower surface of the metal pad 41 and the upper surface of the interlayer insulating film 14.

[0070] Metal layer 61 may contain, for example, the same metal element contained in barrier metal layers 38a and 41a. This metal element may be, for example, Ti, Al, or Mn. Metal layer 61 may further contain oxygen. In this embodiment, barrier metal layers 38a and 41a are Ti layers, and metal layer 61 is TiO. x (Titanium oxide) layer.

[0071] In this embodiment, the metal layer 61 is formed by blocking the diffusion of Ti atoms from the metal layers 38a and 41a to the interface between the padding layer 38b and the insulating film 13e, and the interface between the padding layer 41b and the insulating film 14e, and is self-integratedly formed at these interface locations. The metal layer 61 in this embodiment is a TiO₂ layer containing Ti atoms from the blocking metal layers 38a and 41a and O atoms from the insulating films 14e and 13e. x Therefore, in this embodiment, the lower surface of the metal layer 61 is in contact with the upper surface of the insulating film 14e and the upper surface of the padding material layer 38b, and the upper surface of the metal layer 61 is in contact with the lower surface of the insulating film 13e and the lower surface of the padding material layer 41b.

[0072] It should be noted that metal layer 61 may also contain the same metal element as that contained in either barrier metal layer 38a or barrier metal layer 41a. For example, if only barrier metal layer 38a contains Ti atoms and metal layer 61 is formed by Ti atoms diffusing from barrier metal layer 38a, then barrier metal layer 38a and metal layer 61 contain Ti, while barrier metal layer 41a does not contain Ti.

[0073] Alternatively, the metal layer 61 of this embodiment may be formed between the metal pad 38 and the interlayer insulating film 13, or between the metal pad 41 and the interlayer insulating film 14, with a thickness that cannot be described as a layer. Further details of the process for forming the metal layer 61 of this embodiment will be described below.

[0074] Next, refer to Figure 5 and Figure 6 The semiconductor device of this embodiment is compared with the semiconductor device of the comparative example.

[0075] In the comparative example ( Figure 5 In the comparative example, the blocking metal layers 38a and 41a are not Ti layers but Ta (tantalum) layers. Ta atoms are less prone to diffusion than Ti atoms. Therefore, in the comparative example, no metal layer 61 is formed between the metal pad 38 and the interlayer insulating film 13, and between the metal pad 41 and the interlayer insulating film 14.

[0076] Furthermore, in the comparative example, insulating films 14e and 13e (SiO2 films) are formed between insulating films 14d and 13d (SiCN films) in the same manner as in this embodiment. Compared to the SiCN film, the SiO2 film has a weaker effect in preventing the diffusion of Cu atoms. Therefore, in the comparative example, Cu atoms within the metal pads 38 and 41 diffuse into the interlayer insulating films 14 and 13 via the insulating films 14e and 13e. The diffusion of Cu atoms may occur, for example, during the annealing process in the manufacture of a semiconductor device. Cu atoms diffused into the interlayer insulating films 14 and 13 may become a cause of leakage current between the metal pads 38, between the metal pads 41, and between the metal pads 38 and 41.

[0077] If the metal pads 38 and 41 have the same planar shape, and the metal pad 41 is positioned directly above the metal pad 38, then the diffusion of Cu atoms into the interlayer insulating films 14 and 13 is essentially not a problem. This is because the lower surface of the metal pad 41 becomes only in contact with the upper surface of the metal pad 38, and the upper surface of the metal pad 38 also becomes only in contact with the lower surface of the metal pad 41.

[0078] However, during the bonding of the array chip W1 and the circuit chip W2, misalignment sometimes occurs between the metal pads 38 and 41. In this case, the metal pad 41 is not positioned directly above the metal pad 38, and the lower surface of the metal pad 41 becomes contact with the upper surface of the interlayer insulating film 14, while the upper surface of the metal pad 38 becomes contact with the lower surface of the interlayer insulating film 13.

[0079] Even in this case, as long as the upper surface of the interlayer insulating film 14 is formed by insulating film 14d (SiCN film) and the lower surface of the interlayer insulating film 13 is formed by insulating film 13d (SiCN film), the diffusion of Cu atoms into the interlayer insulating films 14 and 13 can be suppressed. This is because the SiCN film has a strong effect in preventing the diffusion of Cu atoms. However, if the interlayer insulating films 14 and 13 contain insulating films 14e and 13e (SiO2 film) through natural oxidation or the like, Cu atoms in the metal pads 38 and 41 diffuse into the interlayer insulating films 14 and 13 through insulating films 14e and 13e.

[0080] On the other hand, in this embodiment ( Figure 6In this embodiment, metal layers 38a and 41a are blocked from becoming Ti layers. Ti atoms diffuse more easily than Ta atoms. Therefore, in this embodiment, a metal layer 61 is formed between the metal pad 38 and the interlayer insulating film 13, and between the metal pad 41 and the interlayer insulating film 14. Thus, according to this embodiment, even if the metal pad 41 is not positioned directly above the metal pad 38, and the interlayer insulating films 14 and 13 contain insulating films 14e and 13e (SiO2 films) through natural oxidation or the like, the diffusion of Cu atoms from the metal pads 38 and 41 to the interlayer insulating films 14 and 13 can be suppressed by the metal layer 61. It should be noted that the diffusion of Ti atoms that bring about the metal layer 61 occurs, for example, during the annealing process when manufacturing a semiconductor device.

[0081] For Ti layers used as barrier metal layers 38a and 41a, TiO is present. x The layer (metal layer 61) offers advantages such as high barrier properties and low cost in forming the Ti layer. It should be noted that this barrier effect is achieved using an Al layer to form AlO. x In the case of layers, Mn layers are used to form MnO. x It can also be obtained in the case of layers.

[0082] It should be noted that the structure in which there is no metal pad 41 directly above the metal pad 38 in this embodiment can be generated by the misalignment of the metal pad 38 and the metal pad 41, or it can be intentionally generated during the manufacturing of the semiconductor device.

[0083] Figures 7-11 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment. Figures 7-11 The method shown is equivalent to Figure 3 and Figure 4 Specific examples of the methods shown.

[0084] First, the array chip W1 and the circuit chip W2 are processed into Figure 7 The structure shown. Specifically, on substrate 16 (refer to...) Figure 3 An insulating film 13a is formed above the substrate 15 (see reference 13a). A through-hole plug 42 is formed within the insulating film 13a. Insulating films 13b, 13c, and 13d are sequentially formed on the insulating film 13a and the through-hole plug 42. A barrier metal layer 41a and a pad material layer 41b are sequentially formed within the insulating films 13b, 13c, and 13d. Similarly, an insulating film 13a is formed on the substrate 15 (see reference 13a). Figure 3An insulating film 14a is formed above the insulating film 14a, and a through-hole plug 37 is formed within the insulating film 14a. Insulating films 14b, 14c, and 14d are formed sequentially on the insulating film 14a and the through-hole plug 37. A barrier metal layer 38a and a padding material layer 38b are formed sequentially within the insulating films 14b, 14c, and 14d. As a result, metal pads 41 and 38 are formed within the interlayer insulating films 13 and 14, respectively.

[0085] Next, insulating films 13e and 14e are formed on the surfaces of insulating films 13d and 14d respectively by oxidation. Figure 8 Insulating films 13e and 14e are formed, for example, through natural oxidation.

[0086] Next, with the metal pad 41 disposed on the metal pad 38 and the interlayer insulating film 13 disposed on the interlayer insulating film 14, the array chip W1 and the circuit chip W2 are bonded together by mechanical pressure. Figure 9 Thus, interlayer insulating film 13 and interlayer insulating film 14 are bonded together. Figure 9 In the process, the alignment of metal pad 38 and metal pad 41 is incorrect, and a part of the upper surface of metal pad 38 is in contact with a part of the lower surface of metal pad 41.

[0087] Next, the array chip W1 and the circuit chip W2 are annealed. Figure 10 Thus, metal gasket 41 and metal gasket 38 are joined together. Figure 10 The grain boundaries α between grains within the padding layers 38b and 41b are further shown, along with the Ti atom groups β diffused along the grain boundaries α or the bonding surface S. In this embodiment, through... Figure 10 In the annealing process shown, Ti atoms diffuse from the barrier metal layers 38a and 41a.

[0088] As a result, Ti atoms in the metal layers 38a and 41a are prevented from diffusing into the interface between the padding layer 38b and the insulating film 13e, and the interface between the padding layer 41b and the insulating film 14e, where the metal layer 61 is self-integrated at these interface locations. Figure 11 Specifically, Ti atoms diffuse from the barrier metal layers 38a and 41a to these interfaces react with O atoms in the insulating films 14e and 13e to form TiO. x The layer is a metal layer 61. Therefore, according to this embodiment, the diffusion of Cu atoms from the metal pads 38 and 41 to the interlayer insulating films 14 and 13 can be suppressed by the metal layer 61.

[0089] By operating in this way, it was manufactured Figure 6The semiconductor device is then manufactured. Substrate 15 is then thinned using CMP, and substrate 16 is removed using CMP. The array wafer W1 and circuit wafer W2 are then diced into multiple chips. This process is repeated to manufacture the semiconductor device. Figure 1 Semiconductor devices.

[0090] As described above, the semiconductor device of this embodiment has a metal layer 61 containing the same metal element as that contained in the blocking metal layers 38a and 41a between the upper surface of the metal pad 38 and the lower surface of the interlayer insulating film 13, and between the lower surface of the metal pad 41 and the upper surface of the interlayer insulating film 14. Therefore, according to this embodiment, it becomes possible to form suitable metal pads 38 and 41 that can suppress the diffusion of metal atoms (e.g., Cu atoms) from the pad material layers 38b and 41b to the insulating films 14e and 13e.

[0091] (Second Implementation)

[0092] Figure 12 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0093] In this embodiment, the interlayer insulating films 13 and 14 do not have insulating films 13d and 14d (SiCN films), and consequently, they also do not have insulating films 13e and 14e (SiO2 films). In this embodiment, the insulating film 13c (SiO2 film) in the interlayer insulating film 13 and the insulating film 14c (SiO2 film) in the interlayer insulating film 14 are in contact with each other at the bonding surface S.

[0094] The semiconductor device of this embodiment also includes a metal layer 61. The metal layer 61 of this embodiment is formed by reacting Ti atoms that block the diffusion of metal layers 38a and 41a with O atoms in insulating films 14c and 13c.

[0095] According to this embodiment, the process of forming insulating films 13d and 14d can be omitted. Furthermore, according to this embodiment, since insulating films 13d and 14d are not present near the surfaces of the interlayer insulating films 13 and 14, the surfaces of the interlayer insulating films 13 and 14 can be easily planarized by CMP. On the other hand, according to the first embodiment, not only can the diffusion of Cu atoms be suppressed by the metal layer 61, but the diffusion of Cu atoms can also be suppressed by the insulating films 13d and 14d.

[0096] Figures 13-16 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment. Figures 13-16 The method shown is equivalent to Figure 3 and Figure 4 Specific examples of the methods shown.

[0097] First, the array chip W1 and the circuit chip W2 are processed into Figure 13 The structure shown. Specifically, on substrate 16 (refer to...) Figure 3 An insulating film 13a is formed above the substrate 15, and a through-hole plug 42 is formed within the insulating film 13a. Insulating films 13b and 13c are sequentially formed on the insulating film 13a and the through-hole plug 42. A barrier metal layer 41a and a padding material layer 41b are sequentially formed within the insulating films 13b and 13c. Similarly, on the substrate 15 (refer to...) Figure 3 An insulating film 14a is formed above the insulating film 14a, and a through-hole plug 37 is formed within the insulating film 14a. Insulating films 14b and 14c are formed sequentially on the insulating film 14a and the through-hole plug 37. A barrier metal layer 38a and a padding material layer 38b are formed sequentially within the insulating films 14b and 14c. As a result, metal pads 41 and 38 are formed within the interlayer insulating films 13 and 14, respectively.

[0098] Next, with the metal pad 41 disposed on the metal pad 38 and the interlayer insulating film 13 disposed on the interlayer insulating film 14, the array chip W1 and the circuit chip W2 are bonded together by mechanical pressure. Figure 14 Thus, interlayer insulating film 13 and interlayer insulating film 14 are bonded together. Figure 14 In the process, the alignment of metal pad 38 and metal pad 41 is incorrect, and a part of the upper surface of metal pad 38 is in contact with a part of the lower surface of metal pad 41.

[0099] Next, the array chip W1 and the circuit chip W2 are annealed. Figure 15 Thus, metal gasket 41 and metal gasket 38 are joined together. Figure 15 Further shown are the grain boundaries α between grains within the padding layers 38b and 41b, and the Ti atom groups β diffused along the grain boundaries α or the bonding surface S. In this embodiment, by... Figure 15 In the annealing process shown, Ti atoms diffuse from the barrier metal layers 38a and 41a.

[0100] As a result, Ti atoms in the metal layers 38a and 41a are prevented from diffusing to the interface between the padding layer 38b and the insulating film 13c, and the interface between the padding layer 41b and the insulating film 14c, where the metal layer 61 is self-integratedly formed. Figure 16 Specifically, Ti atoms diffuse from the barrier metal layers 38a and 41a to these interfaces react with O atoms in the insulating films 14c and 13c to form TiO. x The layer is a metal layer 61. Therefore, according to this embodiment, the diffusion of Cu atoms from the metal pads 38 and 41 to the interlayer insulating films 14 and 13 can be suppressed by the metal layer 61.

[0101] By operating in this way, it was manufactured Figure 12 The semiconductor device is then manufactured. Substrate 15 is then thinned using CMP, and substrate 16 is removed using CMP. The array wafer W1 and circuit wafer W2 are then diced into multiple chips. This process is repeated to manufacture the semiconductor device. Figure 1 Semiconductor devices.

[0102] As described above, the semiconductor device of this embodiment has a metal layer 61 containing the same metal element as that contained in the blocking metal layers 38a and 41a between the upper surface of the metal pad 38 and the lower surface of the interlayer insulating film 13, and between the lower surface of the metal pad 41 and the upper surface of the interlayer insulating film 14. Therefore, according to this embodiment, it becomes possible to form suitable metal pads 38 and 41 that can suppress the diffusion of metal atoms (e.g., Cu atoms) from the pad material layers 38b and 41b to the insulating films 14c and 13c.

[0103] (Third implementation)

[0104] Figure 17 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

[0105] In this embodiment, the interlayer insulating film 13 does not have an insulating film 13d (SiCN film), and consequently, it also does not have an insulating film 13e (SiO2 film). On the other hand, the interlayer insulating film 14 in this embodiment has an insulating film 14d (SiCN film), and consequently, it also has an insulating film 14e (SiO2 film). In this embodiment, the insulating film 13c (SiO2 film) in the interlayer insulating film 13 and the insulating film 14e (SiO2 film) in the interlayer insulating film 14 are in contact with each other at the bonding surface S.

[0106] The semiconductor device of this embodiment also includes a metal layer 61. The metal layer 61 of this embodiment is formed by reacting Ti atoms that block the diffusion of metal layers 38a and 41a with O atoms in insulating films 14e and 13c.

[0107] According to this embodiment, the interlayer insulating film 14 enjoys the same advantages as in the first embodiment, and the interlayer insulating film 13 enjoys the same advantages as in the second embodiment. The semiconductor device of this embodiment can be applied, for example, to an array wafer W1. Figures 13-16 The method shown is applied to circuit chip W2. Figures 7-11 The method shown is used to manufacture it.

[0108] It should be noted that in the semiconductor device of this embodiment, the interlayer insulating film 13 may also have insulating films 13d and 13e, and the interlayer insulating film 14 may not have insulating films 14d and 14e.

[0109] (Fourth implementation)

[0110] Figure 18 This is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment.

[0111] In the first to third embodiments, the metal pad 38 and the through-hole plug 37 are single-damascene wiring; in contrast, in this embodiment, the metal pad 38 and the through-hole plug 37 are double-damascene wiring. Therefore, the barrier metal layer 37a and the plug material layer 37b in the through-hole plug 37 of this embodiment are the same as the barrier metal layer 38a and the pad material layer 38b in the metal pad 38, respectively, and the plug material layer 37b in the through-hole plug 37 is in contact with the pad material layer 38b in the metal pad 38. In other words, the barrier metal layers 38a and 37a are not provided at the boundary between the pad material layer 38b and the plug material layer 37b. The barrier metal layers 38a and 37a are examples of the first layer, and the pad material layer 38b and the plug material layer 37b are examples of the second layer.

[0112] Similarly, the metal gasket 41 and through-hole plug 42 in the first to third embodiments are single-damascene wiring, while in contrast, the metal gasket 41 and through-hole plug 42 in this embodiment are double-damascene wiring. Therefore, the barrier metal layer 42a and plug material layer 42b in the through-hole plug 42 of this embodiment are the same as the barrier metal layer 41a and gasket material layer 41b in the metal gasket 41, respectively, and the plug material layer 42b in the through-hole plug 42 is in contact with the gasket material layer 41b in the metal gasket 41. In other words, the barrier metal layers 41a and 42a are not provided at the boundary between the gasket material layer 41b and the plug material layer 42b. The barrier metal layers 41a and 42a are examples of the third layer, and the gasket material layer 41b and plug material layer 42b are examples of the fourth layer.

[0113] According to this embodiment, the metal pad 38 and the through-hole plug 37 can be formed with fewer processes, and the metal pad 41 and the through-hole plug 42 can be formed with fewer processes. The semiconductor device of this embodiment, for example, can be applied... Figures 7-11 The method shown is in Figure 7 The process uses double inlay instead of single inlay to manufacture the product.

[0114] (Fifth implementation)

[0115] Figure 19 This is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment.

[0116] In this embodiment, the metal pads 38 and 41 have different planar shapes. Both metal pads 38 and 41 are square or rectangular, but the width of metal pad 41 in the X direction differs from that of metal pad 38, and the width of metal pad 41 in the Y direction differs from that of metal pad 38. For example, the width of metal pad 41 in the X direction is shorter than that of metal pad 38, and the width of metal pad 41 in the Y direction is shorter than that of metal pad 38. The entire lower surface of metal pad 41 is in contact with a portion of the upper surface of metal pad 38.

[0117] The semiconductor device of this embodiment also includes a metal layer 61. The metal layer 61 of this embodiment is formed mainly by the reaction of Ti atoms that block the diffusion of metal layers 38a and 41a with O atoms in the insulating film 13e.

[0118] In the first to fourth embodiments, if an error occurs in the alignment of the metal pads 38 and 41, the contact area between the metal pads 38 and 41 changes, and the contact resistance between the metal pads 38 and 41 changes. On the other hand, in this embodiment, even if a small error occurs in the alignment of the metal pads 38 and 41, the contact area between the metal pads 38 and 41 does not change, and the contact resistance between the metal pads 38 and 41 does not change. Therefore, according to this embodiment, problems arising from errors in the alignment of the metal pads 38 and 41 can be suppressed.

[0119] In this embodiment, because the metal pads 38 and 41 have different planar shapes, even without alignment errors, the upper surface of the metal pad 38 may lie below the lower surface of the interlayer insulating film 13, or the lower surface of the metal pad 41 may lie above the upper surface of the interlayer insulating film 14. In this embodiment, a metal layer 61 can be formed in such portions. Therefore, according to this embodiment, the advantages of the metal pads 38 and 41 having different planar shapes can be enjoyed, and the disadvantages of the metal pads 38 and 41 having different planar shapes can be suppressed.

[0120] The semiconductor device of this embodiment can, for example, be applied... Figures 7-11 The method shown is in Figure 7 In the manufacturing process, the planar shape of the metal pad 38 is made different from that of the metal pad 41. It should be noted that in this embodiment, a single inlay can also be used instead of a double inlay method.

[0121] (Sixth implementation)

[0122] Figure 20 This is a cross-sectional view showing the structure of the semiconductor device according to the sixth embodiment.

[0123] The semiconductor device in this embodiment not only has metal pads 38 and 41 connected to each other (see reference) Figure 1 (etc.), and possesses such as Figure 20 The metal pads 38 and 41 shown are not in contact with each other. Such metal pads 38 and 41 are formed, for example, as dummy pads that are not used to electrically connect the array wafer W1 and the circuit wafer W2. Dummy pads are formed, for example, to adjust the density of the metal pads 38 and 41 in the bonding surface S.

[0124] The semiconductor device of this embodiment also includes a metal layer 61. In this embodiment, the metal layer 61 on the metal pad 38 is formed primarily by the reaction of Ti atoms, which block diffusion from the metal layer 38a, with O atoms within the insulating film 13e. On the other hand, in this embodiment, the metal layer 61 under the metal pad 41 is formed primarily by the reaction of Ti atoms, which block diffusion from the metal layer 41a, with O atoms within the insulating film 14e.

[0125] The semiconductor device of this embodiment can, for example, be applied... Figures 7-11 The method shown is in Figure 9 In the process according to Figure 20 The array chip W1 and the circuit chip W2 are manufactured by bonding them together in a manner in which the metal pads 38 and 41 are not in contact.

[0126] Several embodiments have been described above, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. The novel apparatus and method described in this specification can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the apparatus and method described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass the scope of the invention, the manner and variations contained in its spirit.

Claims

1. A semiconductor memory device comprising: First insulating film; The first liner is a first liner disposed within the first insulating film, comprising a first layer disposed on and in contact with the side and lower surfaces of the first insulating film, and a second layer disposed on and between the first layer and the side and lower surfaces of the first insulating film and being a Cu (copper) layer. A second insulating film is disposed on the first insulating film; The second liner is a second liner disposed within the second insulating film on the first liner, comprising a third layer disposed on and in contact with the side and upper surfaces of the second insulating film, and a fourth layer being a Cu layer disposed on and between the third layer and the side and upper surfaces of the second insulating film. The first part is disposed between the upper surface of the first pad and the lower surface of the second insulating film, or between the lower surface of the second pad and the upper surface of the first insulating film, and contains the same metal element as the metal element contained in the first layer or the third layer; The memory cell array is a memory cell array disposed within the second insulating film, comprising multiple word lines, columnar portions penetrating the multiple word lines, and source lines disposed above the multiple word lines and electrically connected to the columnar portions; Bit lines are disposed within the second insulating film below the memory cell array and electrically connected to the columnar portion; and A control circuit, disposed within the first insulating film and controlling the memory cell array via the first and second pads, is also included. The first gasket is disposed on the first plug comprising the first layer and the second layer, and the second layer within the first plug is in contact with the second layer within the first gasket, or The second gasket is disposed below the second plug, which includes the third and fourth layers, and the fourth layer within the second plug is in contact with the fourth layer within the second gasket. and The first insulating film includes an 11th film containing oxygen and in contact with the lower surface of the first portion, a 12th film containing nitrogen and in contact with the lower surface of the 11th film and the side surface of the first gasket, and a 13th film containing oxygen and in contact with the lower surface of the 12th film and the side surface of the first plug, or The second insulating film includes a 14th film containing oxygen and in contact with the upper surface of the first portion, a 15th film containing nitrogen and in contact with the upper surface of the 14th film and the side surface of the second gasket, and a 16th film containing oxygen and in contact with the upper surface of the 12th film and the side surface of the second plug.

2. The semiconductor memory device according to claim 1, wherein, The first part contains the metal element and oxygen.

3. The semiconductor memory device according to claim 1, wherein, The metallic element includes titanium, aluminum, or manganese.

4. The semiconductor memory device according to claim 1, wherein, The first layer or the third layer is a monomeric metal layer containing the metal element, or a metal compound layer containing the metal element and non-metal elements.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein, The first insulating film includes a fifth film containing oxygen and in contact with the side of the first pad, a sixth film containing nitrogen and in contact with the side of the first pad, and a seventh film containing both carbon and nitrogen and in contact with the side of the first pad, or The second insulating film includes an eighth film containing oxygen and in contact with the side of the second pad, a ninth film containing nitrogen and in contact with the side of the second pad, and a tenth film containing carbon and nitrogen and in contact with the side of the second pad.

6. The semiconductor memory device according to claim 1, wherein, The first pad and the second pad have the same width.

7. The semiconductor memory device according to claim 1, wherein, The first pad and the second pad have different widths.

8. A semiconductor device comprising: First insulating film; The first liner is a first liner disposed within the first insulating film, comprising a first layer disposed on and in contact with the side and lower surfaces of the first insulating film, and a second layer disposed on and between the first layer and the side and lower surfaces of the first insulating film and being a Cu (copper) layer. A second insulating film is disposed on the first insulating film; The second liner, which is a second liner disposed within the second insulating film and on the first liner, comprises a third layer disposed on and in contact with the side and upper surfaces of the second insulating film, and a fourth layer, which is a Cu layer, disposed on the side and upper surfaces of the second insulating film through the third layer; and The first part, disposed between the upper surface of the first pad and the lower surface of the second insulating film, or between the lower surface of the second pad and the upper surface of the first insulating film, contains the same metallic element as that contained in the first layer or the third layer. The first insulating film comprises a first film containing oxygen and in contact with the lower surface of the first portion, and a third film containing carbon and nitrogen and in contact with the lower surface of the first film, wherein the first film is a natural oxide film of the third film, or The second insulating film comprises a second film containing oxygen and in contact with the upper surface of the first portion, and a fourth film containing carbon and nitrogen and in contact with the upper surface of the second film, wherein the second film is a natural oxide film of the fourth film.

9. A method for manufacturing a semiconductor device, comprising: A first pad is formed within a first insulating film. The first pad includes a first layer disposed on and in contact with the side and bottom surfaces of the first insulating film, and a second layer disposed on the side and bottom surfaces of the first insulating film through the first layer and being a Cu (copper) layer. A second liner is formed within the second insulating film. The second liner includes a third layer disposed on and in contact with the side and bottom surfaces of the second insulating film, and a fourth layer, which is a Cu layer, disposed on the side and bottom surfaces of the second insulating film through the third layer. The second insulating film is disposed on the first insulating film, and the second pad is disposed on the first pad; and A first portion is formed between the upper surface of the first pad and the lower surface of the second insulating film, or between the lower surface of the second pad and the upper surface of the first insulating film. The first portion contains the same metallic element as that contained in the first layer or the third layer. The first part is formed by the metal element diffused from the first layer or the third layer.

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