Semiconductor package including stacked semiconductor chips

Abstract

A semiconductor package includes a base layer, and a first chip stack and a second chip stack stacked in sequence over the base layer, each of the first chip stack and the second chip stack including first to fourth semiconductor chips, the first to fourth semiconductor chips being offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack, and first and second chip identification pads for identifying the first to fourth semiconductor chips in each of the first chip stack and the second chip stack.

Description

Technical Field

[0001] This patent document relates to semiconductor packages, and more specifically, to semiconductor packages comprising a plurality of semiconductor chips stacked in a vertical direction. Background Technology

[0002] Electronic products require massive amounts of data processing, and these products are becoming increasingly smaller. Therefore, the need to increase the integration of semiconductor devices used in such electronic products is growing.

[0003] However, due to limitations in semiconductor integration technology, it is difficult to meet the required functions with a single semiconductor chip. Therefore, semiconductor packages containing multiple semiconductor chips have been manufactured.

[0004] Multiple semiconductor chips can be stacked vertically and electrically connected to each other via interconnects such as wiring. Summary of the Invention

[0005] In one embodiment, a semiconductor package may include: a base layer; and a first chip stack and a second chip stack, which are sequentially stacked over the base layer. Each of the first chip stack and the second chip stack includes a first semiconductor chip to a fourth semiconductor chip. The first semiconductor chips to the fourth semiconductor chips are offset from each other to expose chip pads at a side edge of each of the first semiconductor chips to the fourth semiconductor chip. The chip pads include stack identification pads for identifying the first chip stack and the second chip stack, and first chip identification pads and second chip identification pads for identifying the first semiconductor chip to the fourth semiconductor chip in each of the first chip stack and the second chip stack. Power is applied to the first chip stack. The chip stack includes stack identification pads for a first to a fourth semiconductor chip in one of the chip stacks and the second chip stack. In the first chip stack, power is applied to the first chip identification pad and the second chip identification pad of the first semiconductor chip, one of the first chip identification pad and the second chip identification pad of the second semiconductor chip, and the other of the first chip identification pad and the second chip identification pad of the third semiconductor chip. In the second chip stack, power is applied to the first chip identification pad and the second chip identification pad of the first semiconductor chip, one of the first chip identification pad and the second chip identification pad of the second semiconductor chip, and the other of the first chip identification pad and the second chip identification pad of the third semiconductor chip.

[0006] In another embodiment, a semiconductor package may include: a base layer; and a first chip stack and a second chip stack, which are sequentially stacked over the base layer. Each of the first chip stack and the second chip stack includes a first to an eighth semiconductor chip, the first to eighth semiconductor chips being offset from each other to expose chip pads at a side edge of each of the first to eighth semiconductor chips. The chip pads include stack identification pads for identifying the first chip stack and the second chip stack, and pads for identifying the first semiconductor chip in each of the first chip stack and the second chip stack. The first to third chip identification pads of the eighth semiconductor chip are connected to a first chip stack and a second chip stack, wherein power is applied to the stack identification pads of the first to eighth semiconductor chips. In the first chip stack, power is applied to the first to third chip identification pads of the first semiconductor chip, two chip identification pads selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one chip identification pad selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips. A second chip stack comprises chip identification pads, wherein the two selected chip identification pads of the second semiconductor chip, the two selected chip identification pads of the third semiconductor chip, and the two selected chip identification pads of the fourth semiconductor chip are different from each other, and the one selected chip identification pad of the fifth semiconductor chip, the one selected chip identification pad of the sixth semiconductor chip, and the one selected chip identification pad of the seventh semiconductor chip are different from each other. In the second chip stack, power is applied to each of the first to third chip identification pads of the first semiconductor chip and the second to fourth semiconductor chips from the first chip identification pad. The two chip identification pads selected from the first to the third chip identification pads, and the one chip identification pad selected from the first to the third chip identification pads for each of the fifth to the seventh semiconductor chips, wherein the two chip identification pads selected by the second semiconductor chip, the two chip identification pads selected by the third semiconductor chip, and the two chip identification pads selected by the fourth semiconductor chip are different from each other, and the one chip identification pad selected by the fifth semiconductor chip, the one chip identification pad selected by the sixth semiconductor chip, and the one chip identification pad selected by the seventh semiconductor chip are different from each other. Attached Figure Description

[0007] Figure 1A This is a cross-sectional view of a semiconductor package that illustrates a comparative example.

[0008] Figure 1B This is observed from above. Figure 1AA plan view of a portion of a semiconductor package.

[0009] Figure 1C It is an example of a logical value. Figure 1A and Figure 1B A diagram showing the electrical application status of the chip identification pads of multiple semiconductor chips included in a semiconductor package.

[0010] Figure 1D It is used to explain in Figure 1A and Figure 1B A diagram illustrating potential problems in semiconductor packages.

[0011] Figure 2A This is a cross-sectional view illustrating an embodiment of the semiconductor package of the present disclosure.

[0012] Figure 2B This is observed from above. Figure 2A A plan view of a portion of a semiconductor package.

[0013] Figure 2C It is an example of a logical value. Figure 2A and Figure 2B A diagram showing the electrical application status of the stack of multiple semiconductor chips included in a semiconductor package, identifying the pads and chip identification pads.

[0014] Figure 2D This is a diagram illustrating the power application state of the stack identification pads and chip identification pads of a plurality of semiconductor chips included in a semiconductor package according to another embodiment of the present disclosure, which are logic values.

[0015] Figure 3A This is a cross-sectional view illustrating another embodiment of the semiconductor package of this disclosure.

[0016] Figure 3B This is observed from above. Figure 3A A plan view of a portion of a semiconductor package.

[0017] Figure 3C It is an example of a logical value. Figure 3A and Figure 3B A diagram showing the electrical application status of the stack of multiple semiconductor chips included in a semiconductor package, identifying the pads and chip identification pads.

[0018] Figure 3D , Figure 3E and Figure 3F This is a diagram illustrating the power application state of the stack identification pads and chip identification pads of a plurality of semiconductor chips included in a semiconductor package according to another embodiment of the present disclosure, which are logic values.

[0019] Figure 4 A block diagram illustrating an electronic system employing a memory card including a semiconductor package, according to an embodiment, is shown.

[0020] Figure 5 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. Detailed Implementation

[0021] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0022] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated in order to clearly illustrate some features of the described embodiments. When a particular example of a multilayer structure with two or more layers is presented in the drawings or description, the relative positional relationship of such layers or the order in which these layers are arranged reflects the specific implementation of the described or illustrated example, and different relative positional relationships or orders in which the layers are arranged are also possible. In addition, the example of a described or illustrated multilayer structure may not reflect all the layers present in that particular multilayer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate. It will be understood that when a component, wiring, pad, or layer is referred to as being "on," "connected to," or "attached to" another component, wiring, pad, or layer, it can be directly on, directly "connected to," or directly "attached to" the other component, wiring, pad, or layer, or there can be intermediate components, wiring, pads, or layers. Conversely, when a component, wiring, pad, or layer is referred to as being "directly on," "directly connected to," or "directly attached to" another component, wiring, pad, or layer, there are no intermediate components, wiring, pads, or layers.

[0023] Before describing this embodiment, a comparative example of a semiconductor package and its problems will be described.

[0024] Figure 1A This is a cross-sectional view of a semiconductor package illustrating a comparative example, and Figure 1B This is observed from above. Figure 1A A plan view of a portion of a semiconductor package. Figure 1C It is an example of a logical value. Figure 1A and Figure 1BA diagram showing the electrical application status of the chip identification pads of multiple semiconductor chips included in a semiconductor package. Figure 1D It is used to explain in Figure 1A and Figure 1B A diagram illustrating potential problems in semiconductor packages.

[0025] First, refer to Figure 1A and Figure 1B A comparative example of a semiconductor package may include a base layer 100, a chip stack 110, an external connection terminal 130, and a molding layer 140.

[0026] The base layer 100 may be a layer having circuitry and / or wiring structures (not shown) for electrically connecting the chip stack 110 to external components of a semiconductor package. For example, the base layer 100 may include a substrate such as a printed circuit board (PCB), an interposer, a redistribution layer, etc. Alternatively, when the chip stack 110 includes a memory chip, the base layer 100 may be a semiconductor chip including logic circuitry supporting the operation of the memory chip (e.g., reading data from or writing data to the memory chip).

[0027] The substrate 100 may have one surface (e.g., upper surface) on which the chip stack 110 is disposed and another surface (e.g., lower surface) on which the external connection terminals 130 are disposed. Pads 102 for electrical connection with the chip stack 110 may be disposed on the upper surface of the substrate 100. Pads 102 may be part of the circuitry and / or wiring structure of the substrate 100. Furthermore, although not shown, various pads for electrical connections between the substrate 100 and other components (such as the external connection terminals 130) may also be provided on the upper and / or lower surfaces of the substrate 100.

[0028] The chip stack 110 may include a plurality of semiconductor chips 111 to 118, which are stacked vertically above one surface of the substrate 100. In a comparative example, the chip stack 110 includes eight semiconductor chips 111 to 118, but the number of semiconductor chips included in the chip stack 110 can be modified in various ways. Specifically, the number of semiconductor chips included in the chip stack 110 may be 2 NN can be a natural number of 2 or greater. For ease of description, the plurality of semiconductor chips 111 to 118 will be referred to as first semiconductor chip 111, second semiconductor chip 112, third semiconductor chip 113, fourth semiconductor chip 114, fifth semiconductor chip 115, sixth semiconductor chip 116, seventh semiconductor chip 117, and eighth semiconductor chip 118 according to their distance from the substrate 100. First semiconductor chips 111 to eighth semiconductor chips 118 can be the same memory chip, such as a DRAM chip or a NAND flash memory chip. However, this disclosure is not limited thereto, and first semiconductor chips 111 to eighth semiconductor chips 118 can be semiconductor chips with various types and functions.

[0029] The first semiconductor chip 111 to the eighth semiconductor chip 118 can be attached to the upper surface of the base layer 100 and the upper surface of the first semiconductor chip 111 to the seventh semiconductor chip 117 respectively by an adhesive layer (not shown) formed on its lower surface.

[0030] Multiple chip pads CP can be disposed on the upper surface of each of the first semiconductor chips 111 to the eighth semiconductor chips 118. Multiple chip pads CP can be disposed at a side edge region of each of the first semiconductor chips 111 to the eighth semiconductor chips 118 in a first direction. The first semiconductor chips 111 to the eighth semiconductor chips 118 can be stacked with their upper surfaces where the chip pads CP are disposed facing upwards and their lower surfaces facing the substrate 100 (i.e., facing upwards). In this case, the first semiconductor chips 111 to the eighth semiconductor chips 118 can be offset in the stack from the side adjacent to the chip pads CP to the side opposite to that side in the first direction, such that all the chip pads of each of the first semiconductor chips 111 to the eighth semiconductor chips 118 are exposed. The side surfaces of the first semiconductor chips 111 to the eighth semiconductor chips 118 in a second direction intersecting the first direction can be substantially aligned with each other, and the other side surfaces of the first semiconductor chips 111 to the eighth semiconductor chips 118 in the second direction can be substantially aligned with each other.

[0031] In each of the first semiconductor chips 111 to the eighth semiconductor chips 118, a plurality of chip pads CP can be arranged in a row along a second direction. Corresponding chip pads CP in the first semiconductor chips 111 to the eighth semiconductor chips 118 (e.g., chip pads CP substantially aligned with each other along the first direction) can perform the same function. As an example, in Figure 1BIn the plan view, the leftmost chip pads CP of the first semiconductor chip 111 to the eighth semiconductor chip 118 can be connected to each other via wiring 120, and can also be connected to the pads 102 of the substrate 100 via wiring 120. Therefore, the leftmost chip pads CP of the first semiconductor chip 111 to the eighth semiconductor chip 118 can be used as terminals for receiving power from the substrate 100 or exchanging signals with the substrate 100. Specifically, some of the multiple chip pads CP can be used as chip identification pads CP1, CP2, and CP3, which are used to identify the first semiconductor chip 111 to the eighth semiconductor chip 118 included in the chip stack 110, respectively. The arrangement, power application, and corresponding connection to wiring 120 of the chip identification pads CP1, CP2, and CP3 will be described below.

[0032] External connection terminals 130 may be formed above the lower surface of the substrate 100 and may serve to connect to external components of the semiconductor package. External connection terminals 130 may include various interconnects such as solder balls.

[0033] The molding layer 140 can cover the chip stack 110 above the upper surface of the base layer 100. The molding layer 140 can include various molding materials such as EMC (epoxy molding compound).

[0034] In the above semiconductor package, because the chip stack 110 includes 2 3 There are semiconductor chips 111 to 118, so each of the first semiconductor chip 111 to the eighth semiconductor chip 118 may include three chip identification pads CP1, CP2 and CP3, that is, the first chip identification pad CP1, the second chip identification pad CP2 and the third chip identification pad CP3. This is because 2 can be represented by using three chip identification pads CP1, CP2 and CP3. 3 There are two states. If the chip stack 110 includes 2 N If there are N semiconductor chips, then each semiconductor chip can include N chip identification pads. By using N chip identification pads, 2... N There are several states.

[0035] In the first semiconductor chip 111 to the eighth semiconductor chip 118, the first chip identification pad CP1 can be substantially aligned with each other along a first direction, the second chip identification pad CP2 can be substantially aligned with each other along a first direction, and the third chip identification pad CP3 can be substantially aligned with each other along a first direction. Additionally, in each of the first semiconductor chip 111 to the eighth semiconductor chip 118, the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 can be arranged adjacent to each other in a second direction. The first semiconductor chip 111 to the eighth semiconductor chip 118 can be distinguished from each other based on the combination of power applied to the first chip identification pad CP1, the second chip identification pad CP2, and the third chip identification pad CP3. Further reference will follow below. Figure 1C and Figure 1B Let's describe this together.

[0036] Reference Figure 1B and Figure 1CEach of the first chip identification pads CP1, CP2, and CP3 in the first semiconductor chip 111 to the eighth semiconductor chip 118 can be in a powered state or a floating state. Here, the powered state can include voltages of various levels. For example, the powered state can be the power supply voltage (VDD). The powered state of any of the first chip identification pads CP1, CP2, and CP3 can be represented by a logic value "1", and the floating state can be represented by a logic value "0". Each of the first semiconductor chip 111 to the eighth semiconductor chip 118 can be represented by a combination of logic values ​​for its first chip identification pads CP1, CP2, and CP3. In this case, the powered state of each of the first chip identification pads CP1, CP2, and CP3 in the first semiconductor chip 111 to the eighth semiconductor chip 118 can be determined such that the combinations of logic values ​​representing the first semiconductor chip 111 to the eighth semiconductor chip 118 are different from each other. For example, when the first semiconductor chip 111 is represented by the logic value combination "000", all the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the first semiconductor chip 111 can be in a floating state. Furthermore, when the second semiconductor chip 112 is represented by the logic value combination "100", power can be applied to the first chip identification pad CP1 of the second semiconductor chip 112, and the second chip identification pads CP2 and the third chip identification pads CP3 can be in a floating state. Similarly, the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of each of the third semiconductor chips 113 to the eighth semiconductor chip 118 can receive power or be in a floating state, such that each of the third semiconductor chips 113 to the eighth semiconductor chip 118 is represented by a different logic value combination.

[0037] Among the first to third chip identification pads CP1, CP2, and CP3 of the first semiconductor chip 111 to the eighth semiconductor chip 118, those chip identification pads to which power is applied (i.e., Figure 1C Those chip identification pads (represented by logic value "1") can be connected to wiring 120. This is to receive power from the substrate 100 via pads 102 connected to the substrate 100 through wiring 120. On the other hand, among the first to third chip identification pads CP1, CP2, and CP3 of the first semiconductor chip 111 to the eighth semiconductor chip 118, those chip identification pads in a floating state (i.e., Figure 1CThose chip identification pads (represented by the logic value "0") may not be connected to wiring 120. More specifically, among the first chip identification pads CP1 aligned along the first direction, the first chip identification pads CP1 of the second semiconductor chip 112, the fourth semiconductor chip 114, the sixth semiconductor chip 116, and the eighth semiconductor chip 118, which are energized, can be connected to each other via wiring 120 and simultaneously connected to pad 102 of the substrate 100. Furthermore, among the second chip identification pads CP2 aligned along the first direction, the second chip identification pads CP2 of the third semiconductor chip 113, the fourth semiconductor chip 114, the seventh semiconductor chip 117, and the eighth semiconductor chip 118, which are energized, can be connected to each other via wiring 120 and simultaneously connected to pad 102 of the substrate 100. Additionally, among the third chip identification pads CP3 aligned along the first direction, the third chip identification pads CP3 of the fifth semiconductor chip 115 to the eighth semiconductor chip 118, which are energized, can be connected to each other via wiring 120 and simultaneously connected to pad 102 of the substrate 100.

[0038] However, in this case, wiring 120 may have sections that can be considered long wirings. For reference, a long wiring may refer to wiring that skips one or more chip pads CP aligned in the first direction, while a short wiring may refer to wiring that connects adjacent chip pads CP aligned in the first direction, i.e., wiring that does not skip chip pads CP. For example, the portion of wiring 120 that connects the first chip identification pad CP1 of the second semiconductor chip 112 and the first chip identification pad CP1 of the fourth semiconductor chip 114 to each other may be a long wiring because it skips the third semiconductor chip 113. Similarly, for example, wiring 120 that connects the second chip identification pad CP2 of the fourth semiconductor chip 114 and the second chip identification pad CP2 of the seventh semiconductor chip 117 to each other may be a long wiring because it skips the fifth semiconductor chip 115 and the sixth semiconductor chip 116. The portions of wiring 120 corresponding to long wirings may come into contact with each other in the second direction during the molding process, leading to an electrical short circuit fault. This defect can be further exacerbated when the first semiconductor chips 111 to the eighth semiconductor chips 118 are misaligned in the second direction due to process errors in the step of stacking the first semiconductor chips 111 to the eighth semiconductor chips 118. Thus, for example in... Figure 1D The image shows an electrical short-circuit fault.

[0039] Reference Figure 1D The short wiring SW connecting the chip pads CP that are adjacent to each other in the first direction (i.e., without skipping the semiconductor chip) in the chip pads CP aligned in the first direction cannot be bent or fall to the side, so no electrical short circuit fault will occur.

[0040] On the other hand, long traces LW connecting chip pads CP that are not adjacent to each other in the first direction (i.e., skipping at least one semiconductor chip) aligned in the first direction are more likely to bend or fall sideways. Therefore, long traces LW adjacent in the second direction may come into contact with each other, resulting in an electrical short circuit fault.

[0041] In this embodiment described below, by using only short wiring that does not skip the semiconductor chip as the wiring to connect the chip identification pads to each other, it is possible to prevent electrical short-circuit faults in the semiconductor package of the comparative example described above. Furthermore, by optimizing the arrangement of the chip identification pads and the wiring connections to the chip identification pads, the wiring length can be reduced, thereby improving signal transmission characteristics.

[0042] Figure 2A This is a cross-sectional view illustrating an embodiment of the semiconductor package of the present disclosure, and Figure 2B This is observed from above. Figure 2A A plan view of a portion of a semiconductor package. For reference, when viewed from above... Figure 2A In semiconductor packaging, a portion or all of the first chip stack may be covered by the second chip stack; however, for ease of description, Figure 2B The planar diagram illustrates the first and second chip stacks, making all chip pads of both stacks fully visible. Figure 2C It is an example of a logical value. Figure 2A and Figure 2B A diagram showing the electrical application status of the stack of multiple semiconductor chips included in a semiconductor package, identifying the pads and chip identification pads.

[0043] First, refer to Figure 2A and Figure 2B The semiconductor package of this embodiment may include a base layer 200, a first chip stack 210 formed on one surface of the base layer 200 and including a plurality of semiconductor chips 211 to 214, a first wiring 230 connecting the first chip stack 210 and the base layer 200 while connecting the plurality of semiconductor chips 211 to 214 to each other, a second chip stack 220 formed on the first chip stack 210 and including a plurality of semiconductor chips 221 to 224, a second wiring 240 connecting the second chip stack 220 and the base layer 200 while connecting the plurality of semiconductor chips 221 to 224 to each other, an external connection terminal 250 formed on another surface of the base layer 200, and a molding layer 260 covering the first chip stack 210 and the second chip stack 220.

[0044] The base layer 200 may be a layer having circuitry and / or wiring structures (not shown) for electrically connecting the first chip stack 210 and the second chip stack 220 to external components of the semiconductor package. For example, the base layer 200 may include a substrate such as a printed circuit board, an intervention layer, a redistribution layer, etc. Alternatively, when the first chip stack 210 and the second chip stack 220 include a memory chip, the base layer 200 may be a semiconductor chip including logic circuitry supporting the operation of the memory chip (e.g., reading data from or writing data to the memory chip).

[0045] The substrate 200 may have one surface (e.g., an upper surface) on which the first chip stack 210 and the second chip stack 220 are disposed, and another surface (e.g., a lower surface) on which the external connection terminal 250 is disposed. Pads 202 for electrical connection with the first chip stack 210 and the second chip stack 220 may be disposed on the upper surface of the substrate 200. The pads 202 may be part of the circuitry and / or wiring structure of the substrate 200. Furthermore, although not shown, various pads for electrical connection between the substrate 200 and other components (such as the external connection terminal 250) may be further disposed on the upper and / or lower surfaces of the substrate 200.

[0046] The first chip stack 210 may include a plurality of semiconductor chips 211 to 214 stacked vertically above one surface of the substrate 200. In this embodiment, the first chip stack 210 includes four semiconductor chips 211 to 214, but the number of semiconductor chips included in the first chip stack 210 can be modified in various ways. Specifically, the number of semiconductor chips included in the first chip stack 210 may be 2 N-1 N can be a natural number of 2 or greater. For ease of description, based on their distance from the substrate 200, the plurality of semiconductor chips 211 to 214 will be referred to as first semiconductor chip 211, second semiconductor chip 212, third semiconductor chip 213, and fourth semiconductor chip 214. First semiconductor chip 211 to fourth semiconductor chip 214 can be the same memory chip, such as a DRAM chip or a NAND flash memory chip. However, this disclosure is not limited thereto, and first semiconductor chip 211 to fourth semiconductor chip 214 can be semiconductor chips of various types and functions.

[0047] An adhesive layer AL can be formed above the lower surface of each of the first semiconductor chips 211 to the fourth semiconductor chips 214. Through the adhesive layer AL, the first semiconductor chip 211 can be attached to the upper surface of the substrate 200, and the second semiconductor chips 212 to the fourth semiconductor chips 214 can be attached to the upper surfaces of the first semiconductor chip 211 to the third semiconductor chip 213, respectively. The adhesive layer AL may include an insulating adhesive material, such as a die attachment film (DAF).

[0048] Multiple chip pads CP can be disposed on the upper surface of each of the first semiconductor chips 211 to the fourth semiconductor chips 214. Multiple chip pads CP can also be disposed on a side edge region of each of the first semiconductor chips 211 to the fourth semiconductor chips 214 in a first direction. The first semiconductor chips 211 to the fourth semiconductor chips 214 can be stacked with their upper surfaces where the chip pads CP are disposed facing upwards and their lower surfaces facing the base layer 200 (i.e., face-up configuration). In this case, the first semiconductor chips 211 to the fourth semiconductor chips 214 can be offset in the stack from one side adjacent to the chip pad CP to the other side located in the first direction opposite to that side, such that all the chip pads CP of each of the first semiconductor chips 211 to the fourth semiconductor chips 214 are exposed. The side surfaces of the first semiconductor chips 211 to the fourth semiconductor chips 214 in a second direction intersecting the first direction can be substantially aligned with each other, and the other side surfaces of the first semiconductor chips 211 to the fourth semiconductor chips 214 in the second direction can be substantially aligned with each other.

[0049] In each of the first semiconductor chip 211 to the fourth semiconductor chip 214, a plurality of chip pads CP can be arranged in a row along the second direction. Corresponding chip pads CP in the first semiconductor chip 211 to the fourth semiconductor chip 214 (e.g., chip pads CP substantially aligned with each other along the first direction) can perform the same function. As an example, in Figure 2BIn the plan view, the leftmost chip pads CP of the first semiconductor chip 211 to the fourth semiconductor chip 214 can be connected to each other via the first wiring 230, and can also be connected to the pads 202 of the substrate 200 via the first wiring 230. Therefore, the leftmost chip pads CP of the first semiconductor chip 211 to the fourth semiconductor chip 214 can be used as terminals for receiving power from the substrate 200 or exchanging signals with the substrate 200. Specifically, some of the multiple chip pads CP can be used as stack identification pads CP0 for distinguishing the first chip stack 210 from the second chip stack 220, and chip identification pads CP1 and CP2 for identifying the first semiconductor chip 211 to the fourth semiconductor chip 214 included in the first chip stack 210. The arrangement of the stack identification pads CP0 and the chip identification pads CP1 and CP2 in the first chip stack 210, the application of power, and their corresponding connection to the first wiring 230 will be described later.

[0050] The first wiring 230 provides connections between the first semiconductor chips 211 to 214 included in the first chip stack 210 and between the first chip stack 210 and the base layer 200. For ease of description, the portion of the first wiring 230 connecting the chip pads CP between the first semiconductor chips 211 to 214 will be referred to as the first inter-chip wiring 232, and the portion of the first wiring 230 connecting the chip pads CP of the first semiconductor chip 230 located at the bottom of the first chip stack 210 and the pads 202 of the base layer 200 will be referred to as the first stack wiring 234. For convenience, the first inter-chip wiring 232 is shown as a solid line, while the first stack wiring 234 is shown as a dashed line, but this does not reflect the actual shape of the wiring.

[0051] The second chip stack 220 may include a plurality of semiconductor chips 221 to 224 stacked vertically above the first chip stack 210. In this embodiment, the second chip stack 220 includes four semiconductor chips 221 to 224, but the number of semiconductor chips included in the second chip stack 220 can be modified in various ways. Specifically, the number of semiconductor chips included in the second chip stack 220 may be 2 N-1 This is the same number of semiconductor chips included in the first chip stack 210. Therefore, the semiconductor package of this embodiment can include a total of 2 NA plurality of semiconductor chips. For ease of description, based on their distance from the first chip stack 210, the plurality of semiconductor chips 221 to 224 of the second chip stack 220 will be referred to as first semiconductor chip 221, second semiconductor chip 222, third semiconductor chip 223, and fourth semiconductor chip 224. First semiconductor chips 221 to fourth semiconductor chips 224 may be the same memory chip, such as a DRAM chip or a NAND flash memory chip. However, this disclosure is not limited thereto, and first semiconductor chips 221 to fourth semiconductor chips 224 may be semiconductor chips of various types and functions. Furthermore, the first semiconductor chips 221 to fourth semiconductor chips 224 of the second chip stack 220 may be the same as the first semiconductor chips 211 to fourth semiconductor chips 214 of the first chip stack 210.

[0052] An adhesive layer AL can be formed above the lower surface of each of the first semiconductor chips 221 to the fourth semiconductor chips 224 in the second chip stack 220. Through the adhesive layer AL, the first semiconductor chip 221 can be attached to the upper surface of the fourth semiconductor chip 214 located at the uppermost part of the first chip stack 210, and the second semiconductor chips 222 to the fourth semiconductor chips 224 can be attached to the upper surfaces of the first semiconductor chips 221 to the third semiconductor chips 223, respectively.

[0053] Multiple chip pads CP can be disposed on the upper surface of each of the first semiconductor chips 221 to the fourth semiconductor chips 224. Multiple chip pads CP can also be disposed in a side edge region of each of the first semiconductor chips 221 to the fourth semiconductor chips 224 in a first direction. The first semiconductor chips 221 to the fourth semiconductor chips 224 can be stacked with their upper surfaces where the chip pads CP are disposed facing upwards and their lower surfaces facing the base layer 200 (i.e., facing upwards). In this case, the first semiconductor chips 221 to the fourth semiconductor chips 224 can be offset in a direction from the side adjacent to the chip pads CP to the side opposite that side in the first direction, such that all the chip pads CP of each of the first semiconductor chips 221 to the fourth semiconductor chips 224 are exposed. The first semiconductor chips 221 to the fourth semiconductor chips 224 of the second chip stack 220 can be stacked in the same offset direction as the first semiconductor chips 211 to the fourth semiconductor chips 214 of the first chip stack 210. Therefore, the second chip stack 220 can have the same / similar stepped shape as the first chip stack 210. The first semiconductor chips 221 to 224 can be substantially aligned with each other on one side in the second direction, and the first semiconductor chips 221 to 224 can be substantially aligned with each other on the other side in the second direction. Furthermore, one side surface of the first semiconductor chips 221 to 224 of the second chip stack 220 can be substantially aligned with one side surface of the first semiconductor chips 211 to 214 of the first chip stack 210 in the second direction, and the other side surface of the first semiconductor chips 221 to 224 of the second chip stack 220 can be substantially aligned with the other side surface of the first semiconductor chips 211 to 214 of the first chip stack 210 in the second direction.

[0054] In each of the first semiconductor chips 221 to the fourth semiconductor chips 224, a plurality of chip pads CP can be arranged in a row along a second direction. Corresponding chip pads CP in the first semiconductor chips 221 to the fourth semiconductor chips 224 (e.g., chip pads CP substantially aligned with each other along the first direction) can perform the same function. For example, in Figure 2BIn the plan view, the leftmost chip pads CP of the first semiconductor chip 221 to the fourth semiconductor chip 224 can be connected to each other via the second wiring 240, and can also be connected to the pads 202 of the substrate 200 via the second wiring 240. Therefore, the leftmost chip pads CP of the first semiconductor chip 221 to the fourth semiconductor chip 224 can be used as terminals for receiving power from the substrate 200 or exchanging signals with the substrate 200. Furthermore, the chip pads CP of the first semiconductor chip 211 to the fourth semiconductor chip 214 aligned in the first direction and the corresponding and / or aligned chip pads CP of the first semiconductor chip 221 and the fourth semiconductor chip 224 can perform the same function. Therefore, the first wiring 230 and the second wiring 240 connected to the aligned chip pads CP in the first direction can be jointly connected to the same pads 202 of the substrate 200. Some of the multiple chip pads CP can be used as stack identification pads CP0 for distinguishing the second chip stack 220 from the first chip stack 210, and chip identification pads CP1 and CP2 for identifying the first semiconductor chips 221 to the fourth semiconductor chips 224 included in the second chip stack 220. The arrangement of the stack identification pads CP0 and the chip identification pads CP1 and CP2 in the second chip stack 220, the power application, and the corresponding connection to the second wiring 240 will be described later.

[0055] The second wiring 240 provides connections between the first semiconductor chip 221 to the fourth semiconductor chip 224 included in the second chip stack 220, and between the second chip stack 220 and the base layer 200. For ease of description, the portion of the second wiring 240 connecting the chip pad CP between the first semiconductor chip 221 to the fourth semiconductor chip 224 will be referred to as the second inter-chip wiring 242, and the portion of the second wiring 230 connecting the chip pad CP of the first semiconductor chip 221 located at the bottom of the second chip stack 220 and the pad 202 of the base layer 200 will be referred to as the second stack wiring 244. For convenience, the second inter-chip wiring 242 is shown as a solid line, and the second stack wiring 244 is shown as a dashed line, but this does not reflect the actual shape of the wiring.

[0056] Furthermore, when the second chip stack 220 is stacked on top of the first chip stack 210, a side surface of the first semiconductor chip 221 located at the bottom of the second chip stack 220 can protrude from a side surface of the fourth semiconductor chip 214 located at the top of the first chip stack 210 in a direction opposite to the offset direction. This is to reduce the area occupied by the first chip stack 210 and the second chip stack 220 in the plan view, to prevent the second stack wiring 244 from contacting the first wiring 230, and to minimize the increase in the length of the second stack wiring 244. For reference, due to the vertical distance between the second chip stack 220 and the base layer 200, the second stack wiring 244 can have a relatively long length compared to the first inter-chip wiring 232, the first stack wiring 234, and the second inter-chip wiring 242. As the wiring length increases, the electrical path through the wiring becomes longer, and the signal transmission characteristics may deteriorate. Therefore, it is desirable to reduce the length of the second stack wiring 244.

[0057] In this configuration, the thickness T2 of the adhesive layer AL on the lower surface of the first semiconductor chip 221 located at the bottommost portion of the second chip stack 220 can be greater than the thickness T1 of the adhesive layer AL on the lower surfaces of each of the other semiconductor chips 211 to 214 and 222 to 224 of the first chip stack 210 and the second chip stack 220. This is because the loop of the first inter-chip wiring 232 connected to the chip pad CP of the fourth semiconductor chip 214 protrudes above the upper surface of the fourth semiconductor chip 214. The thickness T2 of the adhesive layer AL on the lower surface of the first semiconductor chip 221 can be sufficiently large such that the loop is covered by the adhesive layer AL on the lower surface of the first semiconductor chip 221, and the lower surface of the first semiconductor chip 221 is spaced apart from the fourth semiconductor chip 214 of the first chip stack 210.

[0058] External connection terminals 250 may be formed above the lower surface of the substrate 200 and may function as connections to external components of the semiconductor package. External connection terminals 250 may include various interconnects such as solder balls.

[0059] The molding layer 260 can cover the first chip stack 210 and the second chip stack 220 above the upper surface of the base layer 200. The molding layer 260 may include various molding materials such as EMC.

[0060] In the above semiconductor package, because the first chip stack 210 includes 2 2There are semiconductor chips 211 to 214, so each of the first semiconductor chips 211 to the fourth semiconductor chip 214 may include at least two chip identification pads to distinguish / identify them within the first chip stack 210. For example, each of the first semiconductor chips 211 to the fourth semiconductor chip 214 may include a first chip identification pad CP1 and a second chip identification pad CP2. This is because by using two chip identification pads, 2 2 There are two states. Furthermore, to distinguish / identify the first chip stack 210 and the second chip stack 220, each of the first semiconductor chips 211 to the fourth semiconductor chips 214 of the first chip stack 210 may include a stack identification pad CP0. Additionally, because the second chip stack 220 includes 2... 2 Each of the first semiconductor chips 221 to 224 may include at least two chip identification pads (i.e., a first chip identification pad CP1 and a second chip identification pad CP2) to distinguish / identify them within the second chip stack 220. Furthermore, to distinguish / identify the first chip stack 210 and the second chip stack 220, each of the first semiconductor chips 221 to 224 of the second chip stack 220 may include a stack identification pad CP0.

[0061] In the first semiconductor chips 211 to 214 of the first chip stack 210 and the first semiconductor chips 221 to 224 of the second chip stack 220, stack identification pads CP0, CP1, and CP2 are substantially aligned with each other along a first direction. In each of the first semiconductor chips 211 to 214 of the first chip stack 210 and the first semiconductor chips 221 to 224 of the second chip stack 220, stack identification pads CP0, CP1, and CP2 are arranged adjacent to each other in a second direction. However, this disclosure is not limited thereto, and in another embodiment, the first chip identification pads CP1 and CP2 are adjacent to each other, and the stack identification pads CP0 are spaced apart from the first chip identification pads CP1 and CP2 in the second direction. In other words, another chip pad CP can be positioned between the stack-up identification pad CP0 and the first chip identification pad CP1 and the second chip identification pad CP2, without any chip pad CP inserted between the first chip identification pad CP1 and the second chip identification pad CP2. The first semiconductor chips 211 to 214 of the first chip stack 210 and the first semiconductor chips 221 to 224 of the second chip stack 220 can be distinguished from each other based on the combination of the power applied to the stack-up identification pad CP0 and the first chip identification pad CP1 and the second chip identification pad CP2. Further reference will follow below. Figure 2C and Figure 2B Let's describe this together.

[0062] Reference Figure 2B and Figure 2C Each of the stack-up identification pad CP0, the first chip identification pad CP1, and the second chip identification pad CP2 can be in a powered state or a floating state. Here, the powered state can include voltages of various levels. For example, the powered state can be the power supply voltage (VDD). The powered state of any of the stack-up identification pad CP0, the first chip identification pad CP1, and the second chip identification pad CP2 can be represented by a logic value "1", and the floating state can be represented by a logic value "0".

[0063] Here, the power application state of the stack identification pad CP0 of the first chip stack 210 can be different from the power application state of the stack identification pad CP0 of the second chip stack 220, enabling the differentiation / identification of the first chip stack 210 and the second chip stack 220. That is, the logic value of the stack identification pad CP0 of the first chip stack 210 can be different from the logic value of the stack identification pad CP0 of the second chip stack 220. In this embodiment, the stack identification pads CP0 of the first semiconductor chip 211 to the fourth semiconductor chip 214 of the first chip stack 210 can be powered (i.e., can have a logic value "1"), and the stack identification pads CP0 of the first semiconductor chip 221 to the fourth semiconductor chip 224 of the second chip stack 220 can be in a floating state (i.e., can have a logic value "0"). Because the stack identification pads CP0 of the first semiconductor chips 221 to the fourth semiconductor chips 224 of the second chip stack 220 do not receive power, the bonding wiring connection with them can be omitted, as shown in the figure. Conversely, in this embodiment, it is also possible for the stack identification pads CP0 of the first chip stack 210 to be in a floating state and for the stack identification pads CP0 of the second chip stack 220 to be powered. However, this embodiment is desirable in terms of reducing wiring length and correspondingly improving signal transmission characteristics.

[0064] The stack-up identification pads CP0 of the first chip stack 210 can be connected to the base layer 200 via the first wiring 230. More specifically, the stack-up identification pads CP0 of the first semiconductor chip 211 to the fourth semiconductor chip 214 of the first chip stack 210 can be connected to each other via the first inter-chip wiring 232, and the stack-up identification pad CP0 of the first semiconductor chip 211 can be connected to the pad 202 of the base layer 200 via the first stack-up wiring 234. Because the stack-up identification pads CP0 of the second chip stack 220 are in a floating state, they may not be connected to wiring.

[0065] Furthermore, to distinguish / identify the first semiconductor chip 211 to the fourth semiconductor chip 214 in the first chip stack 210, the four logic value combinations represented by the power application states of the first chip identification pad CP1 and the second chip identification pad CP2 can be different from each other. In this embodiment, the first chip identification pad CP1 and the second chip identification pad CP2 of the bottommost first semiconductor chip 211 can be in a power-applied state, that is, a state with a logic value "1". The second semiconductor chip 212 can be in the following state: one of the first chip identification pad CP1 and the second chip identification pad CP2 (e.g., the first chip identification pad CP1) receives power (i.e., has a logic value "1"), and the other of the first chip identification pad CP1 and the second chip identification pad CP2 (e.g., the second chip identification pad CP2) is in a floating state (i.e., has a logic value "0"). The third semiconductor chip 213 can be in the following state: another of the first chip identification pad CP1 and the second chip identification pad CP2 (e.g., the second chip identification pad CP2) receives power (i.e., has a logic value "1"), and one of the first chip identification pad CP1 and the second chip identification pad CP2 (e.g., the first chip identification pad CP1) is in a floating state (i.e., has a logic value "0"). The fourth semiconductor chip 214 can be in a state where the first chip identification pad CP1 and the second chip identification pad CP2 are in a floating state (i.e., have a logic value "0").

[0066] The first chip identification pad CP1 and the second chip identification pad CP2 of the first chip stack 210 can be connected to the base layer 200 via the first wiring 230. More specifically, the second chip identification pad CP2 of the third semiconductor chip 213, the first chip identification pad CP1 of the second semiconductor chip 212, and the first chip identification pad CP1 of the first semiconductor chip 211 can be connected to each other via the first inter-chip wiring 232, and the first chip identification pad CP1 and the second chip identification pad CP2 of the first semiconductor chip 211 can be connected to the pad 202 of the base layer 200 via the first stack wiring 234. Specifically, because the first chip identification pads CP1 and CP2 of the second semiconductor chip 212 and the third semiconductor chip 213 connected to the first inter-chip leads 232 are arranged along a diagonal direction intersecting the first direction and the second direction, they can be connected to each other in the diagonal direction via the first inter-chip wiring 232. In this configuration, since the first inter-chip wiring 232 does not include long wiring that skips semiconductor chips, the occurrence of electrical short-circuit faults caused by wiring interference in the first chip stack 210 can be reduced. Furthermore, since the first chip identification pad CP1 and the second chip identification pad CP2 of the first semiconductor chip 211, which has the closest distance to the substrate 200, are connected to the first wiring 230, while the first chip identification pad CP1 and the second chip identification pad CP2 of the fourth semiconductor chip 211, which has the farthest distance to the substrate 200, are not connected to the first wiring 230, the length of the wiring used in the first chip stack 210 can be reduced, and signal transmission characteristics can be improved accordingly.

[0067] Similarly, to distinguish / identify the first semiconductor chip 221 to the fourth semiconductor chip 224 in the second chip stack 220, the four combinations of logic values ​​represented by the power application states of the first chip identification pad CP1 and the second chip identification pad CP2 can be different from each other. In this embodiment, the first chip identification pad CP1 and the second chip identification pad CP2 of the bottommost first semiconductor chip 221 can be in a powered state, i.e., a state with a logic value "1". The second semiconductor chip 222 can be in the following state: one of the first chip identification pad CP1 and the second chip identification pad CP2 (e.g., the first chip identification pad CP1) receives power (i.e., has a logic value "1"), and the other of the first chip identification pad CP1 and the second chip identification pad CP2 (e.g., the second chip identification pad CP2) is in a floating state (i.e., has a logic value "0"). The third semiconductor chip 223 can be in the following state: another of the first chip identification pad CP1 and the second chip identification pad CP2 (e.g., the second chip identification pad CP2) receives power (i.e., has a logic value "1"), and one of the first chip identification pad CP1 and the second chip identification pad CP2 (e.g., the first chip identification pad CP1) is in a floating state, i.e., has a logic value "0". The fourth semiconductor chip 224 can be in a state where the first chip identification pad CP1 and the second chip identification pad CP2 are in a floating state (i.e., have a logic value "0").

[0068] The first chip identification pad CP1 and the second chip identification pad CP2 of the second chip stack 220 can be connected to the base layer 200 via the second wiring 240. More specifically, the second chip identification pad CP2 of the third semiconductor chip 223, the first chip identification pad CP1 of the second semiconductor chip 222, and the first chip identification pad CP1 of the first semiconductor chip 221 can be connected to each other via the second inter-chip wiring 242, and the first chip identification pad CP1 and the second chip identification pad CP2 of the first semiconductor chip 221 can be connected to the pad 202 of the base layer 200 via the second stack wiring 244. Specifically, because the first chip identification pads CP1 and CP2 of the second semiconductor chip 222 and the third semiconductor chip 223 connected to the second inter-chip wiring 242 are arranged in a diagonal direction intersecting the first and second directions, they can be connected to each other in the diagonal direction via the second inter-chip wiring 242. In this case, because the second inter-chip wiring 242 does not include long wiring that skips semiconductor chips, the occurrence of electrical short-circuit faults caused by wiring interference in the second chip stack 220 can be reduced. Furthermore, since the first chip identification pad CP1 and the second chip identification pad CP2 of the first semiconductor chip 221, which has the closest distance to the substrate 200, are connected to the second wiring 240, and the first chip identification pad CP1 and the second chip identification pad CP2 of the fourth semiconductor chip 224, which has the farthest distance to the substrate 200, are not connected to the second wiring 240, the length of the wiring used in the second chip stack 230 can be reduced, and the signal transmission characteristics can be improved accordingly. Unlike the first inter-chip wiring 232, the second inter-chip wiring 242, and the first stack wiring 234, the second stack wiring 244 can be a long wiring that skips the first chip stack 210. However, by protruding from and stacking the second chip stack 220 above the first chip stack 210, interference between the second stack wiring 244 and the first wiring 230, as well as electrical short-circuit faults caused by this, can be prevented.

[0069] Furthermore, the power application states of the first chip identification pad CP1 and the second chip identification pad CP2 of the first chip stack 210 and the corresponding connection forms of the first wiring 230, as well as the power application states of the first chip identification pad CP1 and the second chip identification pad CP2 of the second chip stack 220 and the corresponding connection forms of the second wiring 240, are not limited to the illustrated cases. When power is applied to all the first chip identification pads CP1 and CP2 of the first semiconductor chips 211 and 221 located at the bottom of the first chip stack 210 and the second chip stack 220 respectively, and the first chip identification pads CP1 and CP2 of the fourth semiconductor chips 214 and 224 located at the top of the first chip stack 210 and the second chip stack 220 are in a floating state, the power application state of the first chip identification pads CP1 and CP2 of the second semiconductor chips 212 and 222 and the third semiconductor chips 213 and 223, and the corresponding connection form of the first inter-chip wiring 232 and the second inter-chip wiring 242, can be modified in various ways. (Refer to, for example...) Figure 2D This will be described.

[0070] Figure 2D This is a diagram illustrating the power application state of the stack-up identification pads and chip identification pads of a plurality of semiconductor chips included in a semiconductor package according to another embodiment of this disclosure, which are logic values. In this diagram, wiring connected to the stack-up identification pads and chip identification pads is shown in the form of arrows. The description will focus on the aspects described above. Figures 2A to 2C The differences between semiconductor packages.

[0071] Reference Figure 2D In addition to the embodiments described above, power can be applied to the first chip identification pad CP1 of the third semiconductor chips 213 and 223 and the second chip identification pad CP2 of the second semiconductor chips 212 and 222. Therefore, the chip identification pad CP1 of each of the third semiconductor chips 213 and 223, the second chip identification pad CP2 of each of the second semiconductor chips 212 and 222, and the second chip identification pad CP2 of each of the first semiconductor chips 211 and 221 can be connected to each other via inter-chip wiring. Each of the first chip identification pad CP1 and the second chip identification pad CP2 of the first semiconductor chips 211 and 221 can be connected to the substrate via laminate wiring.

[0072] Although not shown, other implementations are possible. For example, the power application state and wiring connection state of the first chip identification pad CP1 and the second chip identification pad CP2 of the first chip stack 210 can be compared with... Figure 2B and Figure 2CThe implementation method is the same, and the power application state and wiring connection state of the first chip identification pad CP1 and the second chip identification pad CP2 of the second chip stack 220 can be the same as those of the second chip stack 220. Figure 2D The implementation method is the same. Alternatively, for example, the power application state and wiring connection state of the first chip identification pad CP1 and the second chip identification pad CP2 of the first chip stack 210 can be the same as those of the other chip stack. Figure 2D The implementation method is the same, and the power application state and wiring connection state of the first chip identification pad CP1 and the second chip identification pad CP2 of the second chip stack 220 can be the same as those of the second chip stack 220. Figure 2B and Figure 2C The implementation method is the same.

[0073] In addition, Figures 2A to 2D In the embodiments described, the case where each of the two chip stacks includes four semiconductor chips has been described, but this disclosure is not limited thereto. Each of the two chip stacks may include eight semiconductor chips. Reference will be made below. Figures 3A to 3F This will be described in more detail.

[0074] Figure 3A This is a cross-sectional view illustrating another embodiment of the semiconductor package of this disclosure, and Figure 3B This is observed from above. Figure 3A A plan view of a portion of a semiconductor package. Figure 3C It is an example of a logical value. Figure 3A and Figure 3B A diagram showing the power application state of the stacked identification pads and chip identification pads of multiple semiconductor chips included in a semiconductor package. The description will focus on the differences from the embodiments described above.

[0075] First, refer to Figure 3A and Figure 3B The semiconductor package of this embodiment may include a base layer 300, a first chip stack 310 formed on one surface of the base layer 300 and including a plurality of semiconductor chips 311 to 318, a first wiring 330 connecting the first chip stack 310 and the base layer 300 while connecting the plurality of semiconductor chips 311 to 318 to each other, a second chip stack 320 formed on the first chip stack 310 and including a plurality of semiconductor chips 321 to 328, a second wiring 340 connecting the second chip stack 320 and the base layer 300 while connecting the plurality of semiconductor chips 321 to 328 to each other, an external connection terminal 350 formed on another surface of the base layer 300, and a molding layer 360 covering the first chip stack 310 and the second chip stack 320.

[0076] The first chip stack 310 may include eight semiconductor chips 311 to 318, namely, the first semiconductor chip 311 to the eighth semiconductor chip 318, stacked in a vertical direction above one surface of the base layer 300. The first semiconductor chip 311 to the eighth semiconductor chip 318 may be attached to the base layer 300 and the upper surface of the first semiconductor chip 311 to the seventh semiconductor chip 317 respectively by an adhesive layer AL formed above its lower surface.

[0077] Multiple chip pads CP can be disposed on the upper surface of each of the first semiconductor chips 311 to the eighth semiconductor chips 318. Multiple chip pads CP can also be disposed in a side edge region of each of the first semiconductor chips 311 to the eighth semiconductor chips 318 in a first direction. The first semiconductor chips 311 to the eighth semiconductor chips 318 can be offset in stack, thereby exposing all chip pads CP. One side surface and the other side surface of the first semiconductor chips 311 to the eighth semiconductor chips 318 in a second direction intersecting the first direction can be substantially aligned with each other.

[0078] In each of the first semiconductor chips 311 to the eighth semiconductor chips 318, a plurality of chip pads CP can be arranged in a row along a second direction. Specifically, some of the plurality of chip pads CP can serve as a stack identification pad CP0 for distinguishing the first chip stack 310 from the second chip stack 320, and chip identification pads CP1, CP2, and CP3 for identifying the first semiconductor chips 311 to the eighth semiconductor chips 318 included in the first chip stack 310. The arrangement of chip identification pads CP0 and CP1, CP2, and CP3 in the first chip stack 310, power application, and corresponding connection to the first wiring 330 will be described later.

[0079] The first wiring 330 can provide connections between the first semiconductor chips 311 to the eighth semiconductor chips 318 included in the first chip stack 310, and between the first chip stack 310 and the base layer 300. For ease of description, the portion of the first wiring 330 that connects the chip pads CP between the first semiconductor chips 311 to the eighth semiconductor chips 318 will be referred to as the first inter-chip wiring 332, and the portion of the first wiring 330 that connects the chip pads CP of the first semiconductor chip 311 located at the bottom of the first chip stack 310 and the pads 302 of the base layer 300 will be referred to as the first stack wiring 334.

[0080] The second chip stack 320 may include a plurality of semiconductor chips 321 to 328 stacked vertically above the first chip stack 310. The first semiconductor chips 321 to the eighth semiconductor chips 328 may be attached to the upper surfaces of the eighth semiconductor chip 318 and the first semiconductor chips 321 to the seventh semiconductor chips 327 of the first chip stack 310 respectively by an adhesive layer AL formed above their lower surfaces.

[0081] Multiple chip pads CP can be disposed on the upper surface of each of the first semiconductor chips 321 to the eighth semiconductor chips 328. Multiple chip pads CP can also be disposed in a side edge region of each of the first semiconductor chips 321 to the eighth semiconductor chips 328 in a first direction. The first semiconductor chips 321 to the eighth semiconductor chips 328 can be offset in stacking to expose all chip pads CP. One side surface and the other side surface of the first semiconductor chips 321 to the eighth semiconductor chips 328 in a second direction can be substantially aligned with each other. Furthermore, one side surface and the other side surface of the first semiconductor chips 321 to the eighth semiconductor chips 328 in the second direction can be aligned with one side surface and the other side surface of the first semiconductor chips 311 to the eighth semiconductor chips 318.

[0082] In each of the first semiconductor chips 321 to the eighth semiconductor chips 328, a plurality of chip pads CP can be arranged in a row along a second direction. Specifically, some of the plurality of chip pads CP can serve as a stack identification pad CP0 for distinguishing the first chip stack 310 from the second chip stack 320, and chip identification pads CP1, CP2, and CP3 for identifying the first semiconductor chips 321 to the eighth semiconductor chips 328 included in the second chip stack 320. The arrangement of the stack identification pads CP0 and the chip identification pads CP1, CP2, and CP3 in the second chip stack 320, the power application, and the corresponding connection to the second wiring 340 will be described later.

[0083] The second wiring 340 can provide connections between the first semiconductor chips 321 to the eighth semiconductor chips 328 included in the second chip stack 320 and between the second chip stack 320 and the base layer 300. For ease of description, the portion of the second wiring 340 that connects the chip pads CP between the first semiconductor chips 321 to the eighth semiconductor chips 328 will be referred to as the second inter-chip wiring 342, and the portion of the first wiring 330 that connects the chip pads CP of the first semiconductor chip 321 located at the bottom of the second chip stack 320 and the pads 302 of the base layer 300 will be referred to as the second stack wiring 344.

[0084] In the above semiconductor package, because the first chip stack 310 includes 23 There are semiconductor chips 311 to 318, so each of the first semiconductor chips 311 to the eighth semiconductor chip 318 may include at least three chip identification pads to distinguish / identify them within the first chip stack 310. For example, each of the first semiconductor chips 311 to the eighth semiconductor chip 318 may include first chip identification pads to third chip identification pads CP1, CP2, and CP3. This is because by using three chip identification pads, 2 3 There are two states. Furthermore, to distinguish / identify the first chip stack 310 and the second chip stack 320, each of the first semiconductor chips 311 to the eighth semiconductor chips 318 of the first chip stack 310 may include a stack identification pad CP0. Additionally, because the second chip stack 320 includes 2... 3 Each of the semiconductor chips 321 to 328 may include at least three chip identification pads, namely, first chip identification pads to third chip identification pads CP1, CP2, and CP3, to distinguish / identify them within the second chip stack 320. Furthermore, to distinguish / identify the first chip stack 310 and the second chip stack 320, each of the first semiconductor chips 321 to the eighth semiconductor chips 328 of the second chip stack 320 may include a stack identification pad CP0.

[0085] In the first chip stack 310 and the second chip stack 320, stack identification pads CP0, CP1, CP2, and CP3 can be substantially aligned with each other along a first direction. Furthermore, in a second direction, stack identification pads CP0, CP1, CP2, and CP3 can be arranged adjacent to each other. However, this disclosure is not limited to this, and in another embodiment, in the second direction, the first to third chip identification pads CP1, CP2, and CP3 can be adjacent to each other, and stack identification pad CP0 can be spaced apart from the first to third chip identification pads CP1, CP2, and CP3. That is, another chip pad CP can be disposed between stack identification pad CP0 and the first to third chip identification pads CP1, CP2, and CP3. The first semiconductor chips 311 to the eighth semiconductor chip 318 of the first chip stack 310 and the first semiconductor chips 321 to the eighth semiconductor chip 328 of the second chip stack 320 can be distinguished from each other based on the combination of power applied to the stack identification pad CP0, the first chip identification pad CP1, the second chip identification pad CP2, and the third chip identification pad CP3. Further reference will be made below. Figure 3C and Figure 3B Let's describe this together.

[0086] Reference Figure 3B and Figure 3C The power application state of the stack identification pad CP0 of the first chip stack 310 can be different from that of the stack identification pad CP0 of the second chip stack 320, enabling the differentiation / identification of the first chip stack 310 and the second chip stack 320. In other words, the logic value of the stack identification pad CP0 of the first chip stack 310 can be different from the logic value of the stack identification pad CP0 of the second chip stack 320. In this embodiment, the stack identification pads CP0 of the first semiconductor chips 311 to the eighth semiconductor chips 318 of the first chip stack 310 can be powered, i.e., can have a logic value of "1", and the stack identification pads CP0 of the first semiconductor chips 321 to the eighth semiconductor chips 328 of the second chip stack 320 can be in a floating state, i.e., can have a logic value of "0". Since the stack identification pads CP0 of the first semiconductor chip 321 to the eighth semiconductor chip 328 of the second chip stack 320 do not receive power, the bonding wire connection can be omitted, as shown in the figure.

[0087] The stack-up identification pads CP0 of the first chip stack 310 can be connected to the base layer 300 via the first wiring 330. More specifically, the stack-up identification pads CP0 of the first semiconductor chip 311 to the eighth semiconductor chip 318 of the first chip stack 310 can be connected to each other via the first inter-chip wiring 332, and the stack-up identification pad CP0 of the first semiconductor chip 311 can be connected to the pad 302 of the base layer 300 via the first stack-up wiring 334. Because the stack-up identification pads CP0 of the second chip stack 320 are in a floating state, they may not be connected to wiring.

[0088] Furthermore, to distinguish / identify the first semiconductor chip 311 to the eighth semiconductor chip 318 in the first chip stack 310, the eight logic value combinations representing the power application states of the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 can be different from each other. In this embodiment, the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the bottommost first semiconductor chip 311 can be in a state where power is applied. In each of the second to fourth semiconductor chips 312, 313, and 314, two selected chip identification pads among the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 can be powered, while the other chip identification pad can be in a floating state. Specifically, in order to form short wirings that do not skip semiconductor chips in the diagonal and / or vertical directions, power can be applied to the first to third chip identification pads CP1, CP2, and CP3, such that those chip identification pads in a floating state among the first to third chip identification pads CP1, CP2, and CP3 are arranged diagonally. For example, the first chip identification pad CP1 and the second chip identification pad CP2 of the second semiconductor chip 312 can receive power, the first chip identification pad CP1 and the third chip identification pad CP3 of the third semiconductor chip 313 can receive power, and the second chip identification pad CP2 and the third chip identification pad CP3 of the fourth semiconductor chip 314 can receive power. In this case, the third chip identification pad CP3 of the second semiconductor chip 312, the second chip identification pad CP2 of the third semiconductor chip 313, and the first chip identification pad CP1 of the fourth semiconductor chip 314 can be in a floating state and can be arranged diagonally (see dashed line ①). In each of the fifth to seventh semiconductor chips 315, 316, and 317, power can be applied to one of the selected chip identification pads CP1, CP2, and CP3 from the first to the third chip identification pads. Specifically, in order to form short wirings that do not skip over the semiconductor chip in the diagonal and / or vertical directions, those chip identification pads CP1, CP2, and CP3 to which power is applied can be arranged diagonally. For example, the third chip identification pad CP3 of the fifth semiconductor chip 315 can receive power, the second chip identification pad CP2 of the sixth semiconductor chip 316 can receive power, and the first chip identification pad CP1 of the seventh semiconductor chip 317 can receive power (see dashed line ②). In the eighth semiconductor chip 318, the first to the third chip identification pads CP1, CP2, and CP3 can be in a floating state.

[0089] The first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the first chip stack 310 can be connected to the base layer 300 via the first wiring 330. More specifically, the first chip identification pad CP1 of the seventh semiconductor chip 317, the second chip identification pad CP2 of the sixth semiconductor chip 316, the third chip identification pad CP3 of the fifth semiconductor chip 315, the second chip identification pad CP2 of the fourth semiconductor chip 314, the first chip identification pad CP1 of the third semiconductor chip 313, the first chip identification pad CP1 of the second semiconductor chip 312, and the first chip identification pad CP1 of the first semiconductor chip 311 can be connected to each other via the first inter-chip wiring 332. In addition, the third chip identification pads CP3 of the fourth semiconductor chip 314, the third chip identification pad CP3 of the third semiconductor chip 313, the second chip identification pad CP2 of the second semiconductor chip 312, and the second chip identification pad CP2 of the first semiconductor chip 311 can be connected to each other via the first inter-chip wiring 332. The first chip identification pads to the third chip identification pads CP1, CP2 and CP3 of the first semiconductor chip 311 can be connected to the pads 302 of the base layer 300 via the first stack wiring 334.

[0090] Similarly, to distinguish / identify the first semiconductor chip 321 to the eighth semiconductor chip 328 in the second chip stack 320, the eight logic value combinations represented by the power application states of the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 can be different from each other. In this embodiment, the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the bottommost first semiconductor chip 321 can be in a powered state. In each of the second to fourth semiconductor chips 322, 323, and 324, two selected chip identification pads among the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 can be powered, while the other chip identification pad can be in a floating state. Specifically, in order to form short wirings that do not skip over semiconductor chips in the diagonal and / or vertical directions, power can be applied to the first to third chip identification pads CP1, CP2, and CP3, such that those chip identification pads in a floating state among the first to third chip identification pads CP1, CP2, and CP3 are arranged diagonally. For example, the first chip identification pad CP1 and the second chip identification pad CP2 of the second semiconductor chip 322 can receive power, the first chip identification pad CP1 and the third chip identification pad CP3 of the third semiconductor chip 323 can receive power, and the second chip identification pad CP2 and the third chip identification pad CP3 of the fourth semiconductor chip 324 can receive power. In this case, the third chip identification pad CP3 of the second semiconductor chip 322, the second chip identification pad CP2 of the third semiconductor chip 323, and the first chip identification pad CP1 of the fourth semiconductor chip 324 can be in a floating state and can be arranged diagonally (see dashed line ③). In each of the fifth to seventh semiconductor chips 325, 326, and 327, power can be applied to one of the selected chip identification pads CP1, CP2, and CP3 from the first to the third chip identification pads. Specifically, in order to form short wirings that do not skip over the semiconductor chip in the diagonal and / or vertical directions, those chip identification pads CP1, CP2, and CP3 to which power is applied can be arranged diagonally. For example, the third chip identification pad CP3 of the fifth semiconductor chip 325 can receive power, the second chip identification pad CP2 of the sixth semiconductor chip 326 can receive power, and the first chip identification pad CP1 of the seventh semiconductor chip 327 can receive power (see dashed line ④). In the eighth semiconductor chip 328, the first to the third chip identification pads CP1, CP2, and CP3 can be in a floating state.

[0091] The first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the second chip stack 320 can be connected to the base layer 300 via the second wiring 340. More specifically, the first chip identification pad CP1 of the seventh semiconductor chip 327, the second chip identification pad CP2 of the sixth semiconductor chip 326, the third chip identification pad CP3 of the fifth semiconductor chip 325, the second chip identification pad CP2 of the fourth semiconductor chip 324, the first chip identification pad CP1 of the third semiconductor chip 323, the first chip identification pad CP1 of the second semiconductor chip 322, and the first chip identification pad CP1 of the first semiconductor chip 321 can be connected to each other via the second inter-chip wiring 342. Additionally, the third chip identification pads CP3 of the fourth semiconductor chip 324, the third chip identification pad CP3 of the third semiconductor chip 323, the second chip identification pad CP2 of the second semiconductor chip 322, and the second chip identification pad CP2 of the first semiconductor chip 321 can be connected to each other via the second inter-chip wiring 342. The first chip identification pads to the third chip identification pads CP1, CP2 and CP3 of the first semiconductor chip 321 can be connected to the pads 302 of the base layer 300 via the second stack wiring 344.

[0092] Furthermore, the power application states of the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the first chip stack 310 and the corresponding connection forms of the first wiring 330, as well as the power application states of the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the second chip stack 320 and the corresponding connection forms of the second wiring 340, are not limited to the illustrated cases. When power is applied to all the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the first semiconductor chips 311 and 321 located at the bottommost portions of the first chip stack 310 and the second chip stack 320, respectively, power is applied to two chip identification pads selected from the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of each of the second to fourth semiconductor chips 312 to 314 and 322 to 324, and power is applied to the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of each of the fifth semiconductor chips 315 and 325 to the seventh semiconductor chips 317 and 327, power is applied to the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of each of the second to fourth semiconductor chips 312 to 314 and 322 to 324, power is applied to the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of each of the fifth semiconductor chips 315 and 325 to the seventh semiconductor chips 317 and 327, power is applied to the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of each of the second to fourth semiconductor chips 315 to 325, respectively. When power is applied to one of the chip identification pads CP1, CP2, and CP3, and all the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the eighth semiconductor chips 318 and 328 located at the top of the first chip stack 310 and the second chip stack 320 are in a floating state, the power application state of the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the second semiconductor chips 312 to the seventh semiconductor chips 317, as well as the corresponding connection form of the first inter-chip wiring 332 and the second inter-chip wiring 342, can be modified in various ways. Here, in the first chip stack 310, the two selected chip identification pads of the second semiconductor chip 312, the two selected chip identification pads of the third semiconductor chip 313, and the two selected chip identification pads of the fourth semiconductor chip 314 can be different from each other. Similarly, in the second chip stack 320, the two selected chip identification pads of the second semiconductor chip 322, the two selected chip identification pads of the third semiconductor chip 323, and the two selected chip identification pads of the fourth semiconductor chip 324 can be different from each other. Furthermore, in the first chip stack 310, the one selected chip identification pad of the fifth semiconductor chip 315, the one selected chip identification pad of the sixth semiconductor chip 316, and the one selected chip identification pad of the seventh semiconductor chip 317 can be different from each other. Likewise, in the second chip stack 320, the one selected chip identification pad of the fifth semiconductor chip 325, the one selected chip identification pad of the sixth semiconductor chip 326, and the one selected chip identification pad of the seventh semiconductor chip 327 can be different from each other. For example, referencing 3D to Figure 3F This will be described.

[0093] Figures 3D to 3F These are diagrams illustrating the power application states of stack-up identification pads and chip identification pads of a plurality of semiconductor chips included in a semiconductor package according to another embodiment of this disclosure, serving as logical values. In these diagrams, wiring connected to the stack-up identification pads and chip identification pads is shown in the form of arrows. The description will focus on the aspects described above. Figures 3A to 3C The differences between semiconductor packages.

[0094] Reference Figure 3D The second chip identification pads CP2 and CP3 of the second semiconductor chips 312 and 322 can be powered, the first chip identification pads CP1 and CP3 of the third semiconductor chips 313 and 323 can be powered, and the first chip identification pads CP1 and CP2 of the fourth semiconductor chips 314 and 324 can be powered. In this configuration, the first chip identification pads CP1 of the second semiconductor chips 312 and 322, the second chip identification pads CP2 of the third semiconductor chips 313 and 323, and the third chip identification pads CP3 of the fourth semiconductor chips 314 and 324 (which are in a floating state) can be arranged diagonally (see dashed lines ① and ③). However, this diagonal direction can be different from... Figure 3C The directions shown are opposite.

[0095] The third chip identification pad CP3 of the fifth semiconductor chips 315 and 325 can be powered, the second chip identification pad CP2 of the sixth semiconductor chips 316 and 326 can be powered, and the first chip identification pad CP1 of the seventh semiconductor chips 317 and 327 can be powered, and they can be arranged diagonally (see dashed lines ② and ④). This diagonal direction can be... Figure 3C The diagonals shown are in the same direction.

[0096] In this configuration, the first chip identification pad CP1 of the seventh semiconductor chips 317 and 327, the second chip identification pad CP2 of the sixth semiconductor chips 316 and 326, the third chip identification pad CP3 of the fifth semiconductor chips 315 and 325, the second chip identification pad CP2 of the fourth semiconductor chips 314 and 324, the third chip identification pad CP3 of the third semiconductor chips 313 and 323, the third chip identification pad CP3 of the second semiconductor chips 312 and 322, and the third chip identification pad CP3 of the first semiconductor chips 311 and 321 can be interconnected via inter-chip wiring. Additionally, the first chip identification pad CP1 of the fourth semiconductor chips 314 and 324, the first chip identification pad CP1 of the third semiconductor chips 313 and 323, the second chip identification pad CP2 of the second semiconductor chips 312 and 322, and the second chip identification pad CP2 of the first semiconductor chips 311 and 321 can be interconnected via another inter-chip wiring. Each of the first chip identification pads to the third chip identification pads CP1, CP2 and CP3 of the first semiconductor chips 311 and 321 can be connected to the base layer via stack-up wiring.

[0097] Reference Figure 3E The second chip identification pads CP2 and CP3 of the second semiconductor chips 312 and 322 can be powered, the first chip identification pads CP1 and CP3 of the third semiconductor chips 313 and 323 can be powered, and the first chip identification pads CP1 and CP2 of the fourth semiconductor chips 314 and 324 can be powered. In this configuration, the first chip identification pads CP1 of the second semiconductor chips 312 and 322, the second chip identification pads CP2 of the third semiconductor chips 313 and 323, and the third chip identification pads CP3 of the fourth semiconductor chips 314 and 324 (which are in a floating state) can be arranged diagonally (see dashed lines ① and ③). However, this diagonal direction can be different from... Figure 3C The directions shown are opposite.

[0098] The first chip identification pad CP1 of the fifth semiconductor chips 315 and 325 can be powered, the second chip identification pad CP2 of the sixth semiconductor chips 316 and 326 can be powered, and the third chip identification pad CP3 of the seventh semiconductor chips 317 and 327 can be powered, and they can be arranged diagonally (see dashed lines ② and ④). This diagonal direction can be... Figure 3C The directions shown are opposite.

[0099] In this configuration, the third chip identification pad CP3 of the seventh semiconductor chips 317 and 327, the second chip identification pad CP2 of the sixth semiconductor chips 316 and 326, the first chip identification pad CP1 of the fifth semiconductor chips 315 and 325, the second chip identification pad CP2 of the fourth semiconductor chips 314 and 324, the third chip identification pad CP3 of the third semiconductor chips 313 and 323, the third chip identification pad CP3 of the second semiconductor chips 312 and 322, and the third chip identification pad CP3 of the first semiconductor chips 311 and 321 can be interconnected via inter-chip wiring. Additionally, the first chip identification pad CP1 of the fourth semiconductor chips 314 and 324, the first chip identification pad CP1 of the third semiconductor chips 313 and 323, the second chip identification pad CP2 of the second semiconductor chips 312 and 322, and the second chip identification pad CP2 of the first semiconductor chips 311 and 321 can be interconnected via another inter-chip wiring. Each of the first chip identification pads to the third chip identification pads CP1, CP2 and CP3 of the first semiconductor chips 311 and 321 can be connected to the base layer via stack-up wiring.

[0100] Reference Figure 3F The first chip identification pad CP1 and the second chip identification pad CP2 of the second semiconductor chips 312 and 322 can be powered, the first chip identification pad CP1 and the third chip identification pad CP3 of the third semiconductor chips 313 and 323 can be powered, and the second chip identification pad CP2 and the third chip identification pad CP3 of the fourth semiconductor chips 314 and 324 can be powered. In this case, the third chip identification pad CP3 of the second semiconductor chips 312 and 322, the second chip identification pad CP2 of the third semiconductor chips 313 and 323, and the first chip identification pad CP1 of the fourth semiconductor chips 314 and 324 (which is in a floating state) can be arranged in a diagonal direction (see dashed lines ① and ③). This diagonal direction can be... Figure 3C The diagonals shown are in the same direction.

[0101] The first chip identification pad CP1 of the fifth semiconductor chips 315 and 325 can be powered, the second chip identification pad CP2 of the sixth semiconductor chips 316 and 326 can be powered, and the third chip identification pad CP3 of the seventh semiconductor chips 317 and 327 can be powered, and they can be arranged diagonally (see dashed lines ② and ④). This diagonal direction can be... Figure 3C The directions shown are opposite.

[0102] In this configuration, the third chip identification pad CP3 of the seventh semiconductor chips 317 and 327, the second chip identification pad CP2 of the sixth semiconductor chips 316 and 326, the first chip identification pad CP1 of the fifth semiconductor chips 315 and 325, the second chip identification pad CP2 of the fourth semiconductor chips 314 and 324, the first chip identification pad CP1 of the third semiconductor chips 313 and 323, the first chip identification pad CP1 of the second semiconductor chips 312 and 322, and the first chip identification pad CP1 of the first semiconductor chips 311 and 321 can be interconnected via inter-chip wiring. Additionally, the third chip identification pad CP3 of the fourth semiconductor chips 314 and 324, the third chip identification pad CP3 of the third semiconductor chips 313 and 323, the second chip identification pad CP2 of the second semiconductor chips 312 and 322, and the second chip identification pad CP2 of the first semiconductor chips 311 and 321 can be interconnected via another inter-chip wiring. Each of the first chip identification pads to the third chip identification pads CP1, CP2 and CP3 of the first semiconductor chips 311 and 321 can be connected to the base layer via stack-up wiring.

[0103] Although not shown, other implementations are possible. For example, the power application state and wiring connection state of the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the first chip stack 310 can be compared with... Figure 3B and Figure 3C Implementation methods Figure 3D Implementation methods Figure 3E Implementation methods and Figure 3F The same as one of the embodiments. Furthermore, the power application state and wiring connection state of the first chip identification pads to the third chip identification pads CP1, CP2, and CP3 of the second chip stack 320 can be the same as... Figure 3B and Figure 3C Implementation methods Figure 3D Implementation methods Figure 3E Implementation methods and Figure 3F The same as one of the embodiments. The power application state and wiring connection state of the first chip identification pad to the third chip identification pad CP1, CP2 and CP3 of the first chip stack 310 may be different from the power application state and wiring connection state of the first chip identification pad to the third chip identification pad CP1, CP2 and CP3 of the second chip stack 320.

[0104] In the above embodiments, when the semiconductor package includes two chip stacks and each chip stack includes four or eight semiconductor chips, the arrangement of stack identification pads and chip identification pads, power application, and wiring connections have been described. However, this disclosure is not limited thereto, and the concept is extended and described as follows.

[0105] The semiconductor package according to this embodiment may include a base layer and a first chip stack and a second chip stack formed on the base layer.

[0106] Each of the first and second chip stacks may include a plurality of semiconductor chips. Chip pads may be disposed in a side edge region of each semiconductor chip in a first direction and may be arranged in a row in a second direction. The plurality of semiconductor chips may be offset in a direction away from one side in the first direction, thereby exposing the chip pads. Furthermore, in the first direction, one side of the lowermost semiconductor chip of the second chip stack may protrude in the opposite direction to the offset direction compared to one side of the uppermost semiconductor chip of the first chip stack.

[0107] The chip pads may include: a stack identification pad for identifying a first chip stack and a second chip stack, and a chip identification pad for identifying a semiconductor chip included in each of the first chip stack and the second chip stack. Each semiconductor chip may include one stack identification pad. The stack identification pads may be substantially aligned in a row along a first direction. When each of the first chip stack and the second chip stack includes 2 N-1 When there are multiple semiconductor chips, each semiconductor chip may include N-1 chip identification pads. When the N-1 chip identification pads are sequentially referred to as the first chip identification pad to the (N-1)th chip identification pad, starting from either side of each semiconductor chip in the second direction, the nth chip identification pad of the semiconductor chip can be substantially aligned in a row along the first direction, where n is a natural number greater than 1 and less than N-1. Based on the distance from the substrate, each of the first and second chip stacks includes 2... N-1 Each semiconductor chip can be referred to as the first semiconductor chip to the Kth semiconductor chip, where K is related to 2. N-1 same.

[0108] The stack identification pads of semiconductor chips included in one of the first and second chip stacks (e.g., the stack identification pads of the first chip stack) can be in a powered state, and the stack identification pads of semiconductor chips included in the other of the first and second chip stacks (e.g., the stack identification pads of the second chip stack) can be in a floating state. The stack identification pads of the first to Kth semiconductor chips of the first chip stack can be connected to each other through inter-chip wiring, and the stack identification pads of the first semiconductor chip of the first chip stack can be connected to the substrate through stack wiring.

[0109] In each of the first and second chip stacks, each of the first to Kth semiconductor chips can be distinguished by a combination of the power application state and floating state of its N-1 chip identification pads. That is, the combinations of the power application state and floating state of the chip identification pads of the first to Kth semiconductor chips can be different from each other.

[0110] All chip identification pads of the first semiconductor chip can be in a powered state, and all chip identification pads of the Kth semiconductor chip can be in a floating state. Some chip identification pads of the second to K-1th semiconductor chips can be powered, while the remaining chip identification pads can be in a floating state. In each of the first and second chip stacks, the chip identification pads of the first semiconductor chip can be connected to the substrate via stack wiring. Furthermore, in each of the first and second chip stacks, the powered chip identification pads between the first to K-1th semiconductor chips can be connected to each other via inter-chip wiring.

[0111] Here, the electrically powered chip identification pads in the second to (K-1)th semiconductor chips located between the first and Kth semiconductor chips can be arranged such that long inter-chip wiring does not skip semiconductor chips. To this end, the chip identification pads in the second to (K-1)th semiconductor chips that are electrically powered and / or in a floating state can be arranged diagonally in a direction intersecting the first and second directions. In this case, the inter-chip wiring connecting the nth chip identification pad of the kth semiconductor chip among the first to (K-1)th semiconductor chips can be connected to one of the n-1th, nth, and n+1th chip identification pads of the (k-1)th and / or (k+1)th semiconductor chips adjacent to the kth semiconductor chip, where k is a natural number greater than 1 and less than K-1. That is, by connecting the chip identification pads of adjacent semiconductor chips to each other in a diagonal direction or a first direction, the inter-chip wiring can be formed as short wiring that does not skip semiconductor chips.

[0112] Furthermore, the second to K-1 semiconductor chips can be grouped into one or more groups, and the number of chip identification pads with applied power in each semiconductor chip belonging to a specific group can decrease sequentially according to the distance between the specific group and the first semiconductor chip. Examples of grouping methods have been described in the above embodiments. For example, when each of the first and second chip stacks includes the first to fourth semiconductor chips, a group comprising the second and third semiconductor chips can exist, and each of the second and third semiconductor chips in this group can have one chip identification pad with applied power. Here, it has been described that the chip identification pads with applied power can be arranged diagonally. Alternatively, for example, when each of the first and second chip stacks includes the first to eighth semiconductor chips, a first group comprising the second to fourth semiconductor chips and a second group comprising the fifth to seventh semiconductor chips can exist, and each of the second to fourth semiconductor chips in the first group can have two chip identification pads with applied power, and each of the fifth to seventh semiconductor chips in the second group can have one chip identification pad with applied power. Here, it has been described that the floating chip identification pads in the second to fourth semiconductor chips can be arranged in a diagonal direction, and the electrically applied chip identification pads in the fifth to seventh semiconductor chips can be arranged in a diagonal direction.

[0113] According to the above embodiments of this disclosure, a semiconductor package can be provided that can reduce failures and improve operating characteristics while meeting high performance / high capacity requirements.

[0114] Figure 4 A block diagram of an electronic system is illustrated, including a memory card 7800 employing at least one of a semiconductor package according to an embodiment. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of a semiconductor package according to the described embodiment.

[0115] The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that stored data or stored data can be read in response to a read / write request from the host 7830.

[0116] Figure 5 A block diagram illustrating an electronic system 8710 is shown. The electronic system 8710 includes at least one of a semiconductor package according to the described embodiments. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be interconnected via a bus 8715 providing a data movement path.

[0117] In embodiments, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include one or more semiconductor packages according to embodiments of this disclosure. Input / output device 8712 may include at least one selected from a keypad, keyboard, display device, touchscreen, etc. Memory 8713 is a means for storing data. Memory 8713 may store data and / or commands to be executed by controller 8711.

[0118] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory can be installed in information processing systems such as mobile terminals or desktop computers. Flash memory can form a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0119] The electronic system 8710 may also include an interface 8714 configured to transmit data to and receive data from a communication network. The interface 8714 may be of wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0120] The electronic system 8710 can be implemented as a logic system, mobile system, personal computer, or industrial computer performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), portable computer, tablet computer, mobile phone, smartphone, wireless phone, laptop computer, memory card, digital music system, and information sending / receiving system.

[0121] If electronic system 8710 represents equipment capable of performing wireless communication, then electronic system 8710 can be used in communication systems using the following technologies: CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0122] Although various embodiments have been described for exemplary purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the teachings as defined by the appended claims.

[0123] Cross-reference to related applications

[0124] This application claims priority to Korean Patent Application No. 10-2020-0176359, filed on December 16, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package comprising: grassroots level; as well as A first chip stack and a second chip stack are sequentially stacked on the substrate. Each of the first chip stack and the second chip stack includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip. The first semiconductor chip to the fourth semiconductor chip are offset from each other to expose chip pads at one side edge of each of the first semiconductor chip to the fourth semiconductor chip. The chip pads include stack identification pads for identifying the first chip stack and the second chip stack, and first chip identification pads and second chip identification pads for identifying the first semiconductor chip to the fourth semiconductor chip in each of the first chip stack and the second chip stack. In this process, power is applied to the stack identification pads of the first semiconductor chip to the fourth semiconductor chip in one of the first and second chip stacks. In the first chip stack, the power is applied to one of the first chip identification pads and the second chip identification pad of the first semiconductor chip, one of the first chip identification pads and the second chip identification pad of the second semiconductor chip, and the other of the first chip identification pads and the second chip identification pad of the third semiconductor chip. In the second chip stack, the power is applied to one of the first chip identification pads and the second chip identification pads of the first semiconductor chip, one of the first chip identification pads and the second chip identification pads of the second semiconductor chip, and the other of the first chip identification pads and the second chip identification pads of the third semiconductor chip. The semiconductor package further includes a plurality of inter-chip wirings, which electrically connect the stack-up identification pads, the first chip identification pads, and the second chip identification pads to which the power is applied. The plurality of inter-chip wirings provide pad-to-pad electrical connections, each of which is established between pads disposed on two adjacent semiconductor chips. Among the stack-up identification pads, the first chip identification pads, and the second chip identification pads, the pads other than the pads to which the power is applied are in a floating state.

2. The semiconductor package according to claim 1, further comprising: The stack-up wiring connects the stack-up identification pads of the first semiconductor chip, to which the power is applied, to the base layer.

3. The semiconductor package according to claim 1, wherein, The power is applied to the stack identification pads of the first semiconductor chip to the fourth semiconductor chip of the first chip stack.

4. The semiconductor package according to claim 1, wherein, In at least one of the first chip stack and the second chip stack, the power is applied to the first chip identification pad of the second semiconductor chip and the second chip identification pad of the third semiconductor chip. The semiconductor package further includes: The stacked wiring connects the first chip identification pad and the second chip identification pad of the first semiconductor chip to the substrate. The inter-chip wiring connects the second chip identification pad of the third semiconductor chip, the first chip identification pad of the second semiconductor chip, and the first chip identification pad of the first semiconductor chip.

5. The semiconductor package according to claim 1, wherein, In at least one of the first chip stack and the second chip stack, the power is applied to the second chip identification pad of the second semiconductor chip and the first chip identification pad of the third semiconductor chip. The semiconductor package further includes: The stacked wiring connects the first chip identification pad and the second chip identification pad of the first semiconductor chip to the substrate. The inter-chip wiring connects the first chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip.

6. The semiconductor package according to claim 1, wherein, The stack identification pads, the first chip identification pad, and the second chip identification pad, which are in the floating state, are not connected to wiring.

7. The semiconductor package according to claim 1, wherein, The stack-up identification pads are aligned with each other along the offset direction. The first chip identification pads are aligned with each other along the offset direction, and The second chip identification pads are aligned with each other along the offset direction.

8. The semiconductor package according to claim 1, wherein, The surface of the first semiconductor chip of the second chip stack adjacent to the chip pad protrudes in a direction opposite to the offset direction than the surface of the fourth semiconductor chip of the first chip stack adjacent to the chip pad.

9. A semiconductor package comprising: grassroots level; as well as A first chip stack and a second chip stack are sequentially stacked on the substrate. Each of the first and second chip stacks includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a fourth semiconductor chip, a fifth semiconductor chip, a sixth semiconductor chip, a seventh semiconductor chip, and an eighth semiconductor chip. The first to eighth semiconductor chips are offset from each other to expose chip pads at one side edge of each of the first to eighth semiconductor chips. The chip pads include stack identification pads for identifying the first and second chip stacks, and first to third chip identification pads for identifying the first to eighth semiconductor chips in each of the first and second chip stacks. In this process, electricity is applied to the stack identification pads of the first semiconductor chip to the eighth semiconductor chip in one of the first and second chip stacks. In the first chip stack, the power is applied to the first to third chip identification pads of the first semiconductor chip, two chip identification pads selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one chip identification pad selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, wherein the two selected chip identification pads of the second semiconductor chip, the two selected chip identification pads of the third semiconductor chip, and the two selected chip identification pads of the fourth semiconductor chip are different from each other, and the one selected chip identification pad of the fifth semiconductor chip, the one selected chip identification pad of the sixth semiconductor chip, and the one selected chip identification pad of the seventh semiconductor chip are different from each other. In the second chip stack, the power is applied to the first to third chip identification pads of the first semiconductor chip, two chip identification pads selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one chip identification pad selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, wherein the two selected chip identification pads of the second semiconductor chip, the two selected chip identification pads of the third semiconductor chip, and the two selected chip identification pads of the fourth semiconductor chip are different from each other, and the one selected chip identification pad of the fifth semiconductor chip, the one selected chip identification pad of the sixth semiconductor chip, and the one selected chip identification pad of the seventh semiconductor chip are different from each other. The semiconductor package further includes multiple inter-chip wirings, which electrically connect the stack-up identification pads, the first chip identification pads, the second chip identification pads, and the third chip identification pads to which the power is applied. The plurality of inter-chip wirings provide pad-to-pad electrical connections, each of which is established between pads disposed on two adjacent semiconductor chips. Among the stack-up identification pads, the first chip identification pads, the second chip identification pads, and the third chip identification pads, all pads except the ones to which the power is applied are in a floating state.

10. The semiconductor package of claim 9, further comprising: The stack-up wiring connects the stack-up identification pads of the first semiconductor chip, to which the power is applied, to the base layer.

11. The semiconductor package according to claim 9, wherein, The power is applied to the stack identification pads of the first semiconductor chip to the eighth semiconductor chip of the first chip stack.

12. The semiconductor package according to claim 9, wherein, The power is applied to the first and second chip identification pads of the second semiconductor chip, the first and third chip identification pads of the third semiconductor chip, the second and third chip identification pads of the fourth semiconductor chip, the third chip identification pad of the fifth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, and the first chip identification pad of the seventh semiconductor chip in at least one of the first and second chip stacks. The semiconductor package further includes: The stacked wiring connects the first chip identification pad to the third chip identification pad of the first semiconductor chip to the base layer. The inter-chip wiring connects the first chip identification pad of the seventh semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the third chip identification pad of the fifth semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the first chip identification pad of the third semiconductor chip, the first chip identification pad of the second semiconductor chip, and the first chip identification pad of the first semiconductor chip, and also connects the third chip identification pad of the fourth semiconductor chip, the third chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip.

13. The semiconductor package according to claim 9, wherein, The power is applied to the second chip identification pad and the third chip identification pad of the second semiconductor chip, the first chip identification pad and the third chip identification pad of the third semiconductor chip, the first chip identification pad and the second chip identification pad of the fourth semiconductor chip, the third chip identification pad of the fifth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, and the first chip identification pad of the seventh semiconductor chip in at least one of the first chip stack and the second chip stack. The semiconductor package further includes: The stacked wiring connects the first chip identification pad to the third chip identification pad of the first semiconductor chip to the base layer. The inter-chip wiring connects the first chip identification pad of the seventh semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the third chip identification pad of the fifth semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the third chip identification pad of the third semiconductor chip, the third chip identification pad of the second semiconductor chip, and the third chip identification pad of the first semiconductor chip, and also connects the first chip identification pad of the fourth semiconductor chip, the first chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip.

14. The semiconductor package according to claim 9, wherein, The power is applied to the second chip identification pad and the third chip identification pad of the second semiconductor chip, the first chip identification pad and the third chip identification pad of the third semiconductor chip, the first chip identification pad and the second chip identification pad of the fourth semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, and the third chip identification pad of the seventh semiconductor chip in at least one of the first chip stack and the second chip stack. The semiconductor package further includes: The stacked wiring connects the first chip identification pad to the third chip identification pad of the first semiconductor chip to the base layer. The inter-chip wiring connects the third chip identification pad of the seventh semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the third chip identification pad of the third semiconductor chip, the third chip identification pad of the second semiconductor chip, and the third chip identification pad of the first semiconductor chip, and also connects the first chip identification pad of the fourth semiconductor chip, the first chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip.

15. The semiconductor package according to claim 9, wherein, The power is applied to the first and second chip identification pads of the second semiconductor chip, the first and third chip identification pads of the third semiconductor chip, the second and third chip identification pads of the fourth semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, and the third chip identification pad of the seventh semiconductor chip in at least one of the first and second chip stacks. The semiconductor package further includes: The stacked wiring connects the first chip identification pad to the third chip identification pad of the first semiconductor chip to the base layer. The inter-chip wiring connects the third chip identification pad of the seventh semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the first chip identification pad of the third semiconductor chip, the first chip identification pad of the second semiconductor chip, and the first chip identification pad of the first semiconductor chip, and also connects the third chip identification pad of the fourth semiconductor chip, the third chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip.

16. The semiconductor package according to claim 9, wherein, The stack identification pads, the first chip identification pads to the third chip identification pads, which are in the floating state, are not connected to wiring.

17. The semiconductor package according to claim 9, wherein, The stack-up identification pads are aligned with each other along the offset direction. The first chip identification pads are aligned with each other along the offset direction. The second chip identification pads are aligned with each other along the offset direction, and The third chip identification pads are aligned with each other along the offset direction.

18. The semiconductor package according to claim 9, wherein, The surface of the first semiconductor chip of the second chip stack adjacent to the chip pad protrudes in a direction opposite to the offset direction than the surface of the eighth semiconductor chip of the first chip stack adjacent to the chip pad.

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