3D memory device and method of manufacturing the same

Abstract

Disclosed are a 3D memory device and a manufacturing method thereof, the method comprising: forming an insulating stack structure on a substrate, the insulating stack structure comprising a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked; forming a plurality of channel columns through the insulating stack structure; forming a plurality of gate line slits through the insulating stack structure; removing a plurality of sacrificial layers via the gate line slits to form cavities; sequentially forming a high-K dielectric layer, a titanium nitride layer and a gate conductor in the cavities; and forming a first insulating layer and a conductive channel in the gate line slits, wherein the high-K dielectric layer and the titanium nitride layer are located between adjacent interlayer insulating layers in a direction perpendicular to the surface of the substrate. The 3D memory device and the manufacturing method thereof of the present application reduce the leakage problem of the device by etching back the high-K dielectric layer, thereby improving the yield and reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a 3D memory device and its manufacturing method. Background Technology

[0002] The increase in storage density of memory devices is closely related to advancements in semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes shrinks, the storage density of memory devices increases. To further improve storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. 3D memory devices consist of multiple memory cells stacked along a vertical direction, which can multiply the integration density on a unit area of ​​wafer and reduce costs.

[0003] In NAND-structured 3D memory devices, a stacked structure is used to provide the gate conductors for the select transistor and the storage transistor, and a single-channel formation structure is used to form a string of memory cells with storage function. During the manufacturing process of 3D memory devices, after the structure in the gate line gaps is formed, wet cleaning of the wafer or semiconductor structure can cause the cleaning agent to etch along the high-k dielectric layer in the gate line gaps, resulting in leakage currents (LKG) between adjacent conductors in the subsequently deposited polysilicon layer. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a 3D memory device and a method for manufacturing the same, which reduces leakage current by etching back the high-k dielectric layer, thereby improving device yield and reliability.

[0005] According to one aspect of the present invention, a method for manufacturing a 3D memory device is provided, comprising: forming an insulating stack structure on a substrate, the insulating stack structure including a plurality of alternately stacked sacrificial layers and a plurality of interlayer insulating layers; forming a plurality of channel pillars penetrating the insulating stack structure; forming a plurality of gate wire slots penetrating the insulating stack structure; removing the plurality of sacrificial layers through the gate wire slots to form a cavity; sequentially forming a high-k dielectric layer, a titanium nitride layer, and a gate conductor in the cavity; and forming a first insulating layer and a conductive channel in the gate wire slots, wherein the high-k dielectric layer and the titanium nitride layer are located between adjacent interlayer insulating layers in a direction perpendicular to the substrate surface.

[0006] Optionally, the step of sequentially forming a high-K dielectric layer, a titanium nitride layer, and a gate conductor in the cavity includes: depositing a high-K dielectric material in the gate line gaps and the cavity, and etching back the high-K dielectric material to form a high-K dielectric layer covering the gate line gaps and the surface of the cavity; depositing a TiN material in the gate line gaps and the cavity, and etching back the TiN material to form a titanium nitride layer covering the gate line gaps and the surface of the cavity; and depositing a metal material in the gate line gaps and the cavity, and etching back the metal material to form a gate conductor filling the cavity.

[0007] Optionally, after the step of etching back the metal material to form a gate conductor filling the cavity, the method further includes: performing a second etching back on the titanium nitride layer to remove the titanium nitride layer exposed in the gate line gap; and performing a second etching back on the high-K dielectric layer to remove the high-K dielectric layer exposed in the gate line gap.

[0008] Optionally, the high-K dielectric layer is made of aluminum oxide.

[0009] Optionally, the high-K dielectric layer is etched back a second time using phosphoric acid at 160°C.

[0010] Optionally, between the steps of forming an insulating stack structure on the substrate and forming a plurality of channel pillars through the insulating stack structure, a protective layer is further formed on the surface of the insulating stack structure.

[0011] Optionally, after the step of forming the first insulating layer and conductive channel in the gate line gap, the method further includes: removing the protective layer and cleaning the semiconductor structure; forming a polysilicon layer and a stacked structure on the surface of the insulating stacked structure, the stacked structure comprising an oxide-nitride compound.

[0012] According to another aspect of the present invention, a 3D memory device is provided, comprising: a substrate; a gate stack structure located above the substrate, the gate stack structure comprising a plurality of alternately stacked gate conductors and a plurality of interlayer insulating layers; a plurality of channel pillars extending through the gate stack structure, wherein a high-k dielectric layer and a titanium nitride layer are further comprising between the gate conductors and the interlayer insulating layers, and the high-k dielectric layer and the titanium nitride layer are located only between adjacent interlayer insulating layers in a direction perpendicular to the substrate surface.

[0013] Optionally, the high-K dielectric layer is made of aluminum oxide.

[0014] Optionally, it further includes: a gate line gap, the gate line gap penetrating the gate stack structure and dividing the plurality of gate conductors into a plurality of gate lines.

[0015] Optionally, it further includes: a first insulating layer and a conductive channel located in the gate line gap, wherein the first insulating layer isolates the conductive channel and the gate stack structure.

[0016] The 3D memory device manufacturing method provided by this invention uses wet etching to etch back the high-k dielectric layer in the gate line gaps, ensuring that there is no high-k dielectric layer on the sidewalls and bottom of the gate line gaps. This avoids the device leakage problem caused by the cleaning agent etching back along the high-k dielectric layer during the subsequent wet cleaning step, thereby improving the device yield and reliability. Furthermore, using wet etching to etch back the high-k dielectric layer is less expensive than dry etching. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1a and Figure 1b A partial view of a 3D storage device according to the prior art is shown;

[0019] Figure 2a and 2b The equivalent circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively;

[0020] Figure 3 A perspective view of a 3D storage device according to an embodiment of the present invention is shown;

[0021] Figures 4a to 4g Cross-sectional views of various stages of a 3D storage device manufacturing method according to an embodiment of the present invention are shown. Detailed Implementation

[0022] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0023] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0024] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0025] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0026] Figure 1a and Figure 1b A partial view of a 3D storage device according to the prior art is shown. Figure 1a As shown, an insulating stacked structure is formed on the surface of substrate 101, a channel pillar 110 is formed penetrating the insulating stacked structure, and a gate line slot is formed penetrating the insulating stacked structure. After removing the sacrificial layer in the stacked structure through the gate line slot to form a cavity, a high-K dielectric layer 103, a titanium nitride layer 104, a gate conductor layer 109, a first insulating layer 105, and a conductive channel 143 are sequentially formed on the surface of the cavity through the gate line slot. The material of the high-K dielectric layer 103 is, for example, AlO. The gate conductor layer 109 is located between the interlayer insulating layers, the high-K dielectric layer 103 is located on the entire sidewall of the cavity, the titanium nitride layer 104 is located between the gate conductor layer 109 and the high-K dielectric layer 103, and the first insulating layer 105 isolates the conductive channel 143 from the gate conductor layer 109.

[0027] Furthermore, such as Figure 1b As shown, a semiconductor structure is wet-cleaned, and then a polysilicon layer 107 and a second insulating layer 108 are deposited on the surface of the semiconductor structure. However, during the wet cleaning step, the cleaning agent etches back along the high-k dielectric layer 103, causing the polysilicon layer 107 deposited in subsequent steps to also be deposited along the etch-back gaps of the high-k dielectric layer 103, resulting in leakage problems between adjacent conductors.

[0028] Furthermore, dry etching is costly when removing the high-K dielectric layer 103 at the bottom of the gate gap.

[0029] The inventors of this application have noticed the aforementioned problems affecting the yield and reliability of 3D memory devices, and therefore propose further improved 3D memory devices and their manufacturing methods.

[0030] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0031] This invention can be presented in various forms, some of which will be described below.

[0032] Figure 2a and 2b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively. In this embodiment, the storage cell string shown includes four storage cells. It is understood that the invention is not limited thereto, and the number of storage cells in the storage cell string can be any number, for example, 32 or 64.

[0033] like Figure 2a As shown, the first end of the memory cell string 100 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first and second ends, including: a first selection transistor Q1, storage transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string select line SSL, and the gate of the second selection transistor Q2 is connected to the ground select line GSL. The gates of the storage transistors M1 to M4 are respectively connected to the corresponding word lines WL1 to WL4.

[0034] like Figure 2b As shown, the first selection transistor Q1 and the second selection transistor Q2 of the memory cell string 100 each include gate conductors 122 and 123, and the memory transistors M1 to M4 each include a gate conductor 121. The gate conductors 121, 122, and 123 are arranged in the same stacking order as the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a barrier dielectric layer 114 are sandwiched between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 to M4. At both ends of the channel pillar 110, the gate conductors 122 and 123 are sandwiched between the gate conductors 122 and 123 and the channel layer 111, thereby forming the first selection transistor Q1 and the second selection transistor Q2.

[0035] In this embodiment, the channel layer 111 is composed, for example, of doped polysilicon; the tunneling dielectric layer 112 and the barrier dielectric layer 114 are each composed of oxides, such as silicon oxide; the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles; and the gate conductors 121, 122, and 123 are composed of metals, such as tungsten. The channel layer 111 provides the channel region for the select transistor and the storage transistor, and the doping type of the channel layer 111 is the same as the type of the select transistor and the storage transistor. For example, for an N-type select transistor and a storage transistor, the channel layer 111 can be N-type doped polysilicon.

[0036] In this embodiment, the core of the channel post 110 is a channel layer 111, and the tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 form a stacked structure surrounding the sidewalls of the core. In an alternative embodiment, the core of the channel post 110 is an additional insulating layer, and the channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 form a stacked structure surrounding the core.

[0037] In this embodiment, the first selection transistor Q1, the second selection transistor Q2, and the storage transistors M1 to M4 use a common channel layer 111 and a barrier dielectric layer 114. In the channel pillar 110, the channel layer 111 provides the source / drain regions and channel layer for the plurality of transistors. In an alternative embodiment, the epitaxial layers and barrier dielectric layers of the first selection transistor Q1 and the second selection transistor Q2, as well as the epitaxial layers and barrier dielectric layers of the storage transistors M1 to M4, can be formed in separate steps.

[0038] During the write operation, the memory cell string 100 utilizes FN tunneling efficiency to write data to selected memory transistors among memory transistors M1 to M4. Taking memory transistor M2 as an example, while the source line SL is grounded, the ground select line GSL is biased to approximately zero volts, causing the select transistor Q2 corresponding to the ground select line GSL to turn off, and the string select line SSL is biased to a high voltage VDD, causing the select transistor Q1 corresponding to the string select line SSL to turn on. Further, the bit line BIT2 is grounded, the word line WL2 is biased to the programming voltage VPG, for example, around 20V, and the remaining word lines are biased to a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 through the tunneling dielectric layer 112, thereby converting data into charge and storing it in the charge storage layer 113 of the memory transistor M2.

[0039] During the read operation, the memory cell string 100 determines the amount of charge in the charge storage layer based on the conduction state of selected memory transistors M1 to M4, thereby obtaining the data represented by that charge amount. Taking memory transistor M2 as an example, word line WL2 is biased at the read voltage VRD, while the other word lines are biased at a high voltage VPS2. The conduction state of memory transistor M2 is related to its threshold voltage, i.e., related to the amount of charge in the charge storage layer, thus the data value can be determined based on the conduction state of memory transistor M2. Memory transistors M1, M3, and M4 are always in the conduction state; therefore, the conduction state of memory cell string 100 depends on the conduction state of memory transistor M2. The control circuit determines the conduction state of memory transistor M2 based on the electrical signals detected on bit line BL and source line SL, thereby obtaining the data stored in memory transistor M2.

[0040] Figure 3A perspective view of the 3D storage device is shown. For clarity, [the view is shown in the original text]. Figure 3 The individual insulating layers in the 3D storage device are not shown.

[0041] The 3D storage device 200 shown in this embodiment includes 16 4x4 storage cell strings 100, each storage cell string 100 including 4 storage cells, thereby forming a 4x4x4 storage cell array with a total of 64 storage cells. It is understood that the present invention is not limited thereto; the 3D storage device may include any number of storage cell strings, for example, 1024, and the number of storage cells in each storage cell string may be any number, for example, 32 or 64.

[0042] In the 3D memory device 200, each memory cell string includes its own channel pillar 110 and common gate conductors 121, 122, and 123. The gate conductors 121, 122, and 123 are arranged in the same stacking order as the transistors in the memory cell string 100. Adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

[0043] The internal structure of the channel column 110 is as follows Figure 2b As shown, no further details will be provided here. The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The first ends of multiple channel pillars 110 in the same column are connected to the same bit line (i.e., one of bit lines BL1 to BL4), and the second ends are connected to the substrate 101. The second ends form a common source connection through the substrate 100.

[0044] The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit 161. The gate lines of multiple channel pillars 110 in the same row are connected to the same series select line (i.e., one of the series select lines SSL1 to SSL4).

[0045] The gate conductors 121 of storage transistors M1 and M4 are respectively connected to the corresponding word lines. If the gate conductors 121 of storage transistors M1 and M4 are divided into different gate lines by gate line gaps 171, the gate lines on the same layer reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same word line (i.e., one of word lines WL1 to WL4) through conductive channels 133.

[0046] The gate conductors of the second selection transistor Q2 are connected as one. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line gap 171, the gate lines reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same ground selection line GSL through the conductive channel 133.

[0047] The internal structure of the dummy channel pillar 140 may be the same as or different from that of the channel pillar 110, and it passes through at least a portion of the gate conductor in the gate stack structure. In the final 3D memory device, the dummy channel pillar 140 is not connected to the bit line, thus providing only mechanical support and not being used to form select transistors and storage transistors. Therefore, the dummy channel pillar 131 does not form a valid memory cell.

[0048] Figures 4a to 4g Cross-sectional views of various stages of a 3D storage device manufacturing method according to an embodiment of the present invention are shown. Figures 4a to 4g For example, it is shown below. Figure 3 Cross-sectional view along the dashed line AA.

[0049] This method begins with a semiconductor structure on which an insulating stacked structure has already been formed on a semiconductor substrate 101, such as... Figure 4a As shown.

[0050] The semiconductor structure includes a semiconductor substrate 101 and an insulating stack structure thereon. The insulating stack structure includes a plurality of alternately stacked interlayer insulating layers 102 and a plurality of sacrificial layers 142. In this embodiment, the semiconductor substrate 101 is, for example, a single-crystal silicon substrate, the interlayer insulating layers 102 are, for example, composed of silicon oxide, and the sacrificial layers 142 are, for example, composed of silicon nitride.

[0051] To form a conductive path from the gate conductor to the word line, multiple sacrificial layers 142 are patterned, for example, in a stepped shape. Figure 4a Not shown in the image, please refer to the following: Figure 3 That is, the edge portion of each sacrificial layer 142 is exposed relative to the sacrificial layer above to provide an electrical connection region. After the patterning steps of the plurality of sacrificial layers 142, a protective layer 141 is used to cover the insulating stack structure, and channel pillars 110 are formed throughout the insulating stack structure. As described below, the sacrificial layers 142 are replaced with gate conductors, which are further connected to word lines.

[0052] To facilitate programming operations on the memory cells in the 3D memory device, a plurality of well regions and CMOS circuitry (not shown) for driving selection transistors and storage transistors are formed in the semiconductor substrate 101.

[0053] Furthermore, in forming the gate wire gaps 106 that penetrate the insulating multilayer structure, and removing the sacrificial layer 142 through the gate wire gaps to form cavities, such as... Figure 4a and Figure 4b As shown.

[0054] In this step, when forming the gate line gap 106, anisotropic etching can be used, such as dry etching, like ion milling, plasma etching, reactive ion etching, or laser ablation. For example, by controlling the etching time, the etching can be stopped near the surface of the semiconductor substrate 101.

[0055] In this embodiment, the gate line gap 106 divides the gate conductor into multiple gate lines. For this purpose, the gate line gap 106 extends through the insulating laminate structure.

[0056] During cavity formation, the gate gap 106 is used as an etchant channel, and isotropic etching is employed to remove the sacrificial layer 142 in the insulating stack structure, thereby forming the cavity. Isotropic etching can be performed using selective wet etching or vapor phase etching. In wet etching, an etchant solution is used as the etchant, wherein the semiconductor structure is immersed in the etchant solution. In vapor phase etching, an etching gas is used as the etchant, wherein the semiconductor structure is exposed to the etching gas.

[0057] In the case where the interlayer insulating layer 102 and the sacrificial layer 142 in the insulating stack structure are composed of silicon oxide and silicon nitride, respectively, phosphoric acid solution can be used as the etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 can be used in vapor phase etching. During the etching step, the etchant fills the gate line gaps 106. The ends of the sacrificial layer 142 in the insulating stack structure are exposed in the openings of the gate line gaps 106, thus the sacrificial layer 142 comes into contact with the etchant. The etchant gradually etches the sacrificial layer 142 into the interior of the insulating stack structure from the openings of the gate line gaps 106. Due to the selectivity of the etchant, this etching removes the sacrificial layer 142 relative to the interlayer insulating layer 102 in the insulating stack structure.

[0058] Preferably, after the above-described wet etching step, an additional etching step can be used to remove the etching products (e.g., silicon oxide) attached to the interlayer insulating layer 102, so that the surface of the interlayer insulating layer 102 exposed in the cavity is flat.

[0059] Furthermore, a high-k dielectric layer 103 is formed on the surface of the cavity and the gate wire slots via the gate wire slots 106, such as Figure 4c As shown.

[0060] In this step, dielectric material is deposited in the gate gaps 106 and cavities using deposition processes such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). The dielectric material is then etched back to retain only the dielectric material on the surfaces of the gate gaps 106 and cavities, thereby forming a high-k dielectric layer 103. The material of the high-k dielectric layer 103 is aluminum oxide (AlO).

[0061] Preferably, prior to the etch-back step on the dielectric material, the dielectric material on the semiconductor surface is chemically mechanically polished to thin or remove the dielectric material from the surface of the semiconductor structure. The final semiconductor structure may or may not have a high-k dielectric layer 103 on its surface.

[0062] Furthermore, a titanium nitride layer 104 is formed on the surface of the cavity and the gate line slots via the gate line slots 106, such as Figure 4d As shown.

[0063] In this step, TiN material is deposited in the gate gap 106 and cavity through deposition processes such as atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the TiN material is etched back to retain only one layer of TiN material on the surface of the high-K dielectric layer 103, thereby forming the titanium nitride layer 104.

[0064] Preferably, prior to the etch-back step on the TiN material, the TiN material on the semiconductor surface is chemically mechanically polished to thin or remove the TiN material from the surface of the semiconductor structure. The final semiconductor structure may or may not have a titanium nitride layer 104 on its surface.

[0065] Further, metal material is deposited in the cavity via the gate gap 106, and the metal material and the titanium nitride layer 104 are etched back, as shown. Figure 4e As shown.

[0066] When forming the gate conductor 109, the gate line gap 106 is used as a deposition channel, and atomic layer deposition (ALD) is used to fill the gate line gap 106 and the cavity with a metal layer.

[0067] In this embodiment, the metal layer is, for example, composed of tungsten. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride (WF6), and the reducing gas used is, for example, silane (SiH4) or diborane (B2H6). In the atomic layer deposition step, the tungsten material is obtained by the chemisorption of the reaction product of tungsten hexafluoride (WF6) and silane (SiH4), thus achieving the deposition process.

[0068] Furthermore, the metal material and titanium nitride layer 104 are etched back to remove the metal material and titanium nitride layer 104 in the gate line gaps, leaving only the metal material and titanium nitride layer 104 in the cavity.

[0069] Furthermore, the high-k dielectric layer 103 is etched back, such as... Figure 4f As shown.

[0070] In this step, the high-K dielectric layer 103 exposed on the surface of the semiconductor structure and in the gate line gaps is removed by a wet etching process, leaving only the high-K dielectric layer 103 between the titanium nitride layer 104 and the gate conductor layer 109.

[0071] The high-k dielectric layer 103 is removed by wet etching, for example, using phosphoric acid (H3PO4) at 160°C. The semiconductor structure is immersed in the solution, and the etching time is controlled so that the etching stops after the high-k dielectric layer 103 is exposed in the gate line gaps 106. Further, the high-k dielectric layer 103 in the semiconductor structure is treated with rapid thermal annealing (RTA), in which the heating rate is 60 A / min and the temperature is 1100°C.

[0072] Furthermore, a first insulating layer 105 and a conductive channel 106 are formed in the gaps of the grid lines, such as... Figure 4g As shown.

[0073] In this step, insulating material is deposited in the gate gap 106 by deposition processes such as atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition (CVD), and then through-holes are formed through the insulating material, and conductive material is deposited in the through-holes to form conductive channels 143.

[0074] In this embodiment, the first insulating layer 105 isolates the conductive channel and the gate conductor layer 109.

[0075] Following this step, the process also includes removing the protective layer 141 from the surface of the semiconductor structure, cleaning the semiconductor structure, and forming a polysilicon layer 144 and a stacked structure 145 on the surface of the semiconductor structure, wherein the stacked structure 145 is, for example, an oxide-nitride stacked structure.

[0076] In this embodiment, since the high-K dielectric layer 103 is etched back, after the protective layer 141 on the surface of the semiconductor structure is removed, there is no longer a high-K dielectric layer 103 between the first insulating layers 105 of the gate stack structure, nor are there any other materials. Therefore, in the subsequent cleaning steps, there will be no phenomenon of cleaning and etching back along the high-K dielectric layer 103, thereby reducing the leakage problem between adjacent conductors of the device.

[0077] The 3D memory device manufacturing method provided by this invention uses wet etching to etch back the high-k dielectric layer in the gate line gaps, ensuring that there is no high-k dielectric layer on the sidewalls and bottom of the gate line gaps. This avoids the device leakage problem caused by the cleaning agent etching back along the high-k dielectric layer during the subsequent wet cleaning step, thereby improving the device yield and reliability. Furthermore, using wet etching to etch back the high-k dielectric layer is less expensive than dry etching.

[0078] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a 3D storage device, comprising: An insulating stack structure is formed on a substrate, the insulating stack structure comprising a plurality of sacrificial layers and a plurality of interlayer insulating layers stacked alternately; Multiple channel pillars are formed that penetrate the insulating laminate structure; Multiple gate wire gaps are formed that penetrate the insulating laminate structure; Multiple sacrificial layers are removed through the grid line gaps to form a cavity; A high-k dielectric layer, a titanium nitride layer, and a gate conductor are sequentially formed in the cavity; A first insulating layer and a conductive channel are formed in the gaps of the grid lines. The high-K dielectric layer and the titanium nitride layer are located between adjacent interlayer insulating layers in a direction perpendicular to the substrate surface, and the end of the high-K dielectric layer near the gate line gap is recessed relative to the interlayer insulating layer toward the side away from the gate line gap.

2. The manufacturing method according to claim 1, characterized by, The steps of sequentially forming a high-k dielectric layer, a titanium nitride layer, and a gate conductor in the cavity include: A high-K dielectric material is deposited in the gate line gaps and the cavity, and the high-K dielectric material is etched back to form a high-K dielectric layer covering the surface of the gate line gaps and the cavity; TiN material is deposited in the gate gaps and the cavity, and the TiN material is etched back to form a titanium nitride layer covering the surface of the gate gaps and the cavity; Metal material is deposited in the gate line gaps and the cavity, and the metal material is etched back to form a gate conductor that fills the cavity.

3. The production method according to claim 2, characterized by After the step of etching back the metal material to form the gate conductor filling the cavity, the method further includes: The titanium nitride layer is etched back a second time to remove the titanium nitride layer exposed in the gate line gaps; A second etch-back process is performed on the high-K dielectric layer to remove the high-K dielectric layer exposed in the gate line gaps.

4. The production method according to claim 3, characterized by The high-K dielectric layer is made of aluminum oxide.

5. The manufacturing method according to claim 3 or 4, characterized in that, The high-k dielectric layer was etched back a second time using phosphoric acid at 160°C.

6. The production method according to claim 1, characterized by Between the steps of forming an insulating stack structure on the substrate and forming a plurality of channel pillars through the insulating stack structure, the method further includes: A protective layer is formed on the surface of the insulating laminate structure.

7. The production method according to claim 6, wherein After the step of forming the first insulating layer and conductive channel in the grid wire gap, the method further includes: Remove the protective layer and clean the semiconductor structure; A polycrystalline silicon layer and a stacked structure are formed on the surface of the insulating stacked structure, the stacked structure comprising an oxide-nitride.

8. A 3D storage device, comprising: Substrate; A gate stack structure located above the substrate, the gate stack structure comprising alternating stacked gate conductors and multiple interlayer insulating layers; Multiple channel posts, the channel posts penetrating the grid stack structure, Gate line gaps, which penetrate the gate stack structure, divide the plurality of gate conductors into a plurality of gate lines; The gate conductor and the interlayer insulating layer are further divided into a high-K dielectric layer and a titanium nitride layer. The end of the high-K dielectric layer near the gate line gap is recessed relative to the interlayer insulating layer toward the side away from the gate line gap. 9.The 3D memory device of claim 8, wherein, The high-K dielectric layer is made of aluminum oxide. 10.The 3D memory device of claim 8, wherein, The end of the titanium nitride layer near the gate gap is recessed relative to the interlayer insulating layer toward the side away from the gate gap. 11.The 3D memory device of claim 10, wherein, Also includes: A first insulating layer and a conductive channel are located in the gap of the gate line, wherein the first insulating layer isolates the conductive channel and the gate stack structure. 12.The 3D memory device of claim 11, wherein, The first insulating layer includes a plurality of protrusions, which are disposed corresponding to the gate conductor and in contact with the high-k dielectric layer and the titanium nitride layer.

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