Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a substrate and a plurality of discrete fins located on the substrate, an isolation layer formed on the substrate where the fins are exposed, the isolation layer covering a portion of the sidewalls of the fins, a gate structure formed on the isolation layer spanning the fins along a direction perpendicular to the extension direction of the fins, the substrate including adjacent first device regions and second device regions, the first device region being used to form a first type transistor, and the second device region being used to form a second type transistor; sequentially etching the gate structure and the isolation layer at the boundary between the first device region and the second device region to form a trench surrounded by the gate structure and the isolation layer; forming a diffusion barrier layer in the trench; and performing channel stop ion implantation on the fins of the first device region and the second device region on both sides of the diffusion barrier layer. The diffusion barrier layer reduces the impact of anti-penetration ions in each device region on other device regions, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] As the critical dimensions of metal-oxide-semiconductor field-effect transistors (MOSFETs) shrink, the short-channel effect (SCE) becomes a critical issue. FinFETs, with their excellent gate control capabilities, effectively suppress the short-channel effect. Therefore, FinFET devices are commonly used in the design of small-size semiconductor devices.

[0003] As device size decreases, punch-through effect is more likely to occur. To suppress punch-through effect, channel stop ion implantation (CMP) is usually performed on the fin below the top surface of the isolation layer to form a punch-through ion doped region. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a base and a fin protruding from the base, wherein, along a direction perpendicular to the extending direction of the fin, the substrate includes adjacent first device regions and second device regions, the first device region being used to form a first type transistor and the second device region being used to form a second type transistor, the first type and the second type being different; an isolation layer located on the substrate exposed by the fin, the isolation layer covering a portion of the sidewalls of the fin; a penetration-resistant ion-doped region located in the fin below the top surface of the isolation layer; a diffusion barrier layer located in the isolation layer at the boundary between the first device region and the second device region; and a device gate structure spanning the fin and covering a portion of the top and a portion of the sidewalls of the fin, the device gate structure further covering the diffusion barrier layer.

[0006] Optionally, the top of the diffusion barrier layer is lower than the top of the fin.

[0007] Optionally, the distance from the top of the diffusion barrier layer to the top of the device gate structure is 200 angstroms to 400 angstroms.

[0008] Optionally, with the extension direction of the device gate structure as the lateral direction, the lateral dimension of the diffusion barrier layer is 8 nanometers to 30 nanometers.

[0009] Optionally, the isolation layer has an initial height; the distance from the bottom of the diffusion barrier layer to the top of the isolation layer is one-third to one-half of the initial height.

[0010] Optionally, the material of the diffusion barrier layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0011] Optionally, the gate structure of the device is a metal gate structure.

[0012] Optionally, the first type and the second type have different conductivity types.

[0013] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and a plurality of discrete fins located on the substrate, an isolation layer formed on the substrate exposed by the fins, the isolation layer covering a portion of the sidewalls of the fins, a gate structure formed on the isolation layer spanning the fins along a direction perpendicular to the extension direction of the fins, the substrate including an adjacent first device region and a second device region, the first device region being used to form a first type transistor, and the second device region being used to form a second type transistor, the first type and the second type being different; sequentially etching the gate structure and the isolation layer at the junction of the first device region and the second device region to form a groove surrounded by the gate structure and the isolation layer; forming a diffusion barrier layer in the groove; performing channel stop ion implantation on the fins of the first device region and the second device region on both sides of the diffusion barrier layer, respectively, and forming a penetration-resistant ion doped region in the fin below the top surface of the isolation layer.

[0014] Optionally, the gate structure is a pseudo-gate structure.

[0015] Optionally, after ion implantation is stopped in the channel, the method further includes: removing the gate structure to form an opening exposing the fin; and forming a device gate structure spanning the fin in the opening.

[0016] Optionally, after ion implantation is stopped in the channel and before the device gate structure is formed, the method further includes: etching back a portion of the diffusion barrier layer in the trench, with the top of the remaining diffusion barrier layer lower than the top of the fin.

[0017] Optionally, a dry etching process can be used to etch back a portion of the diffusion barrier layer in the groove.

[0018] Optionally, the distance from the top of the remaining diffusion barrier layer to the top of the groove is 200 to 400 angstroms.

[0019] Optionally, in the step of providing the substrate, the isolation layer has an initial thickness; after the groove is formed, the distance from the bottom of the groove to the top of the isolation layer is one-third to one-half of the initial thickness.

[0020] Optionally, a dry etching process is used to etch the gate structure and isolation layer at the junction of the first device region and the second device region to form a groove surrounded by the gate structure and isolation layer.

[0021] Optionally, with the extension direction of the gate structure as the lateral direction, the lateral dimension of the groove is 8 nanometers to 30 nanometers.

[0022] Optionally, the material of the diffusion barrier layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0023] Optionally, a high aspect ratio deposition process can be used to form a diffusion barrier layer in the groove.

[0024] Optionally, the first type and the second type have different conductivity types.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0026] This invention provides a semiconductor structure in which an isolation layer is provided on the substrate exposed by the fins. The isolation layer covers part of the sidewalls of the fins. A punch-through ion doped region is provided in the fins near the top surface of the isolation layer. A diffusion barrier layer is located in the isolation layer at the boundary between the first device region and the second device region. The punch-through ion doped region is typically formed by channel stop ion implantation of the fins. Since a diffusion barrier layer is formed between adjacent first and second device regions, the diffusion barrier layer can prevent punch-through ions implanted in the first device region from laterally diffusing into the second device region during channel stop ion implantation, and similarly prevent punch-through ions implanted in the second device region from laterally diffusing into the first device region. Accordingly, the diffusion range of punch-through ions is limited to their respective regions, thereby reducing the impact of punch-through ions in each device region on other device regions. For example, when the first and second types of conductivity are different, the probability of transistor inversion in the first and second device regions is reduced, thereby improving the performance of the semiconductor structure.

[0027] In the semiconductor structure formation method provided by this invention, a gate structure and an isolation layer at the boundary between a first device region and a second device region are sequentially etched to form a groove surrounded by the gate structure and the isolation layer. A diffusion barrier layer is then formed in the groove. Next, channel stop ion implantation is performed on the fins of the first and second device regions on both sides of the diffusion barrier layer, forming a punch-through ion doped region in the fins near the top surface of the isolation layer. Because a diffusion barrier layer is formed between adjacent first and second device regions, it prevents punch-through ions implanted in the first device region from laterally diffusing into the second device region during channel stop ion implantation, and similarly prevents punch-through ions implanted in the second device region from laterally diffusing into the first device region. Consequently, the diffusion range of punch-through ions is limited to their respective regions, reducing the impact of punch-through ions in each device region on other device regions. For example, when the first and second conductivity types are different, the probability of transistor inversion in the first and second device regions is reduced, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0028] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0029] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 4 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0031] Currently, the electrical performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example. Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0032] refer to Figure 1The substrate provides a substrate including a substrate 10 and a plurality of discrete fins 12 located on the substrate 10. An isolation layer 11 is formed on the substrate 10 where the fins 12 are exposed. The isolation layer 11 covers a portion of the sidewalls of the fins 12. A gate structure 13 is formed on the isolation layer 11 across the fins 12 in a direction perpendicular to the extension direction of the fins 12. The substrate includes adjacent first device regions 100A and second device regions 100B. The first device region 100A is used to form NMOS (N-Metal Oxide Semiconductor) transistors, and the second device region 100B is used to form PMOS (P-Metal Oxide Semiconductor) transistors.

[0033] refer to Figure 2 Channel stop ion implantation is performed on the fins 12 of the first device region 100A and the second device region 100B, respectively (e.g., Figure 2 As shown in CD), a penetration-resistant ion-doped region 14 is formed in the fin 12 located near the top surface of the isolation layer 11.

[0034] Specifically, P-type ions are implanted in the first device region 100A, and N-type ions are implanted in the second device region 100B.

[0035] Research has shown that as the feature size of the device decreases, the spacing between adjacent fins 12 also decreases. Therefore, the spacing between adjacent first device regions 100A and second device regions 100B decreases accordingly. Consequently, during channel-stop ion implantation of the fins 12 in the first device regions 100A and second device regions 100B, the implanted ions diffuse laterally. Figure 2 As shown by the dashed arrow, it is easy for the anti-penetration ions injected into the first device region 100A to diffuse laterally into the second device region 100B. Similarly, it is easy for the anti-penetration ions injected into the second device region 100B to diffuse laterally into the first device region 100A. Accordingly, the probability of inversion of the transistors in the first device region 100A and the second device region 100B is increased, thereby reducing the performance of the semiconductor structure.

[0036] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and a plurality of discrete fins located on the substrate, an isolation layer formed on the substrate exposed by the fins, the isolation layer covering a portion of the sidewalls of the fins, a gate structure formed on the isolation layer spanning the fins along a direction perpendicular to the extension direction of the fins, the substrate including adjacent first device regions and second device regions, the first device region being used to form a first type transistor, and the second device region being used to form a second type transistor, the first type and the second type being different; sequentially etching the gate structure and the isolation layer at the boundary between the first device region and the second device region to form a groove surrounded by the gate structure and the isolation layer; forming a diffusion barrier layer in the groove; performing channel stop ion implantation on the fins of the first device region and the second device region on both sides of the diffusion barrier layer, respectively, and forming a penetration-resistant ion doped region in the fin below the top surface of the isolation layer.

[0037] In the scheme disclosed in this embodiment of the invention, the gate structure and the isolation layer at the boundary between the first device region and the second device region are etched sequentially to form a groove surrounded by the gate structure and the isolation layer. Then, a diffusion barrier layer is formed in the groove. Next, channel stop ion implantation is performed on the fins of the first and second device regions on both sides of the diffusion barrier layer, forming a punch-through ion doped region in the fins near the top surface of the isolation layer. Since a diffusion barrier layer is formed between adjacent first and second device regions, this layer can prevent punch-through ions implanted in the first device region from laterally diffusing into the second device region during channel stop ion implantation, and similarly prevent punch-through ions implanted in the second device region from laterally diffusing into the first device region. Consequently, the diffusion range of punch-through ions is limited to their respective regions, reducing the impact of punch-through ions in each device region on other device regions. For example, when the first and second types of conductivity are different, the probability of transistor inversion in the first and second device regions is reduced, thereby improving the performance of the semiconductor structure.

[0038] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0040] The semiconductor structure includes: a substrate, the substrate including a substrate 200 and a fin 202 protruding from the substrate 200 in a direction perpendicular to the extending direction of the fin 202; the substrate including adjacent first device region 200A and second device region 200B, the first device region 200A being used to form a first type transistor and the second device region 200B being used to form a second type transistor, the first type and the second type being different; an isolation layer 201 located on the substrate 200 exposed by the fin 202, the isolation layer 201 covering a portion of the sidewalls of the fin 202; a penetration-resistant ion-doped region 230 located in the fin 202 below the top surface of the isolation layer 201; a diffusion barrier layer 208 located in the isolation layer 201 at the junction of the first device region 200A and the second device region 200B; and a device gate structure 242 spanning the fin 202 and covering a portion of the top and a portion of the sidewalls of the fin 202, the device gate structure 242 also covering the diffusion barrier layer 208.

[0041] The anti-penetration ion doped region 230 is located in the fin 202 below the top surface of the isolation layer 201, and the anti-penetration ion doped region 230 is typically formed by channel stop ion implantation of the fin 202. Since a diffusion barrier layer 208 is formed between the adjacent first device region 200A and second device region 200B, and the diffusion barrier layer 208 is located in the isolation layer 201, the diffusion barrier layer 208 can prevent the anti-penetration ion from being implanted into the first device region 200A during channel stop ion implantation. The lateral diffusion of punch-through ions into the second device region 200B also prevents the lateral diffusion of anti-punch-through ions injected into the second device region 200B into the first device region 200A. Consequently, the diffusion range of anti-punch-through ions is limited to their respective regions, thereby reducing the impact of anti-punch-through ions in each device region on other device regions. For example, when the first and second types of conductivity are different, the probability of inversion of transistors in the first device region 200A and the second device region 200B is reduced, thereby improving the performance of the semiconductor structure.

[0042] In this embodiment, the semiconductor structure is a FinFET (Fin Field-Effect Transistor). The substrate includes a substrate 200 and fins 202 protruding from the substrate 200. In other embodiments, when the semiconductor structure is a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0043] In this embodiment, the material of the fin 202 is the same as that of the substrate 200, which is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0044] In this embodiment, the substrate includes an adjacent first device region 200A and a second device region 200B. The first device region 200A is used to form a first type transistor, and the second device region 200B is used to form a second type transistor. The first type and the second type are different.

[0045] Specifically, the difference between the first type and the second type refers to the different conductivity types of the first type and the second type. In this embodiment, the first type is N-type and the second type is P-type. That is, the first device region 100A is an NMOS device region, and the first type transistor is an NMOS transistor; the second device region 100B is a PMOS device region, and the second type transistor is a PMOS transistor.

[0046] In other embodiments, the difference between the first type and the second type can also refer to the different performance characteristics of the first type transistor and the second type transistor. For example, the first type transistor and the second type transistor may have the same channel conductivity type, but their operating voltages may differ.

[0047] The isolation layer 201 is used to isolate adjacent devices. The material of the isolation layer 201 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 201 is silicon oxide.

[0048] In this embodiment, the isolation layer 201 has an initial height, thereby providing a process basis for forming a diffusion barrier layer 208 at the junction of the first device region 200A and the second device region 200B.

[0049] In this embodiment, the anti-penetration ion doped region 230 is located in the fin 202 below the top surface of the isolation layer 201.

[0050] The anti-penetration ion doped region 230 is used to control the source / drain punch-through at the bottom of the fin 202.

[0051] The anti-penetration ion doped region 230 contains anti-penetration ions, and the conductivity type of the anti-penetration ions is different from the channel conductivity type of the corresponding transistor.

[0052] In this embodiment, the first type transistor is an NMOS transistor, the second type transistor is a PMOS transistor, and correspondingly, the anti-penetration ions in the first device region 200A are P-type ions, and the anti-penetration ions in the second device region 200B are N-type ions.

[0053] The anti-penetration ion doped region 230 is located in the fin 202 below the top surface of the isolation layer 201. Therefore, the top surface of the anti-penetration ion doped region 230 is lower than or flush with the top surface of the isolation layer 201. As an example, the top surface of the anti-penetration ion doped region 230 is lower than the top surface of the isolation layer 201.

[0054] In this embodiment, the diffusion barrier layer 208 is located in the isolation layer 201 at the junction of the first device region 200A and the second device region 200B. The anti-penetration ion doped region 230 is located in the fin 202 below the top surface of the isolation layer 201. Therefore, by placing the diffusion barrier layer 208 in the isolation layer 201, the diffusion barrier layer 208 can block the diffusion of anti-penetration ions.

[0055] It should be noted that, taking the extension direction of the device gate structure 242 as the lateral direction, the lateral dimension of the diffusion barrier layer 208 should not be too large or too small. If the lateral dimension of the diffusion barrier layer 208 is too large, it will occupy too much space in the semiconductor device, causing the distance between the diffusion barrier layer 208 and the first device region 200A and the second device region 200B to become smaller and smaller. This can easily lead to the deposition effect of each film layer in the device gate structure 242 failing to meet the process requirements, thereby affecting the performance of the semiconductor. If the lateral dimension of the diffusion barrier layer 208 is too small, in the process of stopping channel ion implantation, the diffusion barrier layer 208 will not be effective in preventing the penetration-blocking ions implanted into the first device region 200A from diffusing laterally into the second device region 200B. Similarly, the diffusion barrier layer 208 will not be effective in preventing the penetration-blocking ions implanted into the second device region 200B from diffusing laterally into the first device region 200A, thereby affecting the performance of the semiconductor. Therefore, in this embodiment, with the extension direction of the device gate structure as the lateral direction, the lateral dimension of the diffusion barrier layer 208 is 8 nanometers to 30 nanometers. For example, the lateral dimension of the diffusion barrier layer 208 is 10 nanometers, 15 nanometers, 20 nanometers, or 25 nanometers.

[0056] It should be noted that the distance from the bottom of the diffusion barrier layer 208 to the top of the isolation layer 201 as a percentage of the initial height should not be too large or too small. If the distance from the bottom of the diffusion barrier layer 208 to the top of the isolation layer 201 is too large as a percentage of the initial height, it can easily lead to a smaller deposition process window for forming the diffusion barrier layer 208, increasing the process difficulty and thus affecting the structural performance of the semiconductor. If the distance from the bottom of the diffusion barrier layer 208 to the top of the isolation layer 201 is too small as a percentage of the initial height, then during the channel ion stop implantation process, the diffusion barrier layer 208 will not be effective in preventing the lateral diffusion of anti-penetration ions implanted into the first device region 200A into the second device region 200B. Similarly, the diffusion barrier layer 208 will not be effective in preventing the lateral diffusion of anti-penetration ions implanted into the second device region 200B into the first device region 200A, thus affecting the performance of the semiconductor. Therefore, in this embodiment, the distance from the bottom of the diffusion barrier layer 208 to the top of the isolation layer 201 is one-third to one-half of the initial height.

[0057] The diffusion barrier layer 208 has a high material density, thus improving its effectiveness in preventing the lateral diffusion of penetration-blocking ions implanted into the first device region 200A into the second device region 200B, and in preventing the lateral diffusion of penetration-blocking ions implanted into the second device region 200B into the first device region 200A. In this embodiment, the material of the diffusion barrier layer 208 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. As an example, the material of the diffusion barrier layer 208 is silicon nitride.

[0058] In this embodiment, the diffusion barrier layer 208 is embedded in the isolation layer 201 at the junction of the first device region 200A and the second device region 200B, that is, the top of the diffusion barrier layer 208 is higher than the top of the isolation layer 201.

[0059] It should be noted that the distance from the top of the diffusion barrier layer 208 to the top of the device gate structure 242 should not be too large or too small. If the distance from the top of the diffusion barrier layer 208 to the top of the device gate structure 242 is too large, the probability of damaging the first work function layer 209 in the second device region 200B increases during the removal of the first work function layer 209 in the first device region 200A. As the device feature size continues to shrink, the lateral distance between the diffusion barrier layer 208 and the adjacent fin 202 also continues to shrink. If the distance from the top of the diffusion barrier layer 208 to the top of the device gate structure 242 is too small, the deposition difficulty of each film layer in the device gate structure 242 increases, making the filling window of the device gate structure 242 between the first device region 200A and the second device region 200B smaller. For example, the deposition difficulty of each film layer in the device gate structure 242 between the diffusion barrier layer 208 and the adjacent fin 202 increases, thereby affecting the performance of the semiconductor. Therefore, in this embodiment, the distance from the top of the diffusion barrier layer 208 to the top of the device gate structure 242 is 200 angstroms to 400 angstroms. For example, the distance from the top of the diffusion barrier layer 208 to the top of the device gate structure 242 is 250 angstroms, 300 angstroms, or 350 angstroms.

[0060] In this embodiment, the top of the diffusion barrier layer 208 is lower than the top of the fin 202, thereby providing a better filling window for the deposition of each film layer in the device gate structure 242.

[0061] It should also be noted that in other embodiments, the top of the diffusion barrier layer may be flush with the top of the isolation layer.

[0062] In this embodiment, the device gate structure 242 spans the fin 202 and covers part of the top and part of the sidewall of the fin 202, and the device gate structure 242 also covers the diffusion barrier layer 208.

[0063] In this embodiment, the device gate structure 242 is used to control the opening and closing of the transistor channel.

[0064] Specifically, the device gate structure 242 is a metal gate structure, therefore, the device gate structure 242 includes multiple stacked functional film layers. In this embodiment, the device gate structure 242 includes a first device gate structure 240 located in the first device region 200A and a second device gate structure 232 located in the second device region 200B.

[0065] In this embodiment, in the first device region 200A, the first device gate structure 240 includes a gate dielectric layer 210 that conformally covers the fin 202 and the isolation layer 201, a second work function layer 212 that conformally covers the gate dielectric layer 210, and a gate electrode layer 213 that covers the second work function layer 212.

[0066] In this embodiment, in the second device region 200B, the second device gate structure 232 includes a gate dielectric layer 210 that conformally covers the fin 202 and the isolation layer 201, a first work function layer 209 that conformally covers the gate dielectric layer 210, and a gate electrode layer 213 that covers the first work function layer 209.

[0067] It should be noted that, in this embodiment, the gate dielectric layer 210 also conformally covers the diffusion barrier layer 208.

[0068] Specifically, the gate dielectric layer 210 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the gate dielectric layer 210 is made of HfO2. In other embodiments, the high-k gate dielectric layer material can also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0069] The first work function layer 209 is used to adjust the threshold voltage of the transistor formed in the second device region 200A. In this embodiment, the second type transistor is a PMOS transistor; therefore, the first work function layer 209 is a P-type work function layer. The material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. In this embodiment, the material of the first work function layer 209 is TiN.

[0070] The second work function layer 212 is used to adjust the threshold voltage of the transistor formed in the first device region 200B. In this embodiment, the first type transistor is an NMOS transistor; therefore, the second work function layer 212 is an N-type work function layer. The material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. In this embodiment, the material of the second work function layer 212 is TiAl.

[0071] The gate electrode layer 213 is used for subsequent electrical connection with external structures. In this embodiment, the material of the gate electrode layer 213 includes W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0072] The semiconductor structure further includes a sidewall 231 located on the sidewall of the device gate structure 242. The sidewall 231 protects the sidewall of the device gate structure 242. The sidewall 231 can be a single-layer structure or a multilayer structure, and the material of the sidewall 231 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 231 is a single-layer structure, and the material of the sidewall 231 is silicon nitride.

[0073] The semiconductor structure further includes an interlayer dielectric layer 206 located on the substrate 200 exposed by the device gate structure 242, and covering the sidewall of the sidewall 231.

[0074] The interlayer dielectric layer 206 is used to isolate adjacent devices. The material of the interlayer dielectric layer 206 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 206 is silicon nitride.

[0075] Accordingly, the present invention also provides a method for forming a semiconductor structure, with reference to... Figures 4 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0076] refer to Figures 4 to 7 The substrate provides a substrate including a substrate 100 and a plurality of discrete fins 102 located on the substrate 100. An isolation layer 101 is formed on the substrate 100 where the fins 102 are exposed. The isolation layer 101 covers a portion of the sidewalls of the fins 102. A gate structure 103 is formed on the isolation layer 101 across the fins 102 in a direction perpendicular to the extension direction of the fins 102. The substrate includes adjacent first device regions 100A and second device regions 100B. The first device region 100A is used to form a first type transistor, and the second device region is used to form a second type transistor. The first type and the second type are different.

[0077] like Figure 4 As shown, in this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. The substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0078] In this embodiment, the fin 102 is disposed on the substrate 100, and the material of the fin 102 is the same as that of the substrate, which is silicon.

[0079] In this embodiment, the substrate includes an adjacent first device region 100A and a second device region 100B. The first device region 100A is used to form a first type transistor, and the second device region 100B is used to form a second type transistor. The first type and the second type are different.

[0080] Specifically, the difference between the first type and the second type refers to the different conductivity types of the first type and the second type. In this embodiment, the first type is N-type and the second type is P-type. That is, the first device region 100A is an NMOS device region, and the first type transistor is an NMOS transistor; the second device region 100B is a PMOS device region, and the second type transistor is a PMOS transistor.

[0081] In other embodiments, the difference between the first type and the second type can also refer to the different performance characteristics of the first type transistor and the second type transistor. For example, the first type transistor and the second type transistor may have the same channel conductivity type, but their operating voltages may differ.

[0082] Continue as Figure 4 As shown, in this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 102, forming an isolation layer 101 on the substrate 100 exposed by the fin 102, the isolation layer 101 covering part of the sidewall of the fin 102.

[0083] The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon oxide.

[0084] In this embodiment, during the step of providing the substrate, the isolation layer 101 has an initial thickness, thereby providing a process basis for the subsequent formation of a diffusion barrier layer 108 at the junction of the first device region 100A and the second device region 100B.

[0085] like Figure 5 As shown, a gate structure 103 spanning the fin 102 is formed on the isolation layer 101.

[0086] In this embodiment, the gate structure 103 is a pseudo-gate structure, used to occupy space for the subsequent formation of the device gate structure. Specifically, the material of the gate structure 103 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, amorphous carbon, amorphous silicon, or polycrystalline silicon, or other materials. As an example, the material of the gate structure 103 is amorphous silicon.

[0087] It should be noted that a mask layer 105 is formed on the top of the gate structure 103.

[0088] The mask layer 105 serves as a mask for forming the gate structure 103 and also protects the top of the gate structure 103 during the subsequent formation of the interlayer dielectric layer and sidewalls.

[0089] Continue to refer to Figure 5 It should be noted that before forming the gate structure 103 spanning the fin 102 on the isolation layer 101, the method further includes forming a pseudo-gate oxide layer 104 on the top and sidewalls of the fin 102 that exposes the isolation layer 101.

[0090] Specifically, the dummy gate oxide layer 104 protects the fins 102 exposed by the isolation layer 101 during the formation of the gate structure 103.

[0091] In this embodiment, the pseudo-gate oxide layer 104 is formed by a rapid thermal oxidation process, and the material of the pseudo-gate oxide layer 104 is silicon oxide.

[0092] like Figure 6 As shown, after the gate structure 103 is formed, a sidewall 131 is formed on the sidewall of the gate structure 103.

[0093] The sidewall 131 is used to protect the sidewalls of the subsequently formed device gate structure. The sidewall 131 can be a single-layer structure or a multilayer structure, and the material of the sidewall 131 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 131 is a single-layer structure, and the material of the sidewall 131 is silicon nitride.

[0094] In this embodiment, after forming the sidewall 131, the method further includes: using the sidewall 131 as a mask to form source / drain doped regions (not shown) in the fins 102 on both sides of the gate structure 103.

[0095] In this embodiment, the first device region 100A is an NMOS transistor, and the material of the source and drain doped regions is silicon carbide or silicon doped with N-type ions, wherein the N-type ions include P, As, or Sb. In this embodiment, the second device region 100B is a PMOS transistor, and the material of the source and drain doped regions is silicon germanide doped with P-type ions, wherein the P-type ions include B, Ga, or In.

[0096] It should be noted that, as Figure 6 As shown, after forming source and drain doped regions (not shown), an interlayer dielectric layer 106 is formed on the substrate 100 exposed by the gate structure 103, and the interlayer dielectric layer 106 covers the sidewalls of the gate structure 103.

[0097] The interlayer dielectric layer 106 is used to isolate adjacent devices. The material of the interlayer dielectric layer 106 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 106 is silicon nitride.

[0098] In this embodiment, after the interlayer dielectric layer 106 is formed, the interlayer dielectric layer 106 covers the top of the gate structure 103.

[0099] Therefore, as Figure 7 As shown, after forming the interlayer dielectric layer 106, the method further includes: using the top of the gate structure 103 as the stop position, planarizing the interlayer dielectric layer 106, the mask layer 105, and the sidewall 131 until the top of the gate structure 103 is exposed, so that the top of the remaining interlayer dielectric layer 106 and the top of the sidewall 131 are flush with the top of the gate structure 103.

[0100] In this embodiment, the planarization process is performed using a chemical mechanical polishing process.

[0101] refer to Figure 8 The gate structure 103 and the isolation layer 101 at the junction of the first device region 100A and the second device region 100B are etched sequentially to form a groove 107 surrounded by the gate structure 103 and the isolation layer 101.

[0102] Specifically, the groove 107 provides space for the subsequent formation of a diffusion barrier layer.

[0103] In this embodiment, a dry etching process is used to etch the gate structure 103 and the isolation layer 101 at the junction of the first device region 100A and the second device region 100B to form a groove 107 surrounded by the gate structure 103 and the isolation layer 101.

[0104] The dry etching process includes anisotropic dry etching. Because of its anisotropic etching characteristics, the longitudinal etching rate is much higher than the lateral etching rate. This reduces the lateral etching amount while forming the groove 107, resulting in less damage to the sidewalls of the gate structure 103 and lowering the probability of accidental etching of the fin 102.

[0105] In this embodiment, after the groove 107 is formed, the distance from the bottom of the groove 107 to the top of the isolation layer 101 is one-third to one-half of the initial thickness.

[0106] It should be noted that the distance from the bottom of the groove 107 to the top of the isolation layer 101 should not be too large or too small as a proportion of the initial thickness. If the distance from the bottom of the groove 107 to the top of the isolation layer 101 is too large as a proportion of the initial thickness, it will easily lead to a smaller deposition process window for forming the diffusion barrier layer, increasing the process difficulty and thus affecting the structural performance of the semiconductor. If the distance from the bottom of the groove 107 to the top of the isolation layer 101 is too small as a proportion of the initial thickness, the diffusion barrier layer formed in the groove 107 will not be effective in preventing the lateral diffusion of anti-penetration ions implanted into the first device region 100A into the second device region 100B during the subsequent channel ion stop implantation process. Similarly, the diffusion barrier layer formed in the groove 107 will not be effective in preventing the lateral diffusion of anti-penetration ions implanted into the second device region 100B into the first device region 100A, thus affecting the performance of the semiconductor. Therefore, in this embodiment, the distance from the bottom of the groove 107 to the top of the isolation layer 101 is one-third to one-half of the initial thickness.

[0107] It should be noted that the lateral dimension of the groove 107 should not be too large or too small. If the lateral dimension of the groove 107 is too large, it will occupy too much space in the semiconductor device, causing the distance between the sidewall of the groove 107 and the first device region 100A and the second device region 100B to become smaller and smaller. This can easily lead to the deposition effect of each film layer in the subsequently formed device gate structure not meeting the process requirements, thus affecting the performance of the semiconductor. If the lateral dimension of the groove 107 is too small, the diffusion barrier layer formed in the groove 107 will not be effective in preventing the anti-penetration ions implanted into the first device region 100A from diffusing laterally into the second device region 100B during the subsequent channel ion stop implantation process. Similarly, the diffusion barrier layer 108 will not be effective in preventing the anti-penetration ions implanted into the second device region 100B from diffusing laterally into the first device region 100A, thus affecting the performance of the semiconductor. Therefore, in this embodiment, with the extension direction of the gate structure 103 as the lateral direction, the lateral dimension of the groove 107 is 8 nanometers to 30 nanometers. For example, the lateral dimension of the groove 107 is 10 nanometers, 15 nanometers, 20 nanometers or 25 nanometers.

[0108] refer to Figure 9 In the groove 107 (e.g. Figure 8 A diffusion barrier layer 108 is formed in the (shown).

[0109] A diffusion barrier layer 108 is formed in the groove 107. Subsequently, channel stop ion implantation is performed on the fins 102 of the first device region 100A and the second device region 100B on both sides of the diffusion barrier layer 108. A penetration-proof ion doping region is formed in the fins 102 near the top surface of the isolation layer 101. In this design, a diffusion barrier layer 108 is formed between adjacent first device regions 100A and second device regions 100B. This diffusion barrier layer 108 prevents the lateral diffusion of anti-penetration ions implanted into the first device region 100A into the second device region 100B during the channel ion implantation stop process, and similarly prevents the lateral diffusion of anti-penetration ions implanted into the second device region 100B into the first device region 100A. Consequently, the diffusion range of anti-penetration ions is limited to their respective regions, thereby reducing the impact of anti-penetration ions in each device region on other device regions. For example, when the first and second types of conductivity are different, the probability of transistors in the first device region 100A and the second device region 100B undergoing inversion is reduced, thereby improving the performance of the semiconductor structure.

[0110] Specifically, the process for forming the diffusion barrier layer 108 in the groove 107 includes a high aspect ratio deposition process or an atomic layer deposition process. In this embodiment, a high aspect ratio deposition process is used to form the diffusion barrier layer 108 in the groove.

[0111] The high aspect ratio deposition process or atomic layer deposition process has the characteristics of good gap filling performance and step coverage performance, which correspondingly improves the filling and coverage ability of the diffusion barrier layer 108 and makes the thickness uniformity of the diffusion barrier layer 108.

[0112] The diffusion barrier layer 108 has a high material density, thus improving its effectiveness in preventing the lateral diffusion of penetration-blocking ions implanted into the first device region 100A into the second device region 100B, and in preventing the lateral diffusion of penetration-blocking ions implanted into the second device region 100B into the first device region 100A. In this embodiment, the material of the diffusion barrier layer 108 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. As an example, the material of the diffusion barrier layer 108 is silicon nitride.

[0113] refer to Figure 10 Channel stop ion implantation is performed on the fins 102 of the first device region 100A and the second device region 100B on both sides of the diffusion barrier layer 108, respectively, to form a penetration-resistant ion doped region 130 in the fins 102 below the top surface of the isolation layer 101.

[0114] The anti-penetration ion-doped region 130 is used to prevent punch-through between the source and drain doped regions (not shown). In this embodiment, during channel stop ion implantation, ion implantation can be performed on the fins 102 of the first device region 100A and the second device region 100B on both sides of the diffusion barrier layer 108.

[0115] In this embodiment, when performing channel stop ion implantation, anti-penetration ions are implanted into the fin 102 located below the top surface of the isolation layer 101. The conductivity type of the anti-penetration ions is different from the channel conductivity type of the corresponding transistor.

[0116] Therefore, the top surface of the anti-penetration ion doped region 130 is lower than or flush with the top surface of the isolation layer 101. As an example, the top surface of the anti-penetration ion doped region 130 is lower than the top surface of the isolation layer 101.

[0117] It should be noted that during the channel stop ion implantation process, the gate structure 103 and the isolation layer 101 are also implanted. That is, channel stop ion implantation is performed on the entire first device region 100A, implanting the corresponding type of anti-penetration ions; similarly, channel stop ion implantation is performed on the entire second device region 100B, implanting the corresponding type of anti-penetration ions. In this embodiment, the first and second types have different conductivity types; therefore, the conductivity types of the anti-penetration ions in the first device region 100A and the second device region 100B are also different.

[0118] The first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor. Accordingly, for the first device region 100A, P-type ion implantation is performed on the fin 102 to form a punch-through ion doped region 130 in the fin 102, that is, the punch-through ions in the first device region 100A are P-type ions; for the second device region 100B, N-type ion implantation is performed on the fin 102 to form a punch-through ion doped region 130 in the fin 102, that is, the punch-through ions in the second device region 100B are N-type ions. It should be noted that the P-type ions include boron ions or boron difluoride ions, etc., and the N-type ions include arsenic ions or phosphorus ions, etc.

[0119] It should also be noted that the gate structure 103 is a pseudo-gate structure. Since the gate structure 103 will be removed subsequently, even if anti-penetration ions are still implanted into the gate structure 103 during channel stop ion implantation, the impact on the device gate structure is minimal. Moreover, the gate structure 103 can also protect the isolation layer 101, thereby reducing the impact of anti-penetration ions on the isolation layer 101.

[0120] refer to Figures 11 to 16 After ion implantation is stopped in the channel, the method further includes: removing the gate structure 103 to form an opening 133 exposing the fin 102; and forming a device gate structure 142 spanning the fin 102 in the opening 133.

[0121] In this embodiment, the device gate structure 142 is a metal gate structure, used to control the opening and closing of the transistor channel.

[0122] In this embodiment, the opening 133 is formed in the interlayer dielectric layer 106.

[0123] Specifically, the steps for forming the gate structure of the device include: as follows Figure 12 As shown, the gate structure 103 is removed, and an opening 133 is formed in the interlayer dielectric layer 106 to expose the fin 102; as Figure 13 As shown, a gate dielectric layer 110 is formed on the isolation layer 101 exposed by the opening 133. The gate dielectric layer 110 also conformally covers the fin 102, the barrier layer 108, and the sidewall of the opening 133, continuing as shown. Figure 13 As shown, a first work function layer 109 is formed to conformally cover the gate dielectric layer 110; as Figure 14 As shown, a pattern layer 111 covering the first work function layer 109 is formed in the second device region 100B; using the pattern layer 111 as a mask, the first work function layer 109 in the first device region 100A is removed until the gate dielectric layer 110 is exposed; as shown Figure 15 As shown, after removing the first work function layer 109 of the first device region 100A, the pattern layer 111 is removed; after removing the pattern layer 111, a second work function layer 112 is formed in the first device region 100A, conformally covering the gate dielectric layer 110; as shown Figure 16 As shown, after the second work function layer 112 is formed, a gate electrode layer 113 is formed in the remaining opening 133, and the gate electrode layer 113 covers the top and sidewalls of the first work function layer 109 and the second work function layer 112.

[0124] In this embodiment, during the formation of the second work function layer 112, the second work function layer 112 also conformally covers the first work function layer 109. Therefore, the step of forming the device gate structure further includes removing the second work function layer 112 located on the first work function layer 109 before forming the gate electrode layer 113. In other embodiments, to simplify the process steps, the second work function layer located on the first work function layer may also be retained.

[0125] In this embodiment, a first device gate structure 140 is formed in the first device region 100A. The first device gate structure 140 includes the gate dielectric layer 110, a second work function layer 112 conformally covering the gate dielectric layer 110, and a gate electrode layer 113 filling the remaining opening 133. A second device gate structure 132 is formed in the second device region 100B. The second device gate structure 132 includes the gate dielectric layer 110, a first work function layer 109 conformally covering the gate dielectric layer 110, and a gate electrode layer 113 filling the remaining opening 133. The first device gate structure 140 and the second device gate structure 132 constitute the device gate structure 142.

[0126] Specifically, the gate dielectric layer 110 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the gate dielectric layer 110 is made of HfO2. In other embodiments, the high-k gate dielectric layer material can also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0127] The first work function layer 109 is used to adjust the threshold voltage of the transistor formed in the second device region 100A. In this embodiment, the second type transistor is a PMOS transistor; therefore, the first work function layer 109 is a P-type work function layer. The material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. In this embodiment, the material of the first work function layer 109 is TiN.

[0128] The second work function layer 112 is used to adjust the threshold voltage of the transistor formed in the first device region 100B. In this embodiment, the first type transistor is an NMOS transistor; therefore, the second work function layer 112 is an N-type work function layer. The material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. In this embodiment, the material of the second work function layer 112 is TiAl.

[0129] The gate electrode layer 113 is used for subsequent electrical connection with external structures. In this embodiment, the material of the gate electrode layer 113 includes W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0130] like Figure 11As shown, in this embodiment, after the ion implantation of the channel is stopped and before the device gate structure 142 is formed, the method further includes: etching back a portion of the diffusion barrier layer 108 in the groove 107, with the top of the remaining diffusion barrier layer 108 being lower than the top of the fin 102.

[0131] It should be noted that the diffusion barrier layer 108 with a thickness of etched back increases the process window for the subsequent formation of the gate dielectric layer 110, the first work function layer 109, and the second work function layer 112, thereby improving the deposition effect of the gate dielectric layer 110, the first work function layer 109, and the second work function layer 112.

[0132] In this embodiment, a dry etching process is used to etch back a portion of the diffusion barrier layer 108 in the groove 107.

[0133] The dry etching process includes anisotropic dry etching processes.

[0134] Anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its transverse etching rate, which can obtain a fairly accurate pattern transformation. While etching away part of the diffusion barrier layer 108, it reduces the impact on the sidewalls of the gate structure 103.

[0135] In this embodiment, the distance from the top of the remaining diffusion barrier layer 108 to the top of the groove 107 is 200 angstroms to 400 angstroms.

[0136] It should be noted that the distance from the top of the remaining diffusion barrier layer 108 to the top of the groove 107 should not be too large or too small. If the distance from the top of the remaining diffusion barrier layer 108 to the top of the groove 107 is too large, the probability of damaging the first work function layer 109 in the second device region 100B increases during the removal of the first work function layer 109 in the first device region 100A. As the device feature size continues to shrink, the lateral distance between the diffusion barrier layer 108 and the adjacent fin 102 also continues to shrink. If the distance from the top of the remaining diffusion barrier layer 108 to the top of the groove 107 is too small, the deposition difficulty of the gate dielectric layer 110, the first work function layer 109, and the second work function layer 112 increases during the formation of the device gate structure 142, making the filling window of the device gate structure 142 between the first device region 100A and the second device region 100B smaller, thereby affecting the performance of the semiconductor. Therefore, in this embodiment, the distance from the top of the remaining diffusion barrier layer 108 to the top of the groove 107 is 200 angstroms to 400 angstroms. For example, the distance from the top of the remaining diffusion barrier layer 108 to the top of the groove 107 is 250 angstroms, 300 angstroms, or 350 angstroms.

[0137] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0138] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a semiconductor device and a manufacturing method thereof. The base comprises a substrate and a fin protruding from the substrate, and the base comprises adjacent first and second device regions for forming first and second type transistors, respectively, the first and second types being different. An isolation layer is formed on the substrate exposed by the fin, and the isolation layer covers part of the sidewall of the fin. A punch-through ion doping region is formed in the fin below the position of the top surface of the isolation layer, and the punch-through ion doping region is used for inhibiting punch-through effect. A diffusion barrier layer is formed in the isolation layer at the junction of the first and second device regions, and the diffusion barrier layer is used for limiting the diffusion range of the punch-through ions in the respective regions. A device gate structure is formed across the fin and covers part of the top and sidewall of the fin, and the device gate structure also covers the diffusion barrier layer.

2. The semiconductor structure of claim 1, wherein, The top of the diffusion barrier layer is lower than the top of the fin.

3. The semiconductor structure of claim 1, wherein, The distance from the top of the diffusion barrier layer to the top of the device gate structure is 200-400 angstroms.

4. The semiconductor structure of claim 1, wherein, In the lateral direction of the extension direction of the device gate structure, the lateral dimension of the diffusion barrier layer is 8-30 nanometers.

5. The semiconductor structure of claim 1, wherein, The isolation layer has an initial height. The distance from the bottom of the diffusion barrier layer to the top of the isolation layer accounts for one-third to one-half of the initial height.

6. The semiconductor structure of claim 1, wherein, The material of the diffusion barrier layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron silicon carbon nitride.

7. The semiconductor structure of claim 1, wherein, The device gate structure is a metal gate structure.

8. The semiconductor structure of claim 1, wherein, The first and second types are different in conductive type.

9. A method of forming a semiconductor structure, comprising: The application relates to a semiconductor device and a manufacturing method thereof. The base comprises a substrate and a plurality of discrete fins on the substrate, and an isolation layer is formed on the substrate exposed by the fins, the isolation layer covering part of the sidewall of the fin, and a gate structure is formed on the isolation layer and across the fin, and the base comprises adjacent first and second device regions for forming first and second type transistors, respectively, the first and second types being different. The gate structure and the isolation layer at the junction of the first and second device regions are etched in sequence to form a groove surrounded by the gate structure and the isolation layer. A diffusion barrier layer is formed in the groove, and the diffusion barrier layer is used for limiting the diffusion range of the punch-through ions in the respective regions. Channel stop ion implantation is performed on the fins of the first and second device regions on both sides of the diffusion barrier layer, respectively, to form a punch-through ion doping region in the fin below the position of the top surface of the isolation layer, and the punch-through ion doping region is used for inhibiting punch-through effect.

10. The method of forming a semiconductor structure of claim 9, wherein, The gate structure is a dummy gate structure.

11. The method of forming a semiconductor structure of claim 10, wherein, After the channel stop ion implantation, the gate structure is removed to form an opening exposing the fin, and a device gate structure is formed in the opening and across the fin.

12. The method of forming a semiconductor structure of claim 11, wherein, After the channel stop ion implantation and before forming the device gate structure, further comprising: etching back a portion of the diffusion barrier layer in the recess, leaving a top of the remaining diffusion barrier layer below a top of the fin.

13. The method of forming a semiconductor structure of claim 12, wherein, The etching back of the portion of the diffusion barrier layer in the recess is performed using a dry etching process.

14. The method of forming a semiconductor structure of claim 12, wherein, A distance from the top of the remaining diffusion barrier layer to the top of the recess is 200 angstroms to 400 angstroms.

15. The method of forming a semiconductor structure of claim 9, wherein, In the step of providing the substrate, the isolation layer has an initial thickness. After forming the recess, a distance from a bottom of the recess to the top of the isolation layer is one third to one half of the initial thickness.

16. The method of forming a semiconductor structure of claim 9, wherein, The gate structure and the isolation layer at the junction of the first device region and the second device region are etched using a dry etching process to form a recess surrounded by the gate structure and the isolation layer.

17. The method of forming a semiconductor structure of claim 9, wherein, In a direction of extension of the gate structure is a lateral direction, a lateral dimension of the recess is 8 nanometers to 30 nanometers.

18. The method of forming a semiconductor structure of claim 9, wherein, The diffusion barrier layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride, and boron silicon carbon nitride.

19. The method of forming a semiconductor structure of claim 9, wherein, The diffusion barrier layer is formed in the recess using a high aspect ratio deposition process.

20. The method of forming a semiconductor structure of claim 9, wherein, The first type and the second type are different conductive types.

Images