Semiconductor structure and its formation method

Abstract

A semiconductor structure and its formation method are disclosed. The formation method includes: providing a substrate, including a device region and a zero-layer marking region; forming a zero-layer marking trench within the substrate in the zero-layer marking region; filling the zero-layer marking trench to form a dielectric layer; forming a fin mask material layer covering the substrate and the dielectric layer; forming a core layer on the fin mask material layer above the dielectric layer and the substrate in the device region, the core layer covering the top of the dielectric layer; forming mask sidewalls on the sidewalls of the core layer; removing the core layer; after removing the core layer, etching the fin mask material layer using the mask sidewalls as a mask to form a fin mask layer; etching a portion of the substrate using the fin mask layer as a mask, the remaining substrate after etching serving as a substrate, and the protrusions on the substrate in the device region serving as fins, and simultaneously etching a portion of the dielectric layer during the substrate etching process. This invention, by filling the zero-layer marking trench with a dielectric layer to form fins, reduces the probability of residual defects or detachment defects.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the shrinking feature size, the channel length of MOSFETs is also continuously shortening. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, thus reducing the gate's control over the channel and making it increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Moreover, FinFETs have better compatibility with existing integrated circuit manufacturing compared to other devices.

[0004] Furthermore, as device channel lengths shorten, device linewidths also decrease. If well implantation is performed after fin formation, the smaller linewidth fins are more susceptible to damage during ion implantation. Therefore, well ion implantation of the substrate before fin formation has become a preferred approach. Correspondingly, this process requires the formation of zero-mark trenches in the substrate, which serve as alignment marks for the photolithography process during well ion implantation. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a device region and a zero-layer marking region; a fin protruding from the substrate of the device region; a zero-layer marking trench located within the substrate of the zero-layer marking region, the top of the zero-layer marking trench being flush with the top of the substrate; and a dielectric layer filling the zero-layer marking trench.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a device region and a zero-layer marking region for forming a zero-layer marking trench; forming the zero-layer marking trench within the substrate of the zero-layer marking region; filling the zero-layer marking trench to form a dielectric layer located in the zero-layer marking trench; forming a fin mask material layer covering the substrate and the dielectric layer; forming a core layer on the fin mask material layer above the substrate of the dielectric layer and the device region, the core layer covering the top of the dielectric layer; forming a mask sidewall on the sidewall of the core layer; removing the core layer; after removing the core layer, etching the fin mask material layer using the mask sidewall as a mask to form a fin mask layer; using the fin mask layer as a mask to etch a portion of the substrate, the remaining substrate after etching serving as a substrate, and the protrusions on the substrate of the device region serving as fins, and simultaneously etching a portion of the dielectric layer during the etching of the substrate.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure in which a zero-layer marking trench is formed within the substrate of the zero-layer marking region. The top of the zero-layer marking trench is flush with the top of the substrate, and the zero-layer marking trench is filled with a dielectric layer. The zero-layer marking trench is typically formed before the formation of fins. Therefore, by filling the zero-layer marking trench with a dielectric layer to fill its space, the probability of material residue forming on the sidewalls of the zero-layer marking trench during the fin formation process is significantly reduced. Consequently, after the fins are formed, the probability of residue defects or peeling defects caused by the material residue is lower, thereby improving the performance of the semiconductor structure.

[0010] In the formation method provided by the embodiments of the present invention, after forming the zero-layer marking trench in the substrate of the zero-layer marking region, a dielectric layer is first filled into the zero-layer marking trench, followed by the formation of a fin mask material layer covering the substrate and the dielectric layer, and a core layer is formed on the fin mask material layer. The dielectric layer provides a flat surface for the formation of the fin mask material layer. Compared with the scheme of directly forming the fin mask material layer and the core layer after forming the zero-layer marking trench, the present invention significantly reduces the probability of material residue forming the fin mask material layer or the core layer on the sidewall of the zero-layer marking trench after forming the mask sidewall. Correspondingly, after forming the fin, the probability of residue defects or peeling defects caused by the material residue is low, which is beneficial to improving the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 10 A schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure;

[0012] Figure 11 This is a top view of an embodiment of the semiconductor structure of the present invention;

[0013] Figure 12 yes Figure 11 Sectional view along the secant line A1A2;

[0014] Figures 13 to 33 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0016] Figures 1 to 10 A schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0017] refer to Figure 1 A substrate 10 is provided, including a device region 10d and a zero-layer marking region 10z for forming zero-layer marking trenches.

[0018] Specifically, the device region 10d includes a first sub-device region (not shown) for forming a first type transistor and a second sub-device region (not shown) for forming a second type transistor, wherein the channel materials of the first type transistor and the second type transistor are different. As an example, the substrate 10 is made of Si, the first type transistor is an NMOS transistor, and the second type transistor is a PMOS transistor.

[0019] Continue to refer to Figure 1 A first photoresist layer 11 is formed on the substrate 10, and the first photoresist layer 11 exposes the substrate 10 of the zero-layer marking region 10z.

[0020] Reference Figure 2 and Figure 3 , Figure 2 It is a top view. Figure 3 yes Figure 2 A cross-sectional view along line a1a2 shows a portion of the substrate 10 etched using the first photoresist layer 11 as a mask, forming a zero-layer marking trench 12 in the substrate 10 of the zero-layer marking region 10z.

[0021] After forming the zero-layer marking trench 12, the process further includes: removing the first photoresist layer 11.

[0022] It should be noted that after removing the first photoresist layer 11, the process further includes: performing well region implantation on the substrate 10 of the device region 10d.

[0023] refer to Figure 4 A first hard mask material layer 20 is formed to conformally cover the bottom and sidewalls of the zero-layer marking trench 12 and the top of the substrate 10; a first mask stack (not shown) is formed to cover the first hard mask material layer 20, the first mask stack including a first planarization layer 21 filling the zero-layer marking trench 12, a first anti-reflective coating 22 located on the first planarization layer 21, and a second photoresist layer 23 located on the first anti-reflective coating 22, the second photoresist layer 23 exposing the anti-reflective coating 22 of the second sub-device region (not shown).

[0024] refer to Figure 5 Using the second photoresist layer 23 as a mask, the first anti-reflection coating 22, the first planarization layer 21 and the first hard mask material layer 20 are etched sequentially, and the first hard mask material layer 20 is patterned into a first hard mask layer 25; using the first hard mask layer 25 as a mask, a portion of the thickness of the substrate 10 is etched, and a groove 13 is formed in the substrate 10 of the second sub-device region (not shown).

[0025] The process includes, after forming the groove 13, removing the remaining first mask stack (not shown).

[0026] refer to Figure 6 A channel material layer (not shown) is epitaxially grown in the groove 13; the channel material layer is planarized to remove the channel material layer above the top surface of the substrate 10, forming a channel layer 15 located in the groove 13, and the hard mask layer 25 is removed during the planarization process.

[0027] As an example, the second type of transistor is a PMOS transistor, and the material of the channel material layer (i.e., channel layer 15) is SiGe.

[0028] refer to Figure 7 A second hard mask material layer 30 is formed to conformally cover the substrate 10, the channel layer 15 and the first hard mask layer 25, and a core material layer 31 is formed to conformally cover the second hard mask material layer 30; a second mask stack (not shown) is formed to cover the core material layer 31, the second mask stack including a second planarization layer 32 filling the zero layer marking trench 12, a second anti-reflection coating 33 on the second planarization layer 32, and a third photoresist layer 34 on the second anti-reflection coating 33.

[0029] In the zero-layer marking region 10z, the projection of the third photoresist layer 34 on the substrate 10 covers the projection of the zero-layer marking trench 12 on the substrate 10. In the device region 10d, the third photoresist layer 34 is located above a portion of the substrate 10 in the first sub-device region (not shown) and above a portion of the channel layer 15 in the second sub-device region (not shown).

[0030] refer to Figure 8 Using the third photoresist layer 34 as a mask, the second anti-reflective coating 33, the second planarization layer 32, and the core material layer 31 are etched sequentially. The core material layer 31 is patterned into a core layer 35. In the zero-layer marking region 10z, the core layer 35 conformally covers the bottom and sidewalls of the zero-layer marking trench 12 and extends to cover part of the surface of the second hard mask material layer 30 located on top of the substrate 10.

[0031] After forming the core layer 35, the process also includes: removing the remaining second mask stack (not shown).

[0032] refer to Figure 9 This forms a conformally compliant mask sidewall material layer 36 that covers the core layer 35 and the second hard mask material layer 30.

[0033] refer to Figure 10 The mask sidewall material layer 36 is anisotropically etched without a mask to form a mask sidewall (not shown) located on the sidewall of the core layer 35. After forming the mask sidewall, the core layer 35 is removed. After removing the core layer 35, the second hard mask material layer 30 is etched using the mask sidewall as a mask to form a second hard mask layer 45. Using the second hard mask layer 45 as a mask, a portion of the thickness of the substrate 10 is etched, and the channel layer 15 is etched simultaneously. The remaining substrate 10 after etching serves as the substrate 40, and the protrusions on the substrate 40 located in the device region 10d serve as fins 41.

[0034] When removing the core layer 35, the core layer 35 at the bottom of the zero-layer marking trench 12 is also removed simultaneously. Similarly, when etching the substrate 10, the substrate 10 at the bottom of the zero-layer marking trench 12 is also etched simultaneously. However, since the depth of the zero-layer marking trench 12 is usually quite large, residues 45 of the second hard mask material layer 30 and residues 43 of the core layer 35 will remain on the sidewalls of the zero-layer marking trench 12, resulting in residue defects.

[0035] Furthermore, a cleaning process will be carried out subsequently. During the cleaning process, the residue 45 of the second hard mask material layer 30 or the residue 43 of the core layer 35 is easily detached under the rinsing of the cleaning solution, resulting in peeling defects.

[0036] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a device region and a zero-layer marking region for forming a zero-layer marking trench; forming the zero-layer marking trench within the substrate of the zero-layer marking region; filling the zero-layer marking trench to form a dielectric layer located within the zero-layer marking trench; forming a fin mask material layer covering the substrate and the dielectric layer; forming a core layer on the fin mask material layer above the substrate of the dielectric layer and the device region, the core layer covering the top of the dielectric layer; forming a mask sidewall on the sidewall of the core layer; removing the core layer; after removing the core layer, using the mask sidewall as a mask, etching the fin mask material layer to form a fin mask layer; using the fin mask layer as a mask, etching a portion of the substrate, the remaining substrate after etching serving as a substrate, and protrusions on the substrate of the device region serving as fins, and simultaneously etching a portion of the dielectric layer during the etching of the substrate.

[0037] In the semiconductor structure formation method provided by the embodiments of the present invention, after forming the zero-layer marking trench in the substrate of the zero-layer marking region, a dielectric layer is first filled in the zero-layer marking trench, followed by the formation of a fin mask material layer covering the substrate and the dielectric layer, and a core layer is formed on the fin mask material layer. The dielectric layer provides a flat surface for the formation of the fin mask material layer. Compared with the scheme of directly forming the fin mask material layer and the core layer after forming the zero-layer marking trench, the present invention significantly reduces the probability of material residue forming the fin mask material layer or the core layer on the sidewall of the zero-layer marking trench after forming the mask sidewall. Correspondingly, after forming the fin, the probability of residue defects or detachment defects caused by the material residue is low, which is beneficial to improving the performance of the semiconductor structure.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 11 and Figure 12 , Figure 11 This is a top view of an embodiment of the semiconductor structure of the present invention. Figure 12 yes Figure 11 A sectional view along the secant line A1A2.

[0040] The semiconductor structure includes: a substrate 600, including a device region 10d and a zero-layer marking region 10z; a fin 610 protruding from the substrate 600 of the device region 10d; a zero-layer marking trench (not shown) located within the substrate 600 of the zero-layer marking region 10z, the top of the zero-layer marking trench being flush with the top of the substrate 600; and a dielectric layer 810 filling the zero-layer marking trench.

[0041] The zero-layer marking trench is typically formed before the fin 610 is formed. Therefore, by filling the zero-layer marking trench with a dielectric layer 810 to fill the space of the zero-layer marking trench, and the fin 610 is typically formed using a self-aligned double patterning process, such as self-aligned double patterning (SADP), the probability of material residue forming on the sidewalls of the zero-layer marking trench during the fin 610 formation process is significantly reduced by using the dielectric layer 810 to fill the zero-layer marking trench. Consequently, after the fin 610 is formed, the probability of residue defects or detachment defects caused by the material residue is low, which is beneficial to improving the performance of the semiconductor structure.

[0042] In this embodiment, the substrate 600 is a bulk substrate. Specifically, the material of the substrate 600 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0043] The substrate 600 includes a device region 10d for forming a fin field-effect transistor.

[0044] In this embodiment, the device region 10d includes a first sub-device region 10p for forming a first type transistor and a second sub-device region 10n for forming a second type transistor. The channel materials of the first type transistor and the second type transistor are different. By using different channel materials, the respective performance requirements of the first type transistor and the second type transistor are met.

[0045] Specifically, the first type transistor and the second type transistor have different channel conductivity types, including N-type and P-type. As an example, the first type transistor is a PMOS transistor, and the second type transistor is an NMOS transistor. In other embodiments, depending on the performance requirements of the transistors, even if the first type transistor and the second type transistor have the same channel conductivity type, they can still use different channel materials.

[0046] The fin 610 protrudes from the substrate 600 of the device region 10d and serves to provide a channel for the fin field-effect transistor. As an example, in the first sub-device region 10p, the fin 610 includes a bottom fin layer 610b and a channel layer 610t located on top of the bottom fin layer 610b, the material of the channel layer 610t being different from the material of the bottom fin layer 610b.

[0047] Correspondingly, in the second sub-device region 10n, the fin portion 610 provides the channel for the fin field-effect transistor, and in the first sub-device region 10p, the channel layer 610t provides the channel for the fin field-effect transistor.

[0048] Specifically, the fin 610 in the second sub-device region 10n and the bottom fin layer 610b are integral with the substrate 600, and the material of the fin 610 in the second sub-device region 10n and the bottom fin layer 610b is silicon.

[0049] The channel layer 610t also serves to provide the channel for the fin field-effect transistor; therefore, the material of the channel layer 610t is a semiconductor material. Specifically, the material of the channel layer 610t includes silicon, silicon germanide, germanium, or group III-V semiconductor materials.

[0050] In this embodiment, the first type of transistor is a PMOS transistor, and the second type of transistor is an NMOS transistor. Therefore, the channel layer 610t is made of silicon germanide. By using silicon germanide for the channel of the PMOS transistor, the channel mobility of the PMOS transistor is improved. At the same time, it helps to improve the negative bias temperature instability (NBTI) problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.

[0051] It should be noted that, in other embodiments, depending on the actual situation, the fin in the second sub-device region may include a bottom fin layer and a channel layer located on top of the bottom fin layer, and the fin in the first sub-device region and the bottom fin layer are integrally formed with the substrate.

[0052] In this embodiment, the fin 610 is also located in the zero-layer marking region 10z and surrounds the zero-layer marking trench. The fin 610 in the zero-layer marking region 10z is an integral structure with the substrate 600. The fin 610 in the zero-layer marking region 10z is formed together with the fin 610 in the device region 10d, and the fin 610 in the zero-layer marking region 10z is a dummy fin, not used to form a transistor. In other embodiments, during the formation of the semiconductor structure, the fin in the zero-layer marking region can also be removed by fin cutting. Correspondingly, in the semiconductor structure, the area around the zero-layer marking trench may not contain fins.

[0053] The zero-layer marking trench is located within the substrate 600 of the zero-layer marking region 10z.

[0054] During the formation of the semiconductor structure, the substrate 600 and the fin 610 are formed by patterning the substrate. Before forming the fin 610, the zero-layer marking trench is formed in the substrate. The zero-layer marking trench serves as an alignment mark for the photolithography process. For example, the zero-layer marking trench is used as an alignment mark during well ion implantation or fin formation. During well ion implantation and fin formation, no other patterns have yet formed on the substrate; therefore, the zero-layer marking trench must be formed first as an alignment mark.

[0055] In this embodiment, during the formation of the semiconductor structure, after the dielectric layer 810 is filled in the zero-layer marking trench, the relevant process for forming the fin 610 is performed. Correspondingly, when etching a portion of the substrate to form the fin 610, the dielectric layer 810 is usually also etched. Therefore, the top of the zero-layer marking trench is flush with the top of the substrate 600.

[0056] It should be noted that the distance H1 from the bottom of the zero-layer marking trench to the top of the fin 610 is the distance from the bottom of the zero-layer marking trench to the substrate before the fin 610 is formed, which is also the depth of the zero-layer marking trench before the fin 610 is formed. During the photolithography process of well region ion implantation on the substrate, alignment is achieved by the signal phase difference between the top of the substrate and the bottom of the zero-layer marking trench. Therefore, the distance H1 from the bottom of the zero-layer marking trench to the top of the fin 610 will affect the signal strength during photolithography alignment, thereby affecting the alignment accuracy.

[0057] Therefore, the distance H1 from the bottom of the zero-layer marking groove to the top of the fin 610 should not be too small or too large.

[0058] If the distance H1 is too large or too small, the signal strength will be weak, resulting in poor alignment accuracy and alignment deviation.

[0059] Furthermore, during the formation of the semiconductor structure, after the dielectric material corresponding to the dielectric layer 810 is filled into the zero-layer marking trench, the dielectric material needs to be planarized (e.g., chemical mechanical polishing). If the distance H1 is too large, it will result in an excessive amount of dielectric material filling the dielectric layer 810, and the amount of polishing required for planarization will be correspondingly large, which may easily cause the top surface of the dielectric layer 810 to be recessed.

[0060] Furthermore, if the distance H1 is too large, the depth of the zero-layer marking trench will also be too large. This can easily lead to a decrease in the stability of the etching process that forms the zero-layer marking trench and the process of filling the dielectric material in the zero-layer marking trench. This will also affect the signal strength during photolithography alignment, thereby causing alignment deviation.

[0061] In summary, in this embodiment, the distance H1 from the bottom of the zero-layer marking groove to the top of the fin 610 is... to For example, the distance H1 from the bottom of the zero-layer marking groove to the top of the fin 610 is or

[0062] In this embodiment, the channel layer 610t is also located at the bottom and sidewall of the zero-layer marking trench.

[0063] During the formation of the semiconductor structure, after the dielectric material corresponding to the dielectric layer 810 is filled into the zero-layer marking trench, it needs to be planarized to make the top of the dielectric layer 810 flush with the top of the substrate. The channel layer 610t occupies part of the space of the zero-layer marking trench to reduce the opening size of the remaining space of the zero-layer marking trench, and correspondingly reduce the filling amount of the dielectric material corresponding to the dielectric layer 810. Therefore, after the planarization treatment of the dielectric material corresponding to the dielectric layer 810, it is beneficial to improve the top surface depression problem of the dielectric layer 810.

[0064] The dielectric layer 810 fills the zero-layer marker trench. The dielectric layer 810 is made of a dielectric material. During the photolithography process using the zero-layer marker trench as an alignment mark, the signal at the bottom of the zero-layer marker trench can be easily obtained through the dielectric layer 810, thereby reducing the impact on the signal strength during photolithography alignment. For example, the fin 610 is typically formed using a self-aligned multiple patterning process, and the zero-layer marker trench serves as an alignment mark during the photolithography process of forming the core layer.

[0065] In this embodiment, the channel layer 610t is located between the sidewall of the zero-layer marking trench and the dielectric layer 810, and between the bottom of the zero-layer marking trench and the dielectric layer 810.

[0066] Specifically, the dielectric layer 810 includes one or more of silicon nitride (SiN), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon oxycarbonitrile (SiOCN). These materials have a relatively small impact on signal strength.

[0067] In this embodiment, the dielectric layer 810 is made of silicon nitride.

[0068] During the formation of the semiconductor structure, after the dielectric material corresponding to the dielectric layer 810 is filled into the zero-layer marking trench, the dielectric material also covers the surface of the channel material layer corresponding to the channel layer 610t. Since silicon nitride has a high density, by selecting silicon nitride, it is beneficial to improve the anti-oxidation effect of the dielectric material on the channel material layer, thereby improving the quality of the channel layer 610t.

[0069] It should be noted that the distance H2 from the bottom of the dielectric layer 810 to the top of the fin 610 is the thickness of the dielectric layer 810 before the fin is formed. The distance H2 from the bottom of the dielectric layer 810 to the top of the fin 610 should not be too small or too large.

[0070] If the distance H2 from the bottom of the dielectric layer 810 to the top of the fin 610 is too small, when the thickness of the channel layer 610t in the zero-layer marking trench is constant, in order for the dielectric layer 810 to fill the zero-layer marking trench, the distance H1 from the bottom of the zero-layer marking trench to the top of the fin 610 will be too small, which will easily weaken the signal strength during photolithography alignment. Alternatively, when the depth of the zero-layer marking trench is constant, the thickness of the channel layer 610t in the zero-layer marking trench needs to be increased accordingly. The channel layer 610t and the substrate 100 are made of similar materials. When acquiring signals, the top of the channel material layer at the bottom of the zero-layer marking trench may be mistaken for the bottom of the zero-layer marking trench, which will also weaken the signal strength during photolithography alignment.

[0071] If the distance H2 from the bottom of the dielectric layer 810 to the top of the fin 610 is too large, the amount of dielectric material corresponding to the dielectric layer 810 filling the zero-layer marking trench will be large during the formation of the semiconductor structure. After planarizing the dielectric material corresponding to the dielectric layer 810, the probability of the top surface depression problem of the dielectric layer 810 will increase.

[0072] In summary, in this embodiment, the distance H2 from the bottom of the dielectric layer 810 to the top of the fin 610 is to For example, the distance H2 from the bottom of the dielectric layer 810 to the top of the fin 610 is or

[0073] In this embodiment, the semiconductor structure further includes a well region (not shown) located in the substrate 600 and the fin 610 which is integral with the substrate 600.

[0074] The well region is used to provide the N-type or P-type substrate required for the operation of the corresponding transistor and to achieve electrical isolation between adjacent transistors.

[0075] The well region contains well ions, and the conductivity type of these well ions is opposite to that of the channel conductivity type of the corresponding transistor. That is, the well ions in the well region corresponding to an NMOS transistor are P-type ions, and the well ions in the well region corresponding to a PMOS transistor are N-type ions.

[0076] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0077] Figures 13 to 33 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0078] refer to Figure 13 and Figure 14 , Figure 13 It is a top view. Figure 14 yes Figure 13 A cross-sectional view along line A1A2 provides a substrate 100, including a device region 10d and a zero-layer marking region 10z for forming zero-layer marking trenches.

[0079] The substrate 100 is used to provide a process platform for the formation of the semiconductor structure.

[0080] In this embodiment, the substrate 100 is a bulk substrate. Specifically, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0081] In this embodiment, the substrate 100 includes a device region 10d for forming a fin field-effect transistor.

[0082] In this embodiment, the device region 10d includes a first sub-device region 10p for forming a first type transistor and a second sub-device region 10n for forming a second type transistor. The channel materials of the first type transistor and the second type transistor are different. By using different channel materials, the respective performance requirements of the first type transistor and the second type transistor are met.

[0083] Specifically, the first type transistor and the second type transistor have different channel conductivity types, including N-type or P-type.

[0084] As an example, the first type of transistor is a PMOS transistor, and the second type of transistor is an NMOS transistor. In other embodiments, depending on the performance requirements of the transistors, even if the first type of transistor and the second type of transistor have the same channel conductivity type, the first type of transistor and the second type of transistor may still use different channel materials.

[0085] Continue to refer to Figure 13 and Figure 14 The forming method further includes: forming a hard mask layer 110 on the substrate 100; forming a first mask opening 130 in the hard mask layer 110, wherein the sidewall of the first mask opening 130 is flush with the sidewall of the zero layer marking trench.

[0086] The sidewall of the first mask opening 130 is flush with the sidewall of the zero-layer marking trench, and the first mask opening 130 is used to define the opening size and position of the subsequent zero-layer marking trench.

[0087] Specifically, the step of forming the first mask opening 130 includes: forming a first photoresist layer 111 on the hard mask layer 110, the first photoresist layer 111 exposing the hard mask layer 110 at the location where the zero-layer marking trench is to be formed; using the first photoresist layer 111 as a mask, etching the hard mask layer 110 to form the first mask opening 130 penetrating the hard mask layer 110.

[0088] In this embodiment, after forming the first mask opening 130, the first photoresist layer 111 can be retained, so that in the subsequent process of forming the zero-layer marking trench, the first photoresist layer 111 and the hard mask layer 110 can jointly serve as an etching mask. In other embodiments, the first photoresist layer can also be removed.

[0089] The material of the hard mask layer 110 may include one or more of amorphous carbon (aC), silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiOC), and titanium nitride (TiN). In this embodiment, the material of the hard mask layer 110 is silicon oxide.

[0090] Reference Figure 15 and Figure 16 , Figure 15 Based on Figure 13 Top view, Figure 16 yes Figure 15 A cross-sectional view along line A1A2 shows a zero-layer marking groove 120 formed within the base 100 of the zero-layer marking region 10z (e.g., ...). Figure 16 (As shown).

[0091] Subsequent processes also include well ion implantation of the substrate 100 of the device region 10d, and patterning the substrate 100 to form fins, wherein the zero-layer marking trench 120 is used as an alignment mark for the photolithography process during well ion implantation and fin formation.

[0092] In this embodiment, the zero-layer marking trench 120 is formed after the first mask opening 130 is formed.

[0093] Specifically, using the hard mask layer 110 as a mask, a portion of the thickness of the substrate 100 is etched along the first mask opening 130 to form the zero-layer marking trench 120.

[0094] As an example, an anisotropic dry etching process is used to etch a portion of the substrate 100 to form the zero-layer marking trench 120. The anisotropic dry etching process possesses the characteristics of anisotropic etching; its longitudinal etching rate is greater than its transverse etching rate, which is beneficial for improving the sidewall morphology quality of the zero-layer marking trench 120. Furthermore, the anisotropic dry etching process offers high controllability, facilitating precise control of the depth H3 of the zero-layer marking trench 120 (e.g., ...). Figure 16 (As shown).

[0095] It should be noted that in the subsequent photolithography process of ion implantation in the trap region and formation of fins, alignment is achieved by the signal phase difference between the top of the substrate 100 and the bottom of the zero-layer marking trench 120. Therefore, the depth H3 of the zero-layer marking trench 120 will affect the signal strength during photolithography alignment, thereby affecting the alignment accuracy.

[0096] Therefore, the depth H3 of the zero-layer marking groove 120 should not be too small or too large.

[0097] If the depth H3 of the zero-layer marking groove 120 is too large or too small, the signal strength will be weak, resulting in poor alignment accuracy and alignment deviation.

[0098] Furthermore, a dielectric layer will be filled into the zero-layer marking trench 120. After the dielectric material corresponding to the dielectric layer is filled into the zero-layer marking trench 120, the dielectric material needs to be planarized. If the depth H3 of the zero-layer marking trench 120 is too large, it will result in an excessive amount of dielectric material filling, and the grinding amount of the planarization process will be correspondingly large, which may easily cause the top surface of the dielectric layer to be concave.

[0099] Furthermore, when the depth H3 of the zero-layer marking trench 120 is too large, it can easily lead to a decrease in the stability of the etching process that forms the zero-layer marking trench 120 and the subsequent process of filling the dielectric material in the zero-layer marking trench 120. This will also affect the signal strength during photolithography alignment, thereby causing alignment deviation.

[0100] In summary, in this embodiment, the depth H3 of the zero-layer marking trench 120 is... to For example, the depth H3 of the zero-layer marking trench 120 is or

[0101] It should also be noted that during the etching of the substrate 100 to form the zero-layer marking trench 120, the first photoresist layer 111 is easily removed. Specifically, after forming the zero-layer marking trench 120, if a portion of the first photoresist layer 111 remains, the formation method further includes removing the remaining first photoresist layer 111 to prepare for subsequent processes.

[0102] In this embodiment, after removing the first photoresist layer 111, the formation method further includes: performing a well region implantation process on the substrate 100 of the device region 10d to form a well region (not shown).

[0103] The well region provides the N-type or P-type substrate required for the corresponding transistor to operate and achieves electrical isolation between adjacent transistors. The well region contains well ions, and the conductivity type of these ions is opposite to the channel conductivity type of the corresponding transistor. That is, the well ions in the well region corresponding to an NMOS transistor are P-type ions, and the well ions in the well region corresponding to a PMOS transistor are N-type ions.

[0104] In this embodiment, the channel conductivity types of the first type transistor and the second type transistor are different. Therefore, the well ions in the well regions of the first sub-device region 10p and the second sub-device region 10n have different conductivity types. As an example, the first type transistor is a PMOS transistor and the second type transistor is an NMOS transistor. Therefore, the well ions formed in the well region of the first sub-device region 10p are N-type ions, and the well ions formed in the well region of the second sub-device region 10n are P-type ions.

[0105] Specifically, a well implantation process is used to implant ions of the corresponding conductivity type into the substrate 100 of the first sub-device region 10p and the second sub-device region 10n, respectively.

[0106] It should be noted that the formation method is used to form a fin field-effect transistor, that is, the substrate 100 is subsequently patterned to form the fin. As the critical dimensions of the device continue to decrease, the linewidth of the fin becomes smaller and smaller. If well region ion implantation is performed on the fin after its formation, it is easy to damage the fin. Therefore, in this embodiment, well region ion implantation is performed before the fin is formed, thereby avoiding damage to the fin caused by the well region formation process.

[0107] Reference Figures 17 to 20 The forming method further includes: forming a second mask opening 140 in the hard mask layer 110 (e.g., Figure 20 As shown), the second mask opening 140 is located above the substrate 100 of the first sub-device region 10p.

[0108] In this embodiment, after forming the zero-layer marker trench 120, the hard mask layer 110 in the first sub-device region 10p is removed to form the second mask opening 140. Specifically, the second mask opening 140 is formed after forming the well region (not shown).

[0109] The second mask opening 140 is used to define the opening size and position of the groove subsequently formed in the substrate 100.

[0110] Reference Figure 17 and Figure 18 , Figure 17 Based on Figure 15 Top view, Figure 18 yes Figure 17 A cross-sectional view along line A1A2. In this embodiment, before forming the second mask opening 140, the forming method further includes: forming a filling in the zero-layer marking trench 120 (e.g., Figure 16A planarization layer 200 is formed on top of the hard mask layer 110 (as shown); a pattern layer 210 with a patterned opening (not shown) is formed on the planarization layer 200, the patterned opening being located above the substrate 100 of the first sub-device region 10p.

[0111] The pattern layer 210 is used as a mask for the hard mask layer 110 of the subsequent etching of the first sub-device region 10p.

[0112] The planarization layer 200 provides a flat surface for the formation of the pattern layer 210, thereby improving exposure uniformity and consequently improving the dimensional accuracy and topographic quality of the pattern openings. As an example, the material of the planarization layer 200 is spin-on carbon (SOC).

[0113] The pattern layer 210 includes an anti-reflective coating 220 and a second photoresist layer 230 located on the anti-reflective coating 220. In the photolithography process of forming the second photoresist layer 230, the anti-reflective coating 220 is used to increase the depth of field (DOF) during the photolithography process, which is beneficial to improving exposure uniformity.

[0114] In this embodiment, the anti-reflective coating 220 is made of Si-ARC (silicon-based anti-reflective coating) material. The Si-ARC layer is rich in silicon, which also helps to increase the hardness of the anti-reflective coating 220, thereby further improving the transfer accuracy of the pattern.

[0115] Specifically, after forming the second photoresist layer 230 by steps such as coating, exposure, and development, the anti-reflective coating 220 is etched using the second photoresist layer 230 as a mask, thereby forming a patterned layer 210 with a stacked structure, and a patterned opening is formed in the patterned layer 210.

[0116] Reference Figure 19 and Figure 20 , Figure 19 Based on Figure 17 Top view, Figure 20 yes Figure 19 In the cross-sectional view along line A1A2, in this embodiment, after forming the pattern layer 210 with patterned openings (not shown) and before forming the second mask opening 140, the forming method further includes: using the pattern layer 210 as a mask, removing the planarization layer 200 exposed by the patterned openings to expose the hard mask layer 110 located above the substrate 100 of the first sub-device region 10p.

[0117] The hard mask layer 110 located above the substrate 100 in the first sub-device region 10p is exposed, thereby preparing for subsequent etching of the exposed hard mask layer 110.

[0118] Therefore, continue to refer to Figure 19 and Figure 20 The step of forming the second mask opening 140 includes: removing the planarization layer 200 exposed by the pattern opening, and then removing the hard mask layer 110 exposed by the remaining planarization layer 200.

[0119] In this embodiment, after the patterned second photoresist layer 230 is formed, an anisotropic dry etching process is used to sequentially etch the antireflective coating 220, the planarization layer 200, and the hard mask layer 110, thereby accurately realizing the transfer of the pattern and improving the dimensional accuracy and morphological quality of the second mask opening 140.

[0120] Reference Figure 21 and Figure 22 , Figure 21 Based on Figure 19 Top view, Figure 22 yes Figure 21 A cross-sectional view along line A1A2 shows that in the first sub-device region 10p, a portion of the thickness of the substrate 100 has been removed, and a groove 150 is formed in the substrate 100 (e.g., ...). Figure 24 As shown), and the depth of the groove 150 is less than the depth H3 of the zero-layer marking groove 120 (as shown). Figure 16 (As shown).

[0121] The groove 150 is used to provide space for the subsequent formation of the channel material layer.

[0122] The substrate 100 of a certain thickness is subsequently etched, and the channel material layer is etched at the same time to form the fin.

[0123] In this embodiment, in the first sub-device region 10p, the etched remaining channel material layer is used to form a fin, and the etched remaining channel material layer is used to provide a channel for the first transistor.

[0124] In order to improve the signal strength during photolithography alignment, the depth H3 of the zero-layer marking trench 120 is usually large. Therefore, the depth of the groove 150 is less than the depth H3 of the zero-layer marking trench 120.

[0125] Specifically, the step of forming the groove 150 includes: using the hard mask layer 110 as a mask, along the second mask opening 140 (e.g. Figure 20 (As shown) The thickness of the etched portion of the substrate 100.

[0126] In this embodiment, an anisotropic dry etching process is used to etch a portion of the thickness of the substrate 100 to form the groove 150, thereby improving the sidewall morphology quality of the groove 150 and facilitating precise control of the depth of the groove 150.

[0127] In this embodiment, after the groove 150 is formed, the remaining pattern layer 210 and planarization layer 200 are removed. During the etching of the substrate 100 to form the groove 150, the planarization layer 200 protects the bottom and sidewalls of the zero-layer marking groove 120, thereby reducing its impact on the size and morphology of the zero-layer marking groove 120. Furthermore, removing the remaining pattern layer 210 and planarization layer 200 prepares for the subsequent formation of a channel material layer in the groove 150.

[0128] It should be noted that this embodiment uses the formation of a groove 150 in the substrate 100 of the first sub-device region 10p as an example for illustration. In other embodiments, depending on the actual situation, the groove can also be formed in the substrate of the second sub-device region. Correspondingly, the patterned opening is located above the substrate of the second sub-device region, and the second mask opening is located above the substrate of the second sub-device region. The specific process is similar to the process of forming the groove in the first sub-device region, and will not be described again here.

[0129] It should also be noted that, in other embodiments, after forming a zero-layer marking trench in the substrate of the zero-layer marking region, a hard mask layer with a first mask opening and a second mask opening can be formed, followed by the formation of the groove. For example, the formation method may include: after forming the zero-layer marking trench, filling the zero-layer marking trench with a sacrificial layer; after forming the sacrificial layer, forming a hard mask layer covering the substrate and the sacrificial layer; forming a first mask opening and a second mask opening in the hard mask layer; using the hard mask layer as a mask, etching a portion of the substrate along the second mask opening to form a groove in the substrate; after forming the groove, removing the sacrificial layer along the first mask opening.

[0130] Specifically, the sacrificial layer occupies the zero-layer marking trench to prevent the hard mask layer from covering the bottom and sidewalls of the zero-layer marking trench. Consequently, after the sacrificial layer is removed, the substrate material at the bottom and sidewalls of the zero-layer marking trench is exposed. Furthermore, since the zero-layer marking trench is filled with a sacrificial layer, the sacrificial layer can protect the sidewalls and bottom of the zero-layer marking trench during the etching of a portion of the substrate thickness.

[0131] Specifically, the material of the sacrificial layer can be an organic material, such as ODL (organic dielectric layer) or DUO (Deep UV Light Absorbing Oxide) material.

[0132] Reference Figure 23 and Figure 24 , Figure 23 Based on Figure 21 Top view, Figure 24 yes Figure 23 A cross-sectional view along line A1A2 shows that after the zero-layer marking groove 120 and groove 150 are formed, a channel material layer 300 is epitaxially grown in the zero-layer marking groove 120 and groove 150.

[0133] In device region 10d, the channel material layer 300 is used to provide the channel for the fin field-effect transistor.

[0134] Specifically, the groove 150 is formed in the substrate 100 of the first sub-device region 10p, and therefore, the channel material layer 300 is used to provide a channel for the first type of transistor. Similarly, in other embodiments, when the groove is formed in the substrate of the second sub-device region, the channel material layer is correspondingly used to provide a channel for the second type of transistor.

[0135] Therefore, the material of the channel material layer 300 is a channel material that can be used in transistors. Specifically, the material of the channel material layer 300 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials.

[0136] In this embodiment, the channel materials of the first type transistor and the second type transistor are different. Therefore, the channel material layer 300 and the substrate 100 are made of different materials.

[0137] Specifically, the groove 150 is formed in the substrate 100 of the first sub-device region 10p. The first type of transistor is a PMOS transistor. Therefore, in this embodiment, the channel material layer 300 is made of silicon germanide. By using silicon germanide for the channel of the PMOS transistor, the channel mobility of the PMOS transistor is improved. At the same time, it helps to improve the NBTI problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.

[0138] In this embodiment, the channel material layer 300 is formed by an epitaxial growth process, thereby resulting in a better formation quality of the channel material layer 300.

[0139] It should be noted that, in this embodiment, before forming the groove 150, the hard mask layer 110 is first formed, and a first mask opening 130 is formed in the hard mask layer 110. The first mask opening 130 is connected to the zero-layer marking trench 120, so that the substrate 100 material of the bottom and sidewall of the zero-layer marking trench 120 is exposed. Thus, during the epitaxial growth of the channel material layer 300 in the groove 150, the bottom and sidewall of the zero-layer marking trench 120 can also be used as the basis for epitaxial growth, thereby allowing the channel material layer 300 to also be formed on the bottom and sidewall of the zero-layer marking trench 120.

[0140] It should also be noted that in this embodiment, the hard mask layer 110 is used as a mask, and the substrate of the zero-layer marking region 10z is etched along the first mask opening 130 to form the zero-layer marking trench 120, so that the sidewall of the first mask opening 130 is flush with the sidewall of the zero-layer marking trench 120, and the first mask opening 130 is aligned with the zero-layer marking trench 120, thereby making it easy to expose the substrate 100 material at the bottom and sidewall of the zero-layer marking trench 120.

[0141] Furthermore, since the depth of the groove 150 is less than the depth H3 of the zero-layer marking groove 120 (e.g. Figure 16 As shown, after the channel material layer 300 is epitaxially grown in the groove 150, the channel material layer 300 will not completely fill the zero-layer marking groove 120. The channel material layer 300 conformally covers the bottom and sidewalls of the zero-layer marking groove 120, thereby providing space for the subsequent formation of a dielectric layer in the zero-layer marking groove 120.

[0142] In this embodiment, the hard mask layer 110 is formed on the substrate 100 surrounding the zero-layer marking trench 120 and the groove 150. Therefore, the hard mask layer 110 protects the top of the substrate 100, and the substrate 100 surrounding the zero-layer marking trench 120 and the groove 150 is not exposed to the epitaxial growth environment in which the channel material layer 300 is formed, so that the channel material layer 300 is formed only in the zero-layer marking trench 120 and the groove 150.

[0143] Accordingly, in this embodiment, the channel material layer 300 is epitaxially grown in the zero-layer marking trench 120 exposed by the first mask opening 130 and in the groove 150 exposed by the second mask opening 140.

[0144] In this embodiment, during the step of epitaxially growing the channel material layer 300 in the groove 150, the top of the channel material layer 300 in the groove 150 is higher than the top of the substrate 100.

[0145] By making the top of the channel material layer 300 in the groove 150 higher than the top of the substrate 100, preparation is made for the subsequent planarization process of the channel material layer 300 in the groove 150, thereby improving the flatness of the top surface of the remaining channel material layer 300 in the groove 150 and the substrate 100 after the planarization process, so as to facilitate the simultaneous etching of the substrate 100 and the channel material layer 300.

[0146] As an example, the top of the channel material layer 300 in the groove 150 is lower than the top surface of the hard mask layer 110, thereby appropriately reducing the amount of material removed during the subsequent planarization process of the channel material layer 300, which in turn helps to improve the flatness of the top surface of the remaining channel material layer 300 in the groove 150 after the planarization process.

[0147] Reference Figure 25 and Figure 30 The zero-layer marking trench 120 is filled to form a dielectric layer 310 located in the zero-layer marking trench 120 (e.g., ...). Figure 30 (As shown).

[0148] Subsequently, a fin mask material layer covering the substrate 100 and the dielectric layer 310 will be formed, and a core layer will be formed on the fin mask material layer. Then, a mask sidewall will be formed on the sidewall of the core layer, and the core layer will be removed. The dielectric layer 310 provides a flat surface for the formation of the fin mask material layer. Compared with the scheme of directly forming the fin mask material layer and the core layer after forming the zero-layer marking trench 120, this embodiment significantly reduces the probability of material residue forming the fin mask material layer or the core layer on the sidewall of the zero-layer marking trench 120. Accordingly, after the fin is formed, the probability of residue defects or detachment defects caused by the material residue is lower, which is beneficial to improving the performance of the semiconductor structure.

[0149] The bottom and sidewalls of the zero-layer marking trench 120 are formed with a channel material layer 300, and the dielectric layer 310 covers the channel material layer 300 located in the zero-layer marking trench 120.

[0150] The steps for forming the dielectric layer 310 are described in detail below with reference to the accompanying drawings.

[0151] Reference Figure 25 and Figure 26 , Figure 25 Based on Figure 23 Top view, Figure 26 yes Figure 25 A cross-sectional view along line A1A2 shows that the zero-layer marking trench 120 is filled with dielectric material 315, which also covers the substrate 100.

[0152] The dielectric material 315 is used to provide a process basis for the subsequent formation of the dielectric layer.

[0153] In this embodiment, a deposition process (e.g., chemical vapor deposition) is used to fill the zero-layer marking trench 120 with dielectric material 315.

[0154] In this embodiment, the dielectric material 315 also covers the hard mask layer 110 and the channel material layer 300.

[0155] The dielectric material 315 also covers the channel material layer 300, and the dielectric material 315 is also used as a buffer layer in the subsequent planarization process of the channel material layer 300, thereby improving the process window for planarization of the channel material layer 300.

[0156] The dielectric material 315 is filled in the zero-layer marking trench 120. By selecting the dielectric material 315, it is easy to obtain the signal at the bottom of the zero-layer marking trench 120 through the dielectric layer in the subsequent photolithography process, thereby reducing the impact on the signal strength during photolithography alignment. For example, in the subsequent formation of fins through a self-aligned multi-patterning process, the zero-layer marking trench 120 serves as an alignment mark during the photolithography process of forming the core layer.

[0157] Specifically, the dielectric material 315 includes one or more of silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, and silicon carbonitride. These materials have a relatively small impact on signal strength.

[0158] In this embodiment, the dielectric material 315 is silicon nitride. Silicon nitride has a high density; therefore, by selecting silicon nitride, it is beneficial to improve the anti-oxidation effect of the dielectric material 315 on the channel material layer 300, thereby improving the quality of the channel material layer 300.

[0159] Furthermore, since the hard mask layer 110 and the dielectric material 315 are made of different materials, during the subsequent planarization process of the dielectric material 315, the top of the hard mask layer 110 can be used as the stop position for the planarization process to remove a portion of the dielectric material 315, and then the remaining dielectric material 315 above the top surface of the substrate 100 can be removed, thereby improving the uniformity of the planarization process.

[0160] Reference Figures 27 to 30 , Figure 27 Based on Figure 25 Top view, Figure 28 yes Figure 27 Sectional view along the secant line A1A2, Figure 29 Based on Figure 30 Top view, Figure 30 yes Figure 29 A cross-sectional view along line A1A2 shows that the dielectric material 315 is planarized, and the dielectric material 315 above the top surface of the substrate 100 is removed, while the remaining dielectric material 315 in the zero-layer marking trench 120 is retained as the dielectric layer 310.

[0161] Specifically, such as Figure 27 and Figure 28 As shown, the dielectric material 315 is subjected to a first planarization process with the top of the hard mask layer 110 as the stop position; as Figure 29 and Figure 30 As shown, after the first planarization process, the remaining dielectric material 315 is subjected to a second planarization process until the top of the substrate 100 is exposed.

[0162] As an example, the planarization process is performed using chemical mechanical polishing (CMP). By employing CMP, global planarization is achieved across the entire wafer.

[0163] In this embodiment, during the planarization process, the hard mask layer 110 and the channel material layer 300 above the top of the substrate 100 are removed. Removing the hard mask layer 110 and the channel material layer 300 above the top of the substrate 100 during the planarization process simplifies the process steps. Furthermore, by employing a chemical mechanical polishing process, it is easy to remove both the hard mask layer 110 and the channel material layer 300 above the top of the substrate 100 simultaneously.

[0164] It should be noted that in the step of forming the dielectric layer 310 located in the zero-layer marking trench 120, the thickness of the dielectric layer 310 should not be too small or too large.

[0165] If the thickness of the dielectric layer 310 is too small, given a fixed epitaxial growth thickness of the channel material layer 300, in order for the dielectric layer 310 to fill the zero-layer marking trench 120, the depth H3 of the zero-layer marking trench 120 will be too small, which will easily weaken the signal strength during photolithography alignment. Alternatively, given a fixed depth H3 of the zero-layer marking trench 120, the epitaxial growth thickness of the channel material layer 300 needs to be increased, i.e., the thickness of the channel material layer 300 located in the zero-layer marking trench 120 needs to be increased. Since the materials of the channel material layer 310 and the substrate 100 are similar, when acquiring signals, the top of the channel material layer 310 located at the bottom of the zero-layer marking trench 120 may be mistaken for the bottom of the zero-layer marking trench 120, which will also weaken the signal strength during photolithography alignment.

[0166] If the thickness of the dielectric layer 310 is too large, the amount of dielectric material 315 filling the zero-layer marking trench 120 will be large. After the dielectric material 315 is planarized, the probability of the top surface depression problem of the dielectric layer 310 will increase.

[0167] In summary, in this embodiment, the thickness of the dielectric layer 310 is... to That is, the distance from the bottom of the dielectric layer 310 to the top of the substrate 100 is to For example, the thickness of the dielectric layer 310 is or

[0168] It should also be noted that, in the actual process, the depth H3 of the zero-layer marking trench 120, the epitaxial growth thickness of the channel material layer 300, and the thickness of the dielectric layer 310 need to be coordinated with each other so that the depth H3 of the zero-layer marking trench 120 and the thickness of the dielectric layer 310 meet the process requirements, while ensuring that the channel material layer 300 can fill the groove 150 and that the channel material layer 300 has a high quality.

[0169] Furthermore, in the process of planarizing the channel material layer 300, it is usually necessary to first cover the buffer layer, and then planarize the buffer layer and the channel material layer 300. Therefore, in this embodiment, the process of planarizing the channel material layer 300 is used to fill the zero-layer marking trench 120 with dielectric material 315 and planarize the dielectric material 315. This embodiment does not add a step of filling dielectric material 315 or a planarization step, and has high process compatibility with the double channel process.

[0170] refer to Figure 31 , Figure 31 Based on Figure 30 A cross-sectional view showing a fin mask material layer 400 forming a layer covering the substrate 100 and the dielectric layer 310.

[0171] The fin mask material layer 400 is used to provide a process basis for the subsequent formation of the fin mask layer.

[0172] The material of the fin mask material layer 400 may include one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the fin mask material layer 400 is silicon nitride.

[0173] In this embodiment, a self-aligned multi-patterning (SAMP) process is used to form the fins, increasing the density of the fins and further reducing the pitch between adjacent fins, thereby enabling the photolithography process to overcome the limitations of photolithography resolution. For example, the self-aligned multi-patterning process may include a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0174] As an example, we will use the self-aligned dual patterning process for illustration.

[0175] Continue to refer to Figure 31 A core layer 450 is formed on the fin mask material layer 400 above the dielectric layer 310 and the substrate 100 of the device region 10d, and the core layer 450 covers the top of the zero-layer marking trench 120.

[0176] The core layer 450 provides support for the subsequent formation of the mask sidewalls.

[0177] The core layer 450 will be removed subsequently; therefore, the core layer 450 is made of a material that is easily removed, and the process of removing the core layer 450 causes minimal damage to other film layers. Therefore, the material of the core layer 450 includes photoresist, amorphous carbon, silicon oxide, silicon nitride, silicon, or titanium nitride, etc. As an example, the material of the core layer 450 is silicon. Specifically, the material of the core layer 450 is amorphous silicon.

[0178] Specifically, after forming a core material layer covering the fin mask material layer 400, the core material layer is patterned using a mask to form a core layer 450 at the target location.

[0179] In this embodiment, the core layer 450 covers the top of the zero-layer marking trench 120, so that after a mask sidewall is subsequently formed on the sidewall of the core layer 450, the mask sidewall exposes the channel material layer 300 and dielectric layer 310 in the zero-layer marking trench 120, so as to prevent the formation of fins at the location of the zero-layer marking trench 120.

[0180] Continue to refer to Figure 31 A mask sidewall 470 is formed on the sidewall of the core layer 450.

[0181] The mask sidewall 470 is used as a mask for etching the fin mask material layer 400.

[0182] The materials of the mask sidewall 470 and the core layer 450 have an etching selectivity ratio, thereby reducing the damage to the mask sidewall 470 caused by the process of removing the core layer 450. Consequently, the morphological quality and dimensional accuracy of the mask sidewall 470 are guaranteed, thereby improving the morphological quality and dimensional accuracy of the subsequent fins.

[0183] In this embodiment, the core layer 450 is made of silicon, and correspondingly, the mask sidewall 470 is made of silicon nitride. Silicon and silicon nitride have a high etching selectivity, and silicon nitride has high hardness and density, enabling the mask sidewall 470 to function effectively as an etching mask.

[0184] Specifically, a mask sidewall material layer is formed by a deposition process to conformally cover the core layer 450 and the fin mask material layer 400, and the mask sidewall material layer is etched using a maskless etching process to form a mask sidewall 470.

[0185] In this embodiment, after forming the mask sidewall 470, the process further includes removing the core layer 450.

[0186] The core layer 450 is removed to prepare for etching the fin mask material layer 400. As an example, a wet etching process is used to remove the core layer 450.

[0187] Reference Figures 32 to 33 , Figure 32 It is a top view. Figure 33 yes Figure 32 In the cross-sectional view along line A1A2, after removing the core layer 450, the fin mask material layer 400 is etched using the mask sidewall 470 as a mask to form a fin mask layer 480. Using the fin mask layer 480 as a mask, a portion of the thickness of the substrate 100 is etched. The remaining substrate 100 after etching serves as the substrate 500. The protrusions on the substrate 500 located in the device region 10d serve as fins 510. During the etching of the substrate 100, a portion of the thickness of the dielectric layer 310 is also etched simultaneously.

[0188] The pattern is first transferred to the fin mask material layer 400, and then the pattern is transferred to the substrate 100 using the fin mask layer 480, thereby improving the accuracy of pattern transfer.

[0189] In this embodiment, a channel material layer 300 is also formed in the groove 150. Correspondingly, in the step of etching a portion of the thickness of the substrate 100, the channel material layer 300 and the portion of the thickness of the substrate 100 are etched.

[0190] Accordingly, in this embodiment, in the device region 10d where the channel material layer 300 is formed, the fin 510 includes a bottom fin layer 510b and a channel layer 510t located on top of the bottom fin layer 510b. The material of the channel layer 510t is different from the material of the bottom fin layer 510b. Specifically, the bottom fin layer 510b and the substrate 500 are an integral structure.

[0191] It should be noted that the mask sidewall 470 is also formed around the zero-layer marking trench 120. Therefore, after the fin 510 is formed, the fin 510 is also formed in the zero-layer marking region 10z and surrounds the zero-layer marking trench 120. The fin 510 in the zero-layer marking region 10z is a pseudo-fin, and the fin 510 in the zero-layer marking region 10z is not used to form a transistor. In other embodiments, the fin in the zero-layer marking region can also be removed by fin cutting according to process requirements.

[0192] It should also be noted that during the etching of the fin mask material layer 400 and the substrate 100, the mask sidewalls 470 are easily damaged, and the fin mask layer 480 is also damaged to some extent during the etching of the substrate 100. As an example, after the fin 510 is formed, the mask sidewalls 470 are removed, and a portion of the thickness of the fin mask layer 480 is still retained on the top of the fin 510.

[0193] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a device region and a zero-layer marking region, the device region including a first sub-device region for forming a first type transistor and a second sub-device region for forming a second type transistor, the channel materials of the first type transistor and the second type transistor being different; The fin protrudes from the substrate of the device region. In the first sub-device region or the second sub-device region, the fin includes a bottom fin layer and a channel layer located on top of the bottom fin layer. The material of the channel layer is different from the material of the bottom fin layer. A zero-layer marking trench is located within the substrate of the zero-layer marking region, and the top of the zero-layer marking trench is flush with the top of the substrate; A dielectric layer is filled in the zero-layer marking trench; The channel layer is also located between the sidewall of the zero-layer marking trench and the dielectric layer, and between the bottom of the zero-layer marking trench and the dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The first type of transistor and the second type of transistor have different channel conductivity types.

3. The semiconductor structure as described in claim 1, characterized in that, The channel layer material includes silicon, silicon germanide, germanium, or group III-V semiconductor materials.

4. The semiconductor structure as described in claim 1, characterized in that, The distance from the bottom of the zero-layer marking groove to the top of the fin is 600 Å to 1500 Å.

5. The semiconductor structure as described in claim 1, characterized in that, The dielectric layer is made of one or more of silicon nitride, silicon oxide, silicon oxycarbonate, silicon oxynitride, and silicon carbonitride.

6. The semiconductor structure as described in claim 2, characterized in that, The distance from the bottom of the dielectric layer to the top of the fin is 100 Å to 1000 Å.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a device region and a zero-layer marking region for forming zero-layer marking trenches; The zero-layer marking groove is formed within the substrate of the zero-layer marking area; Fill the zero-layer marking trench to form a dielectric layer located in the zero-layer marking trench; A fin mask material layer is formed covering the substrate and the dielectric layer; A core layer is formed on the fin mask material layer above the dielectric layer and the substrate of the device region, the core layer covering the top of the zero-layer marking trench; A mask sidewall is formed on the sidewall of the core layer; Remove the core layer; After removing the core layer, the fin mask material layer is etched using the mask sidewall as a mask to form a fin mask layer. Using the fin mask layer as a mask, a portion of the substrate is etched, and the remaining substrate after etching serves as the substrate. The protrusions on the substrate in the device region serve as fins, and during the etching of the substrate, a portion of the dielectric layer is also etched.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of filling the zero-layer marking trench to form a dielectric layer located in the zero-layer marking trench includes: filling the zero-layer marking trench with a dielectric material, the dielectric material further covering the substrate; The dielectric material is planarized by removing the dielectric material above the top surface of the substrate, and retaining the remaining dielectric material in the zero-layer marking trench as the dielectric layer.

9. The method for forming a semiconductor structure as described in claim 7 or 8, characterized in that, In the step of providing the substrate, the device region includes a first sub-device region for forming a first type transistor and a second sub-device region for forming a second type transistor, wherein the channel materials of the first type transistor and the second type transistor are different; After forming the zero-layer marking trench and before forming the dielectric layer, the method further includes: removing a portion of the thickness of the substrate in the first sub-device region or the second sub-device region, forming a groove in the substrate, and the depth of the groove is less than the depth of the zero-layer marking trench; After forming the zero-layer marking trench and groove and before forming the dielectric layer, the method further includes: epitaxially growing a channel material layer in the zero-layer marking trench and groove; In the step of forming the dielectric layer, the dielectric layer covers the channel material layer located in the zero-layer marking trench; In the step of etching a portion of the substrate, the channel material layer and a portion of the substrate are etched.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming the groove, the method further includes: forming a hard mask layer on the substrate; forming a first mask opening in the hard mask layer, the sidewall of the first mask opening being flush with the sidewall of the zero-layer marking trench; and forming a second mask opening in the hard mask layer, the second mask opening being located above the substrate of the first sub-device area or the second sub-device area. The step of forming the groove includes: using the hard mask layer as a mask, etching a portion of the thickness of the substrate along the opening of the second mask; The channel material layer is epitaxially grown in the zero-layer marking trench exposed by the first mask opening and in the groove exposed by the second mask opening; Before forming the fin mask material layer covering the substrate and dielectric layer, the forming method further includes: removing the hard mask layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, After the first mask opening is formed, the zero-layer marking trench is formed, and after the zero-layer marking trench is formed, the second mask opening is formed; The step of forming the zero-layer marking trench includes: using the hard mask layer as a mask, etching a portion of the thickness of the substrate along the opening of the first mask; The step of forming the second mask opening includes: after forming the zero-layer marking trench, removing the hard mask layer in the first sub-device area or the second sub-device area.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before forming the second mask opening, the method further includes: forming a planarization layer that fills the zero-layer marking trench and covers the top of the hard mask layer; forming a patterned layer with a patterned opening on the planarization layer, the patterned opening being located above the substrate of the first sub-device region or the second sub-device region; using the patterned layer as a mask, removing the planarization layer exposed by the patterned opening to expose the hard mask layer located above the substrate of the first sub-device region or the second sub-device region; In the step of forming the second mask opening, after removing the planarization layer exposed by the pattern opening, the hard mask layer exposed by the remaining planarization layer is removed. Before epitaxially growing the channel material layer in the zero-layer marking trenches and grooves, the method further includes: removing the pattern layer and planarization layer.

13. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the zero-layer marking trench, and before forming the dielectric layer located in the zero-layer marking trench, the method further includes: performing well region implantation on the substrate of the device region.

14. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of forming the zero-layer marking trench within the substrate of the zero-layer marking region, the depth of the zero-layer marking trench is 600 Å to 1500 Å.

15. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of forming a dielectric layer located in the zero-layer marking trench, the material of the dielectric layer includes one or more of silicon nitride, silicon oxide, silicon oxycarbonate, silicon oxynitride, and silicon carbonitride.

16. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming a dielectric layer located in the zero-layer marking trench, the thickness of the dielectric layer is 100 Å to 1000 Å.

17. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first type of transistor and the second type of transistor have different channel conductivity types.

18. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the channel material layer includes silicon, silicon germanide, germanium, or group III-V semiconductor materials.

Images