Semiconductor device

Abstract

A semiconductor device includes a gate pattern on a substrate and including a sequentially stacked gate dielectric layer, gate electrode, and gate cap pattern; a gate spacer on a sidewall of the gate pattern; a source / drain pattern in the substrate; a contact pad on the source / drain pattern; a source / drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source / drain contact, wherein the gate spacer includes a first segment between the gate electrode and the contact pad, a second segment extending from the first segment and between the gate electrode and the source / drain contact, and a third segment on the second segment, the buried dielectric pattern being between the third segment and the source / drain contact, not being between the first segment and the contact pad, and not being between the second segment and the source / drain contact.

Description

Technical Field

[0001] The implementation methods relate to semiconductor devices and methods of manufacturing them. Background Technology

[0002] Semiconductor devices are likely to be beneficial in the electronics industry due to their small size, versatility, and low manufacturing cost. Semiconductor devices can include semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices that have both storage and logic elements. Summary of the Invention

[0003] The implementation can be achieved by providing a semiconductor device comprising: a substrate; a gate pattern on the substrate, the gate pattern including sequentially stacked gate dielectric layers, gate electrodes, and gate cap patterns; gate spacers covering the sidewalls of the gate pattern; source / drain patterns on the side of the gate pattern in the substrate; contact pads on the source / drain patterns, the contact pads having a top surface lower than the top surface of the gate electrode; source / drain contacts on the contact pads; and a buried dielectric pattern between the gate spacers and the source / drain contacts. The buried dielectric pattern surrounds the source / drain contact, wherein the gate spacer includes: a first segment between the gate electrode and the contact pad, the first segment having a first width; a second segment extending from the first segment and between the gate electrode and the source / drain contact, the second segment having a first width; and a third segment on the second segment, the third segment having a second width less than the first width, the buried dielectric pattern being between the third segment and the source / drain contact, and the buried dielectric pattern not being present between the first segment and the contact pad and not being present between the second segment and the source / drain contact.

[0004] The implementation can be achieved by providing a semiconductor device comprising: a substrate; active fins protruding from the substrate; a gate pattern extending across the active fins, the gate pattern including sequentially stacked gate dielectric layers, gate electrodes, and gate cap patterns; source / drain patterns in the substrate at the sides of the gate pattern; contact pads on the source / drain patterns, the contact pads having a top surface lower than the top surface of the gate electrode; source / drain contacts on the contact pads; gate spacers including a first segment between the gate pattern and the contact pads, a second segment between the gate pattern and the source / drain contacts, and a third segment on the second segment, the third segment having a width smaller than the width of the second segment; a first dielectric spacer and a second dielectric spacer between the second segment and the source / drain contacts; and a third dielectric spacer and a buried dielectric pattern between the third segment and the source / drain contacts, wherein the width of the buried dielectric pattern is greater than the width of the first dielectric spacer, greater than the width of the second dielectric spacer, and greater than the width of the third dielectric spacer.

[0005] The implementation can be achieved by providing a semiconductor device comprising: a substrate; a gate pattern on the substrate including a gate dielectric layer, a gate electrode, and a gate cap pattern sequentially stacked, the gate pattern having first and second sidewalls opposite to each other; a source / drain pattern in the substrate adjacent to the first sidewall of the gate pattern; contact pads on the source / drain pattern, the contact pads having a top surface lower than the top surface of the gate electrode; source / drain contacts on the contact pads; a first gate spacer covering the first sidewall of the gate pattern; and a second gate spacer covering the second sidewall of the gate pattern, wherein the first gate spacer includes a first segment between the gate pattern and the contact pads, a second segment between the gate pattern and the source / drain contacts, and a third segment on the second segment, the third segment having a width smaller than the width of the second segment, and the width of the third segment being smaller than the width of the second gate spacer.

[0006] The implementation can be achieved by providing a method for manufacturing a semiconductor device, the method comprising: forming a plurality of gate patterns and a plurality of gate spacers covering the sidewalls of the gate patterns, the gate patterns extending across a substrate, and each gate pattern including a sequentially stacked gate dielectric layer, a gate electrode, and a gate cap pattern; forming at least one source / drain pattern on the substrate between the gate spacers; forming contact pads on the at least one source / drain pattern; and forming a plurality of first dielectric spacers covering the lower sidewalls of adjacent gate spacers on the contact pads and exposing adjacent gate spacers on the contact pads. The upper sidewall of the gate spacer; performing a lateral etching process to remove a portion of the gate spacer, thereby forming a plurality of recessed regions on the gate spacer, the portions being adjacent to the upper sidewall of the gate spacer and not covered by a first dielectric spacer; forming a buried dielectric pattern that fills the space between the recessed regions and the gate spacer; removing a portion of the gate cover pattern from the gate pattern to form a gate contact hole exposing the gate electrode; removing a portion of the buried dielectric pattern to form a source / drain contact hole exposing the contact pads; and forming a gate contact in the gate contact hole and a source / drain contact in the source / drain contact hole. Attached Figure Description

[0007] The features will be clear to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1A A plan view of a semiconductor device according to some embodiments is shown.

[0009] Figure 1B It shows along Figure 1A The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0010] Figure 2A It shows Figure 1B A magnified view of part P1.

[0011] Figure 2B It shows Figure 1A A perspective view of portion P2 of the first gate pattern depicted in the image.

[0012] Figure 2C It shows Figure 1B A partial enlarged view of P1.

[0013] Figures 3A to 15A The manufacturing of having Figure 1A A planar diagram of the stages in a method for manufacturing semiconductor devices.

[0014] Figures 3B to 15B It shows the respective along Figures 3A to 15A The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0015] Figure 16A A plan view of a semiconductor device according to some example embodiments is shown.

[0016] Figure 16B It shows along Figure 16A The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0017] Figure 17 It shows along Figure 1A Alternate cross-sectional views taken from lines A-A', B-B', and C-C'.

[0018] Figure 18A It shows along Figure 1A Alternate cross-sectional views taken from lines A-A', B-B', and C-C'.

[0019] Figure 18B It shows along Figure 1A Alternate cross-sectional views taken from lines A-A', B-B', and C-C'. Detailed Implementation

[0020] Figure 1A A plan view of a semiconductor device according to some embodiments is shown. Figure 1B It shows along Figure 1A The cross-sectional views taken from lines A-A', B-B', and C-C'. Figure 1B The semiconductor device can be an example corresponding to the FinFET device.

[0021] Reference Figure 1A and Figure 1BThe active fin AF can protrude from the substrate 1. The substrate 1 may include a device isolation layer 3 on the side of the active fin AF. The active fin AF may have a top surface and upper sidewalls that are higher than the top surface of the device isolation layer 3. The substrate 1 may be a single-crystal silicon substrate or a silicon-on-insulator (SOI) substrate. The device isolation layer 3 may have a single layer or multiple layers, including, for example, a silicon oxide layer, a silicon nitride layer, or a silicon nitride layer. When viewed in a plan view, the active fin AF may have a linear or strip shape extending in a first direction X (e.g., longitudinally). When used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0022] The gate pattern GP can extend or extend across the active fin AF in a second direction Y intersecting the first direction X. The gate pattern GP can include a first gate pattern GP (1), a second gate pattern GP (2), and a third gate pattern GP (3) arranged side-by-side (e.g., spaced apart) in the first direction X. Each gate pattern GP can include a gate dielectric layer GO, a gate electrode GE, and a gate cap pattern GC stacked sequentially. The gate dielectric layer GO can include a silicon oxide layer or a high-k dielectric layer with a dielectric constant greater than that of the silicon oxide layer. The high-k dielectric layer can include a metal oxide layer, such as an aluminum oxide layer.

[0023] The gate electrode GE may include a layer of metal, such as tungsten, copper, or aluminum. In one implementation, the gate electrode GE and the gate dielectric layer GO may include a work function layer, a diffusion interruption layer, etc., between them. The diffusion interruption layer may include, for example, a titanium nitride layer or a metal nitride layer. The gate cap pattern GC may include, for example, a silicon nitride layer.

[0024] The gate pattern GP may have sidewalls, each covered by a gate spacer GS. The gate spacer GS may comprise a silicon nitride layer or a two- or three-layer structure comprising a silicon nitride layer and a silicon oxide layer. The gate dielectric layer GO may extend between the gate electrode GE and the gate spacer GS and may contact (e.g., directly contact) the gate cap pattern GC.

[0025] Each active fin (AF) may have a fin recess region (R1) on one side of the gate spacer (GS). A source / drain pattern (SD) may be correspondingly located within the fin recess region (R1). Adjacent source / drain patterns (SD) may be in contact with each other. The source / drain pattern (SD) may be an epitaxial layer whose material is the same as that of the substrate 1. In one implementation, the source / drain pattern (SD) may be a silicon epitaxial layer. The source / drain pattern (SD) may further include a material different from that of the substrate 1. In one implementation, the source / drain pattern (SD) may be a silicon-germanium epitaxial layer. The source / drain pattern (SD) may be doped with n-type or p-type impurities. In one implementation, the source / drain pattern (SD) may be doped with phosphorus, arsenic, or boron. The source / drain pattern (SD) may be formed from an epitaxial layer having multiple regions with different impurity concentrations, or from multiple epitaxial layers with different impurity concentrations.

[0026] The interlayer dielectric layer IL can cover the gate pattern GP, ​​the gate spacer GS, and the source / drain pattern SD. In one implementation, the interlayer dielectric layer IL can be a multilayer comprising a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, or a porous low-k dielectric layer.

[0027] The interlayer dielectric layer IL can have pad vias SH1 that expose the source / drain pattern SD. For example... Figure 1B As shown in the cross-section taken along line A-A', the sidewalls of the gate spacer GS can be exposed in the pad hole SH1. The pad hole SH1 can accommodate the contact pad CA that contacts the source / drain pattern SD. Figure 1B As shown in the cross-section taken along line A-A', the contact pad CA may have sidewalls that contact (e.g., directly contact) the sidewalls of the gate spacer GS. The contact pad CA may include metal. The metal may include, for example, tungsten, aluminum, cobalt, titanium, or molybdenum. Figure 1B As shown in the cross section taken along line C-C', the sidewall of the contact pad CA can contact the interlayer dielectric layer IL (e.g., direct contact).

[0028] The pad hole SH1 can also accommodate a buried dielectric pattern 25p on the contact pad CA. The buried dielectric pattern 25p can include, for example, SiOC (silicon oxide carbide). The buried dielectric pattern 25p can include a source / drain contact hole CH. A source / drain contact LA can be located within the source / drain contact hole CH. The source / drain contact LA can penetrate the buried dielectric pattern 25p and can contact (e.g., directly contact) the contact pad CA. The source / drain contact LA can have a lower width smaller than the width of the contact pad CA (e.g., it can have a trapezoidal cross-section).

[0029] The gate cap pattern GC may include a gate contact hole GH that exposes the gate electrode GE. The gate contact hole GH may accommodate a gate contact CB that contacts (e.g., in direct contact) the gate electrode GE. The gate contact CB may contact (e.g., in direct contact) the inner wall of the gate spacer GS and the top surface of the gate dielectric layer GO.

[0030] The source / drain contact LA and the gate contact CB can comprise the same conductive material. In one implementation, the source / drain contact LA and the gate contact CB can comprise a crystalline metal or an amorphous metal. The metal can comprise, for example, tungsten, aluminum, cobalt, titanium, or molybdenum. The metal included in the source / drain contact LA can have or be in the same crystalline state as the metal included in the gate contact CB.

[0031] like Figure 1B As shown in the cross-section taken along line A-A', a portion of the first, second, and third dielectric spacers 21s, 23a, and 23b, and a portion of the buried dielectric pattern 25p, are located between the gate spacer GS and the source / drain contact LA. Figure 1B As shown in the cross section taken along line C-C', the first dielectric spacer 21s and the fourth dielectric spacer 23c can be located between the buried dielectric pattern 25p and the interlayer dielectric layer IL.

[0032] The second, third, and fourth dielectric spacers 23a, 23b, and 23c may comprise the same material. The second, third, and fourth dielectric spacers 23a, 23b, and 23c may comprise, for example, the same first material as the first material of the gate spacer GS. The first dielectric spacer 21s may comprise a second material different from the first material of the gate spacer GS and the second, third, and fourth dielectric spacers 23a, 23b, and 23c. The second material may have etch selectivity relative to the first material. In one implementation, the first material may comprise a silicon nitride, and the second material may comprise silicon oxide, SiOC, or Al2O3.

[0033] In one implementation, the second material may have an electrical constant different from that of the first material. The electrical constant of the second material may be smaller than that of the first material. In one implementation, a parasitic capacitance may be provided between the gate contact CB and the source / drain contact LA.

[0034] Figure 2A It shows Figure 1B A magnified view of part P1. Figure 2B It shows Figure 1A A perspective view of portion P2 of the first gate pattern depicted in the image. Figure 2C It shows Figure 1B A partial enlarged view of P1.

[0035] Reference Figure 1A , Figure 1B , Figure 2A and Figure 2B Each gate pattern GP may include a first sidewall GPS1 and a second sidewall GPS2 that are opposite to each other. The gate spacer GS may include a first gate spacer GS(1) covering the first sidewall GPS1 and a second gate spacer GS(2) covering the second sidewall GPS2. The first gate spacer GS(1) may have a cross-section whose shape is the same as or different from that of the second gate spacer GS(2).

[0036] In one implementation method, refer to Figure 2A and Figure 2B The first gate spacer GS(1) covering the first sidewall GPS1 of the first gate pattern GP(1) may have a different shape than the second gate spacer GS(2) covering the second sidewall GPS2 of the first gate pattern GP(1). The first gate spacer GS(1) may be partially recessed at its upper portion. In one implementation, the first gate spacer GS(1) may have a spacer recess region R2 at its upper portion. In one implementation, the first gate spacer GS(1) may include a first segment 30a between the gate electrode GE and the contact pad CA, a second segment 30b between the gate electrode GE and the source / drain contact LA, and a third segment 30c on the second segment 30b. The first, second, and third segments 30a, 30b, and 30c may be integrally connected to each other to form the first gate spacer GS(1).

[0037] The first segment 30a may have a first width W1. The second segment 30b may have a second width W2 (e.g., measured in the same direction as the first width W1). The second width W2 may be the same as the first width W1 at the lower part of the second segment 30b, and may decrease with increasing upward distance away from the lower part of the second segment 30b. The third segment 30c may have a third width W3 (e.g., measured in the same direction as the first width W1), and the third width W3 may be smaller than the first width W1 and the second width W2. In one implementation, the third segment 30c may not be exposed (e.g., it may be covered).

[0038] A portion of the top surface 30bu of the second segment 30b. The spacer recess R2 may have a bottom surface corresponding to the top surface 30bu of the second segment 30b. The spacer recess R2 may have a sidewall corresponding to the sidewall of the third segment 30c.

[0039] The spacer recess R2 may not be above or within the second gate spacer GS (2) of the second sidewall GPS2 covering the first gate pattern GP (1). The second gate spacer GS (2) may have a fourth width W4 at its top surface (e.g., as measured in the same direction as the first width W1). The fourth width W4 may be greater than the third width W3.

[0040] Reference Figure 2A The second segment 30b may have a sidewall covering the first dielectric spacer 21s. The first dielectric spacer 21s may have a sidewall covering the second dielectric spacer 23a. The third segment 30c may have a sidewall covering the third dielectric spacer 23b. The third dielectric spacer 23b may be spaced apart from the first dielectric spacer 21s and the second dielectric spacer 23a. A buried dielectric pattern 25p may be between the third dielectric spacer 23b and the source / drain contact LA. The buried dielectric pattern 25p may cover the top ends of the first and second dielectric spacers 21s and 23a (e.g., the ends of the first and second dielectric spacers 21s and 23a away from the substrate 1). The buried dielectric pattern 25p may cover the top surface 30bu of the second segment 30b and the side surface of the third dielectric spacer 23b.

[0041] In one implementation, such as Figure 2C As shown, the second dielectric spacer 23a and the third dielectric spacer 23b can be integrally connected to each other. The upper part of the second dielectric spacer 23a or the lower part of the third dielectric spacer 23b can extend between the second segment 30b and the buried dielectric pattern 25p, and can contact (e.g., directly contact) the top surface 30bu of the second segment 30b.

[0042] The third dielectric spacer 23b may have a sixth width W6 (or thickness), for example, in the same direction as the first width W1 being measured. The buried dielectric pattern 25p may have a fifth width W5, for example, in the same direction as the first width W1 being measured, between the third dielectric spacer 23b and the source / drain contact LA. The fifth width W5 may be greater than the sixth width W6. Each of the first, second, and fourth dielectric spacers 21s, 23a, and 23c may have the same or similar width (e.g., maximum thickness) as the sixth width W6.

[0043] Return to reference Figure 1A and Figure 1B The gate spacer GS covering the opposite sidewall of the second gate pattern GP(2) can have the same Figure 2A and Figure 2BThe buried dielectric pattern 25p has the same shape as the first gate spacer GS(1) depicted in the figure. When viewed in a plan view, the buried dielectric pattern 25p may have a closed curve or loop shape or annular shape around the source / drain contact LA. The buried dielectric pattern 25p may have a portion called a dielectric spacer between the third dielectric spacer 23b and the source / drain contact LA.

[0044] A semiconductor device according to one embodiment can be configured such that not only the gate spacer GS, but also the dielectric spacers 21s, 23a, and 23b, and the buried dielectric pattern 25p are located between the gate contact CB and the source / drain contact LA. Electrical short circuits between the source / drain contact LA and one or more of the gate electrode GE and gate contact CB can be prevented. In one implementation, the buried dielectric pattern 25p and the first dielectric spacer 21s may comprise a material different from that of the gate spacer GS and different from that of the second and third dielectric spacers 23a and 23b. This reduces the parasitic capacitance between the source / drain contact LA and one or more of the gate electrode GE and gate contact CB, thereby minimizing signal interference. As a result, the reliability of the semiconductor device can be improved.

[0045] Figures 3A to 15A The manufacturing of having Figure 1A A planar diagram of the stages in a method for manufacturing semiconductor devices. Figures 3B to 15B It shows the respective along Figures 3A to 15B The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0046] Reference Figure 3A and Figure 3B The substrate 1 can be etched to form an active fin AF from or within the substrate 1. A device isolation layer 3 can be formed on the substrate 1 and on the sides of the active fin AF. A dummy gate pattern can be formed to extend across the active fin AF, and a gate spacer GS can be formed to cover the sidewalls of the dummy gate pattern. The active fin AF exposed on the side of the gate spacer GS can be etched to form a fin recess region R1. Selective epitaxial growth and in-situ doping processes can be performed to form a source / drain pattern SD on the corresponding fin recess region R1. The dummy gate pattern can be removed, and a gate pattern GP can be formed accordingly at the location where the dummy gate pattern has been removed. The gate pattern GP can include first, second, and third gate patterns GP(1), GP(2), and GP(3). Each gate pattern GP can include a sequentially stacked gate dielectric layer GO, a gate electrode GE, and a gate cap pattern GC. An interlayer dielectric layer IL can be formed to cover the gate pattern GP and the source / drain pattern SD. The interlayer dielectric layer IL may include, for example, tetraethyl orthosilicate (TEOS).

[0047] Reference Figure 4A and Figure 4B A first mask pattern MK1 can be formed on the interlayer dielectric layer IL. The first mask pattern MK1 may have a first opening OP1. The first opening OP1 may be formed wide to overlap with at least three gate patterns GP and the source / drain patterns SD between the at least three gate patterns GP. The first mask pattern MK1 may include a material with etch selectivity relative to the interlayer dielectric layer IL, such as a photoresist, polysilicon, spin-on hard mask (SOH), spin-on carbon (SOC), or amorphous carbon layer (ACL). The first mask pattern MK1 can be used as an etch mask to perform an anisotropic etch process, wherein the interlayer dielectric layer IL is anisotropically etched to form a first trench TR1 (above or in the interlayer dielectric layer IL) exposing the top surface of the gate cap pattern GC, and a plurality of pad holes SH1 are also formed below or at the bottom of the first trench TR1. The pad holes SH1 may correspondingly expose the source / drain patterns SD between the gate patterns GP. The pad holes SH1 may expose the sidewalls of the gate spacers GS. Anisotropic etching can also etch the upper part of the source / drain pattern SD, such as... Figure 4B The cross-section taken along line C-C' is shown. The pad hole SH1 can be formed using a self-aligned contact (SAC) etching method.

[0048] In the fabrication of other semiconductor devices, if the first opening of the first mask pattern is to be formed as a plurality of vias with correspondingly overlapping source / drain patterns, and if the first mask pattern is to be used to perform an etching process, the first trench may not be formed; only pad vias can be formed between the gate patterns. For example, a portion of the interlayer dielectric layer may remain on the gate pattern. In such a process, reducing the spacing between the gate patterns can increase the occurrence of unopened pad vias.

[0049] In contrast, according to one embodiment, because the first opening OP1 can be formed wide and the interlayer dielectric layer IL can be formed as a first trench TR1 partially connecting the pad hole SH1, etchant can be satisfactorily supplied when the pad hole SH1 is formed, which helps to reduce the occurrence of unopened pad holes SH1. According to one embodiment, process defects can be reduced to improve yield and increase the reliability of semiconductor devices.

[0050] Reference Figure 4A , Figure 4B , Figure 5A and Figure 5BThe first mask pattern MK1 can be removed to expose the top surface of the interlayer dielectric layer IL. A conductive layer can be formed on the entire surface of the substrate 1, and the first trench TR1 and pad via SH1 can be filled with the conductive layer. A chemical mechanical polishing (CMP) process can be performed to remove the interlayer dielectric layer IL and the conductive layer on the gate cap pattern GC, thereby exposing the top surface of the gate cap pattern GC. The conductive layer can undergo an etch-back process to form contact pads CA that fill the lower part of the pad via SH1. The contact pads CA can be formed with a top surface lower than the top surface of the gate electrode GE. On the contact pads CA, the sidewalls of the gate spacer GS can be exposed, and similarly, the sidewalls of the interlayer dielectric layer IL can be exposed. Figure 5A In the image, for clarity, the source / drain patterns SD on both sides of the contact pad CA in the second direction Y are shown. (See image) Figure 5B As shown, this portion of the source / drain pattern SD is located below the interlayer dielectric layer IL and is not covered by the contact pad CA.

[0051] Reference Figure 5A , Figure 5B , Figure 6A and Figure 6B A first spacer layer 21 can be conformally formed on the entire surface of substrate 1. The first spacer layer 21 can be formed of a material (e.g., silicon oxide or Al2O3) that has etch selectivity relative to the gate spacer GS. The first spacer layer 21 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). A second mask pattern MK2 with a second opening OP2 can be formed on the first spacer layer 21. The position and shape of the second opening OP2 can be almost identical to the position and shape of the first opening OP1. The second mask pattern MK2 can be used as an etching mask to perform an anisotropic etching process on the first spacer layer 21, thereby forming a first dielectric spacer 21s on the contact pad CA that partially covers the inner wall of the pad hole SH1 (or the sidewall of the gate spacer GS). The first dielectric spacer 21s can expose the upper sidewall and top surface of the gate spacer GS.

[0052] Similar to the first opening OP1, the second opening OP2 of the second mask pattern MK2 can be formed wider to help prevent the aforementioned unopened problem in the current step.

[0053] Reference Figure 6A , Figure 6B , Figure 7A and Figure 7BThe gate spacer GS can undergo a lateral etching process to form a spacer recess region R2 on the gate spacer GS. During this stage, a portion of the gate cap pattern GC can also be etched to round the corners of the gate cap pattern GC. The gate spacer GS can have a portion protected by a first dielectric spacer 21s, and the protected portion may not be etched. The formation of the spacer recess region R2 can enlarge the upper part of the pad via SH1. Therefore, any unopened issues caused by narrow spacing in subsequent processes can be reduced or prevented. The gate spacer GS exposed to the second opening OP2 can be formed with a reference... Figure 2A and Figure 2B The discussion focuses on the first, second, and third paragraphs, 30a, 30b, and 30c.

[0054] Reference Figure 7A , Figure 7B , Figure 8A and Figure 8B After the second spacer layer is conformally formed on the entire surface of the substrate 1, an anisotropic etching process can be performed. Therefore, second, third, and fourth dielectric spacers 23a, 23b, and 23c can be formed. The second dielectric spacer 23a can be formed to cover the sidewalls of the first dielectric spacer 21s on the gate spacer GS, and the third dielectric spacer 23b can be formed to cover the sidewalls of the spacer recess region R2. The fourth dielectric spacer 23c can be formed to cover the sidewalls of the second mask pattern MK2 and the sidewalls of the first spacer layer 21. Figure 8B As shown in the cross section taken along line C-C', the fourth dielectric spacer 23c can extend to cover the sidewalls of the interlayer dielectric layer IL and the sidewalls of the first dielectric spacer 21s.

[0055] Reference Figure 8A , Figure 8B , Figure 9A and Figure 9B A buried dielectric layer 25 can be formed on the entire surface of substrate 1 to fill pad holes SH1 and the second opening OP2. The buried dielectric layer 25 can be formed of a material exhibiting excellent filling characteristics and etch selectivity relative to the gate cap pattern GC. In one implementation, the buried dielectric layer 25 can be formed of SiOC.

[0056] Reference Figure 9A , Figure 9B , Figure 10A and Figure 10BA chemical mechanical polishing (CMP) process can be performed to remove portions of the first spacer layer 21, the second mask pattern MK2, and the buried dielectric layer 25 on the gate cap pattern GC, thereby forming a buried dielectric pattern 25p in the pad via SH1. The formation of the buried dielectric pattern 25p exposes the top surface of the interlayer dielectric layer IL and the top surface of the gate cap pattern GC. The buried dielectric pattern 25p can cover the spacer recess region R2.

[0057] Reference Figure 10A , Figure 10B , Figure 11A and Figure 11B A third mask pattern MK3 can be formed on the interlayer dielectric layer IL. The third mask pattern MK3 may include a third opening OP3 that exposes the top surface of the gate cap pattern GC. The third opening OP3 may be formed to have a width in the first direction X that is larger than the width of the gate cap pattern GC below it. Therefore, the third opening OP3 can partially expose the buried dielectric pattern 25p and the gate spacer GS.

[0058] Reference Figure 11A , Figure 11B , Figure 12A and Figure 12B The third mask pattern MK3 can be used as an etching mask to etch the gate cap pattern GC, thereby forming the gate contact hole GH that exposes the gate electrode GE. In this step, the buried dielectric pattern 25p and the third dielectric spacer 23b can also be partially etched. The gate contact hole GH can be formed using a self-aligned contact (SAC) etching method. Therefore, misalignment of the gate contact CB, which will be discussed below, can be prevented.

[0059] Reference Figure 12A , Figure 12B , Figure 13A and Figure 13B The third mask pattern MK3 can be removed. A fourth mask pattern MK4 can be formed on the interlayer dielectric layer IL. The fourth mask pattern MK4 can fill the gate contact via GH and can include a fourth opening OP4 that partially exposes the buried dielectric pattern 25p. The fourth mask pattern MK4 can be formed from a spin-on hard mask (SOH) with excellent filling properties. The fourth opening OP4 can overlap with the corresponding pad via SH1.

[0060] Reference Figure 13A , Figure 13B , Figure 14A and Figure 14B The fourth mask pattern MK4 can be used as an etching mask to partially remove the buried dielectric pattern 25p, thereby forming the source / drain contact via CH on the top surface of the exposed contact pad CA. For example... Figure 14BAs shown in the cross-section taken along line A-A', the source / drain contact hole CH can expose the sidewalls of the second dielectric spacer 23a. Additionally, the buried dielectric pattern 25p can be partially retained in the spacer recess region R2. When the source / drain contact hole CH is formed, the second dielectric spacer 23a can protect the first dielectric spacer 21s and the gate spacer GS, thereby preventing the first dielectric spacer 21s and the gate spacer GS from being etched. Therefore, an electrical short circuit between the subsequently formed gate contact CB and the source / drain contact LA can be prevented. The source / drain contact hole CH can be formed using a self-aligned contact (SAC) etching method. As a result, misalignment of the source / drain contact LA, which will be discussed below, can be prevented.

[0061] Reference Figure 14A , Figure 14B , Figure 15A and Figure 15B The fourth mask pattern MK4 can be removed to expose the gate electrode GE in the gate contact hole GH. The fourth mask pattern MK4 can be removed by an ashing process. In one implementation, a conductive layer can be formed on the entire surface of the substrate 1 to fill the gate contact hole GH and the source / drain contact hole CH. A chemical mechanical polishing (CMP) process can be performed to remove the conductive layer on the interlayer dielectric layer IL, thereby forming the gate contact CB in the gate contact hole GH and the source / drain contact LA in the source / drain contact hole CH, as shown. Figure 1A and Figure 1B As shown. The CMP process can also partially remove the upper portion of the interlayer dielectric layer IL, the upper portion of the gate spacer GS, the upper portions of the third and fourth dielectric spacers 23b and 23c, and the upper portion of the buried dielectric pattern 25p. In summary, semiconductor devices can be... Figure 1A and Figure 1B Manufactured as shown.

[0062] According to one embodiment, the method for manufacturing semiconductor devices not only helps prevent unopened holes but also helps prevent electrical short circuits. Furthermore, contact holes can be formed using a self-aligned contact (SAC) etching method, thereby preventing contact misalignment. Therefore, the yield and reliability of semiconductor devices can be improved.

[0063] Figure 16A A plan view of a semiconductor device according to some example embodiments is shown. Figure 16B It shows along Figure 16A The cross-sectional views taken from lines A-A', B-B', and C-C'. Figure 16B The semiconductor device can be an example corresponding to the FinFET device.

[0064] Reference Figure 16A and Figure 16BThe semiconductor device according to this embodiment may further include a fifth dielectric spacer 32. For example... Figure 16B As shown in the cross-section taken along line A-A', the fifth dielectric spacer 32 can cover the inner wall of the gate contact hole GH. The fifth dielectric spacer 32 can be located between the gate contact CB and the gate spacer GS. Additionally, as... Figure 16B As shown in the cross-section taken along line A-A', the fifth dielectric spacer 32 can be located between the second dielectric spacer 23a and the source / drain contact LA, and between the buried dielectric pattern 25p and the source / drain contact LA. Figure 16B As shown in the cross-section taken along line B-B', the fifth dielectric spacer 32 can be located between the gate contact CB and the gate cap pattern GC. Figure 16B As shown in the cross-section taken along line C-C', the fifth dielectric spacer 32 can be located between the buried dielectric pattern 25p and the source / drain contact LA. The fifth dielectric spacer 32 can be formed of a silicon oxide layer, a silicon nitride layer, or a silicon nitride layer. Other configurations can be referenced. Figure 1A , Figure 1B , Figure 2A and Figure 2B Those that are the same or similar in the discussion.

[0065] Can manufacture Figure 16A and Figure 16B The semiconductor device allows the third spacer layer to be conformally formed across the entire surface of substrate 1, and then anisotropically etched to form the fifth dielectric spacer 32. Other processes can be referenced. Figures 3A to 15B Those that are the same or similar in the discussion.

[0066] Figure 17 It shows along Figure 1A The alternative cross-sectional views are taken from lines A-A', B-B', and C-C'.

[0067] Reference Figure 17 It can be seen from Figure 1B The semiconductor device omits the second, third, and fourth dielectric spacers 23a, 23b, and 23c. In one implementation, the first dielectric spacer 23s can directly contact the source / drain contact LA. The buried dielectric pattern 25p between the source / drain contact LA and the gate contact CB can directly contact the source / drain contact LA and can directly contact the gate spacer GS. Other configurations may be referenced. Figure 1A and Figure 1B Those that are the same or similar in the discussion. Figure 17 Semiconductor devices can be simplified by omitting... Figure 8A and Figure 8B The process and subsequent execution Figures 9A to 15B It is manufactured using advanced technology.

[0068] Figure 18A It shows along Figure 1A The alternative cross-sectional views are taken from lines A-A', B-B', and C-C'. Figure 18A Examples that could correspond to multi-bridge channel field-effect transistor (MBCFET) devices.

[0069] Reference Figure 18A Semiconductor patterns CP, spaced apart and stacked sequentially, can be placed on an active fin AF. The semiconductor patterns CP can be spaced apart from the active fin AF. The semiconductor patterns CP can include, for example, silicon. Gate electrodes GE can cover the top and side surfaces of the semiconductor patterns CP. The semiconductor patterns CP can have different widths than each other.

[0070] A portion of the gate electrode GE may extend between the semiconductor patterns CP. The gate dielectric layer GO may surround the semiconductor patterns CP. The semiconductor patterns CP may have sidewalls that contact (e.g., direct contact) with the source / drain patterns SD. Other configurations may be referenced. Figure 1B Those that are the same or similar in the discussion.

[0071] Figure 18B It shows along Figure 1A The alternative cross-sectional views are taken from lines A-A', B-B', and C-C'. Figure 18B The semiconductor device can be an example corresponding to a multi-bridge channel field-effect transistor (MBCFET) device.

[0072] Reference Figure 18B The semiconductor device according to this embodiment may further include a barrier dielectric pattern BP beneath the semiconductor pattern CP, the barrier dielectric pattern BP surrounding a portion of the gate electrode GE and between the gate dielectric layer GO and the source / drain pattern SD. The barrier dielectric pattern BP may comprise a material different from the material of the gate dielectric layer GO, such as a silicon nitride layer. The barrier dielectric pattern BP helps prevent bridging between the source / drain pattern SD and a portion of the gate electrode GE, thus improving the reliability of the semiconductor device. Other configurations may be referenced above. Figure 18A Those that are the same or similar in the discussion.

[0073] In summary, with the advanced development of the electronics industry, semiconductor devices are becoming increasingly highly integrated. For example, semiconductor devices are increasingly exhibiting high reliability, high speed, and / or multifunctionality. To meet these characteristics, semiconductor devices may become more complex and integrated.

[0074] A semiconductor device according to one embodiment may include a plurality of dielectric spacers between a gate spacer and a source / drain contact, thereby reducing or preventing electrical short circuits and parasitic capacitances between the source / drain contact and one or more of the gate electrode and gate contact, which can improve the reliability of the semiconductor device.

[0075] The semiconductor device manufacturing method according to one embodiment can reduce process failures and improve yield.

[0076] One or more implementations can provide semiconductor devices with improved reliability.

[0077] One or more implementations may provide a method for manufacturing semiconductor devices that improves yield.

[0078] Exemplary embodiments have been disclosed herein, and while specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing of this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0079] Korean Patent Application No. 10-2020-0175051, entitled "Semiconductor Device and Method of Manufacturing Thereof," filed with the Korean Intellectual Property Office on December 15, 2020, is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: substrate; A gate pattern on the substrate, the gate pattern comprising a gate dielectric layer, a gate electrode, and a gate cap pattern stacked in sequence; Gate spacers covering the sidewalls of the gate pattern; Source / drain patterns on the side of the gate pattern in the substrate; The contact pads on the source / drain pattern have a top surface that is lower than the top surface of the gate electrode; Source / drain contacts on the contact pads; as well as A buried dielectric pattern between the gate spacer and the source / drain contact, the buried dielectric pattern surrounding the source / drain contact. in: The gate spacer includes: A first segment, between the gate electrode and the contact pad, has a first width; A second segment extends from the first segment and lies between the gate electrode and the source / drain contact, the second segment having the first width; and The third segment on the second segment has a second width that is smaller than the first width. The buried dielectric pattern is located between the third segment and the source / drain contact, and The buried dielectric pattern is not present between the first segment and the contact pad, nor is it present between the second segment and the source / drain contact. The buried dielectric pattern is in contact with the top surface of the second segment and spaced apart from the third segment.

2. The semiconductor device of claim 1, wherein the buried dielectric pattern comprises SiOC.

3. The semiconductor device of claim 1, further comprising a first dielectric spacer between the second segment and the source / drain contact, the first dielectric spacer being spaced apart from the third segment. The first dielectric spacer includes a material that is different from the material of the buried dielectric pattern and different from the material of the gate spacer.

4. The semiconductor device of claim 3, wherein: The buried dielectric pattern has a third width, and The first dielectric spacer has a fourth width that is smaller than the third width.

5. The semiconductor device of claim 3, further comprising a second dielectric spacer between the first dielectric spacer and the source / drain contact. The second dielectric spacer includes a material that is different from the material of the buried dielectric pattern and different from the material of the first dielectric spacer.

6. The semiconductor device of claim 5, further comprising a third dielectric spacer between the third segment and the buried dielectric pattern, the third dielectric spacer exposing a portion of the top surface of the second segment. The third dielectric spacer comprises the same material as the second dielectric spacer.

7. The semiconductor device of claim 6, further comprising a fifth dielectric spacer between the buried dielectric pattern and the source / drain contact and between the second dielectric spacer and the source / drain contact.

8. The semiconductor device of claim 7, further comprising: A gate contact that penetrates the gate cap pattern and contacts the gate electrode; as well as A sixth dielectric spacer between the gate contact and the gate spacer, The sixth dielectric spacer comprises the same material as the fifth dielectric spacer.

9. The semiconductor device of claim 1, further comprising a third dielectric spacer between the third segment and the buried dielectric pattern, the third dielectric spacer exposing a portion of the top surface of the second segment. The third dielectric spacer comprises a material different from the material of the buried dielectric pattern.

10. The semiconductor device of claim 1, wherein: The first segment contacts the contact pad. The second segment is spaced apart from the source / drain contact, and The third segment is spaced apart from the source / drain contacts.

11. A semiconductor device, comprising: substrate; Active fins protruding from the substrate; A gate pattern extending across the active fin, the gate pattern comprising a sequentially stacked gate dielectric layer, gate electrode, and gate cap pattern; Source / drain patterns on the side of the gate pattern in the substrate; The contact pads on the source / drain pattern have a top surface that is lower than the top surface of the gate electrode; Source / drain contacts on the contact pads; The gate spacer includes a first segment between the gate pattern and the contact pad, a second segment between the gate pattern and the source / drain contact, and a third segment on the second segment, the third segment having a width smaller than that of the second segment; The first dielectric spacer and the second dielectric spacer between the second segment and the source / drain contact; as well as The third dielectric spacer and buried dielectric pattern between the third segment and the source / drain contact The width of the buried dielectric pattern is greater than the width of the first dielectric spacer, greater than the width of the second dielectric spacer, and greater than the width of the third dielectric spacer.

12. The semiconductor device of claim 11, wherein the width of the bottom surface of the source / drain contact is smaller than the width of the contact pad.

13. The semiconductor device of claim 11, wherein the buried dielectric pattern surrounds the source / drain contact.

14. The semiconductor device of claim 11, wherein: The buried dielectric pattern includes a material that is different from the material of the first dielectric spacer and different from the material of the second dielectric spacer, and The second dielectric spacer and the third dielectric spacer comprise the same material.

15. The semiconductor device of claim 11, wherein the buried dielectric pattern covers the top end of the first dielectric spacer, the top end of the second dielectric spacer, and the sidewall of the third dielectric spacer.

16. A semiconductor device, comprising: substrate; A gate pattern on the substrate and comprising a gate dielectric layer, a gate electrode, and a gate cap pattern stacked in sequence, the gate pattern having a first sidewall and a second sidewall opposite to each other; Source / drain patterns in the substrate adjacent to the first sidewall of the gate pattern; The contact pads on the source / drain pattern have a top surface that is lower than the top surface of the gate electrode; Source / drain contacts on the contact pads; A first gate spacer covers the first sidewall of the gate pattern; A second gate spacer covers the second sidewall of the gate pattern. in: The first gate spacer includes a first segment between the gate pattern and the contact pad, a second segment between the gate pattern and the source / drain contact, and a third segment on the second segment, the third segment having a width smaller than that of the second segment. The width of the third segment is less than the width of the second gate spacer. The first dielectric spacer and the second dielectric spacer between the second segment and the source / drain contact; as well as The third dielectric spacer and buried dielectric pattern between the third segment and the source / drain contact The width of the buried dielectric pattern is greater than the width of the first dielectric spacer, greater than the width of the second dielectric spacer, and greater than the width of the third dielectric spacer.

17. The semiconductor device of claim 16, wherein the buried dielectric pattern surrounds the source / drain contact.

18. The semiconductor device of claim 16, wherein: The buried dielectric pattern includes a material that is different from the material of the first dielectric spacer and different from the material of the second dielectric spacer, and The second dielectric spacer and the third dielectric spacer comprise the same material.

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