A semiconductor structure, memory cell and memory array

Abstract

The application provides a semiconductor structure, a storage unit and a storage array, and nT-MRAM can be realized through a relatively simple structure. A plurality of transistors connected with a plurality of MTJs are connected through a connecting pad, so that n transistors can drive the same MTJ, and meanwhile, the storage density is not reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, memory cell, and memory array. Background Technology

[0002] Magnetic random access memory (MRAM) is a non-volatile magnetic random access memory with high read and write speeds, high integration density, and a high number of repeated read and write cycles. It is widely used in current computers and other devices.

[0003] In existing technologies, MRAM specifically uses magnetic tunnel junctions (MTJs) to read, write, and store information ("0" or "1"). Each MTJ can be driven by multiple transistors, thereby increasing the drive current when driving the MTJ. This type of MRAM, where n transistors drive one MTJ, is also called nT-MRAM. However, multiple transistors occupy a large area, reducing the storage density. Summary of the Invention

[0004] This application provides a semiconductor structure, a memory cell, and a memory array that can realize nT-MRAM with a relatively simple structure. In this structure, transistors connected to multiple MTJs are connected by a connection pad, which enables n transistors to drive the same MTJ while ensuring that the storage density is not reduced.

[0005] This application provides a semiconductor structure, including: a plurality of discrete active regions located on a substrate; a connection pad, the connection pad including a first portion and a second portion, the first portion and the second portion respectively connecting to the ends of adjacent active regions, the first portion extending along a first direction and the second portion extending along a second direction; and a magnetic tunnel junction connected to the connection pad.

[0006] Optionally, the first portion and the second portion are respectively connected to the same end of the active region.

[0007] Optionally, the connecting pad extends in a stepped shape.

[0008] Optionally, the active region is elongated and extends in a third direction.

[0009] Optionally, it also includes: word lines that pass through the active region; and two word lines that divide the single active region into two ends of the active region and the middle of the active region.

[0010] Optionally, it may also include: a selection line, which is connected to the middle of the active region.

[0011] Optionally, the selection line is a broken line, and the extension direction of the selection line is the same as the extension direction of the character line.

[0012] Optionally, it may also include: a first plug, the first plug connecting the middle of the active area and the selection line; and a second plug, the second plug connecting the end of the active area and the connecting pad, wherein the height of the first plug is lower than the height of the second plug.

[0013] Optionally, the selection line is a straight line, and the extension direction of the selection line is perpendicular to the extension direction of the character line.

[0014] Optionally, it further includes: a first plug, the first plug connecting the middle of the active area and the selection line; and a second plug, the second plug connecting the end of the active area and the connecting pad, wherein the height of the first plug is the same as the height of the second plug.

[0015] Optionally, the first plug and the second plug are formed in the same process step.

[0016] Optionally, it also includes: a bit line, which is connected to the magnetic tunnel junction, and the bit line extends in the same direction as the second direction.

[0017] Optionally, the angle between the second direction and the third direction is in the range of 15° to 35°.

[0018] This application also provides a memory cell, including: a transistor and a memory structure, wherein one end of the transistor is connected to one end of the memory structure; the other end of the transistor, the gate of the transistor, the other end of the memory structure, and the end of the transistor connected to the memory structure are respectively the first end, the second end, the third end, and the fourth end of the memory cell.

[0019] Optionally, the storage structure includes at least one of a magnetic tunnel junction, a capacitive storage structure, a resistive storage structure, and a phase-change storage structure.

[0020] This application also provides a storage array, comprising: M*N storage cells forming an M-row N-column array, where M and N are both positive integers greater than or equal to 2; M bit lines, corresponding one-to-one with the storage cells in the M rows, with the third end of each storage cell in the same row connected to the corresponding bit line; N word lines, corresponding one-to-one with the storage cells in the N columns, with the second end of each storage cell in the same column connected to the corresponding word line; wherein the fourth end of the storage cell in the X-row Y-column is connected to the fourth end of the storage cell in the P-row Q-column, where X equals P minus A, and Y equals Q minus B.

[0021] Optionally, A and B are equal.

[0022] Optionally, both A and B are 1.

[0023] Optionally, there are N selection lines, each corresponding to one of the N columns of storage cells, with the first end of the storage cell in the same column connected to the corresponding selection line.

[0024] Optionally, the fourth ends of the storage cells that differ by A in row and by B in column are all connected together.

[0025] In summary, in the semiconductor structure provided by this application, multiple transistors are connected by connection pads, enabling n transistors to drive one MTJ while ensuring that the storage density is not reduced. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of a semiconductor structure according to an embodiment provided in this application; Figure 2 A schematic diagram illustrating the extension direction of the semiconductor structure provided in this application; Figure 3 This is a schematic diagram of the structure of the semiconductor D1 layer provided in this application; Figure 4 This is a schematic diagram of the structure of the semiconductor D2 layer provided in this application; Figure 5 This is a schematic diagram of the structure of the semiconductor D3 layer provided in this application; Figure 6 This is a schematic diagram of the structure of the semiconductor D4 layer provided in this application; Figure 7 This is a schematic diagram of the structure of the semiconductor D5 layer provided in this application; Figure 8 This is a schematic diagram of the structure of the semiconductor D6 layer provided in this application; Figure 9 A schematic diagram of the structure of an embodiment of the first plug provided in this application; Figure 10 A schematic diagram of the structure of an embodiment of the second plug provided in this application; Figure 11 This is a schematic diagram of another embodiment of the semiconductor D3 layer provided in this application; Figure 12 A schematic diagram of another embodiment of the first plug provided in this application; Figure 13 A schematic diagram of another embodiment of the second plug provided in this application; Figure 14 A schematic diagram of the storage unit provided in this application; Figure 15 A schematic diagram of the storage array provided in this application; Figure 16 This is a schematic diagram of the control level of the magnetic tunnel junction provided in this application. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] This application provides a semiconductor structure, such as Figure 1As shown, the semiconductor structure 1 includes a memory array, and the memory array includes multiple magnetic tunnel junctions (MTJs). The multiple MTJs can be arranged in rows and columns in an array form, and each MTJ can be used for reading and writing information. Figure 1 Taking any rectangular region 20 within the semiconductor structure 1 as an example, the rectangular region 20 includes: a plurality of discrete active regions 101, a plurality of connection pads 102, and a plurality of magnetic tunnel junctions (MTJs) 103 located on a substrate (not shown in the figure).

[0031] As an example, a plurality of discrete active regions 101 can be formed in a semiconductor substrate, including a silicon substrate, an SOI substrate, a gallium nitride substrate, silicon carbide, gallium carbide, etc. Specifically, the active regions 101 can be formed on the semiconductor substrate by a patterning process, and trench isolation structures are formed between the active regions 101.

[0032] refer to Figure 2 Multiple active regions 101 in the semiconductor substrate (not shown) are arranged in an array with equal spacing. Specifically, the multiple active regions 101 are elongated strips and extend along a third direction C.

[0033] A connecting pad 102 includes a first portion 1021 and a second portion 1022. The first portion 1021 and the second portion 1022 are respectively connected to the ends of adjacent active regions 101. The first portion 1021 extends along a first direction A, and the second portion 1022 extends along a second direction B. The ends of the first portion 1021 and the second portion 1022 can be connected to the same end of the same active region 101; the other ends of the first portion 1021 and the second portion 1022 are respectively connected to the ends of different active regions 101. Specifically, as shown... Figure 2As shown, the connecting pad 102 is located above the arrayed active regions 101. The first part 1021 and the second part 1022 of the connecting pad 102 are elongated. The first part 1021 of the connecting pad 102 extends in the first direction A, and its two ends are respectively connected to the ends of the active regions 101 labeled ② and ③. The second part 1022 of the connecting pad 102 extends in the second direction B, and its two ends are respectively connected to the ends of the active regions 101 labeled ① and ②. At this time, the same end of the active region 101 labeled ② can be connected to the first part 1021 and the second part 1022 respectively. The included angle β between the second direction B and the third direction C can be an acute angle, specifically between 15° and 35°. The angle α between the first direction A and the second direction B can be 90°; for example, in other possible implementations, the angle α between the first direction A and the second direction B can also be less than 90 degrees, and the implementation method is the same as the principle, so it will not be described again.

[0034] Optionally, the connecting pads extend in a stepped shape. Specifically, connecting pads connecting three adjacent ends of the active region 101 form a stepped unit, and multiple stepped units are connected to form a stepped-extending connecting pad. See also... Figure 2 The first part 1021 and the second part 1022 form a stepped unit, and multiple stepped units on multiple active regions are connected to form a stepped connecting pad.

[0035] Optional, such as Figure 2 As shown, the active regions are arranged in an alternating array. The first part 1021 is connected to the ends of adjacent active regions 101 in different columns, and the second part 1022 is connected to the ends of adjacent active regions 101 in the same column.

[0036] A magnetic tunnel junction (MTJ) 103 can be connected to a connecting pad 102; as an example, a single connecting pad 102 can be connected to multiple magnetic tunnel junctions 103. Figure 1 Taking a rectangular area 20 comprising 39 magnetic tunnel knots 103 arranged in 14 rows and 11 columns as an example, each magnetic tunnel knot 103 is disposed above the connecting pad 102 between two bends extending in a stepped manner and connected to the connecting pad 102. Specifically, the magnetic tunnel knots 103 may be disposed above the midpoint of the first portion 1021 and the second portion 1022 of the connecting pad 102 and connected to the first portion 1021 and the second portion 1022 of the connecting pad 102, respectively.

[0037] Optional, such as Figure 2As shown, multiple magnetic tunnel junctions 103 can be arranged in an array along a first direction A and a second direction B, with the spacing between adjacent magnetic tunnel junctions 103 in each row along the first direction A being the same, and the spacing between adjacent magnetic tunnel junctions 103 in each column along the second direction B being the same.

[0038] The magnetic tunnel junction 103 can be connected to the ends of multiple active regions 101 connected to the connection pad 102 through the connection pad 102. The ends of the active regions 101 can be the source or drain of a transistor (the transistor can be NMOS). In this case, a single magnetic tunnel junction 103 can be driven by multiple transistors.

[0039] like Figure 1 and Figure 2 A schematic diagram of semiconductor structure 1 is shown. To realize the function of semiconductor structure 1, word lines, bit lines, and select lines are also required to control the magnetic tunnel junction 103. The following section combines... Figures 3-8 The layered design structure of a semiconductor structure 1 provided in the embodiments of this application will be described, such as... Figures 3-8 China also Figure 1 The rectangular region 20 of the semiconductor structure 1 is used as an example.

[0040] First layer (D1): Figure 3 This is a schematic diagram of the structure of the semiconductor structure D1 layer provided in this application. Figure 3 Within layer D1 shown, several discrete active regions 101 are arranged at intervals. A description of the active regions 101 can be found in [reference needed]. Figure 1 and Figure 2 Specifically, several discrete active regions 101 can be formed in a silicon substrate using a patterning method. The patterning method includes, but is not limited to, semiconductor fabrication processes such as SADP and SAQP. A trench isolation structure is formed between the active regions 101.

[0041] Second layer (D2): Figure 4 This is a schematic diagram of the structure of the semiconductor structure D2 layer provided in this application. Figure 4Multiple word lines 104 are arranged in parallel within the D2 layer shown. These word lines 104 control the transistors connected to the magnetic tunnel junction 103. As an example, the word lines 104 of the D2 layer can be positioned above the D1 layer; in another example, the word lines 104 of the D2 layer can also pass through the active region 101 of the D1 layer. A single active region 101 can be divided into two ends and a middle section by two adjacent word lines 104. Specifically, the active region 101 and the two passing word lines 104 form two transistors (MOS); the two transistors share a common source, with the middle section of the active region 101 serving as the common source, and the two ends of the active region 101 serving as the drains of the two transistors; or the two transistors share a common drain, with the middle section of the active region 101 serving as the common drain, and the two ends of the active region 101 serving as the sources of the two transistors. In one example, the word lines 104 can be buried gate lines.

[0042] Optionally, word line 104 may extend along the first direction A. A single word line 104 may pass through multiple active regions 101.

[0043] Third layer (D3): Figure 5 This is a schematic diagram of the structure of the semiconductor structure D3 layer provided in this application. Figure 5 Multiple select lines 105 are provided within the D3 layer shown. Each select line 105 can be a zigzag shape and extends in the same direction as the word line 104. For example, the select line 105 can extend along a first direction A. The D3 layer can be positioned above the D1 layer. The select lines 105 can be connected to the center of the active region 101 via contact plugs. Specifically, if the center of the active region 101 is the common source or common drain of two transistors, then the select lines 105 can be connected to the common source or common drain of the two transistors via contact plugs. For example... Figure 9 As shown, the first plug 107 can be located between layers D1 and D3, and the middle part of the active region 101 can be connected to the select line 105 through the first plug 107. A single select line 105 can be connected to the middle part of multiple active regions 101.

[0044] Fourth layer (D4): Figure 6 This is a schematic diagram of the structure of the semiconductor structure D4 layer provided in this application. Figure 6 Multiple connection pads 102 are provided within layer D4 as shown. A description of the connection pads 102 can be found in [reference needed]. Figure 1 and Figure 2 .

[0045] Optionally, the connection pad 102 and the end of the active region 101 can be connected via a second plug. Figure 10 A schematic diagram of an embodiment of the second plug provided in this application is shown below. Figure 10As shown, the second plug 108 is located between layers D1 and D4. One end of the second plug 108 is connected to the end of the active region 101, and the other end of the second plug 108 is connected to the connecting pad 102. Figure 9 and Figure 10 The height of the first plug 107 can be lower than the height of the second plug 108 so that the selection line 105 is located below the connection pad 102, so as to ensure that the subsequent connection of the magnetic tunnel junction 103 is not interfered with; in other examples, the height of the first plug 107 can be higher than the height of the second plug 108.

[0046] Fifth floor (D5): Figure 7 This is a schematic diagram of the structure of the semiconductor structure D5 layer provided in this application, where... Figure 7 Multiple magnetic tunnel junctions 103 are arranged within the D5 layer shown. As an example, the magnetic tunnel junctions 103 are located above and connected to the connecting pad 102. The magnetic tunnel junction 103 includes a free layer, a fixed layer, and a tunnel barrier layer, and uses the magnetic polarization directions of the free layer and the fixed layer to store information. For example, when the magnetic polarization directions of the free layer and the fixed layer are parallel, the resistance is low, representing the information "1"; when the magnetic polarization directions of the free layer and the fixed layer are anti-parallel, the resistance is high, representing the information "0".

[0047] Sixth floor (D6): Figure 8 This is a schematic diagram of the semiconductor structure D6 layer provided in this application, where... Figure 8 Multiple bit lines 106 are arranged within the D6 layer shown, and the bit lines 106 extend along the second direction B. For example, for Figure 1 The 11 rows of magnetic tunnel junctions 103 distributed in the middle can be respectively arranged with 11 bit lines in the D6 layer, and each bit line 106 is used to connect such as Figure 1 as well as Figure 2 The upper end of the magnetic tunnel junction 103 in the second direction B.

[0048] Alternatively, this application also provides another semiconductor structure that can be used as such Figures 3-8 The equivalent replacement of semiconductor structure 1 provided in the paper, wherein, Figure 11 This is a schematic diagram of another embodiment of the semiconductor D3 layer provided in this application, as shown below. Figure 11Multiple selection lines 105 are provided within layer D3. Each selection line 105 is a straight line, and its extension direction is perpendicular to the extension direction of the word line 104. As an example, the selection lines 105 can extend along the second direction B, and a single selection line 105 can be connected to the middle of the active area 101 in the same column. The structures of layers D1, D2, D4, D5, and D6 are the same as in the previous embodiment and will not be described again.

[0049] Optionally, the select line 105 and the active area 101 can be connected via a first plug, wherein, Figure 12 A schematic diagram of another embodiment of the first plug provided in this application is shown below. Figure 12 As shown, the first plug 107 is located between layers D1 and D3. The middle part of the active area 101 can be connected to the select line 105 through the first plug 107. Specifically, the middle parts of the active areas 101 in the same column can be connected to the same select line 105. The connecting pad 102 can be connected to the end of the adjacent active area 101 through a second plug. Figure 13 A schematic diagram of another embodiment of the second plug provided in this application is shown below. Figure 13 As shown, the second plug 108 is located between the D1 layer and the D4 layer. One end of the second plug 108 is connected to the end of the active region 101, and the other end of the second plug 108 is connected to the connecting pad 102.

[0050] Optionally, combined Figure 12 and Figure 13 The height of the first plug 107 can be equal to the height of the second plug 108, in which case the D3 layer and the D4 layer can be located in the same layer. As an example, the first plug 107 and the second plug 108 can be formed in the same process step. For instance, conductive materials can be simultaneously formed in the first through-hole of the first plug and the second through-hole of the second plug to form the first plug and the second plug. The conductive material can be at least one of TiN, W, TaN, Co, Al, WN, polysilicon, and silicon germanide.

[0051] Another embodiment of this application provides a memory cell, including: a transistor and a memory structure, one end of the transistor being connected to one end of the memory structure; the other end of the transistor, the gate of the transistor, the other end of the memory structure, and the end of the transistor connected to the memory structure are respectively the first end, the second end, the third end, and the fourth end of the memory cell.

[0052] like Figure 14As shown, the transistor MOS includes a gate 2, and its two ends are the source and drain, respectively. When one end of the transistor MOS is the source, the other end is the drain; or, when one end of the transistor MOS is the drain, the other end is the source. The transistor can be an NMOS or a PMOS.

[0053] Optionally, the storage structure 5 may include at least one of a magnetic tunnel junction, a capacitor storage structure, a resistive storage structure, and a phase-change storage structure. As an example, when the storage structure 5 is a magnetic tunnel junction (MTJ), the MTJ may include a free layer, a fixed layer, and a tunnel barrier layer. Specifically, the fixed layer of the MTJ is connected to the source of the transistor MOS; the free layer of the MTJ can serve as the third terminal 3 of the storage cell; the drain of the transistor MOS can serve as the first terminal 1 of the storage cell; the gate of the transistor MOS can serve as the second terminal 2 of the storage cell; and the source of the transistor MOS connected to the fixed layer of the MTJ can serve as the fourth terminal 4 of the storage cell.

[0054] Another embodiment of this application provides a storage array, comprising: M*N storage cells forming an M-row N-column array, where M and N are both positive integers greater than or equal to 2; M bit lines, corresponding one-to-one with the storage cells in the M rows, with the third end of each storage cell in the same row connected to the corresponding bit line; N word lines, corresponding one-to-one with the storage cells in the N columns, with the second end of each storage cell in the same column connected to the corresponding word line; wherein the fourth end of the storage cell in the X-row Y-column is connected to the fourth end of the storage cell in the P-row Q-column, where X equals P minus A, and Y equals Q minus B.

[0055] like Figure 15As shown, M*N storage units form an M-row N-column array, where M and N are both positive integers greater than or equal to 2; there are M bit lines BL, namely BL[1] to BL[M]; the M bit lines correspond one-to-one with the storage units in the M rows, and the third end 3 of the storage units in the same row is connected to the corresponding bit line BL. For example, the third end 3 of the storage units in the first row is connected to the bit line BL[1] of the first row, and the third end 3 of the storage units in the Xth row is connected to the bit line BL[X] of the Xth row; there are N word lines WL, namely WL[1] to WL[N], and the N word lines correspond one-to-one with the storage units in the N columns. The second end 2 of the storage units in the same column is connected to the corresponding word line WL. For example, the second end 2 of the storage units in the first column is connected to the word line WL[1] of the first column. The second end 2 of the storage unit in column X is connected to the word line WL[X] of column X; wherein, the fourth end 4 of the storage unit in row X, column Y is connected to the fourth end 4 of the storage unit in row P, column Q, where X equals P minus A, and Y equals Q minus B.

[0056] As an example, A and B are equal. Specifically, the fourth end 4 of the storage unit in row X and column Y is connected to the fourth end 4 of the storage unit in row X+B and column Y+B. B can be any integer such as 1, 2, 3, etc. For example, the fourth end 4 of the storage unit in row 10 and column 10 is connected to the fourth end 4 of the storage unit in row 11 and column 11; or the fourth end 4 of the storage unit in row 10 and column 10 is connected to the fourth end 4 of the storage unit in row 12 and column 12.

[0057] Optionally, N selection lines SL correspond one-to-one with the N columns of storage cells, and the first terminal 1 of the storage cell in the same column is connected to the corresponding selection line SL. For example... Figure 15 As shown, the first end 1 of the storage cell in the first column is connected to the selection line SL[1] of the first column, and the first end 1 of the storage cell in the Yth column is connected to the selection line SL[Y] of the Yth column.

[0058] Optionally, the fourth segments 4 of storage cells that differ by A in row and by B in column are all connected together. For example, when both A and B are 1, the fourth segment 4 of the storage cell in row M, column 1, the fourth segment 4 of the storage cell in row M-1, column 2, the fourth segment 4 of the storage cell in row M-2, column 3, and so on are all connected together.

[0059] Figure 16 This is a schematic diagram illustrating the control level of the magnetic tunnel junction provided in this application. As an example, when storage structure 5 is a magnetic tunnel junction, the magnetic tunnel junction in the storage cell at row i and column j is denoted as M. ij When the magnetic tunnel junction M ij When performing the write operation "1" (WRITE1), the magnetic tunneling junction M is set. ijThe connected bit line BL[i] in the i-th row is high, the other bit lines BL[others] are low, the word lines WL[jk] to WL[j+k] in columns jk to j+k are high, the other word lines WL[others] are low, and the select line SL is low; when the magnetic tunnel junction M ij When performing the write operation "0" (WRITE0), the bit line BL is set to low, the word lines WL[jk] to WL[j+k] of columns jk to j+k are set to high, the other word lines WL[others] are set to low, the selection lines SL[jk] to SL[j+k] of columns jk to j+k corresponding to WL[jk] to WL[j+k] are set to high, and the other selection lines SL[others] are set to low; when the magnetic tunnel junction M ij When performing a read operation, set the magnetic tunneling junction M. ij The connected bit line BL[i] in the i-th row is high, the other bit lines BL[others] are low, the word lines WL[jk] to WL[j+k] in columns jk to j+k are high, the other word lines WL[others] are low, and the select line SL is low. In this example, the same magnetic tunnel junction M is operated. ij The number of transistors is j+k-(jk)+1, that is, 2k+1 transistors operate one magnetic tunnel junction.

[0060] This application connects transistors that are connected to multiple memory structures, enabling multiple transistors to drive the same memory structure while ensuring that the memory density is not reduced.

[0061] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized by, include: Several discrete active regions located on the substrate; A connecting pad, the connecting pad comprising a first portion and a second portion, the first portion and the second portion respectively connecting to the ends of adjacent active regions, the first portion extending along a first direction and the second portion extending along a second direction; A magnetic tunnel junction, wherein the magnetic tunnel junction is connected to the connecting pad; A word line passes through the active region; and two word lines are connected to a single active region, dividing the single active region into two ends and a middle portion of the active region; The first part and the second part are respectively connected to the same end of the active region; The connecting pad extends in a stepped shape.

2. The semiconductor structure according to claim 1, characterized in that, The active region is elongated and extends in a third direction.

3. The semiconductor structure of claim 1, wherein, Also includes: The selection line is connected to the middle of the active region.

4. The semiconductor structure according to claim 3, characterized in that, The selection line is a broken line, and the extension direction of the selection line is the same as the extension direction of the character line.

5. The semiconductor structure of claim 4, wherein, Also includes: A first plug, the first plug being connected to the middle of the active region and the selection line; The second plug connects the end of the active area to the connecting pad, and the height of the first plug is lower than the height of the second plug.

6. The semiconductor structure according to claim 3, characterized in that, The selection line is a straight line, and the extension direction of the selection line is perpendicular to the extension direction of the character line.

7. The semiconductor structure of claim 6, wherein, Also includes: A first plug, the first plug being connected to the middle of the active region and the selection line; The second plug connects the end of the active area and the connecting pad, and the height of the first plug is the same as the height of the second plug.

8. The semiconductor structure according to claim 7, characterized in that, The first plug and the second plug are formed in the same process step.

9. The semiconductor structure of claim 1, wherein, Also includes: Bit lines are connected to the magnetic tunnel junction, and the extension direction of the bit lines is the same as the second direction.

10. The semiconductor structure according to claim 2, characterized in that, The angle between the second direction and the third direction is in the range of 15° to 35°.

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