Apparatus, memory controller, memory device, memory system and method for clock switching and low power consumption

Abstract

In an apparatus, a memory controller, a memory device and a method for switching a frequency of a clock signal to reduce power consumption, when the memory device performs an internal operation according to a command of the memory controller, the frequency of the clock signal of the memory controller is changed. The memory controller switches the frequency of the clock signal to a low frequency according to a declaration of a status signal indicating a busy operation state of the memory device, and switches the frequency of the clock signal to a high frequency according to a release of the status signal indicating a ready operation state of the memory device.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Korean Patent Application No. 10-2020-0177717, filed on December 17, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to apparatus and methods, and more particularly to an apparatus, memory controller, memory device, and memory system, and a method for switching the frequency of a clock signal associated with the operation of the memory device to reduce power consumption. Background Technology

[0004] Electronic systems using semiconductor chips may include dynamic random access memory (DRAM) as working or main memory to store data or instructions used by the host and / or to perform computational operations, and may include storage devices as storage media. Storage devices may include non-volatile storage devices. With the recent increase in storage device capacity, the demand for non-volatile storage devices with high capacity and the ability to perform stable and fast real-time processing of large amounts of data is constantly increasing. In mobile systems, low-power operation of storage devices is an important consideration and is required to save power and extend battery life. Summary of the Invention

[0005] An embodiment of the present invention provides an apparatus comprising: a plurality of signal pins, each connected to an external device via a plurality of signal lines; and a clock control circuit that instructs the external device to perform an operation having a first operating mode and a second operating mode via some of the signal pins, and generates a clock signal related to the first and second operating modes for the operation of the external device. During the first operating mode of the operation, the clock control circuit switches the frequency of the clock signal to a first frequency, and during the second operating mode, based on a status signal provided to the apparatus from the external device, switches the frequency of the clock signal to a second frequency different from the first frequency.

[0006] An embodiment of the present invention also provides a memory controller for controlling a memory device. The memory controller includes: a plurality of signal pins connected to signal lines respectively carrying signals; and a clock control circuit that receives a status signal indicating the operating state of the memory device through one of the signal pins, and generates a clock signal based on the status signal. The clock control circuit generates a clock signal set to a relatively low frequency based on the status signal indicating that the memory device is in a busy state, and generates a clock signal set to a relatively high frequency based on the status signal indicating that the memory device is in a ready state.

[0007] Embodiments of the present invention also provide a storage device comprising: a plurality of signal pins connected to signal lines respectively carrying signals; and control logic circuitry for controlling a first operation related to a first command received via a first signal pin of the plurality of signal pins. During the first operation, the storage device transmits a status signal indicating the operating state of the storage device via a second signal pin of the plurality of signal pins, and transmits and receives a clock signal that switches at a frequency related to changes in the status signal via a third signal pin of the plurality of signal pins.

[0008] Embodiments of the present invention also provide a storage system comprising: a storage device including a plurality of storage cells; and a storage controller that sends commands and clock signals to the storage device to control the storage device. The storage controller, based on the commands, switches the frequency of the clock signal to a first frequency according to a declaration of a status signal indicating the operating state of the storage device provided from the storage device, and switches the frequency of the clock signal to a second frequency different from the first frequency according to a declaration of the status signal.

[0009] Embodiments of the present invention also provide a method for providing a clock signal, comprising: determining a first command for operating conditions of a storage device by a storage controller; performing a first operation by the storage device in response to the first command; declaring a state signal indicating the state of the first operation by the storage device; switching the frequency of the clock signal to a first frequency by the storage controller in response to the declaration of the state signal; declaring the state signal by the storage device; and switching the frequency of the clock signal to a second frequency different from the first frequency by the storage controller based on the declaration of the state signal. Attached Figure Description

[0010] Embodiments of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A block diagram illustrating a storage device according to an embodiment of the present invention;

[0012] Figure 2 Show Figure 1 Example block diagram of a storage device;

[0013] Figure 3 Showing applicable Figure 2 Circuit diagram of a three-dimensional (3D) V-NAND structure for a memory device;

[0014] Figure 4 Showing applicable Figure 2 A cross-sectional view of the three-dimensional (3D) V-NAND structure of the storage device;

[0015] Figure 5A flowchart illustrating a method of operating a storage device according to an embodiment of the concept of the present invention is shown;

[0016] Figure 6A A timing diagram illustrating a read operation in a storage device according to an embodiment of the present invention is shown;

[0017] Figure 6B A schematic diagram illustrating a page read operation in a storage device according to an embodiment of the concept of the present invention is shown;

[0018] Figure 7 A flowchart illustrating a method of operating a storage device according to an embodiment of the concept of the present invention is shown;

[0019] Figure 8 A flowchart illustrating a method of operating a storage device according to an embodiment of the concept of the present invention is shown;

[0020] Figure 9A and Figure 9B A timing diagram illustrating the programming operations of a storage device according to an embodiment of the present invention;

[0021] Figure 9C Show Figure 1 Exemplary programming bias conditions for storage devices in the example;

[0022] Figure 9D Show Figure 1 A schematic diagram of incremental step programming for memory devices in the diagram;

[0023] Figure 10 A flowchart illustrating a method of operating a storage device according to an embodiment of the concept of the present invention is shown;

[0024] Figure 11 A block diagram illustrating a storage system including a storage device according to an embodiment of the present invention;

[0025] Figure 12 Show Figure 11 A schematic diagram of the interface between the host and storage devices;

[0026] Figure 13 A schematic diagram of a system to which an embodiment of a storage device according to the present invention can be applied is shown;

[0027] Figure 14 A schematic diagram illustrating a universal flash memory (UFS) system according to an embodiment of the present invention;

[0028] Figure 15 A block diagram illustrating a non-volatile memory according to an embodiment of the present invention; and

[0029] Figure 16A and Figure 16BA timing diagram illustrating a method of operating a storage device according to an embodiment of the present invention is shown. Detailed Implementation

[0030] As is common in the field of inventive conception, embodiments can be described and illustrated based on blocks that perform one or more described functions. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and / or digital circuitry such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc., and may optionally be driven by firmware and / or software. For example, the circuitry may be specifically implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. Each block of an embodiment may be physically divided into two or more interactive and discrete blocks without departing from the scope of the inventive conception. Similarly, the blocks of an embodiment may be physically combined into more complex blocks without departing from the scope of the inventive conception.

[0031] Figure 1 A block diagram of a storage device according to an embodiment of the present invention is shown.

[0032] refer to Figure 1 Storage device 100 may include storage device 110 and storage controller 120. Although a conceptual hardware configuration included in storage device 100 is described below, other embodiments may include other configurations. Storage controller 120 may control storage device 110 such that data is written to storage device 110 in response to a write request from a host (not shown), or may control storage device 110 such that data stored in storage device 110 is read from storage device 110 in response to a read request from a host.

[0033] In some embodiments, storage device 100 may include internal memory embedded in an electronic device. For example, storage device 100 may include embedded general-purpose flash memory (UFS) devices, embedded multimedia cards, etc. Or a solid-state drive (SSD). However, the inventive concept is not limited thereto. In other embodiments, the storage device 100 may include, for example, non-volatile memory, such as one-time programmable read-only memory (OTPROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), mask read-only memory (ROM), or flash memory ROM, etc. In some embodiments, the storage device 100 may include external memory that is attachable to and removable from an electronic device. For example, the storage device 100 may include at least one of the following: UFS memory card, Compact... (CF) card, Security Digital TM Card (SD) Card, Cards, Limit Digital (xD) and Memory Stick TM (MS).

[0034] The storage device 110 may include first pins P11 to eighth pins P18, storage interface (I / F) circuitry 112, control logic circuitry 114, and storage cell array 116.

[0035] The storage interface circuit 112 can receive the chip enable signal nCE from the storage controller 120 via the first pin P11. The storage interface circuit 112 can send signals to and receive signals from the storage controller 120 via the second pin P12 to the eighth pin P18 based on the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the storage interface circuit 112 can send signals to and receive signals from the storage controller 120 via the second pin P12 to the eighth pin P18.

[0036] The storage interface circuit 112 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the storage controller 120 via pins P12 to P14. The storage interface circuit 112 can receive the data signal DQ from the storage controller 120 via pin P17, or can send the data signal DQ to the storage controller 120 via pin P17. Command CMD, address ADDR, and data DATA can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to multiple data signals.

[0037] The storage interface circuit 112 can acquire the command CMD from the data signal DQ received during the enable period (e.g., high level state) of the command latch enable signal CLE based on the switching timing of the write enable signal nWE. The storage interface circuit 112 can also acquire the address ADDR from the data signal DQ received during the enable period (e.g., high level state) of the address latch enable signal ALE based on the switching timing of the write enable signal nWE.

[0038] In the example embodiment, the write enable signal nWE can be toggled between high and low levels while remaining static (e.g., high or low). For example, the write enable signal nWE can be toggled during the time period of transmitting command CMD or address ADDR. Therefore, the storage interface circuit 112 can obtain command CMD or address ADDR based on the toggling timing of the write enable signal nWE.

[0039] The storage interface circuit 112 can receive the read enable signal nRE from the storage controller 120 via its fifth pin P15. The storage interface circuit 112 can receive the data strobe signal DQS from the storage controller 120 via its sixth pin P16, or it can send the data strobe signal DQS to the storage controller 120.

[0040] During the operation of the storage device 110 to output data DATA, the storage interface circuit 112 may receive a switched read enable signal nRE via pin 5 P15 before outputting data DATA. The storage interface circuit 112 may generate a switched data strobe signal DQS based on the switching of the read enable signal nRE. For example, the storage interface circuit 112 may generate a data strobe signal DQS that begins switching after a previously determined delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. The storage interface circuit 112 may transmit a data signal DQ including data DATA based on the switching timing of the data strobe signal DQS. Therefore, data DATA may be aligned with the switching timing of the data strobe signal DQS and sent to the storage controller 120.

[0041] During the operation of inputting data DATA into storage device 110, when a data signal DQ including data DATA is received from storage controller 120, storage interface circuit 112 can simultaneously receive the switched data strobe signal DQS and the data DATA. Storage interface circuit 112 can obtain data DATA from data signal DQ based on the switching timing of data strobe signal DQS. For example, storage interface circuit 112 can obtain data DATA by sampling data signal DQ at the rising and falling edges of data strobe signal DQS.

[0042] The storage interface circuit 112 can send a ready-busy output signal R / nB to the storage controller 120 via pin 8 P18. The storage interface circuit 112 can also send status information of the storage device 110 to the storage controller 120 via the ready-busy output signal R / nB. When the storage device 110 is in a busy state (i.e., when internal operations of the storage device 110 are being performed), the storage interface circuit 112 can send a ready-busy output signal R / nB indicating the busy state to the storage controller 120. When the storage device 110 is in a ready state (i.e., when internal operations of the storage device 110 are not being performed or have been completed), the storage interface circuit 112 can send a ready-busy output signal R / nB indicating the ready state to the storage controller 120. For example, when the storage device 110 reads data DATA from the storage cell array 116 in response to a page read command, the storage interface circuit 112 can send a ready-busy output signal R / nB indicating a busy state (e.g., a low level) to the storage controller 120. For example, when the storage device 110 programs data DATA into the storage cell array 116 in response to a programming command, the storage interface circuit 112 can send a ready-busy output signal R / nB indicating a busy state to the storage controller 120.

[0043] The control logic circuit 114 can comprehensively control various operations of the storage device 110. The control logic circuit 114 can receive commands / addresses (CMD / ADDR) obtained from the storage interface circuit 112. The control logic circuit 114 can generate control signals for controlling other components of the storage device 110 based on the received commands / addresses (CMD / ADDR). For example, the control logic circuit 114 can generate various control signals for programming data DATA into or reading data DATA from the storage cell array 116.

[0044] The storage cell array 116 can store data DATA obtained from the storage interface circuit 112 under the control of the control logic circuit 114. The storage cell array 116 can also output the stored data DATA to the storage interface circuit 112 under the control of the control logic circuit 114.

[0045] The storage cell array 116 may include a plurality of storage cells. For example, the plurality of storage cells may include flash memory cells. However, the inventive concept is not limited thereto, and in some embodiments, the storage cells may include, for example, resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase-change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, or magnetic random access memory (MRAM) cells. In some embodiments, the storage cells may include static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells. Hereinafter, embodiments of the inventive concept will be described, wherein the storage cells are NAND flash memory cells.

[0046] The storage controller 120 may include first pins P21 to eighth pins P28, controller interface (I / F) circuitry 122, and clock control circuitry 124. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 of the storage device 110.

[0047] The controller interface circuit 122 can send a chip enable signal nCE to the memory device 110 via the first pin P21. The controller interface circuit 122 can send signals to and receive signals from the memory device 110 selected by the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0048] The controller interface circuit 122 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 110 via pins P22 to P24. The controller interface circuit 122 can send the data signal DQ to the memory device 110 via pin P27, or can receive the data signal DQ from the memory device 110.

[0049] The controller interface circuit 122 can send a data signal DQ including a command CMD or an address ADDR along with a toggled write enable signal nWE to the storage device 110. The controller interface circuit 122 can send the data signal DQ including the command CMD to the storage device 110 when a command latch enable signal CLE with an enabled state is sent, and can also send the data signal DQ including the address ADDR to the storage device 110 when an address latch enable signal ALE with an enabled state is sent.

[0050] The controller interface circuit 122 can send a read enable signal nRE to the memory device 110 via its fifth pin P25. The controller interface circuit 122 can receive a data strobe signal DQS from the memory device 110 via its sixth pin P26, or it can send a data strobe signal DQS to the memory device 110.

[0051] During the operation of the storage device 110 outputting data DATA, the controller interface circuit 122 can generate and send a switched read enable signal nRE to the storage device 110. For example, the controller interface circuit 122 can generate a read enable signal nRE that changes from a fixed state (e.g., high or low level) to a switched state before the data DATA is output. Therefore, the storage device 110 can generate a switched data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 122 can receive a data signal DQ including the data DATA and the switched data strobe signal DQS from the storage device 110 together. The controller interface circuit 122 can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0052] During the operation of receiving data DATA in the storage device 110, the controller interface circuit 122 can generate a switched data strobe signal DQS. For example, the controller interface circuit 122 can generate a data strobe signal DQS that changes from a fixed state (e.g., high level or low level) to a switched state before transmitting data DATA. The controller interface circuit 122 can transmit a data signal DQ including data DATA to the storage device 110 based on the switching timing of the data strobe signal DQS.

[0053] The controller interface circuit 122 can receive the ready-busy output signal R / nB from the storage device 110 via pin 8 P28. The controller interface circuit 122 can determine the status information of the storage device 110 based on the ready-busy output signal R / nB.

[0054] Clock control circuit 124 includes a phase-locked loop (hereinafter referred to as "PLL") that generates a clock signal CLK to adjust the timing of memory controller 120, crystal oscillator, and / or other clock logic circuitry. The PLL may be referred to as the component used to generate the clock signal CLK. Clock control circuit 124 may control switching signals (e.g., write enable signal nWE, read enable signal nRE, and data strobe signal DQS) provided to memory device 110 based on the clock signal CLK.

[0055] Clock control circuit 124 can receive a ready-busy output signal R / nB indicating the operating state of storage device 110 via a signal pin, and can switch the frequency of clock signal CLK to a low frequency based on the assertion (busy state) of the ready-busy output signal R / nB, and switch the frequency of clock signal CLK to a high frequency based on the de-assertion (ready state) of the ready-busy output signal R / nB. Clock control circuit 124 can provide switching signals (e.g., write enable signal nWE, read enable signal nRE, and data strobe signal DQS), which are switched to the same clock frequency as the clock signal CLK with a changed frequency. In some embodiments, the storage device can be characterized as a storage system.

[0056] Figure 2 Show Figure 1 Example block diagram of the storage device.

[0057] refer to Figure 2 The storage device 110 may include control logic circuitry 114, a memory cell array 116, a page buffer unit 118, a voltage generator 119, and a row decoder 394. Although Figure 2 Not shown, but storage device 110 may also include Figure 1 The storage interface circuit 112 shown may also include column logic circuits, pre-decoder, temperature sensor, command decoder and address decoder, etc.

[0058] The control logic circuit 114 can comprehensively control various operations of the storage device 110. The control logic circuit 114 can output various control signals in response to commands CMD and / or addresses ADDR from the storage interface circuit 112. For example, the control logic circuit 114 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0059] The storage cell array 116 may include multiple storage blocks BLK1 to BLKz (z is a positive integer), and each of the multiple storage blocks BLK1 to BLKz may include multiple storage cells. The storage cell array 116 can be connected to the page buffer unit 118 via the bit line BL, and can be connected to the line decoder 394 via the word line WL, the string select line SSL, and the ground select line GSL.

[0060] In an example embodiment, the memory cell array 116 may include a three-dimensional (3D) memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells vertically stacked on a substrate and connected to word lines. U.S. Patent Application Publication Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 are incorporated herein by reference. In some other example embodiments, the memory cell array 116 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0061] Page buffer unit 118 may include multiple page buffers PB1 to PBn (n is an integer of 3 or greater), and the multiple page buffers PB1 to PBn may be connected to the memory cell via multiple bit lines BL. Page buffer unit 118 may select at least one of the multiple bit lines BL in response to column address Y-ADDR. Depending on the operating mode, page buffer unit 118 may operate as a write driver or a sense amplifier. For example, during a programming operation, page buffer unit 118 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer unit 118 may sense the data stored in the memory cell by sensing the current or voltage of the selected bit line.

[0062] Voltage generator 119 can generate various voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 119 can generate voltages such as programming voltage, reading voltage, programming verification voltage, and erasing voltage as word line voltage VWL.

[0063] The row decoder 394 can select one of multiple word lines (WL) in response to the row address X-ADDR, and can also select one of multiple string select lines (SSL). For example, during a programming operation, the row decoder 394 can apply a programming voltage and a programming verification voltage to the selected word line, and can apply a read voltage to the selected word line during a read operation.

[0064] Figure 3 and Figure 4 It shows that it is applicable to Figure 2 A schematic diagram of the 3D V-NAND structure of a memory device. When Figure 1 When the storage device 100 is composed of 3D V-NAND flash memory, each of the plurality of storage blocks constituting the storage device 100 can be composed of, for example, Figure 3 The equivalent circuit shown is illustrated.

[0065] Figure 3 The memory block BLKi shown represents a 3D memory block formed in a 3D structure on a substrate. For example, multiple NAND strings included in the memory block BLKi can be formed along a direction perpendicular to the substrate.

[0066] refer to Figure 3 The memory block BLKi may include multiple memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MCI, MC2, ..., MC8, and a ground select transistor GST. Figure 3 The diagram shows that each of the multiple NAND strings NS11 to NS33 includes eight storage cells MC1, MC2, ..., MC8, but the number of storage cells is not limited to this.

[0067] The string select transistor SST can be connected to the corresponding string select lines SSL1, SSL2, and SSL3. Multiple memory cells MC1, MC2, ..., MC8 can be connected to the corresponding gate lines GTL1, GTL2, ..., GTL8. Gate lines GTL1, GTL2, ..., GTL8 can correspond to word lines, and some of the gate lines GTL1, GTL2, ..., GTL8 can correspond to dummy word lines. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The string select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0068] Word lines of the same height (e.g., WL1) are connected together, and ground select lines GSL1, GSL2, and GSL3 can be separated from string select lines SSL1, SSL2, and SSL3. Figure 3 The diagram shows that the memory block BLK is connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2 and BL3, but the number of gate lines and bit lines is not limited to this.

[0069] Figure 4 An embodiment of the invention is shown. Figure 3 Cross-sectional view of storage device 110.

[0070] refer to Figure 4The storage device 110 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by: fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer separate from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process may include a method of electrically connecting bonding metal formed on the topmost metal layer of the upper chip to bonding metal formed on the topmost metal layer of the lower chip. For example, in some embodiments, the bonding metal may include copper (Cu) using a copper-to-copper (Cu) bond, but in other embodiments, the bonding metal may be formed, for example, aluminum (Al) or tungsten (W).

[0071] Each of the peripheral circuit region PERI and cell region CELL of the storage device 110 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0072] The Peripheral Circuit Area (PERI) may include: a first substrate 210; an interlayer insulating layer 215; a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210; first metal layers 230a, 230b, and 230c respectively connected to the plurality of circuit elements 220a, 220b, and 220c; and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c. In an example embodiment, the first metal layers 230a, 230b, and 230c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 240a, 240b, and 240c may be formed of copper, which has a relatively low resistivity.

[0073] exist Figure 4 In the example embodiments shown, although only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are shown and described, in other embodiments, one or more additional metal layers may also be formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more additional metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or the like, which has a lower resistivity than copper, the copper used to form the second metal layers 240a, 240b, and 240c.

[0074] An interlayer insulating layer 215 may be disposed on a first substrate 210 and cover a plurality of circuit elements 220a, 220b and 220c, first metal layers 230a, 230b and 230c and second metal layers 240a, 240b and 240c. The interlayer insulating layer 215 may include an insulating material such as silicon oxide, silicon nitride, etc.

[0075] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding area (WLBA). In the WLBA, the lower bonding metals 271b and 272b in the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 371b and 372b in the cell area (CELL). The lower bonding metals 271b and 272b, along with the upper bonding metals 371b and 372b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 371b and 372b in the cell area (CELL) can be referred to as first metal pads, and the lower bonding metals 271b and 272b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0076] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 310 and a common source line 320. Multiple word lines 331 to 338 (i.e., 330) may be stacked on the second substrate 310 in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 330, respectively, and the multiple word lines 330 may be disposed between the at least one string select line and the at least one ground select line.

[0077] In the bit line bonding region BLBA, the channel structure CH can extend along a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction) and can pass through multiple word lines 330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c can be a bit line contact, and the second metal layer 360c can be a bit line. In an example embodiment, the bit line 360c can extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0078] exist Figure 4 In the example embodiment shown, the region provided with the channel structure CH, bit line 360c, etc., can be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 360c can be electrically connected to circuit element 220c, which provides a page buffer 393 in the peripheral circuit region PERI. Bit line 360c can be connected to upper bonding metals 371c and 372c in the cell region CELL, and upper bonding metals 371c and 372c can be connected to lower bonding metals 271c and 272c, which are connected to the circuit element 220c of the page buffer 393.

[0079] In the word line bonding area (WLBA), multiple word lines 330 can extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and perpendicular to the first direction, and can be connected to multiple cell contact plugs 341 to 347 (i.e., 340). The multiple word lines 330 and the multiple cell contact plugs 340 can be connected to each other in pads provided by at least a portion of the multiple word lines 330 extending at different lengths along the second direction. A first metal layer 350b and a second metal layer 360b can be sequentially connected to the upper portion of the multiple cell contact plugs 340 connected to the multiple word lines 330. The multiple cell contact plugs 340 can be connected to the peripheral circuit region PERI via upper bonding metals 371b and 372b of the cell region CELL in the word line bonding area (WLBA) and lower bonding metals 271b and 272b of the peripheral circuit region PERI.

[0080] Multiple unit contact plugs 340 can be electrically connected to circuit element 220b, which forms line decoder 394 in the peripheral circuit region PERI. In an example embodiment, the operating voltage of circuit element 220b of line decoder 394 may differ from the operating voltage of circuit element 220c forming page buffer 393. For example, the operating voltage of circuit element 220c forming page buffer 393 may be greater than the operating voltage of circuit element 220b forming line decoder 394.

[0081] A common source line contact plug 380 can be disposed in the external pad bonding region PA. The common source line contact plug 380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a can be sequentially stacked on top of the common source line contact plug 380. For example, the area where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed can be defined as the external pad bonding region PA. The common source line contact plug 380 can be connected to the lower metal pattern 273a of the peripheral circuit region PERI via an upper bonding metal 371a and an upper metal pattern 372a.

[0082] Input and output pads 205 and 305 can be set in the external pad bonding area PA. (See reference) Figure 4A lower insulating film 201 covering the lower surface of the first substrate 210 can be formed below the first substrate 210, and first input / output pads 205 can be formed on the lower insulating film 201. The first input / output pads 205 can be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI via first input / output contact plugs 203, and can be separated from the first substrate 210 by the lower insulating film 201. In addition, a side insulating film (not shown) can be provided between the first input / output contact plugs 203 and the first substrate 210 to electrically isolate the first input / output contact plugs 203 from the first substrate 210.

[0083] refer to Figure 4 An upper insulating film 301 covering the upper surface of the second substrate 310 can be formed on the upper insulating film 301, and second input / output pads 305 can be disposed on the upper insulating film 301. The second input / output pads 305 can be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI via second input / output contact plugs 303 and lower bonding metals 271a and 272a. In an example embodiment, the second input / output pads 305 are electrically connected to circuit element 220a.

[0084] According to an embodiment, the second substrate 310 and the common source line 320 may not be located in the area where the second input / output contact plug 303 is provided. Furthermore, the second input / output pad 305 may not overlap with the word line 330 in the third direction (Z-axis direction). Reference Figure 4 The second input / output contact plug 303 can be separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, and can pass through the interlayer insulating layer 315 of the cell region to connect to the second input / output pad 305.

[0085] According to embodiments, the first input / output pad 205 and the second input / output pad 305 can be selectively formed. For example, the storage device 110 may include only the first input / output pad 205 disposed on the first substrate 210 or the second input / output pad 305 disposed on the second substrate 310. Alternatively, the storage device 110 may include both the first input / output pad 205 and the second input / output pad 305.

[0086] In each of the external pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, the metal pattern (not shown) set on the top metal layer can be set as a dummy pattern, or the top metal layer can be missing.

[0087] In the external pad bonding area PA, the storage device 110 may include a lower metal pattern 273a in the uppermost metal layer of the peripheral circuit area PERI. The lower metal pattern 273a corresponds to the upper metal pattern 372a formed in the uppermost metal layer of the cell area CELL and has the same cross-sectional shape as the upper metal pattern 372a of the cell area CELL for interconnection. In the peripheral circuit area PERI, the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, the upper metal pattern 372a may be formed in the uppermost metal layer of the cell area CELL, corresponding to the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI and having the same shape as the lower metal pattern 273a of the peripheral circuit area PERI.

[0088] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI can be electrically connected to the upper bonding metals 371b and 372b of the cell area CELL via copper-to-copper bonding.

[0089] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 392 can be formed in the uppermost metal layer of the cell region CELL. The upper metal pattern 392 corresponds to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit region PERI and has the same cross-sectional shape as the lower metal pattern 252 of the peripheral circuit region PERI. Contacts may not be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL. The upper metal pattern 392 can be connected to the circuit element 220c via the lower metal pattern 252 and the lower bonding metal 251.

[0090] In an example embodiment, corresponding to the metal pattern formed in the uppermost metal layer of one of the cell region (CELL) and the peripheral circuit region (PERI), a reinforcing metal pattern with the same cross-sectional shape can be formed in the uppermost metal layer of the other of the cell region (CELL) and the peripheral circuit region (PERI). Contacts may not be formed on the reinforcing metal pattern.

[0091] Figure 5 A flowchart illustrating a method for operating a storage device according to an embodiment of the concept of the present invention is shown. Figure 5 It shows Figure 1 The operation of the storage controller 120 in the storage device 100.

[0092] refer to Figures 1 to 5In step S510, the storage controller 120 issues a read command READCMD to the storage device 110. The storage controller 120 may send the address ADDR and the read command READ CMD to the storage device 110. The storage device 110 may perform a read operation on the storage cell corresponding to the address ADDR in the storage cell array 116 in response to the read command READ CMD.

[0093] In step S520, the storage controller 120 receives a status signal from the storage device 110 indicating the status of the storage device 110. The status signal asserts or de-asserts any internal operations (e.g., read, program, and erase operations) performed on the storage device 110. According to an embodiment, the storage controller 120 may issue a status check command to the storage device 110, and the storage device 110 may send a status signal to the storage controller 120 in response to the status check command.

[0094] Storage device 110 can indicate the state of performing a read operation by using a ready-busy output signal R / nB. Storage device 110 can send the ready-busy output signal R / nB, indicating a busy state (e.g., low level), to storage controller 120. The ready-busy output signal R / nB can be referred to as a status signal. In the following embodiments, the terms "ready-busy output signal R / nB" and "status signal" can be used interchangeably.

[0095] In step S530, the memory controller 120 switches the clock signal CLK to a lower frequency clock signal CLK based on the assertion of the status signal in step S520. When the status signal is asserted from the memory device 110, in other words, when the memory device 110 is performing internal operations, optimal circuit performance is not required for the memory controller 120 and the memory device 110. Normally, optimal performance is achieved by increasing the frequency of the clock signal CLK, but when optimal performance is not required, the frequency of the clock signal CLK needs to be switched to a lower frequency to save power.

[0096] The memory controller 120 can switch the clock signal CLK to a lower frequency clock signal CLK based on the ready-busy output signal R / nB indicating a busy state received from the memory device 110. When the memory device 110 sends the ready-busy output signal R / nB indicating a busy state, the control logic circuit 114 can perform a page read operation on the memory cell corresponding to address ADDR in the memory cell array 116 according to the read command READ CMD.

[0097] In step S540, the storage controller 120 receives a declaim status signal from the storage device 110. After completing the page read operation, the storage device 110 sends a ready-busy output signal R / nB indicating a ready state (e.g., high level) to the storage controller 120 to send the page-read data DATA to the storage controller 120. The ready-busy output signal R / nB in the ready state can be referred to as the declaim status signal.

[0098] In step S550, the storage controller 120 switches the clock signal CLK to a higher frequency clock signal CLK based on the declaration status signal received in step S540. When the declaration status signal is received from the storage device 110, the storage device 110 can send page-read data DATA to the storage controller 120 via the data signal DQ line. In this case, the storage device 110 needs to output the page-read data DATA as output data DOUT with optimal capability. For optimal capability of the storage controller 120 and the storage device 110, the frequency of the clock signal CLK needs to be switched to a higher frequency. The storage controller 120 can switch the clock signal CLK to a higher frequency clock signal CLK based on the ready-busy output signal R / nB received from the storage device 110 indicating the ready status.

[0099] In step S560, the storage controller 120, in response to the read command READ CMD and address ADDR issued in step S510, receives the output data DOUT of the storage device 110 via the data signal DQ line.

[0100] Figure 6A and Figure 6B A schematic diagram illustrating a method for operating a storage device according to an embodiment of the present invention is shown. Figure 6A It shows Figure 1 Timing diagram of read operations of storage device 110 in storage device 100. Figure 6B A schematic diagram of a page read operation of storage device 110 is shown. Note that... Figure 6A and Figure 6B The horizontal and vertical axes in the diagram represent time and voltage levels, respectively. Figure 6A and Figure 6B It is not shown to scale.

[0101] refer to Figures 1 to 6A At time T1, a read command READ CMD can be received via the data signal DQ line to perform a read operation on the storage device 110. After the read command READ CMD, the address ADDR can be received via the data signal DQ line.

[0102] At time T2, a status check signal STATUSCHECK for a read operation can be received via the data signal DQ line. The status check signal STATUSCHECK can be provided according to the read command READ CMD to check the read operation status of the storage device 110. The status check signal STATUSCHECK can be referred to as the read status check command. The status check signal STATUSCHECK can be received together with a read enable signal nRE that switches at a first frequency. The read enable signal nRE can be received in a switching state from a fixed state (e.g., high level). The storage device 110 can generate a data strobe signal DQS based on the received read enable signal nRE that switches at the first frequency. The data strobe signal DQS can be generated in a switching state from a fixed state (e.g., low level) to the first frequency. The read enable signal nRE that switches at the first frequency and the data strobe signal DQS can be generated based on a clock signal CLK generated by the storage controller 120 and switched to a low frequency in step S530, and can be provided to the storage device 110 for the read operation. According to an embodiment, the read enable signal nRE and the data strobe signal DQS, which are switched at a first frequency, can be switched at the same clock frequency as the clock signal CLK, which has a low frequency.

[0103] In response to the status check signal STATUS CHECK, the storage device 110 can send a status output signal STATUS OUT, indicating that a read operation has been performed, to the storage controller 120 via the data signal DQ line. The storage device 110 can repeatedly receive the status check signal STATUS CHECK and send a status output signal STATUS OUT corresponding to the status check signal STATUS CHECK.

[0104] Simultaneously, the storage controller 120 can use the ready-busy output signal R / nB output from the storage device 110 to check the read operation status of the storage device 110, instead of sending the status check signal STATUSCHECK via the data signal DQ line and receiving the status output signal STATUS OUT corresponding to the status check signal STATUS CHECK. At time point T2, the storage device 110 can send the ready-busy output signal R / nB indicating a busy state (e.g., low level) to the storage controller 120. During the time period tR in which the storage device 110 performs a read operation, the ready-busy output signal R / nB can be output as a busy state.

[0105] One or more bits can be programmed into the memory cells of the memory cell array 116. Depending on the number of bits stored in the memory cell, the memory cells can be classified as single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC). Depending on the number of bits stored in the memory cell, the memory cell can have multiple states. These multiple states can be defined within a threshold voltage range. For example, when each memory cell is a QLC, the state of each memory cell can correspond to one of 16 states S1 to S16, such as... Figure 6B As shown. A memory cell connected to a word line WL may include a least significant bit (LSB) page, a first intermediate bit (CSB1) page, a second intermediate bit (CSB2) page, and a most significant bit (MSB) page.

[0106] The read operation of the storage device 110 may include the operation of detecting the valley positions VR1 to VR15 of the threshold voltage of the storage cell, the operation of inferring the optimal read voltage RD1 to RD15 based on the valley positions VR1 to VR15, the page read operation performed using the read voltage RD1 to RD15 on each of the least significant bit (LSB) page, the first intermediate bit (CSB1) page, the second intermediate bit (CSB2) page, and the most significant bit (MSB) page, etc.

[0107] For example, during a read operation of the least significant bit (LSB) page, the memory device 110 can determine the eleventh state S11 and the twelfth state S12 by applying an eleventh read voltage RD11 to the selected word line WL. Then, it can determine the sixth state S6 and the seventh state S7, the fourth state S4 and the fifth state S5, as well as the first state S1 and the second state S2 by sequentially applying a sixth read voltage RD6, a fourth read voltage RD4, and a first read voltage RD1 to the selected word line WL. During a read operation of the first intermediate bit (CSB) page, the memory device 110 can determine the thirteenth state S13 and the fourteenth state S14, the ninth state S9 and the tenth state S10, the seventh state S7 and the eighth state S8, and the third state S3 and the fourth state S4 by sequentially applying a thirteenth read voltage RD13, a ninth read voltage RD9, a seventh read voltage RD7, and a third read voltage RD3 to the selected word line WL. During the read operation of the second intermediate bit CSB2 page, the memory device 110 can determine the fourteenth state S14 and the fifteenth state S15, the eighth state S8 and the ninth state S9, and the second state S2 and the third state S3 by sequentially applying the fourteenth read voltage RD14, the eighth read voltage RD8 and the second read voltage RD2 to the selected word line WL. During the read operation of the most significant bit MSB page, the memory device 110 can determine the fifteenth state S15 and the sixteenth state S16, the twelfth state S12 and the thirteenth state S13, the tenth state S10 and the eleventh state S11, and the fifth state S5 and the sixth state S6 by sequentially applying the fifteenth read voltage RD15, the twelfth read voltage RD12, the tenth read voltage RD10 and the fifth read voltage RD5 to the selected word line WL. During the time period tR of performing the page read operation, the ready-busy output signal R / nB can be output as busy.

[0108] exist Figure 6AWhen a page read operation of storage device 110 is completed, a status output signal STATUS OUT, indicating the completion of the page read operation in response to a status check signal STATUS CHECK, can be sent to storage controller 120 via the data signal DQ line. Alternatively, a ready-busy output signal R / nB, indicating the ready state (e.g., high level) of storage device 110, can be sent to storage controller 120. Storage controller 120 can send a read enable signal nRE to storage device 110 based on the status output signal STATUS OUT or the ready-busy output signal R / nB. Storage device 110 can receive the read enable signal nRE switched at a second frequency. The read enable signal nRE switched at the second frequency can be generated and provided based on a clock signal CLK generated by storage controller 120 and switched to a high frequency in step S550. According to an embodiment, the read enable signal nRE switched at the second frequency can be switched at the same clock frequency as the clock signal CLK, which has a high frequency.

[0109] At time T3, storage device 110 can send data DATA, which has been read through a page read operation, as output data DOUT to storage controller 120 via the data signal DQ line. Output data DOUT can be sent to storage controller 120 together with a data strobe signal DQS. Storage device 110 can generate the data strobe signal DQS based on a read enable signal nRE that switches at a second frequency, so that it can be received by storage controller 120 from time T3 to time T4, and can send output data DOUT synchronized with the data strobe signal DQS to storage controller 120. The data strobe signal DQS can be switched at the same clock frequency as the read enable signal nRE that switches at a second frequency. Therefore, storage controller 120 can obtain output data DOUT based on the high-frequency switching timing of the data strobe signal DQS.

[0110] Figure 7 A flowchart illustrating a method for operating a storage device according to an embodiment of the concept of the present invention is shown. Figure 7 It shows Figure 1 Read operations between the storage controller 120 and the storage device 110.

[0111] refer to Figures 1 to 7 In step S710, the storage controller 120 sends a read command READCMD and an address ADDR to the storage device 110.

[0112] In step S720, the storage device 110 performs a read operation on the storage cell corresponding to address ADDR in the storage cell array 116 in response to the read command READ CMD. For example, when each storage cell is a QLC, the read operation of the storage device 110 may include an operation to detect the valley position of the threshold voltage of the storage cell, an operation to infer the optimal read voltage level based on the valley position, a page read operation using the read voltage level for each of the least significant bit (LSB) page, the first intermediate bit (CSB1) page, the second intermediate bit (CSB2) page, and the most significant bit (MSB) page, etc.

[0113] In step S730, storage device 110 declares a busy state signal indicating that a read operation is being performed. Storage device 110 may send a ready-busy output signal R / nB to storage controller 120 indicating a busy state (e.g., low level). During the time period tR during which storage device 110 performs the read operation (e.g., see...), Figure 6A During this period, the ready-busy output signal R / nB can be output as busy.

[0114] In step S740, the storage controller 120 switches the clock signal CLK to a lower frequency clock signal CLK based on the busy state signal declaration in step S730. The storage controller 120 may send a read enable signal nRE and a data strobe signal DQS, switched at a first frequency, to the storage device 110 based on the switch to the lower frequency clock signal CLK. The read enable signal nRE and the data strobe signal DQS, switched at the first frequency, can be switched to the same clock frequency as the lower frequency clock signal CLK.

[0115] In step S750, after completing the read operation (S720), the storage device 110 declares the busy state signal. The storage device 110 sends a ready-busy output signal R / nB indicating a ready state (e.g., high level) to the storage controller 120.

[0116] In step S760, the storage controller 120 switches the clock signal CLK to a higher frequency clock signal CLK based on the received busy state signal declaration. The storage controller 120 may send a read enable signal nRE switched at a second frequency to the storage device 110.

[0117] In step S770, storage device 110 performs a data output operation that outputs the data DATA read from the page in step S720 as output data DOUT. Storage device 110 may generate a data strobe signal DQS that switches to a second frequency based on the received read enable signal nRE that switches to a second frequency.

[0118] In step S780, the storage device 110 sends output data DOUT to the storage controller 120, which is synchronized with the data strobe signal DQS switched at the second frequency.

[0119] Figure 8 A flowchart illustrating a method for operating a storage device according to an embodiment of the present invention is shown. Figure 8 It shows Figure 1 The operation of the storage controller 120 in the storage device 100.

[0120] refer to Figures 1 to 4 and Figure 8 In step S810, the storage controller 120 sends the address ADDR and the write command WRITE CMD to the storage device 110. The storage device 110 can perform a write (or program) operation on the storage cell corresponding to the address ADDR in the storage cell array 116 in response to the write command WRITE CMD.

[0121] In step S820, the storage controller 120 switches the clock signal CLK to a clock signal CLK with a high frequency to send write data DIN to the storage device 110.

[0122] In step S830, the storage controller 120 sends write data DIN to the storage device 110. The storage controller 120 can generate a data strobe signal DQS based on a high-frequency clock signal CLK, and can send the write data DIN, synchronized with the data strobe signal DQS, to the storage device 110. The data strobe signal DQS can be switched at the same clock frequency as the high-frequency clock signal CLK. The storage controller 120 can send the write data DIN to the storage device 110 according to the high-frequency switching timing of the data strobe signal DQS.

[0123] In step S840, the storage controller 120 receives a status signal from the storage device 110 indicating the status of the storage device 110. The storage device 110 can indicate the status of performing a programming operation by using a ready-busy output signal R / nB. The storage device 110 can send a ready-busy output signal R / nB indicating a busy state (e.g., low level) to the storage controller 120.

[0124] In step S850, the memory controller 120 switches the clock signal CLK to a low-frequency clock signal CLK based on the declaration of the status signal indicating a busy state in step S840. The memory controller 120 may send a data strobe signal DQS to the memory device 110 based on the low-frequency clock signal CLK, switching at the same clock frequency as the low-frequency clock signal CLK. The data strobe signal DQS, which changes according to the low-frequency switching timing, may be provided during the time period tPROG during which the memory device 110 performs programming operations. The programming portion tPROG of the memory device 110 may include, for example, a channel precharge portion, a bit line setting portion, a serial select line setting portion, a program execution portion, and a program verification portion.

[0125] Figures 9A to 9D A schematic diagram illustrating a method of operating a storage device according to an embodiment of the concept of the present invention is shown. Figure 9A and Figure 9B It shows Figure 1 A timing diagram of the programming operations of the storage device 110 in the storage device 100. Figure 9C A schematic diagram of exemplary programming bias conditions for storage device 110 is shown. Figure 9D A schematic diagram depicting incremental step pulse programming (hereinafter referred to as "ISPP") of the storage device 110 is shown.

[0126] refer to Figures 1 to 4 , Figure 8 and Figure 9A At time point Ta, a write command WRITE CMD can be received via the data signal DQ line to perform a write operation on the storage device 110. After the write command WRITE CMD, the address ADDR can be received via the data signal DQ line.

[0127] At time point Tb, write data DIN for the write operation can be received synchronously via the data signal DQ line and the data strobe signal DQS. The data strobe signal DQS can be generated based on a clock signal CLK that is switched to a high frequency in steps S820 and S830 of the memory controller 120, and can be provided to the memory device 110 for the write operation. According to an embodiment, the data strobe signal DQS can be switched at the same clock frequency as the clock signal CLK, which has a high frequency.

[0128] At time point Tc, storage device 110 may send a ready-busy output signal R / nB to storage controller 120 indicating a busy state (e.g., low level), which indicates that a programming operation is performed in response to the write command WRITE CMD. During the time period tPROG during which storage device 110 performs the programming operation from time point Tc to time point Td, the ready-busy output signal R / nB may be output as an indication of the busy state. Based on the low-frequency clock signal CLK in step S850 of storage controller 120, storage device 110 may receive a data strobe signal DQS that has changed to a low-frequency switching timing. The low-frequency switching data strobe signal DQS can be received during the time period tPROG during which storage device 110 performs the programming operation.

[0129] refer to Figure 9B When with Figure 9A In contrast, in some embodiments, a status check signal STATUSCHECK for a write operation can be received at the storage device 110 via the data signal DQ line at time point Tcd, between time point Tc and time point Td. The storage controller 120 can send the status check signal STATUSCHECK to the storage device 110 via the data signal DQ line to check the programming operation status of the storage device 110. In this case, the storage device 110 may not provide the functionality of outputting a ready-busy output signal R / nB indicating the status of the storage device 110.

[0130] In response to a status check signal STATUS CHECK, storage device 110 can send a status output signal STATUS OUT, indicating that a programming operation has been performed, to storage controller 120 via the data signal DQ line. Storage device 110 can repeatedly receive the status check signal STATUS CHECK and send a status output signal STATUS OUT corresponding to the status check signal STATUS CHECK.

[0131] At time point Tcd, the status check signal STATUS CHECK can be received together with the read enable signal nRE, which switches at a low frequency. The storage device 110 can generate a data strobe signal DQS based on the received read enable signal nRE, which switches at a low frequency. The data strobe signal DQS can be generated from a fixed state (e.g., low level) to a low-frequency switching state. The read enable signal nRE and the data strobe signal DQS, which switch at a low frequency, can be switched to the same clock frequency as the low-frequency clock signal CLK generated in step S530 of the storage controller 120.

[0132] For example, when each memory cell is a QLC, the state of each memory cell can be programmed as one of 16 states S1 to S16, such as... Figure 6B As shown. Figure 9C Examples are shown Figure 3 The NAND strings NS11 and NS21 of the first memory block BLK1 (BLK1 to BLK2) in the memory cell array 116 shown are connected to the first bit line BL1, and the NAND strings NS12 and NS22 are connected to the second bit line BL2. The first bit line BL1 is a programming enable bit line, with a relatively low programming enable voltage applied, such as ground voltage VSS, while the second bit line BL2 is a programming disable bit line, with a relatively high programming disable voltage applied, such as power supply voltage VDD.

[0133] Assuming that during programming, NAND string NS21 is selected from NAND strings NS11 and NS21 connected to the first bit line BL1, a turn-off voltage at the level of ground voltage VSS can be applied to the string select line SSL1 connected to NAND string NS11, and a turn-on voltage VSSL (e.g., power supply voltage VDD) greater than or equal to the threshold voltage Vth of each string select transistor SST can be applied to the string select line SSL2 connected to NAND string NS21. A turn-off voltage at the level of ground voltage VSS can be applied to ground select lines GSL1 and GSL2. A precharge voltage higher than ground voltage VSS can be applied to the source line CSL. A programming voltage VPGM (e.g., 18V) can be applied to the selected word line (e.g., WL3), and a pass voltage VPASS (e.g., 8V) can be applied to the unselected word lines (e.g., WL2 and WL4).

[0134] Under these programming bias conditions, 18V can be applied to the gate of memory cell A, and the channel voltage is 0V. Because a strong electric field is formed between the gate and channel of memory cell A, memory cell A is programmed. Furthermore, since the channel voltage of memory cell B is the supply voltage VDD, and a weak electric field is formed between the gate and channel of memory cell B, memory cell B is not programmed. Because the channels of memory cells C and D are in a floating state, their channel voltages rise to a boost level according to the through voltage VPASS, and memory cells C and D are not programmed.

[0135] The programming operation of storage device 110 can sequentially execute multiple programming loops LOOP(1), LOOP(2), LOOP(3), ..., LOOP(N+2) until programming is completed according to ISPP, such as... Figure 9DAs shown, the programming voltages VPGM1, VPGM2, VPGM3, ..., VGMN+2 can be gradually increased as the programming cycle repeats. Each programming cycle LOOP(i) (where i is a natural number) can include a programming cycle PROGRAM and a verification cycle VERIFY. In the programming cycle PROGRAM, the programming voltages VPGM1, VPGM2, VPGM3, ..., VGMN+2 are applied to the selected word line WL3 to program the selected memory cell. In the verification cycle VERIFY, the read voltage VRD is detected and applied to the selected word line WL3 to verify whether the programming was successful.

[0136] Figure 10 A flowchart illustrating a method for operating a storage device according to an embodiment of the concept of the present invention is shown. Figure 10 It shows Figure 1 Write operations between the storage controller 120 and the storage device 110.

[0137] refer to Figures 1 to 4 and Figures 8 to 9C In step S1010, the storage controller 120 sends a write command WRITE CMD and an address ADDR to the storage device 110.

[0138] In step S1020, the storage controller 120 switches the clock signal CLK to a clock signal CLK with a high frequency to send write data DIN to the storage device 110.

[0139] In step S1030, the storage controller 120 sends write data DIN to the storage device 110. The storage controller 120 can generate a data strobe signal DQS based on a clock signal CLK with a high frequency, and can send the write data DIN, which is synchronized with the data strobe signal DQS that switches at a high frequency, to the storage device 110.

[0140] In step S1040, the storage device 110 performs a programming operation on the memory cell corresponding to address ADDR in the memory cell array 116 in response to the write command WRITE CMD. The programming operation of the storage device 110 sequentially executes multiple programming cycles LOOP(1), LOOP(2), LOOP(3), ..., LOOP(N+2) until programming is completed according to ISPP. As the programming cycle is repeated, the programming voltages VPGM1, VPGM2, VPGM3, ..., VGMN+2 are gradually increased. Each programming cycle LOOP(i) (where i is a natural number) may include a channel precharge operation, a bit line setting operation, a serial select line setting operation, a program execution operation, and a program verification operation.

[0141] In step S1050, storage device 110 declares a busy state signal indicating that programming step S1040 is being executed. Storage device 110 may send a ready-busy output signal R / nB indicating a busy state (e.g., low level) to storage controller 120. During the time period tPROG during which storage device 110 executes programming step S1040, the ready-busy output signal R / nB may be output as an indication of a busy state.

[0142] In step S1060, the storage controller 120 switches the clock signal CLK to a lower frequency clock signal CLK based on the busy state signal declaration in step S1050. The storage controller 120 can then send a data strobe signal DQS with a lower frequency timing change to the storage device 110 based on the switch to the lower frequency clock signal CLK. The lower frequency data strobe signal DQS can be received during the time period tPROG during which the storage device 110 performs a programming operation (S1040).

[0143] Figure 11 A block diagram of a storage system including a storage device is shown, according to an embodiment of the present invention.

[0144] refer to Figure 11 Storage system 410 may include host 420 and storage device 430. Host 420 and storage device 430 may be interconnected according to the interface protocol defined in the Universal Flash Storage (UFS) specification; therefore, storage device 430 may include a UFS storage device, and host 420 may include a UFS host. However, the inventive concept is not limited thereto, and storage device 430 and host 420 may be interconnected according to various standard interfaces. Storage device 430 may correspond to reference [reference missing]. Figures 1 to 10 The storage device 100 is described.

[0145] The host 420 can control data processing operations of the storage device 430, such as data read operations or data write operations. The host 420 can instruct a data processing device capable of processing data, such as a central processing unit (CPU), microprocessor, or application processor (AP). The host 420 can execute an operating system (OS) and / or various applications. In one embodiment, the storage system 410 may be included in a mobile device, and the host 420 may include an application processor (AP). In one embodiment, the host 420 may include a system-on-a-chip (SoC) and therefore may be embedded in an electronic device.

[0146] Although many conceptual hardware configurations included in host 420 and storage device 430 have been described, this embodiment is not limited thereto and may include other configurations. Host 420 may include interconnect unit 422 and host controller 424. Interconnect unit 422 may provide interface 440 between host 420 and storage device 430. Interconnect unit 422 may include a physical layer and a link layer. The physical layer of interconnect unit 422 may include physical configurations for exchanging data with storage device 430, at least one transmitter TX, and at least one receiver RX, etc. Interconnect unit 422 of host 420 may include, for example, four transmitters TX1 to TX4 and four receivers RX1 to RX4. The link layer of interconnect unit 422 may also manage data transmission and / or combination and may manage data integrity and errors.

[0147] Storage device 430 may include interconnect unit 432, memory controller 434, and non-volatile memory (NVM) 436. Memory controller 434 may control NVM 436 to write data to NVM 436 in response to a write request from host 420, or may control NVM 436 to read data stored in NVM 436 in response to a read request from host 420. Memory controller 434 may correspond to reference [reference missing]. Figures 1 to 10 The memory controller 120 is described, and the non-volatile memory 436 may correspond to the memory device 110.

[0148] Interconnect unit 432 can provide an interface 440 between storage device 430 and host 420. For example, interconnect unit 432 may include a physical layer and a data link layer. The physical layer of interconnect unit 432 may include a physical configuration for exchanging data with host 420 and may include at least one receiver RX and at least one transmitter TX, etc. Interconnect unit 432 of storage device 430 may include, for example, four receivers RX1 to RX4 and four transmitters TX1 to TX4. The data link layer of interconnect unit 432 may also manage data transmission and / or combination and may manage data integrity and errors.

[0149] In one embodiment, when the storage system 410 is a mobile device, the physical layer of interconnect units 422 and 432 can be defined by the "M-PHY" specification, and the link layer can be defined by the "UniPro" specification. The M-PHY and UniPro specifications are mobile industry processor interfaces. The interface protocol proposed by the consortium. The link layers of interconnection units 422 and 432 can each include a physical adaptation layer, and the physical adaptation layer can control the physical layer, such as managing data symbols or managing power.

[0150] like Figure 12As shown, the transmitters TX included in the interconnect unit 422 of the host 420 and the receivers RX included in the interconnect unit 432 of the storage device 430 can form a channel. Alternatively, the transmitters TX included in the interconnect unit 432 of the storage device 430 and the receivers RX included in the interconnect unit 422 of the host 420 can also form a channel. In this embodiment, the number of transmitters TX1 to TX4 and receivers RX1 to RX4 included in the interconnect unit 422 of the host 420 is equal to the number of transmitters TX1 to TX4 and receivers RX1 to RX4 included in the interconnect unit 432 of the storage device 430. According to an example embodiment, the number of transmitters TX and receivers RX included in the interconnect unit 422 of the host 420 is equal to the number of transmitters TX and receivers RX included in the interconnect unit 432 of the storage device 430. Furthermore, the capabilities of the host 420 may differ from the capabilities of the storage device 430.

[0151] Host 420 and storage device 430 can perform processes such as identifying the channel they are physically connected to and receiving information about the other device, including link initiation processes. Host 420 and storage device 430 can execute a link initiation sequence before exchanging data. By executing the link initiation sequence, host 420 and storage device 430 can exchange and identify information about the number of transmitters (TX) and receivers (RX), information about the channel they are physically connected to, information about the capabilities of the other device, and so on. After the link initiation sequence is completed, host 420 and storage device 430 can be configured to a linked state where they can stably exchange data with each other.

[0152] In some embodiments, storage device 430 may include a DRAM-free device. A DRAM-free device may refer to a device that does not include a DRAM cache. In this case, memory controller 434 may not include a DRAM controller. For example, storage device 430 may use a portion of non-volatile memory 436 as buffer memory.

[0153] Storage system 410 may include electronic devices such as personal computers (PCs), laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio equipment, portable multimedia players (PMPs), personal navigation devices (PNDs), portable navigation devices (PNDs), MP3 players, handheld game consoles, or e-readers. Furthermore, storage system 410 may also include various types of electronic devices such as wristwatches or wearable devices such as head-mounted displays (HMDs).

[0154] Figure 12 yes Figure 11A schematic diagram of the interface 440 between the host 420 and the storage device 430. (The following will be described...) Figure 12 The concepts of channels, lines, and links in interface 440 are described below. For ease of description, representative examples are described in the following text. Figure 11 The interconnection units 422 and 432 include a plurality of transmitters and a plurality of receivers, including the transmitter TX1 of the interconnection unit 432 of the storage device 430 and the receiver RX1 of the interconnection unit 422 of the host 420.

[0155] refer to Figure 12 Interface 440 can support multiple channels. Each channel is a unidirectional transmission channel carrying a single signal and information. A channel may include a transmitter TX1, a receiver RX1, and lines for point-to-point interconnection between the transmitter TX1 and the receiver RX1. The transmitter TX1 or receiver RX1 may have differential output or input line interfaces corresponding to two signaling pins. The pins include pin DP representing the positive node of the differential signal and pin DN representing the negative node of the differential signal. Each of pins DP and DN may be labeled with the optional prefix TX or RX to indicate that the pin is used by the transmitter TX1 or the receiver RX1. For example, a channel including the transmitter TX1 and the receiver RX1 includes pins TXDP and TXDN at the transmitter TX1, and pins RXDP and RXDN at the receiver RX1. The lines consist of two separately wired conductors connecting the pins of the transmitter TX1 to the pins of the receiver RX1. The conductors are transmission lines.

[0156] Interface 440 includes at least one channel in each direction. The number of channels need not be symmetrical in each direction. The link may include one or more channels in each direction and channel management units 421 and 431 providing bidirectional data transmission capabilities. Channel management units 421 and 431, as well as controllers 424 and 434, are... Figure 12 The components are shown as separate from each other, but are not limited thereto, and channel management units 421 and 431 may be included in controllers 424 and 434.

[0157] Figure 13 A schematic diagram of a system for applying a storage device according to an embodiment of the present invention is shown. Figure 13 The system 1000 can consist of mobile systems such as mobile phones, smartphones, tablet PCs, wearable devices, healthcare devices, or Internet of Things (IoT) devices. However, Figure 13System 1000 is not limited to the described mobile system, but may also include automotive devices such as personal computers, laptop computers, servers, media players, or navigation systems. In the following, subscripts attached to the reference numerals (e.g., a in 1200a and a in 1300a) are used to distinguish multiple circuits having the same function from one another.

[0158] refer to Figure 13 The system 1000 may include a main processor 1100, memories 1200a and 1200b and storage devices 1300a and 1300b, and may also include one or more of the following: an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470 and a connection interface 1480.

[0159] The main processor 1100 can control all operations of the system 1000, and more specifically, can control the operation of other components included in the system 1000. The main processor 1100 may include, for example, a general-purpose processor, a special-purpose processor, or an application processor.

[0160] The main processor 1100 may include one or more CPU cores 1110 and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. In one embodiment, the main processor 1100 may also include an accelerator block 1130, which is dedicated circuitry for high-speed data operations such as artificial intelligence (AI) data manipulation. The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may consist of a separate chip physically separate from other components of the main processor 1100.

[0161] Memory 1200a and 1200b can be used as the main storage device of system 1000 and can include volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. Memory 1200a and 1200b can be embedded in the same package as main processor 1100.

[0162] Storage devices 1300a and 1300b can be used as non-volatile storage devices for storing data regardless of whether they are powered on, and can have a relatively larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may include memory controllers 1310a and 1310b and non-volatile memory (NVM) memories 1320a and 1320b that store data under the control of memory controllers 1310a and 1310b. Non-volatile memories 1320a and 1320b may include V-NAND flash memory with a two-dimensional (2D) or three-dimensional (3D) structure, but may also include other types of non-volatile memory, such as PRAM and / or RRAM.

[0163] Storage devices 1300a and 1300b can be physically separated from the main processor 1100 for inclusion in the system 1000, or they can be embedded in the same package as the main processor 1100. Furthermore, storage devices 1300a and 1300b can have the same shape as a memory card for detachable coupling to other components of the system 1000 via an interface such as connection interface 1480, which will be described below. Storage devices 1300a and 1300b can be devices using standard protocols such as Universal Flash Memory (UFS), but are not limited to these.

[0164] Image capture device 1410 can capture still images or moving images and may include, for example, a camera, a portable camcorder, and / or a webcam.

[0165] User input device 1420 can receive various types of data input from the user in system 1000, and may include, for example, a touchpad, keypad, keyboard, mouse, microphone, etc.

[0166] Sensor 1430 can detect various types of physical quantities that can be acquired from outside the system 1000 and convert the detected physical quantities into electrical signals. Sensor 1430 may include, for example, temperature sensors, pressure sensors, illuminance sensors, position sensors, accelerometers, biosensors, gyroscopes, etc.

[0167] Communication device 1440 can send signals to and receive signals from other devices outside system 1000 according to various communication protocols. Communication device 1440 may include an antenna, transceiver, and / or modem.

[0168] The display 1450 and the speaker 1460 can be used as output devices to output visual and audio information to the user of the system 1000, respectively.

[0169] The power supply device 1470 can suitably convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source to supply the converted power to each component of the system 1000.

[0170] The connection interface 1480 allows the system 1000 to connect to external devices that are connected to and can exchange data with the system 1000. The connection interface 1480 can be implemented using various interface technologies, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Mini-Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), IEEE 1394, Universal Serial Bus (USB), and Security Digital. TM (SD) card, Multi-Media Card TM (MMC), Embedded Multimedia Card Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), and (CF) card interface.

[0171] Figure 14 A schematic diagram of a UFS system 2000 according to an embodiment of the present invention is shown. The UFS system 2000 is a system conforming to the UFS standard published by the Joint Electronic Devices Engineering Committee (JEDEC) and may include a UFS host 2100, a UFS device 2200, and a UFS interface 2300. (Previously...) Figure 13 The description of System 1000 can also be applied to Figure 14 UFS system 2000, as long as the description is consistent with the following Figure 14 The descriptions do not conflict.

[0172] refer to Figure 14 UFS host 2100 and UFS device 2200 can connect to each other via UFS interface 2300. When Figure 13 When the main processor 1100 is an application processor, the UFS host 2100 can be implemented as part of the corresponding application processor. The UFS host controller 2110 and host memory 2140 can be respectively connected to… Figure 13 The main processor 1100 corresponds to the controller 1120 and the memories 1200a and 1200b. The UFS device 2200 can be... Figure 13 The storage devices 1300a and 1300b correspond to each other, and the UFS device controller 2210 and the non-volatile memory 2220 can be respectively connected to Figure 13The memory controllers 1310a and 1310b correspond to the non-volatile memories 1320a and 1320b.

[0173] UFS host 2100 may include UFS host controller 2110, application 2120, UFS driver 2130, host memory 2140, and UFS interconnect (UIC) layer 2150. UFS device 2200 may include UFS device controller 2210, non-volatile memory 2220, memory interface (I / F) 2230, device memory 2240, UIC layer 2250, and regulator 2260. Non-volatile memory 2220 may include multiple memory cells 2221. Each memory cell 2221 may include V-NAND flash memory with a 2D or 3D structure, but may also include other types of non-volatile memory, such as PRAM and / or RRAM. UFS device controller 2210 and non-volatile memory 2220 may be interconnected via memory interface 2230. Memory interface 2230 may be implemented to conform to standard protocols such as Switching or Open NAND Flash Interface Working Group (ONFI).

[0174] Application 2120 can instruct a program that can communicate with UFS device 2200 to use the functions of UFS device 2200. Application 2120 can send an Input-Output Request (IOR) to UFS drive 2130 for input-output to / from UFS device 2200. IOR can indicate read requests, write requests, and / or discard requests, but is not limited to these.

[0175] UFS drive 2130 can manage UFS host controller 2110 via UFS-Host Controller Interface (HCI) (not shown). UFS drive 2130 can translate input / output requests generated by application 2120 into UFS commands defined by the UFS standard and send the translated UFS commands to UFS host controller 2110. One input / output request can be translated into multiple UFS commands. UFS commands can be commands defined primarily by the SCSI standard, but can also be commands specific to the UFS standard.

[0176] The UFS host controller 2110 can send UFS commands translated by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 via the UIC layer 2150 and the UFS interface 2300. In this process, the UFS host register 2111 of the UFS host controller 2110 can be used as a command queue (CQ).

[0177] The UIC layer 2150 of the UFS host 2100 may include M-PHY 2151 and MIPI 2152, and the UIC layer 2250 of the UFS device 2200 may also include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0178] The UFS interface 2300 may include a line for transmitting a reference clock REF_CLK, a line for transmitting a hardware reset signal RESET_n for the UFS device 2200, a pair of lines for transmitting a pair of differential input signals DIN_T and DIN_C, and a pair of lines for transmitting a pair of differential output signals DOUT_T and DOUT_C.

[0179] The frequency value of the reference clock REF_CLK provided by the UFS host 2100 to the UFS device 2200 can be one of four values: 19.2MHz, 26MHz, 38.4MHz, and 52MHz, but is not limited to these. The UFS host 2100 can change the frequency value of the reference clock REF_CLK during operation, i.e., during data transmission and reception between the UFS host 2100 and the UFS device 2200. The UFS device 2200 can generate clocks of various frequencies based on the reference clock REF_CLK provided by the UFS host 2100 using a phase-locked loop (PLL) (not shown). Furthermore, the UFS host 2100 can also set the data rate value between the UFS host 2100 and the UFS device 2200 based on the frequency value of the reference clock REF_CLK. In other words, the data rate value can be determined based on the frequency value of the reference clock REF_CLK.

[0180] The UFS interface 2300 can support multiple channels, and each channel can be implemented as a differential pair. For example, the UFS interface may include one or more receive channels and one or more transmit channels. Figure 14 In this system, a pair of lines transmitting a pair of differential input signals DIN_T and DIN_C can form a receiving channel, and a pair of lines transmitting a pair of differential output signals DOUT_T and DOUT_C ​​can form a transmitting channel. Although Figure 14 It shows one transmit channel and one receive channel, but the number of transmit channels and the number of receive channels can be changed.

[0181] The receive and transmit channels can transmit data serially, and full-duplex communication between the UFS host 2100 and the UFS device 2200 can be achieved through a structure in which the receive and transmit channels are separated from each other. That is, even when receiving data from the UFS host 2100 via the receive channel, the UFS device 2200 can still transmit data to the UFS host 2100 via the transmit channel. Furthermore, control data such as commands from the UFS host 2100 to the UFS device 2200, as well as user data that the UFS host 2100 intends to store in or read from the non-volatile memory 2220 of the UFS device 2200, can be transmitted through the same channel. Therefore, in addition to a pair of receive channels and a pair of transmit channels, no further separate channels are needed for data transmission between the UFS host 2100 and the UFS device 2200.

[0182] The UFS device controller 2210 of the UFS device 2200 can control all operations of the UFS device 2200. The UFS device controller 2210 can manage the non-volatile memory 2220 through logic units (LUs) 2211 (e.g., logic units (circuits) 0, ..., logic units N-1) which serve as logical data storage units. The number of LUs 2211 can be eight, but is not limited to this. The UFS device controller 2210 may include a flash translation layer (FTL) (not shown) and can translate logical data addresses (e.g., logical block addresses (LBAs)) sent from the UFS host 2100 into physical data addresses (e.g., physical block addresses (PBAs)) using address mapping information from the FTL. In the UFS system 2000, the logical blocks used to store user data can have a predetermined size range. For example, the minimum size of the logical block can be set to 4KB.

[0183] When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 can perform the operation according to the input command and can send a completion response to the UFS host 2100 when the operation is completed.

[0184] For example, when UFS host 2100 intends to store user data in UFS device 2200, UFS host 2100 can send a data storage command to UFS device 2200. When it receives a response from UFS device 2200 indicating that the user data is ready for transfer, UFS host 2100 can send the user data to UFS device 2200. UFS device controller 2210 can temporarily store the sent user data in device memory 2240, and can store the user data temporarily stored in device memory 2240 at a selected location in non-volatile memory 2220 based on FTL address mapping information.

[0185] For example, when UFS host 2100 intends to read user data stored in UFS device 2200, UFS host 2100 can send a data read command to UFS device 2200. Upon receiving this command, UFS device controller 2210 can read user data from non-volatile memory 2220 based on the data read command and temporarily store the read user data in device memory 2240. During the read process, UFS device controller 2210 can detect and correct errors in the read user data by using embedded error correction code (ECC) circuitry (not shown). Furthermore, UFS device controller 2210 can send the user data temporarily stored in device memory 2240 to UFS host 2100. Additionally, UFS device controller 2210 may also include Advanced Encryption Standard (AES) circuitry (not shown), which can encrypt or decrypt data input to UFS device controller 2210 using a symmetric key algorithm.

[0186] The UFS host 2100 can sequentially store commands to be sent to the UFS device 2200 in a UFS host register 2111, which can be used as a command queue, and can send the commands to the UFS device 2200 in the aforementioned order. In this case, even while a previously sent command is still being processed by the UFS device 2200—that is, even before receiving notification that the processing of a previously sent command has been completed by the UFS device 2200—the UFS host can send the next command waiting in the command queue to the UFS device 2200, and correspondingly, the UFS device 2200 can receive the next command from the UFS host 2100 while processing the previously sent command. The maximum number of commands that can be stored in the command queue (queue depth) can be, for example, 32. Furthermore, the command queue can be implemented as a circular queue type, which indicates the start and end of the command stream stored in the queue via head and tail pointers.

[0187] Each of the plurality of memory cells 2221 may include a memory cell array and control circuitry for controlling the operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array includes a plurality of memory cells, each of which may be a single-level cell (SLC) storing 1 bit of information, or a cell storing two or more bits of information, such as a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). A 3D memory cell array may include vertically oriented vertical NAND strings, such that at least one memory cell is on top of another memory cell.

[0188] VCC, VCCQ1, VCCQ2, etc., can be used as power supply voltage inputs to the UFS device 2200. VCC is the main power supply voltage for the UFS device 2200 and can have a value from 2.4V to 3.6V. VCCQ is a power supply voltage used to provide a low-range voltage and is mainly used for the UFS device controller 2210, and can have a value from 1.14V to 1.26V. VCCQ2 is a power supply voltage used to provide a voltage in a range lower than VCC but higher than VCCQ and is mainly used for input-output interfaces such as MIPI M-PHY 2251, and can have a value from 1.7V to 1.95V. The power supply voltage can be supplied to each component of the UFS device 2200 through regulator 2260. Regulator 2260 can be implemented as a set of unit regulators, each connected to one of the aforementioned power supply voltages.

[0189] Figure 15 A block diagram illustrating a non-volatile memory according to an embodiment of the present invention is shown.

[0190] refer to Figure 15 The non-volatile memory 2220a may include a storage device 2224 and a storage controller 2222. The non-volatile memory 2220a may support multiple channels CH1 to CHm, and the storage device 2224 and the storage controller 2222 may be interconnected through multiple channels CH1 to CHm. For example, the non-volatile memory 2220a may include a storage device such as a solid-state drive (SSD). The non-volatile memory 2220a may correspond to a reference. Figures 1 to 10 The storage device 100 is described.

[0191] Storage device 2224 may include a plurality of non-volatile storage devices NVM11 to NVMmn. Each of the non-volatile storage devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, non-volatile storage devices NVM11 to NVM1n may be connected to a first channel CH1 via paths W11 to W1n, and non-volatile storage devices NVM21 to NVM2n may be connected to a second channel CH2 via paths W21 to W2n. Similarly, non-volatile storage devices NVMm1 to NVMmn may be connected to the m-th channel CHm via paths Wm1 to Wmn. In an example embodiment, each of the non-volatile storage devices NVM11 to NVMmn may include a specific memory cell capable of operating according to individual commands from storage controller 2222. For example, each of the non-volatile storage devices NVM11 to NVMmn may include a chip or die, but the inventive concept is not limited thereto.

[0192] The storage controller 2222 can send signals to and receive signals from the storage device 2224 through multiple channels CH1 to CHm. For example, the storage controller 2222 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the storage device 2224 through channels CH1 to CHm, or it can receive data DATAa to DATAm from the storage device 2224.

[0193] The storage controller 2222 can select one of the non-volatile storage devices connected to the corresponding channel via each channel, and can send signals to and receive signals from the selected non-volatile storage device. For example, the storage controller 2222 can select non-volatile storage device NVM11 from the non-volatile storage devices NVM11 to NVM1n connected to the first channel CH1. The storage controller 2222 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile storage device NVM11 via the first channel CH1, or can receive data DATAa from the selected non-volatile storage device NVM11.

[0194] The storage controller 2222 can send signals to and receive signals from the storage device 2224 in parallel through different channels. For example, the storage controller 2222 can send command CMDb to the storage device 2224 through a first channel CH1 while simultaneously sending command CMDb to the storage device 2224 through a second channel CH2. Similarly, the storage controller 2222 can receive data DATAa from the storage device 2224 through a first channel CH1 while simultaneously receiving data DATAb from the storage device 2224 through a second channel CH2.

[0195] The storage controller 2222 can control all operations of the storage device 2224. The storage controller 2222 can control the various non-volatile storage devices NVM11 to NVM1n connected to channels CH1 to CHm by sending signals to channels CH1 to CHm. For example, the storage controller 2222 can control a selected non-volatile storage device among NVM11 to NVM1n by sending command CMDa and address ADDRa to the first channel CH1.

[0196] Each of the non-volatile storage devices NVM11 to NVMmn can operate under the control of the storage controller 2222. For example, non-volatile storage device NVM11 can program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided to the first channel CH1. For example, non-volatile storage device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second channel CH2, and can send the read data DATAb to the storage controller 2222.

[0197] although Figure 15 It is shown that the storage device 2224 communicates with the storage controller 2222 through m channels and the storage device 2224 includes n non-volatile storage devices corresponding to each channel, but the number of channels and the number of non-volatile storage devices connected to a channel can be changed differently.

[0198] Storage controller 2222 may include Figure 1 The clock control circuit 124 described herein. The clock control circuit 124 can generate a clock signal CLK to adjust the timing of the memory controller 2222, and can control the switching signals (e.g., read enable signal nRE and data strobe signal DQS) provided to the memory device 2224 based on the clock signal CLK.

[0199] Figure 16A and Figure 16B A timing diagram illustrating a method of operating a storage device according to an embodiment of the present invention is shown. Figure 16A and Figure 16B It shows the connection to Figure 15 The clock signal CLK, data signal DQ, and ready-busy output signal R / nB associated with the operation periods 1602, 1604, 1606, 1608, and 1610 of the non-volatile storage devices NVM11 to NVM1n of the first channel CH1.

[0200] refer to Figure 15 and Figure 16A During the write operation period 1602, write data DIN for writing to the non-volatile storage device NVM11 can be received via the data signal DQ line. In this case, the storage controller 2222 can send the write data DIN to the non-volatile storage device NVM11 synchronously with the data strobe signal DQS generated based on the clock signal CLK which is switched to a high frequency.

[0201] During the busy period 1604, the non-volatile storage device NVM11 may send a ready-busy output signal R / nB indicating a busy state (e.g., low level) to the storage controller 2222 during the time period tPROG during which the programming operation of writing write data DIN to the storage cell is performed. During the busy period 1604 during which the ready-busy output signal R / nB is output while in a busy state, the storage controller 2222 may switch to a clock signal CLK with a low frequency.

[0202] During the read operation period 1606, the non-volatile memory device NVM12 can send output data DOUT to the memory controller 2222 via the data signal DQ line. In this case, the memory controller 2222 can send a switched read enable signal to the non-volatile memory device NVM12 based on the clock signal CLK switched to the highest frequency. The non-volatile memory device NVM12 can generate a data strobe signal based on the read enable signal switched at the highest frequency, and can send the output data DOUT to the memory controller 2222 synchronously with the data strobe signal. The non-volatile memory device NVM12 can output a busy ready-busy output signal R / nB during the time period tR during which the read operation, including the page read operation, is performed before sending the output data DOUT.

[0203] During the write operation period 1608, write data DIN for writing to the non-volatile storage device NVM1n can be received via the data signal DQ line. In this case, the storage controller 2222 can synchronously send the write data DIN to the non-volatile storage device NVM1n along with a data strobe signal DQS generated based on a clock signal CLK switched to a high frequency.

[0204] The non-volatile storage device NVM1n can send a ready-busy output signal R / nB, indicating a busy state, to the storage controller 2222 during the time period tPROG during which the programming operation of writing write data DIN to the storage cell is performed. During the busy time period 1610 during which the ready-busy output signal R / nB is output, the storage controller 2222 can switch to a clock signal CLK with a low frequency.

[0205] refer to Figure 16B ,and Figure 16A In contrast, the storage controller 2222 can control the clock signal CLK to remain unswitched during busy periods 1604a and 1610a. Compared to the high-frequency clock signal CLK, the unswitched clock signal CLK can be characterized as having a low frequency (i.e., no frequency).

[0206] According to the storage device of the present invention, the storage controller can determine a low-power operating mode and a high-power operating mode for an operation of the storage device. The storage device is controlled by switching the clock signal to a low-frequency clock signal during the low-power operating mode and by switching the clock signal to a high-frequency clock signal during the high-power operating mode. Therefore, the power consumption of the storage device can be reduced.

[0207] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. An apparatus comprising: Multiple signal pins are connected to external devices via multiple signal lines; as well as A clock control circuit is configured to instruct the external device to perform an operation having a first operating mode and a second operating mode via some of the plurality of signal pins, and is configured to generate a clock signal related to the first operating mode and the second operating mode for the operation of the external device. The clock control circuit is configured to: switch the frequency of the clock signal to a first frequency during a first operating mode of the operation, and switch the frequency of the clock signal to a second frequency different from the first frequency during a second operating mode based on a status signal of the external device provided to the device from the external device. The external device includes a non-volatile storage device, and One of the operations is a read operation of the non-volatile storage device, and The clock control circuit is configured to generate a low-frequency clock signal when the non-volatile memory device reads data stored in a memory cell of the non-volatile memory device, and to generate a high-frequency clock signal when the non-volatile memory device sends data read from the non-volatile memory device to the device.

2. The apparatus of claim 1, wherein, The first operating mode is a low-power operating mode associated with a clock signal having the first frequency, and the second operating mode is a high-power operating mode associated with a clock signal having the second frequency.

3. The apparatus of claim 1, wherein, The first frequency is a low frequency, and the second frequency is a high frequency.

4. The apparatus of claim 1, wherein, When the non-volatile storage device reads the data stored in the storage cell, the clock signal does not switch.

5. The apparatus of claim 1, wherein, The device receives a status signal indicating a busy state via one of the plurality of signal pins during the first operating mode of the one operation performed by the external device, and The clock control circuit is configured to generate a clock signal with the first frequency based on the status signal indicating a busy state, the first frequency being set to a relatively low frequency.

6. The apparatus according to claim 5, wherein, The device receives the status signal declaring it to be in a ready state during the second operating mode of one of the operations performed by the external device, and The clock control circuit is configured to generate a clock signal having the second frequency based on the state signal being in a ready state, the second frequency being set to a relatively high frequency.

7. An apparatus comprising: Multiple signal pins are connected to external devices via multiple signal lines; as well as A clock control circuit is configured to instruct the external device to perform an operation having a first operating mode and a second operating mode via some of the plurality of signal pins, and is configured to generate a clock signal related to the first operating mode and the second operating mode for the operation of the external device. The clock control circuit is configured to: switch the frequency of the clock signal to a first frequency during a first operating mode of the operation, and switch the frequency of the clock signal to a second frequency different from the first frequency during a second operating mode based on a status signal of the external device provided to the device from the external device. The external device includes a non-volatile storage device. One of the operations is a write operation to the non-volatile memory device, and The clock control circuit is configured to generate a high-frequency clock signal when sending write data to the non-volatile memory device, and to generate a low-frequency clock signal when the non-volatile memory device programs the write data into the memory cell of the non-volatile memory device.

8. The apparatus according to claim 7, wherein, The clock signal does not switch while the written data is programmed into the memory cell of the non-volatile memory device.

9. The apparatus according to claim 7, wherein, The device receives a status signal indicating a busy state via one of the plurality of signal pins during the first operating mode of the one operation performed by the external device, and The clock control circuit is configured to generate a clock signal with the first frequency based on the status signal indicating a busy state, the first frequency being set to a relatively low frequency.

10. The apparatus according to claim 9, wherein, The device receives the status signal declaring it to be in a ready state during the second operating mode of one of the operations performed by the external device, and The clock control circuit is configured to generate a clock signal having the second frequency based on the state signal being in a ready state, the second frequency being set to a relatively high frequency.

11. A storage controller, comprising: Multiple signal pins are connected to non-volatile memory devices via multiple signal lines; as well as A clock control circuit is configured to instruct the non-volatile memory device to perform operations having a first operating mode and a second operating mode via some of the plurality of signal pins, and is configured to generate clock signals related to the first operating mode and the second operating mode for the operations of the non-volatile memory device, wherein the operations are read operations or write operations. The clock control circuit is configured to: switch the frequency of the clock signal to a first frequency during the first operating mode of the operation, and switch the frequency of the clock signal to a second frequency different from the first frequency during the second operating mode based on the declarative status signal of the non-volatile memory device provided from the non-volatile memory device to the memory controller. The clock control circuit is configured to set the second frequency of the clock signal to be relatively high when the non-volatile storage device sends read data to the storage controller during the read operation, compared to when the non-volatile storage device receives write data from the storage controller during the write operation.

12. The storage controller according to claim 11, wherein, The status signal is associated with the ready-busy output signal of the non-volatile storage device, and The ready-busy output signal indicates the ready state of the non-volatile memory device when the internal operation of the non-volatile memory device has not been executed or has been completed, and the ready-busy output signal indicates the busy state of the non-volatile memory device when the internal operation of the non-volatile memory device is executed.

13. The storage controller according to claim 12, wherein, The read operation of the non-volatile storage device includes: reading data stored in the memory cells of the non-volatile storage device; and sending the read data to the memory controller. The first operation mode of the read operation is associated with reading data stored in the memory cell of the non-volatile storage device, and the second operation mode of the read operation is associated with sending the read data to the memory controller.

14. The storage controller according to claim 13, wherein, During the reading of data stored in the memory cells of the non-volatile memory device, a declaration of the ready-busy output signal is provided from the non-volatile memory device to the memory controller.

15. The storage controller according to claim 13, wherein, During the second operating mode of the read operation, the second frequency of the clock signal is higher than the first frequency of the clock signal during the first operating mode of the read operation.

16. The storage controller according to claim 12, wherein, The write operation of the non-volatile storage device includes: receiving write data from the storage controller; and programming the write data into the storage cells of the non-volatile storage device. The first operating mode of the write operation is associated with programming write data into the memory cell of the non-volatile memory device, and the second operating mode of the write operation is associated with receiving write data from the memory controller.

17. The storage controller of claim 16, wherein, The declaration of the status signal is provided from the non-volatile storage device to the storage controller during the process of writing data to the storage cell of the non-volatile storage device.

18. The storage controller according to claim 16, wherein, During the second operating mode of the write operation, the second frequency of the clock signal is higher than the first frequency of the clock signal during the first operating mode of the write operation.

19. The storage controller according to claim 11, wherein, The clock signal is associated with the data strobe signal.

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