Electronic device

Abstract

Disclosed is an electronic device including a display layer including emission regions providing light of different colors, respectively, and non-emission regions adjacent thereto. A sensor layer includes a first sensing insulating layer, a first conductive layer, a second sensing insulating layer, and a second conductive layer, and includes mesh lines extending in a first direction and a second direction. The mesh lines include a first line extending in the first direction, a second line and a third line extending in the second direction from opposite sides of the first line, and a fourth line spaced apart from the third line in the first direction and extending in the second direction from the first line. An enhancement pattern is disposed in an inner region defined by each of the second line to the fourth line from the first line, respectively. The enhancement pattern protrudes from a portion of each of the inner regions defined by the first line to the fourth line.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0179637, filed on December 21, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to an electronic device comprising a sensor layer having increased rigidity and sensing sensitivity. Background Technology

[0003] Electronic devices may include a display layer for displaying images and a sensor layer for sensing external input. The sensor layer may include multiple electrodes. Electronic devices with active areas of various shapes have recently been developed. For example, a sensor layer configured to sense external input can be incorporated into wearable electronic devices such as smartwatches. Summary of the Invention

[0004] The present invention provides an electronic device comprising a sensor layer having increased rigidity and sensing sensitivity.

[0005] According to an embodiment of the present invention, an electronic device includes a display layer comprising a plurality of emitting regions that respectively provide light of different colors and non-emitting regions adjacent to the plurality of emitting regions. A sensor layer includes a first sensing insulating layer disposed on the display layer, a first conductive layer disposed on the first sensing insulating layer, a second sensing insulating layer disposed on the first sensing insulating layer to cover the first conductive layer, and a second conductive layer disposed on the second sensing insulating layer and including grid lines extending in a first and second direction that intersect each other. The grid lines include a first line extending in the first direction, a second line extending in the second direction from a first side of the first line, a third line extending in the second direction from a second side of the first line, and a fourth line spaced apart from the third line in the first direction and extending in the second direction from the second side of the first line, the second side of the first line being opposite to the first side of the first line. An enhancement pattern is disposed in an inner region defined by each of the second, third, and fourth lines, respectively, and the first line. A portion of the enhancement pattern protrudes from each inner region defined by the first line to the fourth line.

[0006] In an embodiment, the angle between the first to fourth lines defining each of the inner regions and the reinforcing pattern can be about 15 degrees or more to about 35 degrees or less.

[0007] In one embodiment, the enhancement pattern may be symmetrical with respect to a virtual extension line that passes through the center of the enhancement pattern and extends diagonally relative to each of the first and second directions.

[0008] In an embodiment, the portion of the reinforcement pattern facing the inner region may have a predetermined curvature.

[0009] In an embodiment, the enhancement pattern may have a width that gradually narrows from the intersection of the first line to the fourth line defining the inner region in the first and second directions.

[0010] In an embodiment, the emission region may include: a first emission region disposed to the left of the first line to provide a first color; a second emission region disposed to the right of the first line and above the fourth line to provide a second color; and a third emission region disposed to the right of the first line and below the fourth line to provide a third color, wherein the first emission region may include a first first emission region and a second first emission region, the first first emission region and the second first emission region being spaced apart from each other in a first direction and having different areas from each other, and a non-emission region between the first first emission region and the second first emission region.

[0011] In an embodiment, the distance in the plane from one side of each of the first to the third emission regions to the corresponding grid line in the adjacent grid line can be less than or equal to the distance from the corner of each of the first to the third emission regions to the adjacent enhancement pattern.

[0012] In an embodiment, an emission groove may be defined in at least one of the second emission region and the third emission region, a portion of which is recessed in a plane.

[0013] In an embodiment, the sensor layer may include: a plurality of first sensing electrodes arranged in a first direction, each of the first sensing electrodes including a first sensing pattern arranged in a second direction and a first bridging pattern disposed between the first sensing patterns; and a plurality of second sensing electrodes insulated from the first sensing electrodes and arranged in a second direction, each of the second sensing electrodes including a second sensing pattern arranged in the first direction and a second bridging pattern disposed between the second sensing patterns, wherein a second conductive layer may include the first sensing pattern, the first bridging pattern and the second sensing pattern, the first conductive layer may include the second bridging pattern, a contact hole superimposed on the second bridging pattern is defined in a second sensing insulating layer, and the second sensing pattern is connected to the second bridging pattern through the contact hole.

[0014] In an embodiment, the second bridging pattern may include additional reinforcement patterns, at least a portion of each of the additional reinforcement patterns being superimposed on the reinforcement pattern.

[0015] In an embodiment, a virtual first center line may be defined that extends in a first direction and passes through the center of the first line, and the center of each of the contact holes may overlap with the corresponding lines in the third and fourth lines, and the center of each of the contact holes is spaced apart from the virtual first center line in a second direction.

[0016] In an embodiment, the additional reinforcement pattern may include: a first additional pattern angled at about 45 degrees relative to the first to fourth lines defining the inner region; and a second additional pattern angled at about 15 degrees or greater to about 35 degrees or less relative to the first to fourth lines defining the inner region.

[0017] In an embodiment, the second additional pattern may be symmetrical with respect to a virtual extension line that passes through the center of the second additional pattern and extends diagonally relative to each of the first and second directions.

[0018] In an embodiment, in the second additional pattern, the portion of the second additional pattern facing the inner region may have a predetermined curvature.

[0019] In an embodiment, a virtual first center line may be defined, extending in a first direction and passing through the center of the first line, and the contact hole may include: a first contact hole, superimposed on the third line and having a center disposed on the virtual first center line; and a second contact hole, superimposed on the fourth line and having a center spaced apart from the virtual first center line.

[0020] In one embodiment, the additional reinforcement pattern may be angled at approximately 45 degrees relative to each of the first to fourth lines defining the inner region.

[0021] In an embodiment, the additional reinforcement pattern may have the same shape as the reinforcement pattern.

[0022] In an embodiment, a virtual first center line may be defined that extends in a first direction and passes through the center of the first line, and the center of the contact hole may be on the virtual first center line.

[0023] In one embodiment, each of the contact holes may have a rhomboid shape relative to a plane defined by a first direction and a second direction.

[0024] In an embodiment, the display layer may include: a circuit layer including transistors; a light-emitting element layer including a first electrode connected to the transistors, a pixel defining layer exposing the first electrode and defining a corresponding emission region in the emission region, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer; and an encapsulation layer configured to cover the light-emitting element layer and to be stacked alternately with inorganic and organic layers, wherein the sensor layer is disposed directly on the encapsulation layer. Attached Figure Description

[0025] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate non-limiting embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0026] Figure 1 This is a plan view illustrating an application example of an electronic device according to an embodiment of the concept of the present invention;

[0027] Figure 2 This is a plan view illustrating an application example of an electronic device according to an embodiment of the inventive concept;

[0028] Figure 3A This is a perspective view of an electronic device according to an embodiment of the present invention;

[0029] Figure 3B It is along the embodiment of the concept of the present invention. Figure 3A A sectional view taken by line I-I';

[0030] Figure 4A This is a perspective view of an electronic device according to an embodiment of the present invention;

[0031] Figure 4B It is along the embodiment of the concept of the present invention. Figure 4A A sectional view taken from line II-II';

[0032] Figure 5 This is a plan view of the sensor layer according to an embodiment of the present invention;

[0033] Figure 6 This illustrates an embodiment based on the concept of the present invention. Figure 5 A floor plan of the area QQ;

[0034] Figure 7 It is along the embodiment of the concept of the present invention. Figure 6 A sectional view taken from line III-III';

[0035] Figure 8 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention;

[0036] Figure 9 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention;

[0037] Figure 10A This is an embodiment of the concept of the present invention. Figure 9 Enlarged plan view of region AA';

[0038] Figure 10B This is an embodiment of the concept of the present invention. Figure 9 Enlarged plan view of area BB';

[0039] Figure 10C This is an embodiment of the concept of the present invention. Figure 9 Enlarged plan view of region AA';

[0040] Figure 10D This is an embodiment of the concept of the present invention. Figure 9 Enlarged plan view of area BB';

[0041] Figure 11 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention;

[0042] Figure 12A This is an embodiment of the concept of the present invention. Figure 11 A magnified plan view of region CC';

[0043] Figure 12B This is an embodiment of the concept of the present invention. Figure 11 A magnified plan view of region DD';

[0044] Figure 13 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention; and

[0045] Figure 14 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention. Detailed Implementation

[0046] In this specification, it will be understood that when a component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" or "attached to" another component, the component may be directly disposed on / directly connected to / directly attached to the other component, or there may be an intervening third component. When a component (or region, layer, part, etc.) is referred to as being "directly on" another component, "directly connected to" or "directly attached to" another component, there may be no intervening third component.

[0047] The same reference numerals always denote the same elements. Furthermore, for clarity, the thickness, scale, and dimensions of components are exaggerated in the accompanying drawings.

[0048] The term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0049] It will be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. Terms are used only to distinguish one element from others. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise stated, singular terms may include plural forms.

[0050] In addition, terms such as "below," "under," "above," and "above" are used to explain the related relationships of the components shown in the accompanying drawings. The terms can be relative concepts and are described based on the directions expressed in the drawings.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted as having overly ideal or formal meanings unless explicitly defined herein.

[0052] The terms "comprising" or "including" describe properties, fixed quantities, steps, operations, elements, components, or combinations thereof, but do not exclude other properties, fixed quantities, steps, operations, elements, components, or combinations thereof. In the following description, embodiments of the inventive concept will be illustrated with reference to the accompanying drawings.

[0053] Figure 1 This is a plan view illustrating an application example of an electronic device according to an embodiment of the present invention. Figure 2 This is a plan view illustrating an application example of an electronic device according to an embodiment of the present invention. Figure 3A This is a perspective view of an electronic device according to an embodiment of the inventive concept. Figure 3B It is along Figure 3A A sectional view taken from line I-I'.

[0054] Reference Figure 1 and Figure 2 In some embodiments, electronic devices 1000 and 1000-1 can be applied to wearable devices 1000WA and 1000WB.

[0055] like Figures 1-2As shown in the embodiments, electronic devices 1000 and 1000-1 can be smartwatches. However, the embodiments of the inventive concept are not limited to this, and electronic devices 1000 and 1000-1 can be applied to various different wearable devices. Electronic devices 1000 and 1000-1 can display one or more moving images and / or still images, such as time information, weather information, telephone call information, or icons for performing various applications or operations. However, the embodiments of the inventive concept are not limited to this, and electronic devices 1000 and 1000-1 can display various different images. Users can operate electronic devices 1000 and 1000-1 through touch operations.

[0056] like Figure 1 As shown in the embodiments, Figure 1 The wearable device 1000WA shown in the diagram may have a circular shape in a planar view (e.g., in a plane defined by a first direction DR1 and a second direction DR2). Furthermore, as... Figure 2 As shown in the embodiments, the wearable device 1000WB may have a rectangular or square shape with rounded corners in a plan view. However, the embodiments of the present invention are not limited to this, and the shape of the wearable device in a plan view may vary.

[0057] In the following description, for ease of explanation, the electronic device 1000 will be based on a wearable device 1000WA having a circular shape. However, the description of all components of the electronic device 1000 can also be applied to a wearable device 1000WB having a square shape or another shape.

[0058] Reference Figure 3A and Figure 3B In some embodiments, the active area 1000A and the peripheral area 1000N may be defined on the electronic device 1000. The peripheral area 1000N may be disposed adjacent to the active area 1000A to surround the active area 1000A. For example, as Figure 3A As shown in the embodiments, the peripheral region 1000N can (e.g., along the first direction DR1 and the second direction DR2) completely surround the active region 1000A. However, embodiments of the inventive concept are not limited thereto.

[0059] The electronic device 1000 can display images and sense externally applied input through the active area 1000A. For example, in an embodiment, the input can be user input, such as the touch of a user's finger.

[0060] The active area 1000A may include a plane defined by a first direction DR1 and a second direction DR2. However, embodiments of the inventive concept are not limited thereto. For example, the active area 1000A may include a curved surface or may include both a curved surface and a flat surface. In this specification, a third direction DR3 intersecting both the first direction DR1 and the second direction DR2 may be referred to as the thickness direction of the electronic device 1000.

[0061] The electronic device 1000 may include a display layer 100 and a sensor layer 200.

[0062] Display layer 100 can be configured to substantially generate an image. In embodiments, display layer 100 can be an emitting display layer (such as an organic emitting display layer, a quantum dot display layer, or a micro-LED display layer) or a non-emitting display layer. In this embodiment, for ease of explanation, display layer 100 will be described as an organic emitting display layer. However, embodiments of the inventive concept are not limited thereto.

[0063] Sensor layer 200 may be disposed on display layer 100. Sensor layer 200 can sense external input applied from the outside. External input may be user input. User input can be provided in various forms. For example, user input may include external input applied near or at a predetermined distance from electronic device 1000 (e.g., hovering) and external input in direct contact with a part of the human body (such as the user's hand). Furthermore, external input can be provided in various forms, such as force, pressure, light, etc., and is not limited to any one embodiment.

[0064] In this embodiment, the sensor layer 200 can be disposed on the display layer 100 via a continuous process. In this embodiment, the sensor layer 200 can be referred to as being "directly" disposed on the display layer 100. Direct disposal can mean that no third component is disposed between the sensor layer 200 and the display layer 100. For example, a separate adhesive member may not be disposed between the sensor layer 200 and the display layer 100 (e.g., on a third-party DR3).

[0065] like Figure 3A As shown in the embodiments, the electronic device 1000 may include a display pad (or "solder pad") 100PD electrically connected to the display layer 100 and a sensor pad 200PD (hereinafter referred to as a pad) electrically connected to the sensor layer 200. In one embodiment, a printed circuit film may be attached to the display pad 100PD and the pad 200PD. However, embodiments of the inventive concept are not limited thereto. For example, in one embodiment, a first printed circuit film may be attached to the display pad 100PD, and a second printed circuit film may be attached to the pad 200PD. The printed circuit film may be connected to a motherboard.

[0066] Reference Figure 3B In some embodiments, the display layer 100 may include a substrate layer 101, a circuit layer 102, a light-emitting element layer 103, and an encapsulation layer 104.

[0067] The substrate layer 101 may be a substrate layer providing a substrate surface on which the circuit layer 102 is disposed. In embodiments, the substrate layer 101 may be a glass substrate, a metal substrate, a plastic substrate, or a polymer substrate. For example, in embodiments, the substrate layer 101 may be an inorganic layer, an organic layer, or a composite layer.

[0068] The substrate layer 101 may have a multilayer structure. For example, in an embodiment, the substrate layer 101 may include a first synthetic resin layer and silicon dioxide (SiO2) disposed on the first synthetic resin layer. x The substrate layer comprises a first synthetic resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second synthetic resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as substrate barrier layers. However, embodiments of the present invention are not limited thereto. For example, in an embodiment, substrate layer 101 may include a first synthetic resin layer, an adhesive layer, and a second synthetic resin layer.

[0069] Each of the first and second synthetic resin layers may include a polyimide resin. Furthermore, each of the first and second synthetic resin layers may include at least one compound selected from acrylate resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. In this specification, "~~" type resin refers to a functional group including "~~".

[0070] Circuit layer 102 may be disposed on substrate layer 101 (e.g., directly disposed on substrate layer 101 on third-party DR3). Circuit layer 102 may include insulating layers, semiconductor patterns, conductive patterns, and signal lines. In embodiments, insulating layers, semiconductor layers, and conductive layers may be formed on substrate layer 101 by means such as coating or vapor deposition, and then the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by multiple photolithography processes. Subsequently, semiconductor patterns, conductive patterns, and signal lines disposed in circuit layer 102 may be provided. However, embodiments of the inventive concept are not limited thereto.

[0071] In an embodiment, at least one inorganic layer may be disposed on the top surface of the substrate layer 101. In an embodiment, the inorganic layer may include at least one compound selected from alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be configured as multiple layers. Multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In this embodiment, the display layer 100 is shown as including a buffer layer BFL.

[0072] The buffer layer BFL can increase the adhesion between the substrate layer 101 and the semiconductor pattern. In an embodiment, the buffer layer BFL may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and silicon nitride layer may be stacked alternately. However, the embodiments of the present invention are not limited thereto.

[0073] Semiconductor patterns can be disposed on the buffer layer BFL (e.g., directly on the buffer layer BFL on the third-party DR3). In embodiments, the semiconductor pattern may include polycrystalline silicon. However, embodiments of the present invention are not limited thereto. For example, the semiconductor pattern may include amorphous silicon or metal oxide.

[0074] Figure 3B Only a portion of the semiconductor pattern is shown. For example, the semiconductor pattern could also be set in... Figure 3B Other areas not shown. In embodiments, semiconductor patterns may be arranged throughout the pixels according to specific rules. Depending on whether the semiconductor pattern is doped, it has different electrical properties. The semiconductor pattern may include doped and undoped regions. Doped regions may be doped with N-type or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant.

[0075] Doped regions can have higher conductivity than undoped regions and can essentially be used as electrodes or signal lines. Undoped regions can essentially correspond to the active region (or channel) of a transistor. For example, a portion of a semiconductor pattern can be the active region of a transistor, another portion can be the source or drain of a transistor, and yet another portion can be a connection electrode or a connection signal line.

[0076] In one embodiment, each pixel may have an equivalent circuit including seven transistors, a capacitor, and a light-emitting element. However, the embodiments of the present invention are not limited to this, and the equivalent circuit diagram of the pixel can be modified in various forms. Figure 3B The example shows a transistor 100PC and a light-emitting element 100PE disposed in a pixel.

[0077] The source (SC), active region (AL), and drain (DR) of transistor 100PC can be provided by a semiconductor pattern. The source (SC) and drain (DR) can extend in opposite directions from the active region (AL) in a cross-section. For example, as... Figure 3B As shown in the embodiments, the source SC and drain DR can be spaced apart from each other in the second direction DR2, and the active region AL is disposed between the source SC and the drain DR. However, the embodiments of the present invention are not limited thereto. Figure 3BA portion of the connection signal line SCL, formed by a semiconductor pattern, is shown. In an embodiment, the connection signal line SCL may be connected to the drain DR of transistor 100PC.

[0078] The first insulating layer 10 may be disposed on the buffer layer BFL (e.g., directly disposed on the buffer layer BFL on the third-party DR3). In embodiments, the first insulating layer 10 is commonly stacked with a plurality of pixels to cover a semiconductor pattern. The first insulating layer 10 may include an inorganic layer and / or an organic layer and has a single-layer or multi-layer structure. For example, in embodiments, the first insulating layer 10 may include at least one compound selected from alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may include a single-layer silicon oxide layer. In addition to the first insulating layer 10, the insulating layers of the circuit layer 102, which will be described later, may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure. Inorganic layers may include at least one of the materials described above, but are not limited thereto.

[0079] The gate GT of transistor 100PC is disposed on the first insulating layer 10 (e.g., directly disposed on the first insulating layer 10 on the third-direction DR3). In an embodiment, the gate GT may be part of a metal pattern. The gate GT is stacked with the active region AL (e.g., stacked on the third-direction DR3). In a process of doping semiconductor patterns, the gate GT may be used as a mask.

[0080] The second insulating layer 20 may be disposed on the first insulating layer 10 (e.g., directly disposed on the first insulating layer 10 on the third-direction DR3) to cover the gate GT. In embodiments, the second insulating layer 20 may be stacked in common with the pixel. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In this embodiment, the second insulating layer 20 may be a single-layer silicon oxide layer or a silicon nitride layer.

[0081] The third insulating layer 30 can be disposed on the second insulating layer 20 (for example, directly disposed on the second insulating layer 20 on the third-direction DR3). In this embodiment, the third insulating layer 30 can be a single layer of silicon oxide or silicon nitride.

[0082] The first connecting electrode CNE1 can be disposed on the third insulating layer 30 (e.g., directly disposed on the third insulating layer 30 on the third directional DR3). Figure 3B As shown in the embodiment, the first connection electrode CNE1 can be connected to the connection signal line SCL through the first contact hole CNT-1 passing through the first insulating layer 10 to the third insulating layer 30.

[0083] A fourth insulating layer 40 may be disposed on the third insulating layer 30 (e.g., directly disposed on the third insulating layer 30 on the third-direction DR3). In an embodiment, the fourth insulating layer 40 may be a single-layer silicon oxide layer. However, embodiments of the present invention are not limited thereto. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40 (e.g., directly disposed on the fourth insulating layer 40 on the third-direction DR3). In an embodiment, the fifth insulating layer 50 may be an organic layer.

[0084] The second connecting electrode CNE2 can be disposed on the fifth insulating layer 50 (for example, directly disposed on the fifth insulating layer 50 on the third-direction DR3). Figure 3B As shown in the embodiment, the second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the second contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0085] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 (e.g., directly disposed on the fifth insulating layer 50 on the third-direction DR3) to cover the second connection electrode CNE2. In an embodiment, the sixth insulating layer 60 may be an organic layer.

[0086] The light-emitting element layer 103 may be disposed on the circuit layer 102 (e.g., directly disposed on the circuit layer 102 on the third-party DR3). The light-emitting element layer 103 may include a light-emitting element 100PE. For example, in embodiments, the light-emitting element layer 103 may include organic light-emitting materials, quantum dots, quantum rods, or micro-LEDs. Hereinafter, the light-emitting element 100PE is described as an example of an organic light-emitting element. However, embodiments of the inventive concept are not limited thereto.

[0087] The light-emitting element 100PE may include a first electrode AE, an emitting layer EL, and a second electrode CE.

[0088] The first electrode AE ​​can be disposed on the sixth insulating layer 60 (e.g., directly disposed on the sixth insulating layer 60 on the third-direction DR3). Figure 3B As shown in the embodiment, the first electrode AE ​​can be connected to the second connecting electrode CNE2 through the third contact hole CNT-3 passing through the sixth insulating layer 60.

[0089] A pixel defining layer 70 may be disposed on the sixth insulating layer 60 to cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining layer 70. The opening 70-OP of the pixel defining layer 70 exposes at least a portion of the first electrode AE. For example, as... Figure 3B As shown in the embodiments, the pixel defining layer 70 may cover the side end of the first electrode AE, and the opening 70-OP may expose the central portion of the first electrode AE. However, embodiments of the present invention are not limited thereto.

[0090] An active area 1000A of an electronic device 1000 according to an embodiment of the present invention may include an emitting region PXA and a non-emitting region NPXA adjacent to the emitting region PXA. The non-emitting region NPXA may surround the emitting region PXA. In this embodiment, the emitting region PXA may correspond to the portion of the first electrode AE ​​exposed by the opening 70-OP, and may be defined as the region of the opening 70-OP. A plurality of emitting regions PXA may be arranged in the active area 1000A. This will be described later.

[0091] An emitting layer EL can be disposed on a first electrode AE. The emitting layer EL can be disposed in a region corresponding to the opening 70-OP. For example, the emitting layer EL can be patterned to overlap with the first electrode AE ​​(e.g., on a third-direction DR3), and the side ends of the emitting layer EL can directly contact the pixel defining layer 70. In an embodiment, each emitting layer EL can emit light of at least one color selected from blue, red, and green. However, embodiments of the inventive concept are not limited thereto. For example, the color of light emitted by one or more emitting layer ELs can be a variety of other colors. Additionally, the emitting layer ELs can be commonly configured to be connected to a pixel. In this embodiment, the emitting layer EL can provide blue light or white light.

[0092] The second electrode CE can be disposed on the emitter layer EL. In an embodiment, the second electrode CE can have a monolithic shape and be commonly disposed across multiple pixels.

[0093] In one embodiment, a hole control layer may be disposed between the first electrode AE ​​and the emitter layer EL. The hole control layer may be commonly disposed in the emitter region PXA and the non-emitter region NPXA. The hole control layer may include a hole transport layer and may also include a hole injection layer. In another embodiment, an electron control layer may be disposed between the emitter layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may also include an electron injection layer. The hole control layer and the electron control layer may be formed by commonly extending across multiple pixels using an aperture mask.

[0094] The encapsulation layer 104 may be disposed on the light-emitting element layer 103 (e.g., directly disposed on the light-emitting element layer 103 on a third-direction DR3). In embodiments, the encapsulation layer 104 may include an inorganic layer, an organic layer, and an inorganic layer stacked sequentially. However, embodiments of the present invention are not limited thereto, and the layers constituting the encapsulation layer 104 may vary. For example, the encapsulation layer 104 may include at least one inorganic layer and at least one organic layer, and the number of inorganic and organic layers may vary.

[0095] The inorganic layer protects the light-emitting element layer 103 from moisture and oxygen, while the organic layer protects it from foreign substances such as dust particles. In embodiments, the inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. However, embodiments of the present invention are not limited thereto. The organic layer may include an acrylic organic layer. However, embodiments of the present invention are not limited thereto.

[0096] like Figure 3B As shown in the embodiments, the sensor layer 200 may include a first sensing insulating layer 201, a first conductive layer 202, a second sensing insulating layer 203, a second conductive layer 204, and a covering insulating layer 205.

[0097] In one embodiment, the first sensing insulating layer 201 may be an inorganic layer comprising at least one compound selected from silicon nitride, silicon oxynitride, and silicon oxide. However, embodiments of the present invention are not limited thereto. For example, in one embodiment, the first sensing insulating layer 201 may be an organic layer comprising epoxy resin, acrylic resin, or imide resin. The first sensing insulating layer 201 may have a monolayer structure or a multilayer structure in which multiple layers are stacked on a third-direction DR3.

[0098] Each of the first conductive layer 202 and the second conductive layer 204 may have a single-layer structure or a multilayer structure in which multiple layers are stacked on a third-direction DR3.

[0099] In an embodiment, the conductive layer having a single-layer structure may include a metal layer comprising molybdenum, silver, titanium, copper, aluminum, or alloys thereof.

[0100] A conductive layer with a multilayer structure may include a metal layer. In an embodiment, the metal layer may have a titanium / aluminum / titanium three-layer structure. A conductive layer with a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0101] In embodiments where each of the first conductive layer 202 and the second conductive layer 204 includes a metal layer, the first conductive layer 202 and the second conductive layer 204 may be opaque. Therefore, the first conductive layer 202 and the second conductive layer 204 may be patterned to not overlap with the emitting region PXA (e.g., on the third-direction DR3) and to overlap with the non-emitting region NPXA (e.g., on the third-direction DR3).

[0102] In an embodiment, at least one of the second sensing insulating layer 203 and the covering insulating layer 205 may include an inorganic layer. For example, in an embodiment, the inorganic layer may include at least one compound selected from alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0103] In an embodiment, at least one of the second sensing insulating layer 203 and the covering insulating layer 205 may include an organic layer. For example, in an embodiment, the organic layer may include at least one material selected from acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0104] A portion of the first conductive layer 202 and a portion of the second conductive layer 204 can be connected to each other through contact holes CNT defined in the second sensing insulating layer 203.

[0105] Figure 4A This is a perspective view of an electronic device according to an embodiment of the present invention. Figure 4B It is along Figure 4A The sectional view taken from line II-II'.

[0106] Reference Figure 4A and Figure 4B In some embodiments, the electronic device 1000_1 may include a first substrate 100_1 and a second substrate 200_1. The first substrate 100_1 may be referred to as a display layer, and the second substrate 200_1 may be referred to as a sensor layer.

[0107] In an embodiment, the first substrate 100_1 and the second substrate 200_1 can be bonded to each other by a bonding member. For example, the bonding member can be disposed between the first substrate 100_1 and the second substrate 200_1 (e.g., on a third-direction DR3) and can be disposed in the peripheral region 1000N. The bonding member can include inorganic or organic materials. For example, in an embodiment, the inorganic material can include a glass frit seal, and the organic material can include a photocurable resin or a photoplastic resin. However, embodiments of the present invention are not limited thereto, and the materials forming the bonding member can vary.

[0108] The first substrate 100_1 may include a substrate layer 101, a circuit layer 102, and a light-emitting element layer 103. (Previously referred to...) Figure 3A and Figure 3B The embodiments described the substrate layer 101, the circuit layer 102, and the light-emitting element layer 103, so repeated descriptions will be omitted for ease of explanation.

[0109] The second substrate 200_1 may include a base substrate 201_1, a first conductive layer 202_1, a second sensing insulating layer 203_1, a second conductive layer 204_1, and a covering insulating layer 205_1.

[0110] In some embodiments, the substrate 201_1 may be a glass substrate, a metal substrate, or a polymer substrate. However, the embodiments of the present invention are not limited thereto. For example, in some embodiments, the substrate 201_1 may be an inorganic layer, an organic layer, or a composite layer.

[0111] The first conductive layer 202_1 may include a conductive layer 202_1. Figure 3B The metal layer in the first conductive layer 202 described in the embodiment. In this embodiment, the second conductive layer 204_1 may include a transparent conductive layer. In this case, the second conductive layer 204_1 may be stacked with both the emitting region PXA and the non-emitting region NPXA (e.g., on a third-direction DR3).

[0112] In this embodiment, the transparent conductive layer disposed in the second conductive layer 204_1 may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium zinc tin oxide (IZTO). Furthermore, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, and graphene.

[0113] In an embodiment, at least one insulating layer may also be disposed between the substrate 201_1 and the first conductive layer 202_1. The at least one insulating layer may be formed directly on the substrate 201_1, or it may be bonded to the substrate 201_1 via an adhesive layer. The adhesive component may include general adhesives or bonding agents.

[0114] The first substrate 100_1 may include a display pad 100PD_1, and the second substrate 200_1 may include a sensor pad 200PD_1 (hereinafter referred to as a pad). In an embodiment, a first printed circuit film may be attached to the display pad 100PD_1, and a second printed circuit film may be attached to the pad 200PD_1.

[0115] Display pad 100PD_1 is electrically connected to circuit layer 102 to provide signals to circuit layer 102. Sensor pad 200PD_1 is electrically connected to first conductive layer 202_1 and second conductive layer 204_1 to provide signals to or receive signals from first conductive layer 202_1 and second conductive layer 204_1.

[0116] Figure 5 This is a plan view of the sensor layer according to an embodiment of the present invention. Figure 6 It is shown Figure 5 A floor plan of the area QQ. Figure 7 It is along Figure 6 A sectional view taken along line III-III'. The same / similar reference numerals are used with... Figures 1 to 4BThe embodiments are identical or similar in construction, and redundant descriptions have been omitted for ease of explanation.

[0117] Reference Figure 5 The sensing area 200A and the peripheral area 200N can be defined within the sensor layer 200. The sensing area 200A is the area for sensing external input and can be connected to... Figure 3A The active area 1000A of the embodiment is superimposed (e.g., on a third-party DR3). The peripheral area 200N surrounds the sensing area 200A and can be coupled with... Figure 3A The peripheral region 1000N of the embodiment is superimposed (e.g., on the third-direction DR3). In this embodiment, in the plan view, the boundary 200BD between the sensing region 200A and the peripheral region 200N can be circular.

[0118] The sensor layer 200 according to an embodiment of the present invention may include a first sensing electrode 210, a second sensing electrode 220, multiple traces 231, 232, 241 and 242, and a sensor pad 200PD.

[0119] The first sensing electrode 210 extends in the second direction DR2. Multiple first sensing electrodes 210 may be configured and may be arranged in the first direction DR1. The first sensing electrode 210 includes multiple first sensing patterns SP1 arranged in the second direction DR2 and (e.g., in the second direction DR2) a first bridging pattern BP1 disposed between the first sensing patterns SP1 to connect adjacent first sensing patterns SP1 to each other.

[0120] The second sensing electrode 220 may be configured to be insulated from the first sensing electrode 210. The second sensing electrode 220 extends in the first direction DR1. Multiple second sensing electrodes 220 may be configured and may be arranged in the second direction DR2. The second sensing electrode 220 includes multiple second sensing patterns SP2 arranged in the first direction DR1 and (e.g., in the first direction DR1) second bridging patterns BP2 disposed between the second sensing patterns SP2 to connect adjacent second sensing patterns SP2 to each other.

[0121] In an embodiment, the sensor layer 200 can sense changes in the mutual capacitance between the first sensing electrode 210 and the second sensing electrode 220 to sense an external input, or sense changes in the self-capacitance of each of the first sensing electrode 210 and the second sensing electrode 220 to sense an external input. The sensor layer 200 according to embodiments of the present invention can sense the external input TC in various ways, but is not limited to one embodiment.

[0122] Traces 231, 232, 241 and 242 may include first traces 231 and 232 connected to the corresponding first sensing electrode 210 and second traces 241 and 242 connected to the corresponding second sensing electrode 220.

[0123] The first trace 231 can be connected to the corresponding end of the first sensing electrode 210 disposed on the first side, and the second trace 232 can be connected to the corresponding other end of the first sensing electrode 210 disposed on the second side.

[0124] The first and second traces 241 can be connected to the corresponding ends of the second sensing electrode 220 disposed on the first side, and the second trace 242 can be connected to the corresponding other ends of the second sensing electrode 220 disposed on the second side. Traces 231, 232, 241, and 242 can be connected to the corresponding sensor pads 200PD.

[0125] The connection relationship between traces 231, 232, 241 and 242 and the first sensing electrode 210 and the second sensing electrode 220 is not limited thereto, and they can be connected in various ways, but are not limited to any one embodiment.

[0126] exist Figure 6 In the embodiment, some of the first sensing pattern SP1, the first bridging pattern BP1, the second sensing pattern SP2, and the second bridging pattern BP2 in the first sensing electrode 210 and the second sensing electrode 220 are shown in magnified view.

[0127] Reference Figure 6 and Figure 7 In embodiments of the present invention, components disposed in the first sensing electrode 210 and the second sensing electrode 220 may be disposed in... Figure 3B In either of the first conductive layer 202 and the second conductive layer 204 shown in the embodiments.

[0128] In the embodiments, reference is made to Figure 3B The second conductive layer 204 described in the embodiments may include a first sensing pattern SP1 of the first sensing electrode 210, a first bridging pattern BP1, and a second sensing pattern SP2 of the second sensing electrode 220. The first sensing pattern SP1 and the first bridging pattern BP1 may be patterned as a substantially integral pattern. A portion of the first bridging pattern BP1 may be superimposed on the second bridging pattern BP2 (e.g., on a third-direction DR3).

[0129] In the embodiments, reference is made to Figure 3BThe first conductive layer 202 described in the embodiments may include a second bridging pattern BP2 of the second sensing electrode 220.

[0130] The second sensing pattern SP2 and the second bridging pattern BP2 can be connected to each other through the first contact hole CNT1 and the second contact hole CNT2. Figure 3B The contact hole CNT defined in the second sensing insulating layer 203 described herein may correspond to either the first contact hole CNT1 or the second contact hole CNT2.

[0131] Traces 231, 232, 241, and 242 may be disposed in at least one of the first conductive layer 202 and the second conductive layer 204. For example, traces 231, 232, 241, and 242 may be disposed in either the first conductive layer 202 or the second conductive layer 204, or connected to each other via contact holes such as the first contact hole CNT1 or the second contact hole CNT2 defined in the second sensing insulating layer 203, so as to be disposed in both layers. However, embodiments of the inventive concept are not limited thereto.

[0132] In an embodiment of the present invention, the first sensing pattern SP1, the first bridging pattern BP1, and the second sensing pattern SP2 disposed in the second conductive layer 204 can be configured as a first grid line MSL1 and a second grid line MSL2.

[0133] The first grid line MSL1 may extend in the first direction DR1, and the second grid line MSL2 may extend in the second direction DR2. However, embodiments of the inventive concept are not limited thereto, and the first grid line MSL1 and the second grid line MSL2 may extend in various other directions that intersect each other. The first grid line MSL1 and the second grid line MSL2 may be... Figure 3B The emission region PXA (e.g., on the third-direction DR3) described in the embodiments is not superimposed, but may be superimposed with the non-emission region NPXA (e.g., on the third-direction DR3).

[0134] The region surrounded by the first grid line MSL1 and the second grid line MSL2 may surround at least a portion of the emission region PXA. This will be described in more detail below.

[0135] According to embodiments of the present invention, even if a second conductive layer 204 comprising metal is disposed on the display layer 100, the second conductive layer 204 may not affect the light supplied from the emitting layer EL. Therefore, an electronic device 1000 with improved light extraction efficiency can be provided.

[0136] Figure 8 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention. Figure 9This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention. Figure 10A This is an embodiment of the concept of the present invention. Figure 9 A magnified plan view of region AA'. Figure 10B This is an embodiment of the concept of the present invention. Figure 9 A magnified plan view of region BB'. Figure 10C This is an embodiment of the concept of the present invention. Figure 9 A magnified plan view of region AA'.

[0137] Figure 10D This is an embodiment of the concept of the present invention. Figure 9 A magnified plan view of region BB'. Same / similar reference numerals are used with... Figures 1 to 7 The elements and / or constructions described herein are the same as or similar to those described herein, and redundant descriptions have been omitted for ease of explanation.

[0138] Figure 8 and Figure 9 The diagram illustrates the arrangement of multiple emission regions PXA-B, PXA-R, and PXA-G with grid lines MSL in a plan view, according to an embodiment of the present invention.

[0139] In the following description, the arrangement of the emission regions PXA-B, PXA-R, and PXA-G with the grid line MSL in the plane (e.g., in the plane defined by the first direction DR1 and the second direction DR2) can be applied to... Figure 5 The entire active area 1000A is described in the embodiment.

[0140] Furthermore, in the embodiments, the grid lines MSL described herein can be set to... Figure 3B The second conductive layer 204 is described in the embodiment. Therefore, the grid lines MSL can be defined as included in... Figure 6 and Figure 7 The embodiments described include the first sensing pattern SP1, the first bridging pattern BP1, and the second sensing pattern SP2.

[0141] Reference Figure 8 In embodiments of the present invention, the emission regions PXA-B, PXA-R, and PXA-G can each provide light of different colors and can each have different areas. Although Figure 8 The embodiment shows three emission regions including a first emission region PXA-B, a second emission region PXA-R, and a third emission region PXA-G, but the number of emission regions and the corresponding colors of their light can vary.

[0142] The shape of each of the emission regions PXA-B, PXA-R, and PXA-G described in this specification in a plane (e.g., in a plane defined by a first direction DR1 and a second direction DR2) may correspond to when Figure 3B The pixel-defining layer 70 described herein has multiple openings 70-OP and the emission regions PXA-B, PXA-R, and PXA-G are patterned in different shapes to visually identify the shapes.

[0143] For example, in an embodiment, the first emitting region PXA-B can be a region that provides blue light. Figure 8 As shown in the embodiments, the first transmission region PXA-B may include a first first transmission region PXA-B1 and a second first transmission region PXA-B2 that are spaced apart from each other in the first direction DR1. For example, the first first transmission region PXA-B1 and the second first transmission region PXA-B2 may be spaced apart from each other in the first direction DR1, and the peripheral region NPXA is located between the first first transmission region PXA-B1 and the second first transmission region PXA-B2.

[0144] In this embodiment, the first first emission region PXA-B1 may have a relatively larger area (e.g., the area in the plane defined by the first direction DR1 and the second direction DR2) than the area of ​​the second first emission region PXA-B2. Therefore, the first width WG1 of the first first emission region PXA-B1 in the first direction DR1 may be larger than the second width WG2 of the second first emission region PXA-B2 in the first direction DR1. In the second direction DR2, the widths of the first first emission region PXA-B1 and the second first emission region PXA-B2 may be substantially the same.

[0145] Blue light supplied from the first emission region PXA-B1 and the second emission region PXA-B2 can be connected to a reference. Figure 3B The embodiments described herein allow individual transistors 100PC to be individually turned on / off, or to be simultaneously turned on / off by being connected to a single transistor 100PC, but are not limited to any one embodiment.

[0146] In an embodiment, the second emission region PXA-R can be a region that provides red light. The second emission region PXA-R can be configured to be spaced apart from the first emission region PXA-B1 in the second direction DR2, and a first grid line MSL1 superimposed on the non-emission region NPXA is disposed between the second emission region PXA-R and the first emission region PXA-B1.

[0147] In this embodiment, the second emission region PXA-R may have an "U" shape, a portion of which is recessed in a plane (e.g., in a plane defined by a first direction DR1 and a second direction DR2). For example, a second emission groove RH may be defined in the second emission region PXA-R, a portion of which is recessed from the lower part of the second emission region PXA-R in the first direction DR1.

[0148] In an embodiment, the third emission region PXA-G may be a region that provides green light. The third emission region PXA-G may be configured to be spaced apart from the second first emission region PXA-B2 in the second direction DR2, and the first grid line MSL1 superimposed on the non-emission region NPXA is located between the third emission region PXA-G and the second first emission region PXA-B2.

[0149] In this embodiment, the third emission region PXA-G may have an "U" shape, with a portion of it recessed in the plane. For example, a third emission groove GH may be defined in the third emission region PXA-G, with a portion of the third emission groove GH recessed from the upper part of the third emission region PXA-G in the first direction DR1.

[0150] like Figure 8 As shown in the embodiments, the second emission recess RH and the third emission recess GH may face each other, and the second grid line MSL2 is between the second emission recess RH and the third emission recess GH. However, the embodiments of the present invention are not limited thereto. For example, in embodiments, the second emission recess RH and the third emission recess GH may be defined in different directions, and each of the second emission recess RH and the third emission recess GH may be recessed toward the first emission region PXA-B. In addition, in embodiments, at least one of the second emission recess RH and the third emission recess GH may be omitted in the second emission region PXA-R and the third emission region PXA-G, respectively.

[0151] According to an embodiment of the present invention, the grid line MSL may include a first grid line MSL1 extending in a first direction DR1 and a second grid line MSL2 extending in a second direction DR2. A cut-out portion C-OP may be disposed at the middle portion of each grid line MSL; the cut-out portion C-OP is an area cut to prevent the user from visually recognizing the patterned shape of the grid line MSL.

[0152] The first grid line MSL1 and the second grid line MSL2 may intersect each other to define, respectively (e.g., in the first direction DR1 and the second direction DR2), a first inner region MOP-B, a second inner region MOP-R, and a third inner region MOP-G surrounding the first emission region PXA-B, the second emission region PXA-R, and the third emission region PXA-G.

[0153] For example, the first inner region MOP-B can surround the first transmission region PXA-B, the second inner region MOP-R can surround the second transmission region PXA-R, and the third inner region MOP-G can surround the third transmission region PXA-G.

[0154] Reference Figures 9 to 10B In an embodiment of the present invention, the grid line MSL can be formed by repeating a pattern comprising multiple lines.

[0155] For example, a portion of the first grid line MSL1 can be defined as the first line L1. The second grid line MSL2 can include the second to fourth lines L2, L3, and L4. The active area 1000A (see [reference]) can be formed by arranging a pattern including the first line L1, the second line L2, the third line L3, and the fourth line L4 on the first direction DR1 and the second direction DR2. Figure 3A The shape of the grid lines MSL in ).

[0156] like Figures 10A-10B As shown in the embodiment, a first line L1 may extend in a first direction DR1. A second line L2 may extend from a first side of the first line L1 in a second direction DR2. A third line L3 may extend from a second side of the first line L1 (e.g., in the second direction DR2) opposite to the first side in the second direction DR2. A fourth line L4 may be spaced apart from the third line L3 in the first direction DR1 and may extend from the first line L1 in the second direction DR2. Although Figures 10A-10B An embodiment includes four lines forming a grid line MSL, but the number of lines and their arrangement can vary.

[0157] The grid line MSL according to an embodiment of the present invention may include reinforcement patterns such as a first reinforcement pattern RP-A and a second reinforcement pattern RP-B. The reinforcement patterns such as the first reinforcement pattern RP-A and the second reinforcement pattern RP-B may be provided in the inner regions MOP-B, MOP-R, and MOP-G defined by each of the first line L1 and the second to fourth lines L2, L3, and L4, and may protrude from portions of the corresponding inner regions MOP-B, MOP-R, and MOP-G defined by lines L1, L2, L3, and L4.

[0158] In an embodiment, the enhancement pattern may include a first enhancement pattern RP-A and a second enhancement pattern RP-B.

[0159] like Figure 10A As shown in the embodiments, the first enhancement pattern RP-A may include a first pattern RP1 to a fourth pattern RP4. For example, the first pattern RP1 may be disposed in a first upper inner region MOP-BU defined by a first line L1 and a second line L2. The first pattern RP1 may protrude from the first line L1 and the second line L2 toward the first upper inner region MOP-BU.

[0160] The second pattern RP2 can be set in the first lower inner region MOP-BB defined by the first line L1 and the second line L2. The second pattern RP2 can protrude from the first line L1 and the second line L2 toward the first lower inner region MOP-BB.

[0161] Each of the first upper inner region MOP-BU and the first lower inner region MOP-BB can be defined as a region that provides blue light. For example, the first upper inner region MOP-BU and the first lower inner region MOP-BB can each surround adjacent first emission regions PXA-B that are spaced apart from each other in the first direction DR1.

[0162] The third pattern RP3 can be set in the second inner region MOP-R defined by the first line L1 and the third line L3. The third pattern RP3 can protrude from the first line L1 and the third line L3 toward the second inner region MOP-R.

[0163] The fourth pattern RP4 can be set in the third upper inner region MOP-GU defined by the first line L1 and the third line L3. The fourth pattern RP4 can protrude from the first line L1 and the third line L3 toward the third upper inner region MOP-GU.

[0164] like Figure 10B As shown in the embodiments, the second enhancement pattern RP-B may include a fifth pattern RP5 and a sixth pattern RP6. For example, the fifth pattern RP5 may be disposed in the second inner region MOP-R defined by the first line L1 and the fourth line L4. The fifth pattern RP5 may protrude from the first line L1 and the fourth line L4 toward the second inner region MOP-R. The sixth pattern RP6 may protrude from the first line L1 and the fourth line L4 toward the third lower inner region MOP-GB.

[0165] Each of the third upper inner region MOP-GU and the third lower inner region MOP-GB can be defined as an area that provides green light. For example, the third upper inner region MOP-GU and the third lower inner region MOP-GB can respectively surround adjacent third emission regions PXA-G that are spaced apart from each other in the first direction DR1, and the second emission region PXA-R is disposed therebetween.

[0166] In this embodiment, the first angle θ1 between the lines defining the corresponding inner regions in the enhancement patterns RP-A and RP-B can range from about 15 degrees to about 35 degrees. In embodiments where the first angle θ1 is less than about 15 degrees, breaks may occur in the intersection regions of the grid lines MSL patterned in micrometers. In embodiments where the first angle θ1 exceeds about 35 degrees, interference with light supplied from the emission region may occur, thereby degrading the light extraction efficiency.

[0167] like Figure 10A As shown in the embodiments, the first pattern RP1 may include a first portion R1-1 and a second portion R1-2. The first portion R1-1 and the second portion R1-2 may be symmetrical with respect to a virtual first extension line X1, which extends diagonally relative to each of the first direction DR1 and the second direction DR2 and passes through the center of the first pattern RP1. For example, the diagonal direction may be between the first direction DR1 and the second direction DR2. The third pattern RP3 may also be applied in the same manner; therefore, the first third portion R3-1 and the second third portion R3-2 may be symmetrical with respect to the virtual first extension line X1. Figure 10B As shown in the embodiment, the sixth pattern RP6 can also be applied in the same way, so that the first sixth part R6-1 and the second sixth part R6-2 can be symmetrical with respect to the virtual first extension line X1.

[0168] like Figure 10A As shown in the embodiments, the second pattern RP2 may include a first second portion R2-1 and a second second portion R2-2. The first second portion R2-1 and the second second portion R2-2 may be symmetrical with respect to a virtual second extension line X2, which extends diagonally relative to each of the first direction DR1 and the second direction DR2 and passes through the center of the second pattern RP2. In an embodiment, the virtual second extension line X2 may be perpendicular to the virtual first extension line X1. The fourth pattern RP4 may also be applied in the same manner; therefore, the first fourth portion R4-1 and the second fourth portion R4-2 may be symmetrical with respect to the virtual second extension line X2. Figure 10BAs shown in the embodiment, the fifth pattern RP5 can also be applied in the same way, so that the first fifth part R5-1 and the second fifth part R5-2 can be symmetrical with respect to the virtual second extension line X2.

[0169] According to an embodiment of the invention, the width of each of the reinforcing patterns RP-A and RP-B can gradually narrow from the intersection of the lines defining the corresponding internal regions in the first direction DR1 and the second direction DR2.

[0170] Refer again Figure 9 In one embodiment, the distance from one side of each of the first transmission region PXA-B, the second transmission region PXA-R, and the third transmission region PXA-G to each of the adjacent grid lines MSL1 and MSL2 may be less than or equal to the distance from the corner of each of the transmission regions PXA-B, PXA-R, and PXA-G to each of the adjacent enhancement patterns RP-A and RP-B.

[0171] For example, such as Figure 9 As shown in the embodiments, the first first distance WB-R from the first side of the first first emission region PXA-B1 to the first grid line MSL1 (e.g., on the second direction DR2) and the second first distance WB-L from the second side of the first first emission region PXA-B1 to the second grid line MSL2 (e.g., on the first direction DR1) can be less than or equal to the distance WB-C from the corner of the first first emission region PXA-B1 to the first enhancement pattern RP-A (e.g., in the diagonal direction between the first direction DR1 and the second direction DR2).

[0172] The first second distance WR-R from the first side of the second emission region PXA-R to the first grid line MSL1 (e.g., on the second direction DR2) and the second second distance WR-L from the second side of the second emission region PXA-R to the second grid line MSL2 (e.g., on the first direction DR1) can be less than or equal to the distance WR-C from the corner of the second emission region PXA-R to the first enhancement pattern RP-A (e.g., in the diagonal direction between the first direction DR1 and the second direction DR2).

[0173] The first third distance WG-R from the first side of the third emission region PXA-G to the first grid line MSL1 (e.g., on the second direction DR2) and the second third distance WG-L from the second side of the third emission region PXA-G to the second grid line MSL2 (e.g., on the first direction DR1) can be less than or equal to the distance WG-C from the corner of the third emission region PXA-G to the second enhancement pattern RP-B (e.g., in the diagonal direction between the first direction DR1 and the second direction DR2).

[0174] According to an embodiment of the invention, since the grid lines MSL include reinforcing patterns, such as a first reinforcing pattern RP-A and a second reinforcing pattern RP-B, arranged adjacent to each other in the intersection regions, a sensor layer 200 with increased rigidity can be provided. Furthermore, since each of the reinforcing patterns, such as the first reinforcing pattern RP-A and the second reinforcing pattern RP-B, has a shape in which interference with the emission regions PXA-B, PXA-R, and PXA-G is minimized, a display layer 100 with improved light extraction efficiency can be provided.

[0175] Reference Figure 10C and Figure 10D In an embodiment of the present invention, the first grid line MSL1 and the second grid line MSL2 may include a first reinforcement pattern RP-A1 and a second reinforcement pattern RP-B1. The description of the first line L1 to the fourth line L4 and the internal regions disposed in the grid lines MSL1 and MSL2 can be consistent with... Figure 10A and Figure 10B The same approach is applied in the embodiments, and repeated descriptions will be omitted for ease of explanation.

[0176] like Figure 10C and Figure 10D As shown in the embodiments, the portion of each of the first reinforcement pattern RP-A1 and the second reinforcement pattern RP-B1 facing the corresponding internal region may have curvature (e.g., a predetermined curvature).

[0177] For example, each of the following portions can have a predetermined curvature: the portion of the first pattern RP1 facing the first upper inner region MOP-BU, the portion of the second pattern RP2 facing the first lower inner region MOP-BB, the portion of the third pattern RP3 facing the second inner region MOP-R, and the portion of the fourth pattern RP4 facing the third upper inner region MOP-GU. For example, as... Figure 10C As shown, the outer edges of each of the first patterns RP1 to the fourth patterns RP4, which are respectively adjacent to the outer edges of the first upper inner region MOP-BU, the first lower inner region MOP-BB, the second inner region MOP-R, and the third upper inner region MOP-GU, may have a predetermined curvature.

[0178] Furthermore, the portions of the fifth pattern RP5 facing the second inner region MOP-R and the portions of the sixth pattern RP6 facing the third lower inner region MOP-GB can have predetermined curvatures. For example, as... Figure 10D As shown, the outer edges of each of the fifth pattern RP5 and the sixth pattern RP6, which are respectively adjacent to the second inner region MOP-R and the third lower inner region MOP-GB, may have a predetermined curvature.

[0179] Figure 11 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention. Figure 12A This is an embodiment of the concept of the present invention. Figure 11 A magnified plan view of region CC'. Figure 12B This is an embodiment of the concept of the present invention. Figure 11 A magnified plan view of region DD'.

[0180] Figure 11 Multiple emission regions, such as the first emission region to the third emission region PXA-B, PXA-R, and PXA-G, are shown, disposed in the second conductive layer 204 (see [link]). Figure 3B The grid lines MSL in the first conductive layer 202 (see) Figure 3B The arrangement of the second bridging patterns BP-A in the plane (e.g., in a plane defined by the first direction DR1 and the second direction DR2). Bridging patterns BP-A can be applied to... Figures 5 to 7 The second bridging pattern BP2 is described in the text.

[0181] Reference Figure 11 According to an embodiment of the present invention, the bridging pattern BP-A can be connected to the first grid line MSL1 and the second grid line MSL2 via the first contact hole CNT1 and the second contact hole CNT2. Embodiments relating to the contact holes described in the embodiments of the present invention can correspond to... Figure 3B The contact hole CNT of the second sensing insulating layer 203 described herein.

[0182] The bridging pattern BP-A can be extended to overlap with grid lines MSL1 and MSL2 (e.g., on the third direction DR3). See reference. Figure 12A and Figure 12B In embodiments, the bridging pattern BP-A may include additional reinforcement patterns, such as a first additional reinforcement pattern LP-A, a second additional reinforcement pattern LP-B, and a third additional reinforcement pattern LP-C, at least a portion of which are associated with... Figure 10A and Figure 10B The enhanced patterns RP-A and RP-B are superimposed as described in the embodiments.

[0183] In an embodiment, the first additional reinforcement pattern LP-A may include a first additional pattern LP1 and a second additional pattern LP2. In an embodiment, the first additional pattern LP1 and the second additional pattern LP2 may respectively have the same characteristics as... Figure 10A The first pattern RP1 and the second pattern RP2 described in the embodiments have the same shape. However, the embodiments of the present invention are not limited thereto. For example, in the embodiments, the outer edges of the first additional pattern LP1 and the second additional pattern LP2 may have a predetermined curvature.

[0184] The second additional reinforcement pattern LP-B may include a third additional pattern LP3 and a fourth additional pattern LP4. For example... Figure 12A As shown in the embodiment, the second angle θ2 defined in the plane by the outer edges of each of the third additional pattern LP3 and the fourth additional pattern LP4, and by each of the first grid line MSL1 and the second grid line MSL2, can be approximately 45 degrees.

[0185] like Figure 12B As shown in the embodiment, the third additional reinforcement pattern LP-C may include a fifth additional pattern LP5 and a sixth additional pattern LP6. The third angle θ3 defined by the outer edge of each of the fifth additional pattern LP5 and the sixth additional pattern LP6 and by each of the first grid line MSL1 and the second grid line MSL2 may be approximately 45 degrees.

[0186] In this embodiment, the first additional reinforcement pattern LP-A can be oriented towards Figure 8 In the embodiments described, the first emission region PXA-B, which provides blue light, protrudes from the first emission region PXA-B, the second emission region PXA-R, and the third emission region PXA-G. The second additional enhancement pattern LP-B and the third additional enhancement pattern LP-C may protrude towards the second emission region PXA-R and the third emission region PXA-G, which provide red and green light, respectively.

[0187] like Figures 11 to 12B As shown in the embodiments, a virtual first center line M1-C can be defined, extending in the first direction DR1 and passing through the center of the first grid line MSL1 (e.g., in the second direction DR2). Furthermore, a virtual second center line M2-C can be defined, extending in the second direction DR2 and passing through the center of the second grid line MSL2 (e.g., in the first direction DR1). The widths of the first portion MW1 and the second portion MW2 of the virtual second center line M2-C in the first direction DR1 can be the same.

[0188] The intersection of the virtual first centerline M1-C and the virtual second centerline M2-C can be defined as the grid center point MSL-P.

[0189] According to this embodiment, the center points CNT-P1 and CNT-P2 of the first contact hole CNT1 and the second contact hole CNT2 can be offset toward the additional reinforcement patterns LP-B and LP-C, respectively, where each of the additional reinforcement patterns LP-B and LP-C has a relatively large area. Therefore, based on the corresponding first grid line MSL1, the center point CNT-P1 of the first contact hole CNT1 and the center point CNT-P2 of the second contact hole CNT2 can be spaced apart from the grid center point MSL-P along the virtual second center line M2-C in the second direction DR2.

[0190] In an embodiment, each of the contact holes CNT1 and CNT2 may have a rhomboid shape relative to the plane defined by the first direction DR1 and the second direction DR2.

[0191] According to the embodiment, because the first contact hole CNT1 and the second contact hole CNT2 are superimposed with the additional reinforcement patterns LP-B and LP-C in the additional reinforcement patterns, each of the additional reinforcement patterns LP-B and LP-C has a relatively large area, misalignment can be reduced. Therefore, contact failure between the sensing pattern and the bridging pattern can be prevented.

[0192] Figure 13 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention. Figure 14 This is a plan view illustrating the arrangement relationship between the emission area and the grid lines according to an embodiment of the present invention. The same / similar reference numerals are used in conjunction with... Figures 11 to 12B The same / similar elements and structures are included, and redundant descriptions are omitted for ease of explanation.

[0193] Reference Figure 13 The bridging pattern BP-B can be extended to overlap with the first grid line MSL1 and the second grid line MSL2. According to this embodiment, the bridging pattern BP-B may include patterns corresponding to… Figure 12A and Figure 12B The additional reinforcement patterns LP-B and LP-C described herein are additional reinforcement patterns. Therefore, the angle defined by the additional reinforcement pattern disposed in the bridging pattern BP-B with each of the first grid line MSL1 and the second grid line MSL2 in the plane (e.g., in the plane defined by the first direction DR1 and the second direction DR2) can be approximately 45 degrees.

[0194] In this embodiment, the center point of each of the contact holes CNT-A and CNT-B can be defined differently within the bridging pattern BP-B.

[0195] For example, the center point CNT-PA of the first contact hole CNT-A can be aligned with the center point MSL-P of the grid (see...). Figure 11 The virtual first center line M1-C and the virtual second center line M2-C are superimposed and intersect each other at the grid center point MSL-P. The first part MW3 and the second part MW4 of the first grid line MSL1, which are divided by the virtual first center line M1-C, can have the same width in the second direction DR2.

[0196] In the area defining the first contact hole CNT-A in the bridging pattern BP-B, since additional reinforcing patterns at approximately 45-degree angles relative to each of the grid lines MSL1 and MSL2 are arranged in four areas, no contact failure will occur even if the first contact hole CNT-A is defined in the grid center point MSL-P.

[0197] The positioning of the contact hole center point CNT-PB of the second contact hole CNT-B can be offset toward the side where the additional reinforcing pattern BP-B is provided. Therefore, based on the corresponding first grid line MSL1, the contact hole center point CNT-PB can be spaced apart from the grid center point MSL-P along the second center line M2-C in the second direction DR2.

[0198] Reference Figure 14 In one embodiment, the bridging pattern BP-C can be extended to overlap with grid lines MSL1 and MSL2. The bridging pattern BP-C according to this embodiment may include... Figure 12A The additional reinforcement pattern corresponding to the first additional reinforcement pattern LP-A described herein. Therefore, the angle defined in the plane (e.g., in the plane defined by the additional reinforcement pattern provided in the bridging pattern BP-C and each of the first grid line MSL1 and the second grid line MSL2) can be in the range of about 15 degrees to about 35 degrees.

[0199] like Figure 14 As shown in the embodiment, the contact hole center point CNT-PC of each contact hole CNT-C can be aligned with the grid center point MSL-P (see [reference]). Figure 11 ) stacked. In this embodiment, as shown in Figure 10B If the grid lines MSL shown only define the intersection points of the three segments, the contact holes can be omitted.

[0200] According to embodiments of the present invention, a rigidly reinforced sensor layer can be provided because the grid lines disposed in the conductive layer include reinforcing patterns arranged adjacent to each other in the intersection regions. Furthermore, since the reinforcing patterns have a shape in which interference with the emission region is minimized, a display layer with improved light extraction efficiency can be provided.

[0201] It will be apparent to those skilled in the art that various modifications and deviations can be made to the inventive concept. Therefore, this disclosure is intended to cover such modifications and deviations.

[0202] Therefore, the technical scope of this invention should not be limited to the content described in the specific description of the specification, but should be determined by the claims.

Claims

1. An electronic device, the electronic device comprising: The display layer includes multiple emitting regions that provide different colors of light and non-emitting regions adjacent to the multiple emitting regions; as well as The sensor layer includes a first sensing insulating layer disposed on the display layer, a first conductive layer disposed on the first sensing insulating layer, a second sensing insulating layer disposed on the first sensing insulating layer to cover the first conductive layer, and a second conductive layer disposed on the second sensing insulating layer and including grid lines extending in a first direction and a second direction that intersect each other. The grid lines include: The first line extends in the first direction; The second line extends from the first side of the first line in the second direction; A third line extends from a second side of the first line in the second direction, the second side of the first line being opposite to the first side of the first line; A fourth line, spaced apart from the third line in the first direction and extending from the second side of the first line in the second direction; and An enhancement pattern is disposed within an interior region defined by each of the second, third, and fourth lines and the first line, respectively, with the enhancement pattern protruding from the portion of each interior region defined by the first line to the fourth line. The enhanced pattern has a width that gradually narrows in the first direction and the second direction from the intersection of the first line defining the inner region to the fourth line.

2. The electronic device according to claim 1, wherein, The angle between the portion of each of the inner regions defined by the first line to the fourth line and the angle defined by the reinforcing pattern is in the range of 15 degrees to 35 degrees.

3. The electronic device according to claim 1, wherein, The enhancement pattern is symmetrical with respect to the virtual extension line, which passes through the center of the enhancement pattern and extends diagonally between the first direction and the second direction.

4. The electronic device according to claim 1, wherein, In the reinforcement pattern, the outer edge of the reinforcement pattern facing the inner region has a predetermined curvature.

5. The electronic device according to claim 1, wherein, The multiple launch areas include: A first emission region is positioned to the left of the first line to provide a first color; A second emission region, located to the right of the first line and above the fourth line, provides a second color; and A third emission region, located to the right of the first line and below the fourth line, is provided to offer a third color. The first emission region includes a first emission region and a second emission region, which are spaced apart from each other in the first direction. The non-emission region is located between the first emission region and the second emission region. The first emission region and the second emission region have different areas.

6. The electronic device according to claim 5, wherein, The distance in the plane from one side of each of the first to the third emission regions to the adjacent portion of the corresponding grid line in the grid line is less than or equal to the distance from the corner of each of the first to the third emission regions to the adjacent portion of the enhancement pattern.

7. The electronic device according to claim 5, wherein, An emission groove having a recessed portion in a plane is defined in at least one of the second emission region and the third emission region.

8. The electronic device according to claim 1, wherein, The sensor layer includes: A plurality of first sensing electrodes are arranged in the first direction, each of the plurality of first sensing electrodes including a plurality of first sensing patterns arranged in the second direction and a first bridging pattern disposed between adjacent first sensing patterns in the plurality of first sensing patterns; and A plurality of second sensing electrodes, insulated from the first sensing electrode and arranged in the second direction, each of the plurality of second sensing electrodes including a plurality of second sensing patterns arranged in the first direction and a second bridging pattern disposed between adjacent second sensing patterns in the plurality of second sensing patterns. The second conductive layer includes the plurality of first sensing patterns, the first bridging pattern, and the plurality of second sensing patterns. The first conductive layer includes the second bridging pattern. The contact hole, which overlaps with the second bridging pattern, is defined within the second sensing insulating layer, and The second sensing pattern is connected to the second bridging pattern through the contact hole.

9. The electronic device according to claim 8, wherein, The second bridging pattern includes at least one additional reinforcement pattern, at least a portion of each of the at least one additional reinforcement pattern being superimposed on the reinforcement pattern.

10. The electronic device according to claim 9, wherein: The center of each of the contact holes overlaps with the corresponding line of the third and fourth lines, and the center of each of the contact holes is spaced apart from the virtual first center line in the second direction, the virtual first center line extending in the first direction and passing through the center of the first line.

11. The electronic device according to claim 10, wherein, The at least one additional reinforcement pattern includes: A first additional pattern is angled at 45 degrees relative to a portion of the first part defining the inner region of the first to fourth lines; and The second additional pattern is angled at an angle ranging from 15 to 35 degrees relative to the portion of the second part of the inner region defined by the first to the fourth lines.

12. The electronic device according to claim 11, wherein, The second additional pattern is symmetrical with respect to the virtual extension line, which passes through the center of the second additional pattern and extends diagonally between the first direction and the second direction.

13. The electronic device according to claim 10, wherein, The at least one additional reinforcement pattern includes a first additional pattern and a second additional pattern, wherein the outer edges of the first additional pattern and the second additional pattern facing the inner region have a predetermined curvature.

14. The electronic device according to claim 9, wherein, The contact hole includes: A first contact hole, overlapping the third line and having a center disposed on a virtual first center line, the virtual first center line extending in the first direction and passing through the center of the first line; and The second contact hole overlaps with the fourth line and has a center spaced apart from the virtual first center line.

15. The electronic device according to claim 14, wherein, The additional reinforcing pattern is angled at 45 degrees relative to the portion of each inner region defined by the first to the fourth lines within the inner region.

16. The electronic device according to claim 9, wherein, The additional reinforcement pattern has the same shape as the reinforcement pattern.

17. The electronic device according to claim 16, wherein, The center of the contact hole is on a virtual first center line, which extends in the first direction and passes through the center of the first line.

18. The electronic device according to claim 8, wherein, Each of the contact holes has a rhomboid shape relative to the plane defined by the first direction and the second direction.

19. The electronic device according to claim 1, wherein, The display layer includes: The circuit layer includes transistors; A light-emitting element layer includes a first electrode connected to the transistor, a pixel defining layer exposing a portion of the first electrode and defining a corresponding emission region among the plurality of emission regions, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer; and The encapsulation layer is configured to cover the light-emitting element layer and consists of alternating inorganic and organic layers. The sensor layer is directly disposed on the encapsulation layer.

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