Output buffer and data driver circuit comprising the same

Abstract

The present application relates to an output buffer and a data driver circuit including the same. The present disclosure relates to an output buffer capable of driving at high speed by increasing a swing rate of an output voltage and reducing power consumption and a data driver circuit including the same. The output buffer includes an input stage monitoring a difference between an input voltage and an output voltage, a current summing stage generating an amplification current and a control voltage according to the difference between the input voltage and the output voltage monitored by the input stage, an output stage performing a pull-up operation or a pull-down operation according to the control voltage output from the current summing stage to generate the output voltage at an output terminal, and a swing boost circuit performing a swing boost operation of adjusting some of the currents provided from the current summing stage to the input stage according to the difference between the input voltage and the output voltage by monitoring the difference between the input voltage and the output voltage and selectively performing the swing boost operation by monitoring the control voltage.

Description

Technical Field

[0001] This disclosure relates to an output buffer capable of high-speed driving and reduced power consumption by increasing the swing rate of the output voltage, and a data driver circuit including the output buffer. Background Technology

[0002] The display device includes a panel that displays images through a pixel matrix, a gating driver circuit that drives the gating lines of the panel, a data driver circuit that provides data signals to the data lines of the panel, and a timing controller that controls the gating driver circuit and the data driver circuit.

[0003] The data driver circuit includes an output buffer to prevent the data signal supplied to the data line from being distorted due to load components. Circuitry other than the data driver circuit may also include an output buffer to prevent output signal distortion.

[0004] As display devices evolve towards high-speed driving, output buffers require high-speed driving methods that increase the swing rate of the output voltage, and also require methods to reduce power consumption. Summary of the Invention

[0005] This disclosure aims to provide an output buffer capable of high-speed driving and reduced power consumption by increasing the swing rate of the output voltage, and a data driver circuit including the output buffer.

[0006] An output buffer according to one aspect of this disclosure includes: an input stage configured to monitor the difference between an input voltage and an output voltage; a current summing stage configured to generate an amplified current and a control voltage based on the difference between the input voltage and the output voltage monitored by the input stage; an output stage configured to perform a pull-up operation or a pull-down operation based on the control voltage output from the current summing stage to generate an output voltage at an output terminal; and a swing boost circuit configured to perform a swing boost operation by monitoring the difference between the input voltage and the output voltage, adjusting some of the currents supplied from the current summing stage to the input stage based on the difference between the input voltage and the output voltage, and selectively performing the swing boost operation by monitoring the control voltage.

[0007] The current summing stage may include a first current path connected to the input stage and a second current path connected to the input stage and the output stage and connected to the first current path in a current mirror structure; and the swing boost circuit may be connected to the first current path of the current summing stage through the input stage.

[0008] When the input voltage and output voltage differ by a predetermined voltage or more, the swing boost circuit can adjust the sink current and pull current supplied to the input stage from the first current path of the current summing stage, in order to adjust the current and control voltage supplied to the output stage from the second current path of the current summing stage.

[0009] When the input voltage and output voltage differ by a predetermined voltage or more, the swing boost circuit can additionally increase any sink current from the current summing stage supplied to the input stage based on the difference between the input voltage and the output voltage, or additionally increase any sourcing current from the current summing stage supplied to the input stage based on the difference between the input voltage and the output voltage, to adjust the current supplied to the output stage and the control voltage from the current summing stage.

[0010] The input stage may include: a first input section including p-channel metal-oxide-semiconductor (PMOS) transistors each controlled by an input voltage and an output voltage; a second input section including n-channel metal-oxide-semiconductor (NMOS) transistors each controlled by an input voltage and an output voltage; a first bias circuit including a PMOS transistor controlled by a first bias voltage to provide a bias current to the first input section; and a second bias circuit including an NMOS transistor controlled by a second bias voltage to provide a bias current to the second input section.

[0011] The current summing stage may include: a first current mirror including a PMOS transistor connected in a current mirror structure to a supply line of a first power supply; a first cascode circuit including a PMOS transistor connected in series to the first current mirror and controlled by a third bias voltage; a second current mirror including an NMOS transistor connected in a current mirror structure to a supply line of a second power supply; a second cascode circuit including an NMOS transistor connected in series to the second current mirror and controlled by a fourth bias voltage; a third bias circuit including a PMOS transistor and an NMOS transistor connected in a first current path between the first and second cascode circuits and controlled by a fifth and a sixth bias voltage, respectively; and a fourth bias circuit including a PMOS transistor and an NMOS transistor connected in a second current path between the first and second cascode circuits and controlled by a seventh and an eighth bias voltage, respectively.

[0012] The output stage may include: a pull-up PMOS transistor controlled by a first control voltage generated in a first output node between a first cascode circuit and a fourth bias circuit, and connected between the supply line of the first power supply and the output terminal; and a pull-down NMOS transistor controlled by a second control voltage generated in a second output node between a second cascode circuit and a fourth bias circuit, and connected between the output terminal and the supply line of the second power supply.

[0013] The output stage may further include: a capacitor section comprising a first capacitor connected between the output terminal and a third output node between the first current mirror and the first cascode circuit; and a second capacitor connected between the output terminal and a fourth output node between the second current mirror and the second cascode circuit.

[0014] The swing boost circuit may further include: a first current control unit configured to control any pull-up current generated in the current summing stage based on the difference between the input voltage and the output voltage; and a first switching unit including a PMOS transistor controlled by a first control voltage and connected between the supply line of the first power supply and the first current control unit.

[0015] The swing boost circuit may further include: a second current control unit configured to control any sink current generated in the current summing stage based on the difference between the input voltage and the output voltage; and a second switching unit including an NMOS transistor controlled by a second control voltage and connected between the supply lines of the second current control unit and the second power supply.

[0016] When the first control voltage is the gate on voltage, the first switching unit can provide bias current to the first current control unit; and when the first control voltage is the gate off voltage, the first switching unit can block the current flow of the first current control unit.

[0017] When the second control voltage is the gate on voltage, the second switching unit can provide bias current to the second current control unit; and when the second control voltage is the gate off voltage, the second switching unit can block the current flow of the second current control unit.

[0018] The first current control unit may include: a third input unit, which includes PMOS transistors controlled by input voltage and output voltage respectively; a fifth bias circuit, which is controlled by a first bias and connected between the supply line of the first power supply and the PMOS transistor of the first switching unit; and an NMOS transistor, which is connected in a diode structure between the PMOS transistor in the third input unit controlled by the input voltage and the supply line of the second power supply, wherein the PMOS transistor in the third input unit controlled by the output voltage is connected to the first current path of the current summing stage.

[0019] The second current control unit may include: a fourth input unit, which includes NMOS transistors controlled by an input voltage and an output voltage; a sixth bias circuit, which is controlled by a second bias voltage and connected between the NMOS transistor in the second switching unit and the supply line of the second power supply; and a PMOS transistor, which is connected in a diode structure between the supply line of the first power supply and the NMOS transistor in the fourth input unit controlled by the input voltage, wherein the NMOS transistor in the fourth input unit controlled by the output voltage is connected to the first current path of the current summing stage.

[0020] In a swing boost circuit, when the difference between the input voltage and the output voltage is a predetermined voltage or higher and the first control voltage is the gate turn-on voltage, the output current of the PMOS transistor controlled by the output voltage in the third input section can be added to the output current of the PMOS transistor controlled by the output voltage in the first input section to increase the pull-up current of the first current path flowing from the swing boost circuit and the input stage to the current summing stage.

[0021] In the swing boost circuit, when the difference between the input voltage and the output voltage is a predetermined voltage or higher and the second control voltage is the gate turn-on voltage, the input current of the NMOS transistor controlled by the output voltage in the fourth input section is added to the input current of the NMOS transistor controlled by the output voltage in the second input section, so as to increase the sink current flowing from the first current path of the current summing stage to the input stage and the swing boost circuit.

[0022] When the first control voltage is the gate turn-on voltage, the PMOS transistor of the first switching section can be turned on to provide the bias current of the fifth bias circuit to the PMOS transistor of the first current control section; and when the first control voltage is the gate turn-off voltage, the PMOS transistor of the first switching section can be turned off to block the current flow of the first current control section.

[0023] When the second control voltage is the gate on voltage, the NMOS transistor of the second switching section can be turned on to provide the bias current of the sixth bias circuit to the NMOS transistor of the second current control section; and when the second control voltage is the gate off voltage, the NMOS transistor of the second switching section can be turned off to block the current flow of the second current control section.

[0024] The swing boost circuit can perform a swing boost operation when either the first control voltage or the second control voltage is a gate on voltage; and the swing boost operation can be turned off when both the first control voltage and the second control voltage are gate off voltages.

[0025] The swing boost circuit can perform a swing boost operation when the input voltage differs from the output voltage by a predetermined voltage or more and any one of the control voltages is a gate on voltage; and the swing boost operation can be turned off when the input voltage and output voltage are equal and the control voltage is a gate off voltage.

[0026] According to one aspect, the data driver circuit includes: a digital-to-analog converter configured to convert input digital data into an analog data signal to output an analog data signal; and an output buffer section including an output buffer for each channel to buffer the input data signal provided from the digital-to-analog converter and output the output data signal to the output channel. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to illustrate the principles of the disclosure. In the drawings:

[0028] Figure 1 This is a block diagram illustrating the construction of an output buffer according to one embodiment;

[0029] Figure 2 This is an equivalent circuit diagram illustrating the construction of an output buffer according to one embodiment;

[0030] Figure 3 This is an equivalent circuit diagram illustrating the construction of an output buffer according to one embodiment;

[0031] Figure 4 This is a driving waveform diagram of the output buffer according to one implementation method;

[0032] Figure 5 This is a block diagram illustrating the construction of a data driver circuit according to one embodiment;

[0033] Figure 6 This is an equivalent circuit diagram illustrating the construction of the output buffer section of a data driver circuit according to one embodiment; and

[0034] Figure 7 This is a block diagram illustrating the construction of a display device according to one embodiment. Detailed Implementation

[0035] The advantages and features of this disclosure, and its implementation methods, will become clear from the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0036] The shapes, dimensions, scales, angles, and quantities shown in the accompanying drawings to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals denote the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it would unnecessarily obscure the focus of this disclosure.

[0037] When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Unless otherwise stated, singular terms may include plural forms.

[0038] When interpreting a component, although it is not explicitly described, it is interpreted as including an error region.

[0039] When describing positional relationships, for example, when the positional relationship between two components is described as "on," "above," "below," and "next to," one or more other components may be positioned between the two components unless more restrictive terms such as "adjacent" or "direct" are used.

[0040] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “immediately after,” “immediately,” or “directly” are used.

[0041] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0042] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify corresponding elements in relation to other elements, and the basis, order, or number of corresponding elements shall not be limited by these terms. The expression “connected,” “linked,” or “attached” to another element or layer, unless otherwise specified, indicates that the element or layer may be directly connected or attached to another element or layer, or indirectly connected or attached to another element or layer, and one or more intermediate elements or layers are “disposed” between these elements or layers.

[0043] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed elements. For example, “at least one of the first element, the second element and the third element” means a combination of all elements derived from two or more of the first element, the second element and the third element, as well as the first element, the second element or the third element.

[0044] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure can be partially or wholly linked or combined with each other, and can be technically interoperable and driven in various ways. Embodiments of this disclosure can be implemented independently of each other, or can be implemented together in a mutually dependent relationship.

[0045] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0046] Figure 1 This is a block diagram illustrating the construction of an output buffer according to one embodiment.

[0047] Reference Figure 1 According to one embodiment, the output buffer BF includes an input stage 10, a current summing stage 20, an output stage 30, and a swing boost circuit 40.

[0048] The output buffer BF includes an operational amplifier with a voltage follower structure, comprising an input stage 10, a current summing stage 20, and an output stage 30. The operational amplifier differentially amplifies the difference between the input voltage VIN and the output voltage OUT to generate an output voltage OUT that rapidly follows the input voltage VIN.

[0049] Input stage 10 can monitor the difference between the input voltage VIN input to the non-inverting terminal and the output voltage OUT fed back to the inverting terminal in order to adjust the control currents I1 to I4 provided from current summing stage 20.

[0050] The current summing stage 20 can amplify the current together with the input stage 10 based on the difference between the input voltage VIN and the output voltage OUT to generate control currents I1 to I4 provided to the input stage 10. It can also generate output currents and control voltages HIP and HIN adjusted according to the control currents I1 to I4 to provide the output currents and control voltages HIP and HIN to the output stage 30.

[0051] Among the control currents I1 to I4 generated by the current summing stage 20, the currents I1 and I2 flowing from the current summing stage 20 to the input stage 10 are sinking currents, while the control currents I3 and I4 flowing from the input stage 10 to the current summing stage 20 are sourcing currents.

[0052] Output stage 30 can perform pull-up and pull-down operations based on the control voltages HIP and HIN provided from current summing stage 20 to output an output voltage OUT that follows the input voltage VIN through the output terminal.

[0053] The swing boost circuit 40 can be operated to monitor the input voltage VIN and the output voltage OUT, as well as the control voltages HIP and HIN of the output stage 30. When the difference between the input voltage VIN and the output voltage OUT is a predetermined voltage or higher, and the control voltages HIP and HIN of the output stage 30 become gate turn-on voltages, the swing boost circuit 40 can be operated to additionally adjust and increase the sink current I generated in the current summing stage 20. sink Or pull current I source This indirectly adjusts the output current of the current summing stage 20, thereby increasing the swing rate of the output voltage OUT.

[0054] In addition, when the control voltages HIP and HIN of the output stage 30 are both gate cutoff voltages, that is, when the input voltage VIN and the output voltage OUT are equal, the power consumption can be reduced because the operation of the swing boost circuit 40 is turned off to block unnecessary current flow.

[0055] Figure 2 and Figure 3 Each illustrates an equivalent circuit diagram of the construction of an output buffer according to one embodiment, while Figure 4 This is a driving waveform diagram of the output buffer according to one implementation method.

[0056] Reference Figure 2 and Figure 3 The output buffer BF includes an input stage 10, a current summing stage 20, an output stage 30, and a swing boost circuit 40. Figure 2 compared to, Figure 3 The specific construction of a swing boost circuit 40 according to one embodiment is illustrated.

[0057] The input stage 10 may include: a first input section including p-channel metal-oxide-semiconductor (PMOS) transistors PM1 and PM2; a second input section including n-channel metal-oxide-semiconductor (NMOS) transistors NM1 and NM2; a first bias circuit including a PMOS transistor PM3; and a second bias circuit including an NMOS transistor NM3.

[0058] The PMOS transistors PM1 and PM2 in the first input section can be controlled by the input voltage VIN and the output voltage OUT, respectively, and the pull-up currents I3 and I4 provided by the current summing stage 20 can be adjusted according to the input voltage VIN and the output voltage OUT.

[0059] The NMOS transistors NM1 and NM2 in the second input section can be controlled by the input voltage VIN and the output voltage OUT, respectively, and the sink currents I1 and I2 provided by the current summing stage 20 can be adjusted according to the input voltage VIN and the output voltage OUT.

[0060] The PMOS transistor PM3 of the first bias circuit can be connected between the supply line of the first power supply (high potential power supply) AVDDH and the first input section, and can be controlled by the bias voltage VB1 to provide bias current to the PMOS transistors PM1 and PM2 of the first input section.

[0061] The NMOS transistor NM3 of the second bias circuit can be connected between the supply line of the second input section and the second power supply (low potential power supply) VSS, and can be controlled by the second bias voltage VB2 to provide bias current to the NMOS transistors NM1 and NM2 of the second input section.

[0062] The current summing stage 20 may include: a first current mirror comprising PMOS transistors PM4 and PM5; a first cascode circuit comprising PMOS transistors PM6 and PM7; a second current mirror comprising NMOS transistors NM4 and NM5; a second cascode circuit comprising NMOS transistors NM6 and NM7; a third bias circuit comprising PMOS transistors PM8 and NMOS transistors NM8; and a fourth bias circuit comprising PMOS transistors PM9 and NMOS transistors NM9. Each of the third and fourth bias circuits may be defined as a floating bias circuit.

[0063] The PMOS transistors PM4 and PM5 of the first current mirror are connected to the NMOS transistors NM1 and NM2 of the second input section of the input stage 10, and are connected between the supply line of the first power supply AVDDH and the first cascode circuit in the form of a current mirror. The gate electrodes of the PMOS transistors PM4 and PM5 of the first current mirror are connected to the output node N3 of the first cascode circuit. The PMOS transistors PM4 and PM5 of the first current mirror provide sink currents I1 and I2 to the NMOS transistors NM1 and NM2 of the second input section through the output nodes N2 and N1, provide output current through the first cascode circuit, and provide output current to the capacitor C1 of the output stage 30 through the output node N4.

[0064] The PMOS transistors PM6 and PM7 of the first common-source common-gate circuit can be connected between the first current mirror and the third and fourth bias circuits, and can be controlled by the third bias voltage VB3 to provide the first control voltage HIP to the output stage 30 through the output node N7.

[0065] The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 of the second current mirror are connected to the PMOS transistors PM1 and PM2 of the first input section of the input stage 10, and are connected in the form of a current mirror between the supply lines of the second cascode circuit and the second power supply VSS. The gate electrodes of the NMOS transistors NM4 and NM5 of the second current mirror are connected to the output node N5 of the second cascode circuit. The NMOS transistors NM4 and NM5 of the second current mirror can provide pull-up currents I3 and I4 to the PMOS transistors PM1 and PM2 of the first input section through the output node, provide output current through the second cascode circuit, and provide output current to the capacitor C2 of the output stage 30 through the output node N6.

[0066] The NMOS transistors NM6 and NM7 of the second common-source common-gate circuit can be connected between the third and fourth bias circuits and the second current mirror, and can be controlled by the fourth bias voltage VB4 to provide the second control voltage HIN to the output stage 30 through the output node N8.

[0067] The PMOS transistor PM8 and NMOS transistor NM8 of the third bias circuit can be connected between the PMOS transistor PM6 of the first cascode circuit and the NMOS transistor NM6 of the second cascode circuit, and can be controlled by the fifth bias voltage VB5 and the sixth bias voltage VB6, respectively, to provide bias current flowing from the output node N3 of the first cascode circuit to the output node N5 of the second cascode circuit.

[0068] The PMOS transistor PM9 and NMOS transistor NM9 of the fourth bias circuit can be connected between the PMOS transistor PM7 of the first cascode circuit and the NMOS transistor NM7 of the second cascode circuit, and can be controlled by the seventh bias voltage VB7 and the eighth bias voltage VB8, respectively, to provide bias current flowing from the output node N7 of the first cascode circuit to the output node N8 of the second cascode circuit.

[0069] The output stage 30 may include a pull-up PMOS transistor PM10, a pull-down NMOS transistor NM10, and a capacitor section including capacitors C1 and C2.

[0070] The pull-up PMOS transistor PM10 is controlled by a first control voltage HIP provided from the first output node N7 of the current summing stage 20, and is connected between the supply line of the first power supply AVDDH and the output terminal. The pull-up PMOS transistor PM10 can perform a pull-up operation under the control of the first control voltage HIP to increase the output voltage OUT. For example, as... Figure 4As shown, when the input voltage VIN increases to be greater than the output voltage OUT, the first control voltage HIP decreases and is applied as the gate turn-on voltage, and during time period t1 or t3, the pull-up PMOS transistor PM10 can perform a pull-up operation to increase the output voltage OUT.

[0071] The pull-down NMOS transistor NM10 is controlled by a second control voltage HIN provided from the second output node N8 of the current summing stage 20, and is connected between the output terminal and the supply line of the second power supply VSS. The pull-down NMOS transistor NM10 can perform a pull-down operation under the control of the second control voltage HIN to reduce the output voltage OUT. For example, as... Figure 4 As shown, when the input voltage VIN drops below the output voltage OUT, the second control voltage HIN rises and is applied as the gate turn-on voltage. During time period t2 or t4, the pull-down NMOS transistor NM10 can perform a pull-down operation to reduce the output voltage OUT.

[0072] The capacitor section may include a first capacitor C1 connected between the third output node N4 of the current summing stage 20 and the output terminal, and a second capacitor C2 connected between the fourth output node N6 of the current summing stage 20 and the output terminal. The capacitor section can stabilize the output voltage OUT, so that the output voltage OUT does not oscillate when it is increasing or decreasing.

[0073] The current summing stage 20 can provide output current to the first capacitor C1 through the third output node N4 connected to the first current mirror, and provide output current to the second capacitor C2 through the fourth output node N6 connected to the second current mirror.

[0074] The swing boost circuit 40 may include: a first current control unit 44, which, together with the input stage 10, controls the pull-up current I4 provided from the current summing stage 20 based on the difference between the input voltage VIN and the output voltage OUT; and a first switching unit, which includes a PMOS transistor PM15 connected between the supply line of the first power supply AVDDH and the first current control unit 44 and controlled by a first control voltage HIP for controlling the output stage 30.

[0075] Additionally, the swing boost circuit 40 may include: a second current control unit 42, which, together with the input stage 10, controls the sink current I2 provided from the current summing stage 20 based on the difference between the input voltage VIN and the output voltage OUT; and a second switching unit, which includes an NMOS transistor NM15 connected between the second current control unit 42 and the supply line of the second power supply VSS and controlled by a second control voltage HIN for controlling the output stage 30.

[0076] Reference Figure 3The first current control unit 44 may include: a third input unit, which includes PMOS transistors PM11 and PM12; and a fifth bias circuit, which includes PMOS transistor PM13.

[0077] The PMOS transistor PM15 of the first switching section can be connected between the PMOS transistor PM13 of the fifth bias circuit and the PMOS transistors PM11 and PM12 of the third input section.

[0078] The PMOS transistor PM13 of the fifth bias circuit can be controlled by the first bias voltage VB1 to provide bias current to the PMOS transistors PM11 and PM12 of the third input section through the PMOS transistor PM15 of the first switching section.

[0079] When the first control voltage HIP drops to the gate turn-on voltage ( Figure 4 During time intervals t1 or t3, that is, when the input voltage VIN is greater than the output voltage OUT, the PMOS transistor PM15 of the first switching section can be turned on to provide the bias current of the fifth bias circuit to the third input section. Conversely, when the first control voltage HIP is the gate cutoff voltage, that is, when the input voltage VIN is equal to the output voltage OUT, the PMOS transistor PM15 of the first switching section can be turned off to block the flow of unnecessary current (DC).

[0080] In the third input section of the oscillating boost circuit 40, the PMOS transistor PM12, controlled by the output voltage OUT, can adjust the pull-up current I4 supplied from the current summing stage 20. In other words, when the output voltage OUT decreases according to the input voltage VIN, the PMOS transistor PM12 in the oscillating boost circuit 40, controlled by the output voltage OUT, can increase the pull-up current I4 flowing to the current summing stage 20 together with the PMOS transistor PM2 in the input stage 10, which is also controlled by the output voltage OUT.

[0081] The PMOS transistor PM11, controlled by the input voltage VIN in the third input section, can be connected to the supply line of the second power supply VSS via an NMOS transistor NM14 with a diode structure having a gate electrode and a drain electrode connection.

[0082] The second current control unit 42 may include: a fourth input unit, which includes NMOS transistors NM11 and NM12; and a sixth bias circuit, which includes NMOS transistor NM13. The NMOS transistor NM15 of the second switching unit may be connected between the NMOS transistors NM11 and NM12 of the fourth input unit and the NMOS transistor NM13 of the sixth bias circuit.

[0083] The NMOS transistor NM13 of the sixth bias circuit can be controlled by the second bias voltage VB2 to provide bias current to the NMOS transistors NM11 and NM12 of the fourth input section through the NMOS transistor NM15 of the second switching section.

[0084] When Figure 4 As shown, the second control voltage HIN supplied from the current summing stage 20 to the output stage 30 is increased to the gate turn-on voltage ( Figure 4 During time period t2 or t4, that is, when the input voltage VIN is less than the output voltage OUT, the NMOS transistor NM15 of the second switching section can be turned on to provide the bias current of the sixth bias circuit to the fourth input section. Conversely, when the second control voltage HIN drops to the gate cutoff voltage, that is, when the input voltage VIN is equal to the output voltage OUT, the NMOS transistor NM15 of the second switching section can be turned off to block the flow of unnecessary current (DC).

[0085] The NMOS transistor NM12 in the fourth input section of the swing boost circuit 40, controlled by the output voltage OUT, can adjust the sink current I2 provided from the current summing stage 20 through the input stage 10. In other words, when the output voltage OUT increases according to the input voltage VIN, the NMOS transistor NM12 in the fourth input section of the swing boost circuit 40, controlled by the output voltage OUT, can increase the sink current I2 provided from the current summing stage 20 together with the NMOS transistor NM2 in the second input section of the input stage 10, which is also controlled by the output voltage OUT.

[0086] The NMOS transistor NM11, which is supplied with input voltage VIN in the fourth input section, can be connected to the supply line of the first power supply AVDDH via a PMOS transistor PM14 with a diode structure having gate and drain electrodes connected.

[0087] Between the supply lines of the first power supply AVDDH and the second power supply VSS, the current summing stage 20 may include: a first current path passing through the PMOS transistor PM4 of the first current mirror, the PMOS transistor PM6 of the first cascode circuit, the NMOS transistor NM8 and PMOS transistor PM8 of the third bias circuit, the NMOS transistor NM6 of the second cascode circuit, and the NMOS transistor NM4 of the second current mirror; and a second current path passing through the PMOS transistor PM5 of the first current mirror, the PMOS transistor PM7 of the first cascode circuit, the NMOS transistor NM9 and PMOS transistor PM9 of the fourth bias circuit, the NMOS transistor NM7 of the second cascode circuit, and the NMOS transistor NM5 of the second current mirror. The first current path may be defined as a current mirror path, and the second current path may be defined as a current mirrored path.

[0088] The swing boost circuit 40 can adjust and increase the sink current I2 and pull current I4 generated in the first current path, which is a current mirror path, in the current path of the current summing stage 20, together with the input stage 10, so as to indirectly control the output current and control voltages HIP and HIN generated in the second current path, which is a current mirror path, thereby performing a swing boost operation that increases the swing rate of the output voltage OUT.

[0089] Reference Figures 2 to 4 Describe the operation of the output buffer BF according to one implementation.

[0090] like Figure 4 As shown, when the input voltage VIN increases to be greater than the output voltage OUT, the first pull-up current I3 flowing from the input stage 10 through the PMOS transistor PM1 in the first input section to the current summing stage 20 decreases, but the second pull-up current I4 flowing from the PMOS transistor PM2 in the first input section to the current summing stage 20 increases. Additionally, the first sink current I1 supplied from the current summing stage 20 and flowing through the NMOS transistor NM1 in the second input section increases, but the second sink current I2 flowing through the NMOS transistor NM2 in the second input section decreases.

[0091] Therefore, the output current flowing through the first current mirror N4 of the current summing stage 20 decreases, while the output current flowing through the first cascode circuit N3 increases. Additionally, the output current flowing through the second current mirror N6 decreases, while the output current flowing through the second cascode circuit N5 increases.

[0092] As a result, the first control voltage HIP provided by the output node N7 of the current summing stage 20 decreases to the gate turn-on voltage, and when the first control voltage HIP decreases to the gate turn-on voltage and is applied (time period t1 or t3), the PMOS transistor PM10 of the output stage 30 can perform a pull-up operation to increase the output voltage OUT. In this case, since the second control voltage HIN is applied as the gate turn-off voltage through the output node N8 of the current summing stage 20, the NMOS transistor NM10 of the output stage 30 is turned off.

[0093] Specifically, when the input voltage VIN is greater than the output voltage OUT and the first control voltage HIP is reduced to the gate turn-on voltage and applied (time period t1 or t3), in the swing boost circuit 40, the PMOS transistor PM15 is turned on, and the output current of the PMOS transistor PM12 in the third input section increases. Since the increased output current of the PMOS transistor PM12 in the swing boost circuit 40 is added to the output current of the PMOS transistor PM2 in the input stage 10, the second pull-out current I4 flowing to the current summing stage 20 can be further increased. Due to the indirect control of the second pull-out current I4, which is further increased by the boost operation of the swing boost circuit 40, the voltages at output nodes N6 and N8 in the current summing stage 20 can be further reduced.

[0094] Therefore, the capacitor section including capacitors C1 and C2 discharges rapidly, and the second control voltage HIN drops further from the gate cutoff voltage to strongly cut off the NMOS transistor NM10 and block the leakage current, thereby shortening the rise time of the output voltage OUT through the PMOS transistor PM10 to increase the swing rate of the output voltage OUT.

[0095] Furthermore, since the second control voltage HIN applied to the swing boost circuit 40 is the gate cutoff voltage, the NMOS transistor NM15 can be turned off, thereby turning off the second current control unit 42.

[0096] When the output voltage OUT increases rapidly and equals the input voltage VIN, the first control voltage HIP and the second control voltage HIN can both become gate cutoff voltages, so that the output stage 30 and the swing boost circuit 40 can be turned off, and the output buffer BF can maintain the output voltage OUT equal to the input voltage VIN.

[0097] like Figure 4 As shown, when the input voltage VIN decreases to below the output voltage OUT, the first pull-up current I3 flowing from the input stage 10 through the PMOS transistor PM1 in the first input section to the current summing stage 20 increases, but the second pull-up current I4 flowing from the PMOS transistor PM2 in the first input section to the current summing stage 20 decreases. Additionally, the first sink current I1 provided by the current summing stage 20 and flowing through the NMOS transistor NM1 in the second input section decreases, but the second sink current I2 flowing through the NMOS transistor NM2 in the second input section increases.

[0098] Therefore, the output current flowing through the first current mirror N4 of the current summing stage 20 increases, but the output current flowing through the first cascode circuit N3 decreases. Additionally, the output current flowing through the second current mirror N6 increases, and the output current flowing through the second cascode circuit N5 decreases.

[0099] As a result, the second control voltage HIN provided by the output node N8 of the current summing stage 20 is increased to the gate turn-on voltage, and when the second control voltage HIN is increased to the gate turn-on voltage and applied (time period t2 or t4), the NMOS transistor NM10 of the output stage 30 can perform a pull-down operation to reduce the output voltage OUT.

[0100] In this case, the first control voltage HIP provided by the output node N7 of the current summing stage 20 is applied as the gate cutoff voltage, causing the PMOS transistor PM10 of the output stage 30 to be turned off.

[0101] Specifically, when the input voltage VIN is less than the output voltage OUT and the second control voltage HIN is increased to the gate turn-on voltage and applied (time period t2 or t4), in the swing boost circuit 40, the NMOS transistor NM15 is turned on, and the drain current (input current) of the NMOS transistor NM12 increases. Since the increased drain current (input current) of the NMOS transistor NM12 in the swing boost circuit 40 is added to the drain current of the NMOS transistor NM2 in the input stage 10, the second sink current I2 provided from the current summing stage 20 can be further increased. Due to the indirect control of the further increased second sink current I2 through the boost operation of the swing boost circuit 40, the voltages of the output nodes N4 and N7 in the current summing stage 20 can be further increased.

[0102] Therefore, the capacitor section including capacitors C1 and C2 is rapidly charged, and the first control voltage HIP is further increased from the gate cutoff voltage to strongly cut off the PMOS transistor PM10 and block the leakage current, thereby shortening the fall time of the output voltage OUT through the NMOS transistor NM10 to increase the swing rate of the output voltage OUT.

[0103] Furthermore, since the first control voltage HIP applied to the swing boost circuit 40 is the gate cutoff voltage, the PMOS transistor PM15 can be turned off, thereby turning off the first current control unit 44.

[0104] When the output voltage OUT drops rapidly and becomes equal to the input voltage VIN, both the first control voltage HIP and the second control voltage HIN can become gate cutoff voltages, allowing the output stage 30 and the swing boost circuit 40 to be turned off, and the output buffer BF to maintain the output voltage OUT equal to the input voltage VIN.

[0105] Figure 5 This is a block diagram illustrating a data driver including an output buffer according to one embodiment, and Figure 6This illustrates an equivalent circuit diagram of the output buffer section according to one embodiment.

[0106] Reference Figure 5 The data driver 300 may include a shift register 310, latches 320 and 330, a digital-to-analog converter (DAC) 340, and an output buffer 350.

[0107] The shift register 310 can sequentially shift the start pulse according to a clock signal to output multiple sampled signals sequentially to the first latch unit 320. The shift register 310 can include multiple channel stages and can perform shift operations to sequentially shift the start pulse according to a clock signal, thereby outputting the sampled signals of multiple channels sequentially to the first latch unit 320. The shift register 310 can include m channel stages corresponding to the number of output channels CH1 to CHm, and can include fewer than m stages.

[0108] In response to sampling signals from multiple channels sequentially input from shift register 310, first latch unit 320 can sequentially latch multiple data entries from the sequentially input channels for each channel of each sub-pixel. When multiple data entries from all channels are latched, first latch unit 320 can simultaneously output these latched data entries from multiple channels to second latch unit 330. First latch unit 320 may include m first latches corresponding to the number of output channels CH1 to CHm.

[0109] The second latch unit 330 can simultaneously output multiple data lines from these channels (sub-pixels) provided by the first latch unit 320 to the DAC unit 340 in response to a load signal. The second latch unit 330 may include m second latches corresponding to the number of output channels CH1 to CHm.

[0110] The DAC unit 340 can use grayscale voltages subdivided from the reference gamma voltage to convert multiple data points from the subpixel provided by the second latch unit 330 into analog data signals for each channel, and can output the converted analog data signals to the output buffer unit 350. The DAC unit 340 may include m channels of DAC corresponding to the number of output channels CH1 to CHm.

[0111] The output buffer unit 350 can buffer the data signal of each sub-pixel provided from the DAC unit 340 for each channel, and output the buffered data signal to each of the multiple output channels CH1 to CHm.

[0112] like Figure 6 As shown, the output buffer unit 350 may include m output buffers BF1 to BFm corresponding to the number of output channels CH1 to CHm.

[0113] Figure 6 The output buffers BF1 to BFm shown can buffer the input data signals VIN1 to VINm provided from the DAC unit 340 respectively, so as to output the output data signals OUT1 to OUTm for each channel.

[0114] Each output buffer BF can use current amplification to output an output data signal OUT that quickly follows the input data signal IN and is equal to the input data signal IN, based on the voltage difference between the input data signal IN input to the non-inverting terminal (+) and the output data signal OUT fed back to the inverting terminal (-). (See above for reference.) Figures 1 to 4 As described, each output buffer BF may include: an operational amplifier including an input stage 10, a current summing stage 20 and an output stage 30; and a swing boost circuit 40.

[0115] When the swing boost circuit 40 monitors the voltage difference between the input data signal IN and the output data signal OUT, and the difference between the input voltage and the output voltage is large, the swing boost circuit 40, together with the input stage 10, can increase the sink current I2 and the pull-in current I4 to increase the swing rate of the output data signal OUT and shorten the rise time and fall time of the output data signal OUT, enabling high-speed driving of each output buffer BF included in the data driver 300. Furthermore, in each output buffer BF included in the data driver 300, the swing boost circuit 40 monitors the control voltages HIP and HIN of the output stage 30 and the difference between the input voltage and the output voltage, and turns the swing boost operation on or off to block unnecessary current (DC) flow, thereby reducing power consumption.

[0116] Figure 7 This is a schematic block diagram illustrating the construction of a display device according to one embodiment, including a data driver with an output buffer.

[0117] The display device according to one embodiment can be any of the following types of display devices: liquid crystal display device, electroluminescent display device, micro light-emitting diode (LED) display device, etc. The electroluminescent display device can be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0118] Reference Figure 7 The display device may include a display panel 100, a gating driver 200, a data driver 300, a gamma voltage generator 500, a timing controller 400, etc. The gating driver 200 and the data driver 300 can be defined as panel drivers. The gating driver 200, the data driver 300, and the timing controller 400 can be defined as display drivers.

[0119] The display panel 100 displays images through a display area DA, in which sub-pixels P are arranged in a matrix. Each sub-pixel P is any one of a red sub-pixel for emitting red light, a green sub-pixel for emitting green light, a blue sub-pixel for emitting blue light, and a white sub-pixel for emitting white light, and is independently driven by at least one thin-film transistor (TFT). A unit pixel may include a combination of two, three, or four sub-pixels with different colors.

[0120] The gate electrode of the TFT belonging to each sub-pixel P is connected to the gate driver 200 through a gate line provided on the display panel 100, and the input electrode of either the source electrode or the drain electrode of each TFT is connected to the data driver 300 through a data line provided on the display panel 100.

[0121] In other words, when the TFT is turned on in response to a scan pulse having a gate turn-on voltage provided from the gate driver 200 through the corresponding gate line, each sub-pixel P can receive a data signal provided from the data driver 300 through the corresponding data line through the turned-on TFT, can be charged with a pixel voltage (driving voltage) corresponding to the data signal, and can emit light corresponding to the charged voltage, thereby expressing a gray level corresponding to the data signal.

[0122] The display panel 100 may also include a touch sensor screen that overlaps with the entire display area and senses user touch, and the touch sensor screen may be embedded in the panel 100 or disposed on the display area of ​​the panel 100.

[0123] The timing controller 400 can receive image data and synchronization signals from a host system (not shown). For example, the host system can be any of a computer, television (TV) system, set-top box, desktop personal computer, and portable terminal system such as a mobile phone. Synchronization signals may include a dot clock, data enable signal, vertical synchronization signal, horizontal synchronization signal, etc.

[0124] By using the received synchronization signal and the timing setting information (start timing, pulse width, etc.) stored in the internal register, the timing controller 400 can generate multiple data control signals and provide them to the data driver 300, and can generate multiple gating control signals and provide them to the gating driver 200.

[0125] The timing controller 400 can perform various image processing on the received image data, such as brightness correction or image quality correction for reducing power consumption, and can provide the processed image data to the data driver 300.

[0126] The gamma voltage generator 500 can generate a set of reference gamma voltages, including multiple reference gamma voltages with different voltage levels, to provide the generated set of reference gamma voltages to the data driver 300. Under the control of the timing controller 400, the gamma voltage generator 500 can generate multiple reference gamma voltages corresponding to the gamma characteristics of the display device, to provide the generated reference gamma voltages to the data driver 300. The gamma voltage generator 500 can be configured as a programmable gamma integrated circuit (IC) that can receive gamma data from the timing controller 400 and generate or adjust the reference gamma voltage level according to the gamma data to output the generated or adjusted reference gamma voltage level to the data driver 300.

[0127] The gating driver 200 can be controlled according to multiple gating control signals received from the timing controller 400 to individually drive the gating lines of the display panel 100. The gating driver 200 can drive multiple gating lines sequentially. The gating driver 200 can provide a scan signal with a gate on voltage to the corresponding gating line during the driving period of each gating line, and can provide a gate off voltage to the corresponding gating line during the non-driving period of each gating line.

[0128] The gate driver 200 can be configured as at least one gate driver IC and can be mounted on a circuit film such as tape-on-carrier (TCP), chip-on-film (COF), or flexible printed circuit (FPC) to be attached to the display panel 100 via tape-on-board (TAB) method, or mounted on the display panel 100 via chip-on-glass (COG) method. Alternatively, the gate driver 200 can be formed on a TFT substrate together with the TFTs belonging to each sub-pixel P of the display panel 100 and embedded in the bezel area of ​​the display panel 100.

[0129] The data driver 300 can be controlled according to the data control signal received from the timing controller 400, and the data driver 300 can convert the digital image data received from the timing controller 400 into analog data signals to provide the data signals to each data line of the display panel 100. The data driver 300 can convert digital image data into analog data signals using grayscale voltages subdivided from multiple reference gamma voltages provided by the gamma voltage generator 500.

[0130] The data driver 300 can be configured as at least one data driver IC and can be mounted on a circuit film such as TCP, COF, FPC, etc. and attached to the display panel 100 by the TAB method, or mounted on the bezel area of ​​the display panel 100 by the COG method.

[0131] Data drive 300 may include, according to the above reference Figures 1 to 4One embodiment of the output buffer BF is described. When the difference between the input data signal VIN and the output data signal OUT is large, the swing boost circuit 40, together with the input stage 10, can increase the sink current I2 and the pull-up current I4 to increase the swing rate of the output data signal OUT, so that the output buffer BF included in the data driver 300 can be driven at high speed. In addition, in each output buffer BF included in the data driver 300, the swing boost circuit 40 monitors the control voltages HIP and HIN of the output stage 30 and starts or stops the swing boost operation to block the flow of unnecessary current (DC), thereby reducing power consumption.

[0132] As described above, when the swing boost circuit monitors the control voltage of the output stage as well as the input voltage and output voltage, and the difference between the input voltage and the output voltage is a predetermined voltage or higher, and the control voltage of the output stage changes to be greater than the predetermined voltage, the swing boost circuit adjusts the sink current and spool current of the current summing stage to indirectly control the output current supplied to the output stage. Therefore, the rise time and fall time of the output voltage can be shortened to increase the swing rate, so that the output buffer according to one embodiment can be driven at high speed.

[0133] In one embodiment of the output buffer, since the swing boost circuit is turned on or off according to the control voltage of the output stage, the flow of unnecessary current (DC) can be blocked when the input voltage and the output voltage are equal, thereby reducing power consumption.

[0134] According to one embodiment, the data driver circuit includes the aforementioned output buffer, thereby enabling high-speed driving and reducing power consumption.

[0135] The output buffer and data driver circuit of the display device according to the embodiments can be applied to various electronic devices. For example, the output buffer and data driver circuit of the display device according to the embodiments can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MPEG audio layer 3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, netbooks, workstations, navigation devices, in-vehicle navigation devices, in-vehicle display devices, televisions, wallpaper display devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, home appliances, etc.

[0136] The features, structures, effects, etc., described above in the various examples of this disclosure are included in at least one example of this disclosure, and are not necessarily limited to one example. Furthermore, those skilled in the art to which the technical concept of this disclosure pertains can combine or modify the features, structures, effects, etc., shown in at least one example of this disclosure with respect to other examples. Therefore, the content related to these combinations and modifications should be interpreted as being included within the technical spirit or scope of this disclosure.

[0137] While this disclosure is not limited to the embodiments and drawings described above, it will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made therein without departing from the scope of this disclosure. Therefore, the scope of this disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope, and equivalents of the claims should be construed as being included within the scope of this disclosure.

[0138] Cross-reference to related applications

[0139] This application claims the benefit of Korean Patent Application No. 10-2020-0178632, filed on December 18, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. An output buffer, the output buffer comprising: The input stage is configured to monitor the difference between the input voltage and the output voltage. A current summing stage is configured to generate an amplified current and a control voltage based on the difference between the input voltage and the output voltage monitored by the input stage. The amplified current includes a control current flowing between the current summing stage and the input stage, and the control current includes a sink current and a pull current. An output stage configured to perform a pull-up or pull-down operation based on the control voltage output from the current summing stage to generate the output voltage at the output terminal; as well as A swing boost circuit is configured to perform a swing boost operation by monitoring the difference between the input voltage and the output voltage, adjusting at least one of the sink current and the sourcing current in the control current according to the difference between the input voltage and the output voltage, and selectively performing the swing boost operation by monitoring the control voltage. Among the control currents generated in the current summing stage, the current flowing from the current summing stage to the input stage is the sinking current, and the current flowing from the input stage to the current summing stage is the sourcing current. When the input voltage and the output voltage differ by a predetermined voltage or more, the swing boost circuit increases at least one of the sink current and the pull current in the control current flowing between the current summing stage according to the difference between the input voltage and the output voltage, so as to adjust the control voltage supplied from the current summing stage to the output stage.

2. The output buffer according to claim 1, wherein, The current summing stage includes a first current path connected to the input stage and a second current path connected to the input stage and the output stage and connected to the first current path in a current mirror structure. as well as The swing boost circuit is connected to the first current path of the current summing stage through the input stage.

3. The output buffer according to claim 2, wherein, When the input voltage and the output voltage differ by a predetermined voltage or more, the swing boost circuit, together with the input stage, adjusts and increases the sink current and pull-up current generated in the first current path of the current summing stage, so as to indirectly control the output current and the control voltage generated in the second current path of the current summing stage.

4. The output buffer according to claim 1, wherein, The input level includes: A first input section includes p-channel metal-oxide-semiconductor (PMOS) transistors each controlled by the input voltage and the output voltage; The second input section includes an n-channel metal-oxide-semiconductor (NMOS) transistor, each controlled by the input voltage and the output voltage. A first bias circuit, comprising a PMOS transistor controlled by a first bias voltage to provide a bias current to the first input; and The second bias circuit includes an NMOS transistor controlled by a second bias voltage to provide bias current to the second input.

5. The output buffer according to claim 4, wherein, The current summing stage includes: A first current mirror, the first current mirror including a PMOS transistor connected to a supply line of a first power source in a current mirror structure; A first common-source cascode circuit includes a PMOS transistor connected in series with the first current mirror and controlled by a third bias voltage; The second current mirror includes an NMOS transistor connected to the supply line of a second power source in a current mirror structure. The second cascode circuit includes an NMOS transistor connected in series with the second current mirror and controlled by a fourth bias voltage; A third bias circuit, comprising a PMOS transistor and an NMOS transistor connected to a first current path between the first cascode circuit and the second cascode circuit and controlled by a fifth bias voltage and a sixth bias voltage, respectively; and The fourth bias circuit includes a PMOS transistor and an NMOS transistor connected to a second current path between the first cascode circuit and the second cascode circuit and controlled by a seventh bias voltage and an eighth bias voltage, respectively.

6. The output buffer according to claim 5, wherein, The output stage includes: A pull-up PMOS transistor, controlled by a first control voltage generated in a first output node between the first cascode circuit and the fourth bias circuit, and connected between the supply line of the first power supply and the output terminal; and A pull-down NMOS transistor, which is controlled by a second control voltage generated in a second output node between the second cascode circuit and the fourth bias circuit, and connected between the output terminal and the supply line of the second power supply.

7. The output buffer according to claim 6, wherein, The output stage further includes a capacitor section comprising: a first capacitor connected between a third output node between the first current mirror and the first cascode circuit and the output terminal; and a second capacitor connected between a fourth output node between the second current mirror and the second cascode circuit and the output terminal.

8. The output buffer according to claim 6, wherein, The swing boost circuit also includes: A first current control unit is configured to control any one of the pull-up currents generated in the current summing stage based on the difference between the input voltage and the output voltage. A first switching section includes a PMOS transistor controlled by the first control voltage and connected between the supply line of the first power supply and the first current control section; A second current control unit is configured to control any one of the sink currents among the control currents generated in the current summing stage based on the difference between the input voltage and the output voltage; and The second switching section includes an NMOS transistor controlled by the second control voltage and connected between the second current control section and the supply line of the second power supply.

9. The output buffer according to claim 8, wherein, When the first control voltage is the gate on voltage, the first switching unit provides a bias current to the first current control unit; as well as When the first control voltage is the gate cutoff voltage, the first switch section blocks the current flow of the first current control section.

10. The output buffer according to claim 8, wherein, When the second control voltage is the gate on-voltage, the second switching unit provides bias current to the second current control unit; as well as When the second control voltage is the gate cutoff voltage, the second switch section blocks the current flow of the second current control section.

11. The output buffer according to claim 8, wherein, The first current control unit includes: The third input section includes PMOS transistors each controlled by the input voltage and the output voltage; A fifth bias circuit, controlled by the first bias voltage and connected between the supply line of the first power supply and the PMOS transistor of the first switching section; and An NMOS transistor, which is connected in a diode configuration between the PMOS transistor controlled by the input voltage in the third input section and the supply line of the second power supply. In this embodiment, the PMOS transistor in the third input section, which is controlled by the output voltage, is connected to the first current path of the current summing stage.

12. The output buffer according to claim 8, wherein, The second current control unit includes: The fourth input section includes NMOS transistors each controlled by the input voltage and the output voltage; A sixth bias circuit, controlled by the second bias voltage and connected between the NMOS transistor of the second switching section and the supply line of the second power supply; and A PMOS transistor, which is connected in a diode configuration between the supply line of the first power supply and the NMOS transistor in the fourth input section controlled by the input voltage. In this circuit, the NMOS transistor in the fourth input section, which is controlled by the output voltage, is connected to the first current path of the current summing stage.

13. The output buffer according to claim 11, wherein, In the swing boost circuit, when the difference between the input voltage and the output voltage is a predetermined voltage or higher and the first control voltage is the gate turn-on voltage, the output current of the PMOS transistor controlled by the output voltage in the third input section is added to the output current of the PMOS transistor controlled by the output voltage in the first input section, so as to increase the pull-up current of the first current path flowing from the swing boost circuit and the input stage to the current summing stage.

14. The output buffer according to claim 12, wherein, In the swing boost circuit, when the difference between the input voltage and the output voltage is a predetermined voltage or higher and the second control voltage is the gate turn-on voltage, the drain current of the NMOS transistor controlled by the output voltage in the fourth input section is added to the drain current of the NMOS transistor controlled by the output voltage in the second input section, thereby increasing the sink current flowing from the first current path of the current summing stage to the input stage and the swing boost circuit.

15. The output buffer according to claim 11, wherein, When the first control voltage is the gate on-state voltage, the PMOS transistor of the first switching section is turned on to provide the bias current of the fifth bias circuit to the PMOS transistor of the first current control section; and When the first control voltage is the gate cutoff voltage, the PMOS transistor of the first switching section is turned off to block the current flow of the first current control section.

16. The output buffer according to claim 12, wherein, When the second control voltage is the gate on-state voltage, the NMOS transistor of the second switching section is turned on to provide the bias current of the sixth bias circuit to the NMOS transistor of the second current control section; and When the second control voltage is the gate cutoff voltage, the NMOS transistor of the second switching section is turned off to block the current flow of the second current control section.

17. The output buffer according to claim 8, wherein, When either the first control voltage or the second control voltage is a gate on-state voltage, the swing boost circuit performs the swing boost operation; and When both the first control voltage and the second control voltage are gate cutoff voltages, the swing boost operation is turned off.

18. The output buffer according to claim 1, wherein, When the input voltage differs from the output voltage by a predetermined voltage or more, and any one of the control voltages is a gate on-state voltage, the swing boost circuit performs the swing boost operation; and The swing boost operation is turned off when the input voltage and the output voltage are equal and the control voltage is the gate cutoff voltage.

19. A data driver circuit, the data driver circuit comprising: A digital-to-analog converter configured to convert input digital data into an analog data signal to output the analog data signal; as well as An output buffer section, comprising an output buffer for each channel according to any one of claims 1 to 18, for buffering input data signals provided from the digital-to-analog converter and outputting output data signals to the output channel.

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