Scan driver and driving method thereof

Abstract

A scan driver and a driving method thereof are disclosed, in which the scan driver includes a plurality of stages outputting an output signal in response to a clock signal supplied at a first frequency during a driving time of one frame, in which the plurality of stages are supplied with the clock signal at a second frequency lower than the first frequency during a holding time of one frame separate from the driving time of one frame.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0177881, filed on December 17, 2020, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0003] Embodiments of the present invention relate to a scan driver and a driving method thereof, and more specifically, to a scan driver and a driving method thereof that can constantly maintain the output voltage of the scan driver to reduce power consumption. Background Technology

[0004] Typically, a display device includes a data driver for supplying data signals to data lines, a scan driver for supplying scan signals to scan lines, a transmitter driver for supplying transmitter control signals to transmitter control lines, and pixels arranged to connect to the data lines, scan lines, and transmitter control lines.

[0005] In order to reduce the power consumption of the display device, the scanning driver is driven by reducing the driving frequency in the traditional fixed-frequency driving method.

[0006] However, when the drive frequency of the scan driver is reduced to reduce power consumption, the clock signal input to the scan driver is maintained at a fast frequency during the hold time when no start pulse is input.

[0007] The information disclosed in this background section is only for understanding the background of the inventive concept and therefore may contain information that does not constitute prior art. Summary of the Invention

[0008] The apparatus / method constructed according to embodiments and implementations of the present invention can reduce the frequency applied to the scan driver during a portion of a frame, thereby saving power consumption of the display device including the scan driver.

[0009] The embodiments are designed to address the aforementioned problems and provide a scan driver that can reduce the drive frequency of the scan driver to provide a clock signal input to the scan driver at a low frequency during the hold time of a frame in which no start pulse is input to the scan driver.

[0010] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0011] An embodiment provides a scan driver, comprising: an input section for controlling the voltage of a first node and the voltage of a second node based on signals supplied to a first input terminal and a second input terminal; a first signal processing section for supplying a voltage of a second power supply to a fourth node based on the voltage of the first node, or electrically connecting the second node and the fourth node through a fifth node based on the voltage of the first power supply; a second signal processing section including a fourteenth transistor connected between a third node and a sixth node, and the second signal processing section being connected to the first input terminal, the second input terminal, and the first power supply to control the voltage of the third node based on the operation of the fourteenth transistor; and an output section for controlling the voltage applied to the third node to be less than or equal to the voltage of the first power supply, and supplying the voltage of the first power supply or the voltage of the second power supply to an output terminal as a scan signal based on the voltage of the third node and the voltage of the fourth node.

[0012] The scan driver can supply a scan signal to the output terminal during multiple drive times and hold times; each of the drive times has a constant frequency; the voltage of the first power supply or the voltage of the second power supply can be supplied to the output terminal by using a first clock signal supplied from the second input terminal and a second clock signal supplied from the third input terminal; and during each of the hold times, the voltage of the first power supply can be supplied to the output terminal by using a first clock signal and a second clock signal having the same voltage level as the voltage of the second power supply.

[0013] The holding time may include a first holding time and a second holding time; during the first holding time, the voltage of the third node may be maintained at twice the voltage of the first power supply; and during the second holding time, the voltage of the third node may rise from twice the voltage of the first power supply to the voltage of the first power supply or less.

[0014] The output section may include: a ninth transistor connected between the second power supply and the output terminal, wherein the gate electrode of the ninth transistor receives the voltage of the fourth node; and a tenth transistor connected between the output terminal and the first power supply, wherein the gate electrode of the tenth transistor receives the voltage of the third node.

[0015] The input section may include: a first transistor connected between a first input terminal and a first node, and the gate electrode of the first transistor is connected to a second input terminal to receive a first clock signal; a fourth transistor connected between a second input terminal and a second node, and the gate electrode of the fourth transistor receives the voltage of the first node; and a fifth transistor connected between the second node and a first power supply, and the gate electrode of the fifth transistor is connected to a second input terminal to receive the first clock signal.

[0016] The first signal processing section may include: a second capacitor having one end connected to a fifth node and the other end connected to a first electrode of a sixth transistor; a seventh transistor connected between the first electrode of the sixth transistor and a third input terminal, and the gate electrode of the seventh transistor receiving the voltage of the fifth node; a sixth transistor connected between the first electrode of the seventh transistor and a fourth node, and the gate electrode of the sixth transistor receiving a second clock signal supplied from the third input terminal; a first capacitor having one end connected to the fourth node and the other end connected to a second power supply; a fourth capacitor having a first end connected to the first node and the other end connected to the second power supply; an eighth transistor connected between the fourth node and the second power supply, and the gate electrode of the eighth transistor receiving the voltage of the first node; and a thirteenth transistor connected between the first node and the second power supply, and the gate electrode of the thirteenth transistor connected to a reset input terminal.

[0017] The second signal processing section may further include: a fifteenth transistor connected between the first input terminal and the sixteenth transistor, and the gate electrode of the fifteenth transistor receiving a first clock signal supplied from the second input terminal; a sixteenth transistor connected between the fifteenth transistor and the sixth node, and the gate electrode of the sixteenth transistor receiving a voltage from the first power supply; a third transistor connected between the third input terminal and the seventh node, and the gate electrode of the third transistor receiving a voltage from the sixth node; a third capacitor having one end connected to the sixth node and the other end connected to the seventh node; and a second transistor connected between the seventh node and the second power supply, and the gate electrode of the second transistor receiving a voltage from the second node.

[0018] The scan driver may further include a stabilization section electrically connected between the input section and the output section, which can limit the voltage drop of the first node and the voltage drop of the second node.

[0019] The stabilizing section may include: an eleventh transistor connected between the second node and the fifth node, wherein the gate electrode of the eleventh transistor receives the voltage of the first power supply; a seventeenth transistor connected between the first node and the twelfth transistor, wherein the gate electrode of the seventeenth transistor receives the first clock signal; and a twelfth transistor connected between the seventeenth transistor and the third node, wherein the gate electrode of the twelfth transistor receives the voltage of the first power supply.

[0020] The scan driver may further include a fifth capacitor having one end connected to the third node and the other end connected to the first power supply, and the fifth capacitor stores the voltage of the third node during the second hold time.

[0021] The scan driver can supply scan signals to the output terminal during multiple drive times and hold times; the drive time has a constant frequency; the voltage of the first power supply or the voltage of the second power supply is supplied to the output terminal by using a first clock signal supplied from the second input terminal and a second clock signal supplied from the third input terminal; each of the hold times includes a third hold time to an nth hold time and has a frequency lower than the frequency in the drive time, and the voltage of the first power supply is supplied to the output terminal by using the first clock signal supplied from the second input terminal and / or the second clock signal supplied from the third input terminal.

[0022] During the third hold time, the first clock signal may have a low voltage level, the same as the voltage of the first power supply, the second clock signal may have a high voltage level, the same as the voltage of the second power supply, and the voltage of the third node may rise from twice the voltage of the first power supply to the voltage of the first power supply or lower.

[0023] During the fourth hold time to the nth hold time, the first clock signal can change from a high voltage level to a low voltage level, the second clock signal can change from a low voltage level to a high voltage level, and the voltage of the third node can rise from twice the voltage of the first power supply to the voltage of the first power supply or lower.

[0024] The output section may include: a ninth transistor connected between the second power supply and the output terminal, wherein the gate electrode of the ninth transistor receives the voltage of the fourth node; and a tenth transistor connected between the output terminal and the first power supply, wherein the gate electrode of the tenth transistor receives the voltage of the third node.

[0025] The input section may include: a first transistor connected between a first input terminal and a first node, and the gate electrode of the first transistor is connected to a second input terminal to receive a first clock signal; a fourth transistor connected between a second input terminal and a second node, and the gate electrode of the fourth transistor receives the voltage of the first node; and a fifth transistor connected between the second node and a first power supply, and the gate electrode of the fifth transistor is connected to a second input terminal to receive the first clock signal.

[0026] The first signal processing section may include: a second capacitor having one end connected to a fifth node and the other end connected to a first electrode of a sixth transistor; a seventh transistor connected between the first electrode of the sixth transistor and a third input terminal, and the gate electrode of the seventh transistor receiving the voltage of the fifth node; a sixth transistor connected between the first electrode of the seventh transistor and a fourth node, and the gate electrode of the sixth transistor receiving a second clock signal supplied from the third input terminal; a first capacitor having one end connected to the fourth node and the other end connected to a second power supply; an eighth transistor connected between the fourth node and the second power supply, and the gate electrode of the eighth transistor receiving the voltage of the first node; and a thirteenth transistor connected between the first node and the second power supply, and the gate electrode of the thirteenth transistor connected to a reset input terminal.

[0027] The second signal processing section may include: a fifteenth transistor connected between a first input terminal and a sixteenth transistor, the gate electrode of the fifteenth transistor receiving a first clock signal supplied from a second input terminal; a sixteenth transistor connected between the fifteenth transistor and a sixth node, the gate electrode of the sixteenth transistor receiving a voltage from a first power supply; a third transistor connected between a third input terminal and a seventh node, the gate electrode of the third transistor receiving a voltage from the sixth node; a third capacitor having one end connected to the sixth node and the other end connected to the seventh node; and a second transistor connected between the seventh node and a second power supply, the gate electrode of the second transistor receiving a voltage from the second node.

[0028] The scan driver may further include a stabilization section electrically connected between the input section and the output section, and limiting the voltage drop of the first node and the voltage drop of the second node.

[0029] The stabilizing section may include: an eleventh transistor connected between the second node and the fifth node, wherein the gate electrode of the eleventh transistor receives the voltage of the first power supply; and a twelfth transistor connected between the first node and the third node, wherein the gate electrode of the twelfth transistor receives the voltage of the first power supply.

[0030] The scan driver may further include a fifth capacitor having one end connected to the third node and the other end connected to the first power supply, and the fifth capacitor may store the voltage of the third node during the third hold time to the nth hold time.

[0031] According to the embodiment of the scan driver, the drive frequency of the scan driver can be reduced so that a scan signal with a constant voltage level is output from the scan driver during the hold time when no start pulse is input.

[0032] It should be understood that both the foregoing general description and the following detailed description are illustrative and exemplary, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0033] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the inventive concept.

[0034] Figure 1 The illustration is a schematic diagram used to explain a display device constructed according to an embodiment based on the principles of the present invention.

[0035] Figure 2 The illustrations according to the embodiments include Figure 1 A circuit diagram of an example pixel in a display device.

[0036] Figure 3 The illustration is for driving according to an embodiment. Figure 2 A time sequence diagram of pixels.

[0037] Figure 4 The figure shows a block diagram of a scan driver according to an embodiment.

[0038] Figure 5 The figure shows a timing diagram of a scan signal output from a scan driver included in a display device, according to an embodiment.

[0039] Figure 6 The illustrations according to the embodiments include Figure 4 A circuit diagram of an example stage in a scan driver.

[0040] Figure 7 Illustration Figure 6 The timing diagram of the operations at the level.

[0041] Figure 8 The diagram is based on Figure 6 A circuit diagram of another example of the level of the embodiment.

[0042] Figure 9A The illustration includes, according to another embodiment, Figure 4 A circuit diagram of an example stage in a scan driver.

[0043] Figure 9B Illustration Figure 9A The timing diagram of the operations at the level.

[0044] Figure 9C The diagram is based on Figure 9A A circuit diagram of another example of the level of the embodiment. Detailed Implementation

[0045] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms for non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent configurations. In other instances, well-known structures and apparatuses are illustrated in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may differ, but are not necessarily exclusive. For example, the specific shape, configuration, and characteristics of one embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0046] Unless otherwise specified, the illustrated embodiments should be understood as providing features in different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0047] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clearly define the boundaries between adjacent elements. Therefore, unless specified otherwise, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between elements, and / or any other characteristics, properties, etc., of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented in different ways, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals refer to the same elements.

[0048] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or coupled to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being “directly” on, directly connected to, or directly coupled to another element or layer, an intermediary element or layer is not present. Therefore, the term “connection” can refer to a physical connection, electrical connection, and / or fluid connection, with or without an intermediary element. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0049] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0050] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “above,” “above,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another(s) as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features would then be oriented “above” other elements or features. Thus, the illustrative term “below” can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a” and “the (described)” as used herein are intended to include the plural forms as well. Furthermore, when used herein, the terms “comprising” and / or “including” indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “basically,” “about,” and other similar terms are used as approximations rather than terms of degree, and are therefore used to include inherent deviations in measured, calculated, and / or provided values ​​recognized by those skilled in the art.

[0052] As is customary in the art, embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (e.g., logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc.) formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It should also be contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or be implemented as a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and associated circuitry) to perform certain functions to perform others. Furthermore, in some embodiments, each block, unit, and / or module may be physically divided into two or more interactive and discrete blocks, units, and / or modules without departing from the scope of the inventive concept. Furthermore, some embodiments of blocks, units, and / or modules can be physically merged into more complex blocks, units, and / or modules without departing from the scope of the inventive concept.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms such as those defined in common dictionaries shall be interpreted as having meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0054] In the following text, reference will be made to Figure 1 A display device according to an embodiment is described.

[0055] Figure 1The illustration is a schematic diagram used to explain a display device constructed according to an embodiment based on the principles of the present invention.

[0056] The display device 1000 may include a display unit 100, a first scan driver 200, a second scan driver 300, a transmission driver 400, a data driver 500, and a timing controller 600.

[0057] The display device 1000 can display images at various drive frequencies (or image refresh rate, screen refresh rate, etc.) depending on the driving conditions. In this case, the drive frequency is the frequency at which data signals are basically written to the drive transistors of the pixels PX.

[0058] Specifically, the drive frequency is also known as the screen refresh rate, and it represents the frequency at which images are displayed on the screen.

[0059] For example, the display device 1000 can display images in response to various driving frequencies from 1 Hz to 120 Hz.

[0060] The display unit 100 displays an image. The display unit 100 includes a pixel PX arranged to be connected to a data line D, scan lines S1 and S2, and an emission control line E. In this case, the pixel PX can receive voltages from a first driving power supply VDD, a second driving power supply VSS, and an initialization power supply Vint, which are located outside the display device 1000.

[0061] In addition, pixel PX can be connected to one or more of the first scan line S1, the second scan line S2, and the emission control line E, corresponding to the pixel circuit structure.

[0062] The timing controller 600 can receive input control signals and input image signals from an image source such as an external graphics device.

[0063] Specifically, the timing controller 600 can generate image data RGB based on the input image signal and the operating conditions of the display unit 100, and provide the image data RGB to the data driver 500.

[0064] In addition, the timing controller 600 can generate a first drive control signal SCS1 for controlling the drive timing of the first scan driver 200 based on the input control signal, so as to provide the first drive control signal SCS1 to the first scan driver 200.

[0065] In addition, the timing controller 600 can provide a second drive control signal SCS2, which is used to control the drive timing of the second scan driver 300, to the second scan driver 300 based on the input control signal.

[0066] In addition, the timing controller 600 can generate a third drive control signal ECS for controlling the drive timing of the transmitter driver 400 based on the input control signal, so as to provide the third drive control signal ECS to the transmitter driver 400.

[0067] In addition, the timing controller 600 can generate a fourth drive control signal DCS for controlling the drive timing of the data driver 500 based on the input control signal, and provide the fourth drive control signal DCS to the data driver 500.

[0068] The first scan driver 200 can receive a first drive control signal SCS1 from the timing controller 600. In addition, the first scan driver 200 can supply a scan signal to the first scan line S1 in response to the first drive control signal SCS1.

[0069] The second scan driver 300 can receive the second drive control signal SCS2 from the timing controller 600. Additionally, the second scan driver 300 can supply a scan signal to the second scan line S2 in response to the second drive control signal SCS2.

[0070] The transmitter driver 400 can receive a third drive control signal ECS from the timing controller 600. Additionally, the transmitter driver 400 can supply a transmit control signal to the transmit control line E in response to the third drive control signal ECS.

[0071] The data driver 500 can receive a fourth drive control signal DCS from the timing controller 600. Additionally, the data driver 500 can convert the image data RGB into an analog data signal (data voltage) in response to the fourth drive control signal DCS and supply this data signal to the data line D.

[0072] In the following text, reference will be made to Figure 2 A circuit diagram describing a pixel included in a display device according to an embodiment.

[0073] Figure 2 The illustrations according to the embodiments include Figure 1 A circuit diagram of an example pixel in a display device.

[0074] exist Figure 2 In order to better understand and be easier to describe, the pixel PXij is shown as arranged on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj (where i and j are integer values ​​greater than or equal to 1).

[0075] refer to Figure 2 Pixel PXij may include a light-emitting element LD, a first pixel transistor M1 to a seventh pixel transistor M7, and a storage capacitor Cst.

[0076] The first electrode of the light-emitting element LD is connected to the fourth pixel node PN4, and the second electrode of the light-emitting element LD is connected to the second driving power supply VSS. In this case, the light-emitting element LD emits light with a predetermined brightness corresponding to the amount of current supplied from the first pixel transistor M1.

[0077] In this embodiment, the light-emitting element LD can be an organic light-emitting diode (OLED) including an organic light-emitting layer. Alternatively, the light-emitting element LD can be an inorganic light-emitting element made of inorganic materials. Additionally, the light-emitting element LD can be a light-emitting element made of a composite of inorganic and organic materials. Alternatively, the light-emitting element LD can have a form in which multiple inorganic light-emitting elements are connected in parallel and / or in series between the second driving power supply VSS and the fourth pixel node PN4.

[0078] The first pixel transistor M1 is connected between the first pixel node PN1 and the third pixel node PN3. In this case, the gate electrode of the first pixel transistor M1 is connected to the second pixel node PN2.

[0079] The first pixel transistor M1 can control the amount of current flowing from the first driving power supply VDD through the light-emitting element LD to the second driving power supply VSS in response to the voltage of the second pixel node PN2. In this case, the first driving power supply VDD can be set to a voltage higher than that of the second driving power supply VSS.

[0080] The second pixel transistor M2 is connected between the data line Dj and the first pixel node PN1. Furthermore, the gate electrode of the second pixel transistor M2 is connected to the i-th first scan line S1i.

[0081] Specifically, the second pixel transistor M2 is turned on when the first scan signal is supplied to the first scan line S1i to electrically connect the data line Dj and the first pixel node PN1.

[0082] The third pixel transistor M3 is connected between the third pixel node PN3 and the second pixel node PN2. Furthermore, the gate electrode of the third pixel transistor M3 is connected to the i-th second scan line S2i.

[0083] Specifically, the third pixel transistor M3 is turned on when the second scan signal is supplied to the i-th second scan line S2i. In this case, the third pixel transistor M3 is turned on, causing the first pixel transistor M1 to be connected by a diode.

[0084] The fourth pixel transistor M4 is connected between the second pixel node PN2 and the first initialization power supply Vint1.

[0085] Specifically, the gate electrode of the fourth pixel transistor M4 is connected to the (i-1)th second scan line S2i-1, and the fourth pixel transistor M4 is turned on when the second scan signal is supplied to the (i-1)th second scan line S2i-1 to supply the voltage of the first initialization power supply Vint1 to the second pixel node PN2. In this case, the voltage of the first initialization power supply Vint1 is set to a voltage lower than the voltage of the data signal supplied to the data line Dj.

[0086] Therefore, the gate voltage of the first pixel transistor M1 (i.e., the voltage of the second pixel node PN2) is initialized to the voltage of the first initialization power supply Vint1 by turning on the fourth pixel transistor M4.

[0087] The fifth pixel transistor M5 is connected between the first driving power supply VDD and the first pixel node PN1. Additionally, the gate electrode of the fifth pixel transistor M5 is connected to the i-th emission control line Ei.

[0088] The sixth pixel transistor M6 is connected between the third pixel node PN3 and the first electrode of the light-emitting element LD (i.e., the fourth pixel node PN4). Additionally, the gate electrode of the sixth pixel transistor M6 is connected to the i-th emission control line Ei.

[0089] Specifically, the fifth pixel transistor M5 and the sixth pixel transistor M6 can be turned off when the transmit control signal is supplied to the i-th transmit control line Ei, and turned on under other conditions.

[0090] The seventh pixel transistor M7 is connected between the first electrode of the light-emitting element LD (i.e., the fourth pixel node PN4) and the second initialization power supply Vint2. Additionally, the gate electrode of the seventh pixel transistor M7 is connected to the i-th first scan line S1i.

[0091] Specifically, when the first scan signal is supplied to the i-th first scan line S1i, the seventh pixel transistor M7 is turned on to supply the voltage of the second initialization power supply Vint2 to the first electrode of the light-emitting element LD.

[0092] However, this is just an example, and the gate electrode of the seventh pixel transistor M7 can be connected to the (i-1)th first scan line or the (i+1)th first scan line.

[0093] The storage capacitor Cst is connected between the first driving power supply VDD and the second pixel node PN2. In this case, the storage capacitor Cst can store the voltage applied to the second pixel node PN2.

[0094] Meanwhile, the first pixel transistor M1, the second pixel transistor M2, the fifth pixel transistor M5, the sixth pixel transistor M6, and the seventh pixel transistor M7 can be formed as polycrystalline silicon semiconductor transistors.

[0095] For example, the first pixel transistor M1, the second pixel transistor M2, the fifth pixel transistor M5, the sixth pixel transistor M6, and the seventh pixel transistor M7 may include a polycrystalline silicon semiconductor layer formed by a low-temperature polycrystalline silicon (LTPS) process as an active layer (channel). Alternatively, the first pixel transistor M1, the second pixel transistor M2, the fifth pixel transistor M5, the sixth pixel transistor M6, and the seventh pixel transistor M7 may be P-type transistors.

[0096] Therefore, the gate turn-on voltage that turns on the first pixel transistor M1, the second pixel transistor M2, the fifth pixel transistor M5, the sixth pixel transistor M6, and the seventh pixel transistor M7 can be a low level (or a logic low level or a low voltage level).

[0097] Because polysilicon semiconductor transistors have the advantage of fast response speed, they can be used in switching elements that require fast switching.

[0098] The third pixel transistor M3 and the fourth pixel transistor M4 can be formed as oxide semiconductor transistors. For example, the third pixel transistor M3 and the fourth pixel transistor M4 can be N-type oxide semiconductor transistors, and can include an oxide semiconductor layer as an active layer. Therefore, the gate turn-on voltage for turning on the third pixel transistor M3 and the fourth pixel transistor M4 can be a high level (or a logic high level or a high voltage level).

[0099] Oxide-semiconductor transistors (OSTs) can be processed at low temperatures and have a lower charge mobility than polysilicon transistors (PSTs). That is, OSTs exhibit excellent cutoff current characteristics. Therefore, when the third pixel transistor M3 and the fourth pixel transistor M4 are formed as OSTs, the leakage current from the second pixel node PN2 and / or the third pixel node PN3 can be minimized, thereby improving display quality.

[0100] Furthermore, each of the second scan lines S2i-1 and S2i can be connected to two or more horizontal lines other than the i-th horizontal line. Therefore, the initialization operation of the gate voltage and / or threshold voltage compensation operation of the first pixel transistor M1 of the pixels arranged on multiple horizontal lines can be performed simultaneously.

[0101] In the following text, reference will be made to Figure 3 Description of a driver according to an embodiment Figure 2 A time sequence diagram of pixels.

[0102] Figure 3 The illustration is for driving according to an embodiment. Figure 2 A time sequence diagram of pixels.

[0103] refer to Figures 1 to 3 The pixel PXij can receive signals for displaying images during the non-emission period (NEP) and emit light based on the received signals during the emission period (EP).

[0104] refer to Figure 3 The gate conduction voltage of the second scan signal supplied to the i-th second scan line S2i and the i-1-th second scan line S2i-1, which are respectively connected to the third pixel transistor M3 and the fourth pixel transistor M4 (which are N-type transistors), is high.

[0105] The gate conduction voltage supplied to the first scan signal of the first scan line S1i, which is connected to the second transistor M2 and the seventh transistor M7 (both are P-type transistors), is low.

[0106] In addition, the gate conduction voltage of the emission control signal supplied to the i-th emission control line Ei, which is a P-type transistor, is low.

[0107] First, during the non-emission period (NEP), a high-level transmit control signal is supplied to the i-th transmit control line Ei. In this state, the fifth pixel transistor M5 and the sixth pixel transistor M6 are turned off. When the fifth pixel transistor M5 and the sixth pixel transistor M6 are turned off, pixel PXij is set to a non-emission state.

[0108] Simultaneously, a second scan signal is supplied to the (i-1)th second scan line S2i-1. When the second scan signal is supplied to the (i-1)th second scan line S2i-1, the fourth pixel transistor M4 is turned on. Furthermore, when the fourth pixel transistor M4 is turned on, the voltage of the first initialization power supply Vint1 is supplied to the second pixel node PN2.

[0109] Subsequently, the first scan signal and the second scan signal are supplied to the i-th first scan line S1i and the i-th second scan line S2i, respectively.

[0110] Specifically, when the second scan signal is supplied to the i-th second scan line S2i, the third pixel transistor M3 is turned on. In this case, when the third pixel transistor M3 is turned on, the first pixel transistor M1 is connected by a diode, and the threshold voltage of the first pixel transistor M1 can be compensated.

[0111] When the first scan signal is supplied to the i-th first scan line S1i, the second pixel transistor M2 is turned on. In this case, when the second pixel transistor M2 is turned on, the data signal from the data line Dj is supplied to the first pixel node PN1.

[0112] Specifically, since the second pixel node PN2 is initialized with a voltage of the first initialization power supply Vint1 that is lower than the voltage of the data signal, the first pixel transistor M1 is turned on.

[0113] In this configuration, when the first pixel transistor M1 is turned on, the data signal supplied to the first pixel node PN1 is supplied to the second pixel node PN2 via the diode-connected first pixel transistor M1. Therefore, a voltage corresponding to the data signal and the threshold voltage of the first pixel transistor M1 is applied to the second pixel node PN2. In this configuration, the storage capacitor Cst can store the voltage of the second pixel node PN2.

[0114] Furthermore, when the first scan signal is supplied to the i-th first scan line S1i, the seventh pixel transistor M7 is turned on. In this case, when the seventh pixel transistor M7 is turned on, the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD (i.e., the fourth pixel node PN4). Therefore, the residual voltage remaining in the parasitic capacitor of the light-emitting element LD can be discharged.

[0115] Subsequently, the transmission control signal is stopped from being supplied to the i-th transmission control line Ei. When the transmission control signal is stopped from being supplied to the i-th transmission control line Ei, the fifth pixel transistor M5 and the sixth pixel transistor M6 are turned on.

[0116] In this case, the first pixel transistor M1 can control the driving current flowing to the light-emitting element LD in response to the voltage of the second pixel node PN2. Therefore, the light-emitting element LD can emit light with a brightness corresponding to the amount of driving current.

[0117] In the following text, reference will be made to Figure 4 A scan driver according to an embodiment is described.

[0118] Figure 4 The figure shows a block diagram of a scan driver according to an embodiment.

[0119] refer to Figure 1 and Figure 4 The scan driver 10 may include multiple levels ST1 to ST4.

[0120] Specifically, multiple stages ST1 to ST4 can be connected to each of the predetermined output lines G1 to G4, and can output output signals corresponding to clock signals CLK1 and CLK2. In this case, stages ST1 to ST4 can be implemented using essentially the same circuit.

[0121] In this case, the scan driver 10 can be configured with a reference. Figure 1The transmit driver 400 and / or the second scan driver 300 are described. For example, output lines G1 to G4 can be understood as transmit control lines ( Figure 1 (E) or the second scan line ( Figure 1 (S2 in the middle).

[0122] According to the embodiment, the first stage ST1 to the fourth stage ST4 can be connected to at least one of the output lines G1 to G4 respectively.

[0123] Specifically, the first stage ST1 can be connected to the first output line G1 to supply an output signal (e.g., a second scan signal or a transmit control signal) to the first output line G1. However, this is merely an example, and the connection relationship between the output lines G1 to G4 and the horizontal line can be configured in various ways depending on the pixel structure and driving method of the display device 1000.

[0124] For example, the first output line G1 connected to the first stage ST1 can be connected to multiple horizontal lines (or pixel rows).

[0125] Each of ST1 to ST4 may be provided with a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

[0126] Specifically, the first input terminal 101 can receive the output signal of the previous stage (e.g., a transmit control signal or a second scan signal) or the start pulse SSP (e.g., a transmit control start pulse or a second scan start pulse).

[0127] For example, the first input terminal 101 of the first stage ST1 can receive the start pulse SSP, and the first input terminal 101 of the second stage ST2 can receive the output signal output from the first stage ST1.

[0128] Additionally, the second input terminal 102 of the k-th stage (k is an integer value greater than or equal to 1) can receive the first clock signal CLK1, and the third input terminal 103 of the k-th stage can receive the second clock signal CLK2.

[0129] In addition, the second input terminal 102 of the (k+1)th stage can receive the second clock signal CLK2, and the third input terminal 103 of the (k+1)th stage can receive the first clock signal CLK1.

[0130] The first clock signal CLK1 and the second clock signal CLK2 have the same period, and their phases do not overlap.

[0131] Specifically, the second clock signal CLK2 can be set to a signal offset from the first clock signal CLK1 by approximately half a cycle.

[0132] Additionally, stages ST1 to ST4 are supplied with the voltages of a first power supply VGL and a second power supply VGH. In this case, the voltages of the first power supply VGL and the second power supply VGH can have DC voltage levels. Furthermore, the voltage of the second power supply VGH can be set to be greater than the voltage of the first power supply VGL.

[0133] Here, the voltage of the first power supply VGL can be set as the gate cutoff voltage, and the voltage of the second power supply VGH can be set as the gate turn-on voltage.

[0134] Specifically, when pixel PX is configured with an N-channel metal-oxide-semiconductor (NMOS) transistor, the voltage of the first power supply VGL corresponds to a low level, and the voltage of the second power supply VGH can correspond to a high level.

[0135] However, this is merely an example, and the first power supply VGL and the second power supply VGH are not limited to this. For example, the voltage of the first power supply VGL and the voltage of the second power supply VGH can be set according to the type of transistor and the usage environment of the display device, etc.

[0136] In the following text, reference will be made to Figure 5 The description includes a scan signal output from a scan driver included in a display device, according to an embodiment.

[0137] Figure 5 The figure shows a timing diagram of a scan signal output from a scan driver included in a display device, according to an embodiment.

[0138] refer to Figure 1 , Figure 3 and Figure 4 The scan driver 10 can be a second scan driver 300. The first stage ST1 to the fourth stage ST4 can sequentially output the second scan signal.

[0139] refer to Figure 5 Within a frame (1 frame) period, the start pulse SSP can overlap with multiple gate on periods and multiple gate off periods of the first clock signal CLK1 and the second clock signal CLK2.

[0140] In this case, the first stage ST1 can output the second scan signal to the first and second scan lines S2_1 based on the start pulse SSP, the first clock signal CLK1, and the second clock signal CLK2.

[0141] Additionally, the second stage ST2 can output the second scan signal, which is offset by a predetermined horizontal time period, from the first second scan line S2_1 to the second second scan line S2_2.

[0142] Similarly, the third stage ST3 and the fourth stage ST4 can sequentially output the second scan signal to the third second scan line S2_3 and the fourth second scan line S2_4 at predetermined intervals based on the first clock signal CLK1 and the second clock signal CLK2.

[0143] In the following text, reference will be made to Figure 6 The description includes, according to the embodiments, the following: Figure 4 A circuit diagram of an example stage in a scan driver.

[0144] Figure 6 The illustrations according to the embodiments include Figure 4 A circuit diagram of an example stage in a scan driver.

[0145] refer to Figure 4 and Figure 6 The i-th stage STi (where i is an integer value greater than or equal to 1) may include an input section 11, an output section 12, a first signal processing section 13, a second signal processing section 14, and a stabilization section 15.

[0146] like Figure 6 As shown, the description will mainly focus on the i-th stage STi (e.g., odd stage) of the third input terminal 103, where the first clock signal CLK1 is supplied to the second input terminal 102 and the second clock signal CLK2 is supplied to the third input terminal 103.

[0147] However, this is merely an example, and in the i+1th stage (e.g., an even stage), the second clock signal CLK2 can be supplied to the second input terminal 102, and the first clock signal CLK1 can be supplied to the third input terminal 103.

[0148] In an embodiment, the start pulse SSP can be supplied to the first input terminal 101 of the i-th stage STi, and the output signal of the previous output line Gi-1 can be supplied to the first input terminal 101 of the remaining stages.

[0149] In the following text, the i-th level STi is referred to as level STi and will be described.

[0150] The input section 11 can control the voltage of the first node N1 and the voltage of the second node N2 in response to the signals supplied to the first input terminal 101 and the second input terminal 102.

[0151] Specifically, the input section 11 may include a first transistor T1, a fourth transistor T4, and a fifth transistor T5.

[0152] The first transistor T1 can be connected between the first input terminal 101 and the first node N1. Additionally, the gate electrode of the first transistor T1 can be connected to the second input terminal 102.

[0153] Specifically, when the first clock signal CLK1 input to the second input terminal 102 has a gate conduction voltage (low level), the first transistor T1 can be in the gate conduction state to electrically connect the first input terminal 101 and the first node N1.

[0154] The fourth transistor T4 can be connected between the second input terminal 102 and the second node N2. In this case, the gate electrode of the fourth transistor T4 can be electrically connected to the first node N1.

[0155] Specifically, the fourth transistor T4 can be turned on or off based on the voltage of the first node N1.

[0156] In one embodiment, the fourth transistor T4 may include a plurality of sub-transistors connected in series. Each of the sub-transistors may include a gate electrode commonly connected to the first node N1. This is referred to as a dual-gate structure.

[0157] Therefore, the current leakage caused by the fourth transistor T4 can be minimized. However, this is merely an example, and at least one of the other transistors besides the fourth transistor T4 may have a dual-gate structure.

[0158] The fifth transistor T5 can be connected between the first power supply VGL and the second node N2. Additionally, the gate electrode of the fifth transistor T5 can be connected to the second input terminal 102.

[0159] Specifically, when the first clock signal CLK1 is supplied to the second input terminal 102, the fifth transistor T5 is turned on to supply the voltage of the first power supply VGL to the second node N2.

[0160] The output section 12 can supply the voltage of the first power supply VGL or the voltage of the second power supply VGH to the output terminal 104 based on the voltage of the third node N3 and the voltage of the fourth node N4.

[0161] Specifically, the voltage of the first power supply VGL can correspond to the low level of the output signal supplied to the i-th output line Gi, and the voltage of the second power supply VGH can correspond to the high level of the output signal supplied to the i-th output line Gi.

[0162] Additionally, the output section 12 may include a ninth transistor T9 and a tenth transistor T10.

[0163] The tenth transistor T10 can be connected between the first power supply VGL and the output terminal 104. Additionally, the gate electrode of the tenth transistor T10 can be connected to the third node N3.

[0164] Specifically, the tenth transistor T10 can be turned on or off in response to the voltage of the third node N3. In this case, when the tenth transistor T10 is turned on, the output signal supplied to the output terminal 104 can have a first power supply voltage VGL that is low.

[0165] The ninth transistor T9 can be connected between the second power supply VGH and the output terminal 104. Additionally, the gate electrode of the ninth transistor T9 can be connected to the fourth node N4.

[0166] Specifically, the ninth transistor T9 can be turned on or off in response to the voltage at the fourth node N4. In this case, when the ninth transistor T9 is turned on, the output signal supplied to the output terminal 104 can have a high-level voltage from the second power supply VGH.

[0167] The first signal processing section 13 may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0168] The first signal processing unit 13 can control the voltage of the fourth node N4. Specifically, the first signal processing unit 13 can supply the voltage of the second power supply VGH to the fourth node N4 based on the voltage of the first node N1, or it can control the voltage of the fourth node N4 based on the second clock signal CLK2 supplied to the third input terminal 103 in response to the voltage of the second node N2.

[0169] For example, when the voltage of the second node N2 is low, the first signal processing section 13 allows the voltage of the fourth node N4 to have a gate conduction voltage (low level), so that the ninth transistor T9 can be turned on.

[0170] One end of the second capacitor C2 can be connected to the fifth node N5, and the other end of the second capacitor C2 can be connected between the sixth transistor T6 and the seventh transistor T7.

[0171] The sixth transistor T6 can be connected between the other end of the second capacitor C2 and the fourth node N4. Additionally, the gate electrode of the sixth transistor T6 can be connected to the third input terminal 103.

[0172] Specifically, the sixth transistor T6 can be turned on in response to the gate conduction voltage (low level) of the second clock signal CLK2 supplied to the third input terminal 103.

[0173] The seventh transistor T7 can be connected between the other end of the second capacitor C2 and the third input terminal 103. Additionally, the gate electrode of the seventh transistor T7 can be connected to the fifth node N5.

[0174] Specifically, the seventh transistor T7 can be turned on or off in response to the voltage of the fifth node N5.

[0175] The eighth transistor T8 can be connected between the second power supply VGH and the fourth node N4. Additionally, the gate electrode of the eighth transistor T8 can be connected to the first node N1.

[0176] Specifically, the eighth transistor T8 can be turned on or off in response to the voltage of the first node N1.

[0177] The thirteenth transistor T13 can be connected between the second power supply VGH and the first node N1. Additionally, the gate electrode of the thirteenth transistor T13 can be connected to the reset input terminal 105. The thirteenth transistor T13 is turned on when the reset signal RST is input to the reset input terminal 105 to supply the voltage of the second power supply VGH to the first node N1.

[0178] In this embodiment, the reset signal RST is a global signal, and the reset signal RST can be applied together to stages ST1 to ST4.

[0179] During the initialization period when the reset signal RST is supplied to the scan driver 10, a high-level output signal can be simultaneously output to output lines G1 to G4. Additionally, a low-level first clock signal CLK1 and a low-level second clock signal CLK2 can be supplied.

[0180] The first capacitor C1 can be connected between the second power supply VGH and the fourth node N4. In this case, the first capacitor C1 can be charged with the voltage applied to the fourth node N4 and stably maintain the voltage of the fourth node N4.

[0181] The fourth capacitor C4 can be connected between the second power supply VGH and the first node N1. In this case, the fourth capacitor C4 can be charged with the voltage applied to the first node N1 and stably maintain the voltage of the first node N1.

[0182] The second signal processing section 14 may include a second transistor T2, a third transistor T3, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a third capacitor C3.

[0183] The fourteenth transistor T14 can be connected between the sixth node N6 and the third node N3. Additionally, the gate electrode of the fourteenth transistor T14 can be connected to the sixth node N6.

[0184] Specifically, the fourteenth transistor T14 can have a diode structure connected in the direction from the third node N3 to the sixth node N6. Therefore, no current flows from the sixth node N6 to the third node N3.

[0185] In this case, the fourteenth transistor T14 can be turned on or off in response to the voltage at the sixth node N6.

[0186] The fifteenth transistor T15 can be connected between the first input terminal 101 and the sixteenth transistor T16. Additionally, the gate electrode of the fifteenth transistor T15 can be connected to the second input terminal 102.

[0187] In this case, when the first clock signal CLK1 is supplied to the second input terminal 102, the fifteenth transistor T15 can be turned on to provide the signal supplied from the first input terminal 101 to the sixteenth transistor T16.

[0188] The sixteenth transistor T16 is connected between the fifteenth transistor T15 and the sixth node N6. Additionally, the gate electrode of the sixteenth transistor T16 can be connected to the first power supply VGL. In this case, since the first power supply VGL is at a low level (L), the sixteenth transistor T16 is always in the gate-on state.

[0189] Therefore, when the low-level (L) first clock signal CLK1 is supplied from the second input terminal 102, the fifteenth transistor T15 can be turned on to provide the signal supplied from the first input terminal 101 to the sixth node N6.

[0190] The third transistor T3 can be connected between the third input terminal 103 and the seventh node N7. Additionally, the gate electrode of the third transistor T3 can be connected to the sixth node N6.

[0191] Therefore, the third transistor T3 can be turned on or off in response to the voltage at the sixth node N6.

[0192] The third capacitor C3 can be connected between the sixth node N6 and the seventh node N7. In this case, through the coupling of the third capacitor C3, the voltage level of the sixth node N6 can fluctuate within a predetermined range according to the voltage change of the seventh node N7. That is, the voltage of the sixth node N6 can depend on the voltage level change of the second clock signal CLK2.

[0193] The second transistor T2 can be connected between the seventh node N7 and the second power supply VGH. Additionally, the gate electrode of the second transistor T2 can be connected to the second node N2.

[0194] Therefore, the second transistor T2 can be turned on or off in response to the voltage of the second node N2.

[0195] The stabilization section 15 can electrically connect the input section 11 and the output section 12. Furthermore, the stabilization section 15 can limit the amount of voltage drop at the first node N1 and the amount of voltage drop at the second node N2.

[0196] Specifically, when the voltage drop at the third node N3 is large, the stabilizing part 15 acts as a resistor, allowing voltage division between the first node N1 and the third node N3.

[0197] Therefore, even if the voltage of the third node N3 changes significantly, it can prevent the drain-source voltage of the first transistor T1 from suddenly increasing and can protect the first transistor T1 connected to the first node N1.

[0198] Furthermore, when the voltage at the fifth node N5 drops significantly due to the coupling of the second capacitor C2, the stabilizing portion 15 can be used as a resistor. Therefore, it is possible to protect the second transistor T2, the fourth transistor T4, and the fifth transistor T5 connected to the second node N2.

[0199] Specifically, the stabilizing section 15 may include the eleventh transistor T11, the twelfth transistor T12, and the seventeenth transistor T17.

[0200] The twelfth transistor T12 can be connected between the third node N3 and the seventeenth transistor T17. Furthermore, the gate electrode of the twelfth transistor T12 can be connected to the first power supply VGL. Therefore, the twelfth transistor T12 can be kept on by the first power supply VGL.

[0201] Specifically, when the voltage of the third node N3 drops below the voltage of the first power supply VGL, the twelfth transistor T12 can divide the voltage, and the voltage of the first node N1 can be stably maintained.

[0202] For example, the voltage of the first node N1 will not drop below the voltage of the first power supply VGL. Therefore, the bias stress that may be applied to the first transistor T1 can be reduced.

[0203] The seventeenth transistor T17 can be connected between the first node N1 and the twelfth transistor T12. Additionally, the gate electrode of the seventeenth transistor T17 can be connected to the second input terminal 102. Therefore, the seventeenth transistor T17 can be in a gate-on state by a first clock signal CLK1 in a low-level (L) state input to the second input terminal 102.

[0204] The eleventh transistor T11 can be connected between the second node N2 and the fifth node N5. Furthermore, the gate electrode of the eleventh transistor T11 can be connected to the first power supply VGL. Therefore, the eleventh transistor T11 can always maintain its gate on state.

[0205] Specifically, when the voltage of the fifth node N5 drops below the voltage of the first power supply VGL due to coupling through the second capacitor C2, the eleventh transistor T11 acts as a resistor, so that the voltage of the second node N2 can be stably maintained.

[0206] For example, the voltage at the second node N2 will not drop below the voltage of the first power supply VGL. Therefore, the bias stress that may be applied to the fourth transistor T4 and the fifth transistor T5 can be reduced.

[0207] In the following text, reference will be made to Figure 7 Description according to embodiments Figure 6 Level of operation.

[0208] Figure 7 Illustration Figure 6 The timing diagram of the operations at the level.

[0209] refer to Figure 1 , Figure 6 and Figure 7 The first clock signal CLK1 and the second clock signal CLK2 are supplied with different timing sequences.

[0210] Specifically, the second clock signal CLK2 is set to be half the period offset (e.g., 1 horizontal period) from the first clock signal CLK1.

[0211] The high level (H) of the start pulse SSP can correspond to the voltage of the second power supply VGH, and the low level (L) of the start pulse SSP can correspond to the voltage of the first power supply VGL.

[0212] Specifically, the voltage of the first power supply VGL can be approximately -8V, and the voltage of the second power supply VGH can be approximately 10V. However, this is illustrative, and the starting pulse SSP in this embodiment and other embodiments is not limited thereto.

[0213] in addition, Figure 7 Assuming by reducing Figure 1 The second scan driver 300 is driven at a frequency that allows it to operate. In this case, a frame period (1 frame) is divided into a drive time and a hold time.

[0214] The scan driver 10 supplies output signals using stages ST1 to ST4 during the drive time of a frame period and does not supply output signals using stages ST1 to ST4 during the hold time of a frame period.

[0215] For this purpose, in reference Figure 7 In the described embodiment, clock signals CLK1 and CLK2 can be supplied at a first frequency during the drive time so that the output signal can be output stably, and clock signals CLK1 and CLK2 can be supplied at a second frequency lower than the first frequency during the hold time so that power consumption can be reduced.

[0216] For example, during the drive time, the first clock signal CKL1 and the second clock signal CLK2 can be repeatedly changed to a high level (H) voltage (the voltage of the second power supply VGH, hereinafter referred to as voltage VGH) or a low level (L) voltage (the voltage of the first power supply VGL, hereinafter referred to as voltage VGL), and during the hold time, the first clock signal CKL1 and the second clock signal CLK2 can be maintained at a high level (H) (VGH).

[0217] The low level (L)(VGL+|Vth|) of the third node N3 can be close to the value obtained by adding the absolute value of the threshold voltage of the twelfth transistor T12 to the voltage of the first power supply VGL. However, since the threshold voltage (|Vth|) of the twelfth transistor T12 is very small compared to the voltage of the first power supply VGL, it will be assumed and described that the low level (L)(VGL+|Vth|) of the third node N3, the low level (L)(VGL) of the fourth node N4, the voltage of the first power supply VGL, the low level (L)(VGL) of the start pulse SSP, and the low level (L)(VGL) of the output voltage Out as the output signal are substantially the same or close to each other.

[0218] Furthermore, the 2-low level (2L) (2VGL+|Vth|) of the third node N3 can be a voltage level close to the value obtained by adding the absolute value of the threshold voltage of the twelfth transistor T12 to 2×VGL. In this case, since the threshold voltage (|Vth|) of the twelfth transistor T12 is very small compared to the voltage of the 2-low level (2L), it will be assumed and described that the 2-low level (2L) is 2×VGL.

[0219] At the first time point t1, the starting pulse SSP can be changed from low level (L) to high level (H) and can be supplied to the first input terminal 101.

[0220] In addition, the first clock signal CLK1 can be changed from high level (H) to low level (L) and can be supplied to the second input terminal 102 at low level (L).

[0221] In addition, the second clock signal CLK2 can be changed from low level (L) to high level (H) and can be supplied to the third input terminal 103 at high level (H).

[0222] In this case, due to the low-level (L) first clock signal CLK1 supplied to the second input terminal 102, the first transistor T1 is in the gate-on state. Therefore, since the high-level (H) start pulse SSP is applied to the first node N1 through the first transistor T1, the voltage VGH of the high-level (H) start pulse SSP is applied to the first node N1.

[0223] Furthermore, due to the low-level (L) first clock signal CLK1 supplied to the second input terminal 102, the fifteenth transistor T15 is in the gate-on state. Therefore, the high-level (H) start pulse SSP is applied to the sixth node N6 through the fifteenth transistor T15 and the sixteenth transistor T16. In this case, the third transistor T3 is turned off by the voltage at the sixth node N6.

[0224] In addition, the fifth transistor T5 and the seventeenth transistor T17 are turned on by the first clock signal CLK1, which is low level (L) supplied to the second input terminal 102.

[0225] When the fifth transistor T5 is turned on, voltage VGL is supplied to the second node N2. In this case, since the eleventh transistor T11 is set to the on state, the fifth node N5 is set to voltage VGL. When the fifth node N5 is set to voltage VGL, the seventh transistor T7 is turned on. In this case, the sixth transistor T6 is turned off by the high-level second clock signal CLK2 supplied to the third input terminal 103, and the voltage of the fourth node N4 is not changed by the voltage of the second node N2 (i.e., the fifth node N5).

[0226] When the seventeenth transistor T17 is turned on, the voltage of the first node N1 (i.e., the voltage of the high-level (H) start pulse SSP) is supplied to the third node N3 via the seventeenth transistor T17 and the twelfth transistor T12.

[0227] As a result, the third node N3 is given a voltage VGH due to the start pulse SSP with a high level (H).

[0228] Additionally, because voltage VGH is applied to the third node N3 due to the high-level (H) start pulse SSP, the tenth transistor T10 is turned off.

[0229] At the second time point t2, the start pulse SSP can be supplied to the first input terminal 101 at a high level (H).

[0230] Additionally, the first clock signal CLK1 can be supplied to the second input terminal 102 at a high level (H). Furthermore, the second clock signal CLK2 can be supplied to the third input terminal 103 at a low level (L).

[0231] In this case, due to the low level (L) second clock signal CLK2 supplied to the third input terminal 103, the sixth transistor T6 is in the gate-on state.

[0232] In this case, the second capacitor C2 stores the voltage corresponding to its conduction based on the voltage at the first time point t1, and therefore, the seventh transistor T7 remains in the conducting state. Thus, when the sixth transistor T6 is turned on, the low-level voltage of the second clock signal CLK2 is supplied to the fourth node N4.

[0233] Therefore, since a low-level (L) voltage VGL is applied to the fourth node N4, the ninth transistor T9 is switched to the on state.

[0234] Therefore, the voltage of the second power supply VGH is output to the output terminal 104. That is, at the second time point t2, a high-level (H) output signal is output to the output terminal 104.

[0235] At the third time point t3, the starting pulse SSP can be changed from high level (H) to low level (L) and can be supplied to the first input terminal 101 at low level (L).

[0236] Additionally, the first clock signal CLK1 can be supplied to the second input terminal 102 at a low level (L). Furthermore, the second clock signal CLK2 can be changed from a low level (L) to a high level (H) and can be supplied to the third input terminal 103 at a high level (H).

[0237] In this case, the first clock signal CLK1 applied to the second input terminal 102 is a low-level (L) voltage VGL, so the first transistor T1 is turned on. Therefore, since the low-level (L) start pulse SSP is applied to the first node N1 through the first transistor T1, the low-level (L) voltage VGL is applied to the first node N1.

[0238] In addition, the fifteenth transistor T15, the fifth transistor T5, and the seventeenth transistor T17 are turned on by the first clock signal CLK1 at a low level (L).

[0239] Additionally, when the seventeenth transistor T17 is turned on, the voltage VGL applied to the first node N1 is supplied to the third node N3 via the twelfth transistor T12. When the voltage VGL is supplied to the third node N3, the tenth transistor T10 is turned on, so that the voltage VGL is supplied to the output terminal 104.

[0240] Additionally, when voltage VGL is applied to the first node N1, the eighth transistor T8 is turned on. When the eighth transistor T8 is turned on, voltage VGH is supplied to the fourth node N4, and therefore the ninth transistor T9 is turned off.

[0241] When the fifteenth transistor T15 is turned on, voltage VGL is supplied to the sixth node N6 via the fifteenth transistor T15 and the sixteenth transistor T16. When voltage VGL is supplied to the sixth node N6, the fourteenth transistor T14 is turned on, and therefore, the voltage VGL of the low-level (L) start pulse SSP is applied to the third node N3.

[0242] Therefore, the tenth transistor T10 is turned on, and an output signal with the voltage of the first power supply VGL is output to the output terminal 104.

[0243] In the embodiments described herein, the voltage of the third node N3 is reduced to voltage VGL by using the fourteenth transistor T14 and the seventeenth transistor T17, so voltage VGL can be applied to the third node N3 in a short time.

[0244] At the fourth time point t4, the start pulse SSP can be supplied to the first input terminal 101 at a low level (L).

[0245] Additionally, the first clock signal CLK1 can be supplied to the second input terminal 102 at a high level (H). Furthermore, the second clock signal CLK2 can be changed from a high level (H) to a low level (L) and can be supplied to the third input terminal 103 at a low level (L).

[0246] When the high-level (H) first clock signal CLK1 is input to the second input terminal 102, transistors T15, T1, T5 and T17 are set to the off state.

[0247] When the low-level (L) second clock signal CLK2 is supplied to the third input terminal 103, the third transistor T3 remains on by the low-level voltage applied to the sixth node N6 in the previous period. That is, the third transistor T3 remains on by the voltage charged in the third capacitor C3. Therefore, the second clock signal CLK2 input to the third input terminal 103 is applied to the seventh node N7 through the third transistor T3.

[0248] In this case, through the coupling of the third capacitor C3, the voltage of the sixth node N6 can drop to 2-low level (2L).

[0249] In addition, since the fourteenth transistor T14 is connected in the forward direction, the voltage of the third node N3 can drop to a 2-low level (2L) similar to the voltage of the sixth node N6.

[0250] In this case, the voltage difference between the third node N3 and the sixth node N6 via the fourteenth transistor T14 can be as large as the threshold voltage of the fourteenth transistor T14, but this can be ignored.

[0251] As a result, the third node N3 is in a 2-low (2L) state, which makes the tenth transistor T10 fully turned on.

[0252] Therefore, the voltage of the first power supply VGL is output to the output terminal 104 through the tenth transistor T10.

[0253] In fact, the stage STi outputs the output signal to the output terminal 104 while repeating the above process during the drive time.

[0254] In the following text, the period from the fifth time point t5 to the seventh time point T7 is referred to as the holding time. Furthermore, the period from the fifth time point t5 to the sixth time point t6 is referred to as the first holding time, and the period from the sixth time point t6 to the seventh time point t7 is referred to as the second holding time.

[0255] In this case, the hold time is the period during which no output signal is output and the first clock signal CKL1 and the second clock signal CLK2 can be maintained at a high level (H)(VGH) or low level (L)(VGL) voltage without repeated changes.

[0256] During the hold time, the start pulse SSP can be supplied to the first input terminal 101 at a low level (L) (VGL), and the first clock signal CLK1 can be supplied to the second input terminal 102 at a high level (H). In addition, the second clock signal CLK2 can be supplied to the third input terminal 103 at a high level (H).

[0257] During the first hold time t5 to t6, the sixth node N6 maintains a voltage VGL (e.g., VGL+|Vth|) corresponding to the drive time.

[0258] In this case, since the fourteenth transistor T14 is connected by a diode in the direction from the third node N3 to the sixth node N6, current does not flow from the sixth node N6 to the third node N3. Therefore, the voltage of the third node N3 is maintained at a voltage 2VGL with a 2-low level (2L).

[0259] Furthermore, since the seventeenth transistor T17 is turned off during the first holding time t5 to t6, it is possible to prevent the voltage of the third node N3 from rising due to the voltage of the first node N1. That is, the voltage of the third node N3 is maintained at a voltage 2VGL with a 2-low level (2L), and therefore, the tenth transistor T10 is stably maintained in the on state.

[0260] During the second holding time t6 to t7, as the holding time continues, the voltage of the third node N3 gradually increases due to the leakage current of the twelfth transistor T12 and the fourteenth transistor T14.

[0261] In this case, the voltage of the third node N3 increases to the maximum voltage (VGL-|Vth|), and therefore, the tenth transistor T10 can remain on during the hold time.

[0262] More specifically, the tenth transistor T10 acts as a pull-down buffer, resulting in a larger size than the other transistors. Therefore, a relatively large parasitic capacitance can be formed between the gate and source electrodes of the tenth transistor T10. Due to this parasitic capacitance, at the seventh time point t7, the voltage at the third node N3 can converge to the voltage level of VGL-|Vth|.

[0263] As described above, during the second hold time t6 to t7, the voltage at the third node N3 converges to VGL-|Vth|. Therefore, the tenth transistor T10 maintains its gate-on state, and the first power supply VGL can be output to the output terminal 104.

[0264] Therefore, during the second holding time t6 to t7, as the holding time continues, the voltage rise width of the third node N3 caused by the leakage current of the twelfth transistor T12 and the fourteenth transistor T14 can be reduced, and since the tenth transistor T10 is maintained in the gate-on state, the output voltage output to the output terminal 104 can be constantly maintained at a low level (L) voltage VGL.

[0265] Therefore, in the embodiments described herein, even if the first clock signal CLK1 and the second clock signal CLK2 are supplied at a high level during the hold time, the output voltage input to the display unit 100 (e.g., the output voltage Out[1]-Out) can be constantly maintained at a low level (L). In addition, since the clock signals CLK1 and CLK2 are supplied at a high level during the hold time, the power consumption consumed by the display device 1000 can be reduced.

[0266] Figure 8 The diagram is based on Figure 6 A circuit diagram of another example of the level of the embodiment.

[0267] According to this embodiment, in order to reduce the voltage rise width of the third node N3 caused by the leakage current of the twelfth transistor T12 and the fourteenth transistor T14 during the second holding time t6 to t7, such as Figure 8 As shown, a fifth capacitor C5 may be further included, connected between the third node N3 and the first power supply VGL.

[0268] In this case, the fifth capacitor C5 can be charged with the voltage applied to the third node N3. Therefore, the voltage rise width of the third node N3 is reduced, allowing the tenth transistor T10 to stably maintain the on state during the hold time.

[0269] In another embodiment, the voltage of the third node N3 can be periodically initialized to 2VGL+|Vth| by applying clock signals CLK1 and CLK2 that are repeated at least once during the hold time, with high (H) and low (L) levels applied at least once.

[0270] In the following text, reference will be made to Figure 9A and Figure 9B The description includes, according to the embodiments, the following: Figure 4 Another example of a stage in a scan driver circuit diagram and timing diagram.

[0271] Figure 9A The illustration includes, according to another embodiment, Figure 4 A circuit diagram of an example stage in a scan driver. Figure 9B Illustration Figure 9A The timing diagram of the operations at the level.

[0272] Figure 9A The circuit diagram is one of those included in Figure 6 The circuit diagram of an example stage in a scan driver removes the seventeenth transistor T17 and the fourth capacitor C4. In an embodiment, it can be performed with the seventeenth transistor T17 and the fourth capacitor C4 included. Figure 9B The driving method. However, considering layout, etc., it will be assumed and described that the seventeenth transistor T17 and the fourth capacitor C4 are removed, as follows. Figure 9A As shown in the image.

[0273] refer to Figure 9A and Figure 9B A first clock signal CLK1 and a second clock signal CLK2 are supplied at a first frequency during the drive time, and the first clock signal CLK1 and the second clock signal CLK2 are supplied at a second frequency lower than the first frequency during the hold time. For example, the second frequency may be set such that the first clock signal CLK1 and the second clock signal CLK2 repeat a low level and a high level at least once during the hold time.

[0274] exist Figure 9A and Figure 9B The description from the first time point t1 to the sixth time point t6 is consistent with... Figure 6 and Figure 7 The descriptions in these figures are the same, so their redundant descriptions will be omitted for ease of interpretation.

[0275] The retention period can include the period from the fifth time point t5 to the eighth time point t8.

[0276] As mentioned above, since the seventeenth transistor T17 and the fourth capacitor C4 have been removed, the leakage current caused by the twelfth transistor T12 has increased.

[0277] In an additional embodiment, the first clock signal CLK1 and the second clock signal CLK2 repeatedly go low and high at a second frequency. In this case, as described above, the voltage of the sixth node N6 periodically (i.e., when the low-level second clock signal CLK2 is supplied to the third input terminal 103) drops to a voltage of 2VGL.

[0278] When the voltage of the sixth node N6 decreases, the voltage of the third node N3 also periodically decreases to 2VGL+|Vth|, and therefore, the tenth transistor T10 can be stably turned on during the hold time.

[0279] During the third hold time t5 to t6, the start pulse SSP can be supplied to the first input terminal 101 at a low level (L) voltage VGL.

[0280] Additionally, the first clock signal CLK1 can be supplied to the second input terminal 102 at a low level (L). Furthermore, the second clock signal CLK2 can be supplied to the third input terminal 103 at a high level (H).

[0281] Therefore, since the output voltage from the second scan driver 300 to the display unit 100 is maintained at a low level (L) for the first power supply VGL, the increase in power consumption consumed by the display device 1000 can be prevented.

[0282] During the fourth hold time t6 to t7, the start pulse SSP is in a low level (L) state, and the first clock signal CLK1 can be supplied to the second input terminal 102 at a high level (H), then changed to a low level (L), and input to the second input terminal 102 at a low level (L).

[0283] In addition, the second clock signal CLK2 can be supplied to the third input terminal 103 at a low level (L), then changed to a high level (H), and supplied to the third input terminal 103 at a high level (H).

[0284] In this case, such as Figure 6 and Figure 7 As described, since the fourteenth transistor T14 is connected by a diode in the direction from the third node N3 to the sixth node N6, the current does not flow from the sixth node N6 to the third node N3.

[0285] Therefore, the voltage of the third node N3 at the sixth time point t6, which begins from the fourth holding time t6 to t7, can be reduced to 2VGL+|Vth|.

[0286] In this case, such as Figure 6 and Figure 7 During the holding time, leakage current occurs in the twelfth transistor T12 and the fourteenth transistor T14, causing the voltage of the third node N3 to increase.

[0287] Specifically, the voltage of the third node N3 can rise from a voltage of 2VGL with a 2-low level (2L) to a voltage of VGH with a high level (H).

[0288] In this scenario, the tenth transistor T10 acts as a pull-down buffer, resulting in a larger size than the other transistors. Consequently, a relatively large parasitic capacitance can be formed between the gate and source electrodes of the tenth transistor T10. Due to this parasitic capacitance, at the seventh time point t7, the voltage at the third node N3 can converge to VGL-|Vth|.

[0289] Therefore, during the fourth hold time t6 to t7, the voltage at the third node N3 can converge to VGL-|Vth|. Thus, the tenth transistor T10 maintains its gate-on state, and the first power supply VGL can be output to the output terminal 104.

[0290] Therefore, during the fourth hold time t6 to t7, as the hold time continues, the voltage rise width of the third node N3 caused by the leakage current of the twelfth transistor T12 and the fourteenth transistor T14 can be reduced, and since the tenth transistor T10 is maintained in the gate-on state, the output voltage output to the output terminal 104 can be constantly maintained at a low level (L) voltage VGL.

[0291] According to the above method, even if the frequency during the holding time of the first clock signal CLK1 and the second clock signal CLK2 being repeatedly changed to a high-level (H) voltage VGH or a low-level (L) voltage VGL is set to a frequency lower than 120Hz and higher than 60Hz, the voltage of the third node N3 can rise to a low-level (L) voltage VGL-|Vth| instead of rising to a high-level (H) voltage VGH, so that the tenth transistor T10 can maintain the gate conduction state, and the first power supply VGL can be stably output to the output terminal 104.

[0292] Figure 9C The diagram is based on Figure 9A A circuit diagram of another example of the level of the embodiment.

[0293] refer to Figure 9C In each holding time, in order to reduce the voltage rise width of the third node N3 caused by the leakage current of the twelfth transistor T12 and the fourteenth transistor T14, a fifth capacitor C5 connected between the third node N3 and the first power supply VGL may be further included.

[0294] In this case, the fifth capacitor C5 can be charged with the voltage applied to the third node N3. Therefore, the voltage rise width of the third node N3 is reduced, allowing the tenth transistor T10 to stably maintain the on state during the hold time.

[0295] Therefore, by constantly maintaining the output voltage output from the second scan driver 300 and input to the display unit 100, the increase in power consumption consumed by the display device 1000 can be prevented.

[0296] While specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from that description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalents that will be apparent to those skilled in the art.

Claims

1. A scan driver, comprising: Multiple levels are configured to output output signals in response to a clock signal supplied at a first frequency during the drive time of a frame. The plurality of stages are supplied with the clock signal at a second frequency lower than the first frequency during a hold time separate from the drive time of the frame. The clock signal includes a first clock signal and a second clock signal, and Each of the plurality of levels includes: The input section controls the voltage of the first node and the voltage of the second node based on the signals supplied to the first input terminal and the second input terminal; The first signal processing section supplies the voltage of the second power supply to the fourth node based on the voltage of the first node, or electrically connects the second node and the fourth node through the fifth node based on the voltage of the first power supply. A second signal processing section includes a first transistor connected between the third node and the sixth node, and the second signal processing section is connected to the first input terminal, the second input terminal, and the first power supply to control the voltage of the third node based on the operation of the first transistor; and In the output section, the voltage applied to the third node is controlled to be less than or equal to the voltage of the first power supply, and the voltage of the first power supply or the voltage of the second power supply is supplied to the output terminal as a scan signal based on the voltage of the third node and the voltage of the fourth node.

2. The scan driver according to claim 1, wherein, The plurality of levels do not output the output signal during the hold time of the frame, and The clock signal maintains a constant voltage level during the hold time of the frame.

3. The scan driver according to claim 1, wherein, The clock signal repeats low and high voltage levels more than once during the hold time of a frame.

4. The scan driver according to claim 1, wherein, The output section includes: A second transistor is connected between the second power supply and the output terminal, and the gate electrode of the second transistor receives the voltage of the fourth node; and A third transistor is connected between the output terminal and the first power supply, and the gate electrode of the third transistor receives the voltage of the third node.

5. The scan driver according to claim 4, wherein, The input section includes: A fourth transistor is connected between the first input terminal and the first node, and the gate electrode of the fourth transistor is connected to the second input terminal to receive the first clock signal; A fifth transistor is connected between the second input terminal and the second node, and the gate electrode of the fifth transistor receives the voltage from the first node; and A sixth transistor is connected between the second node and the first power supply, and the gate electrode of the sixth transistor is connected to the second input terminal to receive the first clock signal.

6. The scan driver according to claim 5, wherein, The first signal processing section includes: The second capacitor has a first end connected to the fifth node and a second end connected to the first electrode of the eighth transistor; A seventh transistor is connected between the first electrode and the third input terminal of the eighth transistor, and the gate electrode of the seventh transistor receives the voltage of the fifth node; The eighth transistor is connected between the first electrode of the seventh transistor and the fourth node, and the gate electrode of the eighth transistor receives the second clock signal supplied from the third input terminal; A first capacitor has a first end connected to the fourth node and a second end connected to the second power supply; The fourth capacitor has a first terminal connected to the first node and a second terminal connected to the second power supply; A ninth transistor is connected between the fourth node and the second power supply, and the gate electrode of the ninth transistor receives the voltage from the first node; and A tenth transistor is connected between the first node and the second power supply, and the gate electrode of the tenth transistor is connected to the reset input terminal.

7. The scan driver according to claim 6, wherein, The second signal processing section further includes: The eleventh transistor is connected between the first input terminal and the thirteenth transistor, and the gate electrode of the eleventh transistor receives the first clock signal supplied from the second input terminal; The thirteenth transistor is connected between the eleventh transistor and the sixth node, and the gate electrode of the thirteenth transistor receives the voltage of the first power supply. The fourteenth transistor is connected between the third input terminal and the seventh node, and the gate electrode of the fourteenth transistor receives the voltage of the sixth node; A third capacitor has a first end connected to the sixth node and a second end connected to the seventh node; and The fifteenth transistor is connected to the seventh node and the second power supply, and the gate electrode of the fifteenth transistor receives the voltage of the second node.

8. The scan driver according to claim 7, wherein, Each of the plurality of levels further includes: The stabilizing section is electrically connected between the input section and the output section, and limits the voltage drop at the first node and the voltage drop at the second node. The stabilizing component includes: A sixteenth transistor is connected between the second node and the fifth node, and the gate electrode of the sixteenth transistor receives the voltage of the first power supply; A seventeenth transistor is connected between the first node and the eighteenth transistor, and the gate electrode of the seventeenth transistor receives the first clock signal; and The eighteenth transistor is connected between the seventeenth transistor and the third node, and the gate electrode of the eighteenth transistor receives the voltage of the first power supply.

9. The scan driver according to claim 1, wherein, Each of the plurality of levels further includes: The fifth capacitor has a first terminal connected to the third node and a second terminal connected to the first power supply. The fifth capacitor stores the voltage of the third node.

10. The scan driver according to claim 5, wherein, The first signal processing section includes: The second capacitor has a first end connected to the fifth node and a second end connected to the first electrode of the ninth transistor; An eighth transistor is connected between the first electrode and the third input terminal of the ninth transistor, and the gate electrode of the eighth transistor receives the voltage of the fifth node; The ninth transistor is connected between the first electrode of the eighth transistor and the fourth node, and the gate electrode of the ninth transistor receives the second clock signal supplied from the third input terminal; A first capacitor has a first end connected to the fourth node and a second end connected to the second power supply; A tenth transistor is connected between the fourth node and the second power supply, and the gate electrode of the tenth transistor receives the voltage from the first node; and The eleventh transistor is connected between the first node and the second power supply, and the gate electrode of the eleventh transistor is connected to the reset input terminal.

11. The scan driver according to claim 10, wherein, The second signal processing section further includes: The twelfth transistor is connected between the first input terminal and the fourteenth transistor, and the gate electrode of the twelfth transistor receives the first clock signal supplied from the second input terminal; The fourteenth transistor is connected between the twelfth transistor and the sixth node, and the gate electrode of the fourteenth transistor receives the voltage of the first power supply; The fifteenth transistor is connected between the third input terminal and the seventh node, and the gate electrode of the fifteenth transistor receives the voltage of the sixth node; A third capacitor has a first end connected to the sixth node and a second end connected to the seventh node; and A sixteenth transistor is connected between the seventh node and the second power supply, and the gate electrode of the sixteenth transistor receives the voltage of the second node.

12. The scan driver according to claim 11, wherein, Each of the plurality of levels further includes: The stabilizing section is electrically connected between the input section and the output section, and limits the voltage drop of the first node and the voltage drop of the second node.

13. The scan driver according to claim 12, wherein, The stabilizing component includes: A seventeenth transistor is connected between the second node and the fifth node, and the gate electrode of the seventeenth transistor receives the voltage of the first power supply; and An eighteenth transistor is connected between the first node and the third node, and the gate electrode of the eighteenth transistor receives the voltage of the first power supply.

14. The scan driver according to claim 10, wherein, Each of the plurality of levels further includes: The fifth capacitor has a first terminal connected to the third node and a second terminal connected to the first power supply. The fifth capacitor stores the voltage of the third node.

15. A driving method for a scan driver comprising multiple levels, comprising: During the driving time of a frame, the plurality of stages output a plurality of output signals in response to a clock signal supplied at a first frequency; as well as During a hold time separate from the drive time of a frame, the plurality of stages receive the clock signal at a second frequency lower than the first frequency. Each of the plurality of levels includes: The input section controls the voltage of the first node and the voltage of the second node based on the signals supplied to the first input terminal and the second input terminal; The first signal processing section supplies the voltage of the second power supply to the fourth node based on the voltage of the first node, or electrically connects the second node and the fourth node through the fifth node based on the voltage of the first power supply. A second signal processing section includes a first transistor connected between the third node and the sixth node, and the second signal processing section is connected to the first input terminal, the second input terminal, and the first power supply to control the voltage of the third node based on the operation of the first transistor; and In the output section, the voltage applied to the third node is controlled to be less than or equal to the voltage of the first power supply, and the voltage of the first power supply or the voltage of the second power supply is supplied to the output terminal as a scan signal based on the voltage of the third node and the voltage of the fourth node.

16. The driving method of the scan driver according to claim 15, wherein, The plurality of levels do not output the plurality of output signals during the hold time of the frame.

17. The driving method of the scan driver according to claim 15, wherein, The clock signal maintains a constant voltage level during the hold time of the frame.

18. The driving method of the scan driver according to claim 15, wherein, The clock signal repeats low and high voltage levels more than once during the hold time of a frame.

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