Organic light emitting diode display device performing sensing operation

Abstract

An organic light emitting diode (OLED) display apparatus performing a sensing operation includes a display panel including a first area and a second area, and a scan driver including a plurality of first stages and a plurality of second stages coupled to each other. The plurality of first stages is configured to provide a scan signal and a sensing signal to the first area, and the plurality of second stages is configured to provide the scan signal and the sensing signal to the second area. Configurations of the plurality of first stages are different from configurations of the plurality of second stages.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices, and more specifically to organic light-emitting diode (“OLED”) display devices that perform sensing operations. Background Technology

[0002] When an organic light-emitting diode (OLED) display device operates over time, the driving transistors and / or OLEDs of the multiple pixels contained within the OLED display device may degrade over time. To compensate for the degradation of the driving transistors and / or OLEDs, the OLED display device can perform a sensing operation that senses the characteristics of the driving transistors and / or OLEDs of the multiple pixels. However, since conventional OLED display devices perform sensing operations on all pixels contained within the device, performing these sensing operations can require a long sensing time. Summary of the Invention

[0003] Some embodiments provide an organic light-emitting diode (“OLED”) display device capable of efficiently performing sensing operations.

[0004] According to an embodiment, an OLED display device is provided, comprising: a display panel including a first region and a second region; and a scan driver including a plurality of first stages and a plurality of second stages coupled to each other. The plurality of first stages are configured to provide scan signals and sensing signals to the first region, and the plurality of second stages are configured to provide scan signals and sensing signals to the second region. The configuration of the plurality of first stages differs from the configuration of the plurality of second stages.

[0005] In an embodiment, the first region may be a deteriorated and vulnerable region with a relatively high degree of degradation, and the second region may be a normal region with a relatively low degree of degradation.

[0006] In an embodiment, the first region may be the upper region and / or the lower region of the display panel, and the second region may be the middle region between the upper region and the lower region of the display panel.

[0007] In an embodiment, each of the plurality of pixels in the first region and the second region may include: a capacitor including a first electrode coupled to a gate node and a second electrode coupled to a source node; a first transistor that generates a drive current based on a voltage stored in the capacitor; a second transistor that couples a data line to the gate node in response to a corresponding scan signal in a scan signal; a third transistor that couples a sensing line to the source node in response to a corresponding sensing signal in a sensing signal; and an OLED that emits light based on the drive current.

[0008] In the embodiment, during the sensing period of each frame period, the sensing operation of each pixel in the first region can be performed, and the sensing operation of one pixel among the N×M pixels in the second region can be performed, where N is an integer greater than 1 and M is an integer greater than 0.

[0009] In an embodiment, each frame period may include an activation period and a sensing period. During the activation period, multiple first stages and multiple second stages may provide scan signals and sensing signals to all pixel rows in the pixel rows of the first region and all pixel rows in the pixel rows of the second region. During the sensing period, multiple first stages may provide scan signals and sensing signals to all pixel rows in the pixel rows of the first region, and multiple second stages may provide scan signals and sensing signals to only a portion of the pixel rows in the pixel rows of the second region.

[0010] In an embodiment, during a sensing period, multiple second levels can provide scanning signals and sensing signals to one pixel row out of every N pixel rows in the second region, where N is an integer greater than 1.

[0011] In an embodiment, two stages in a plurality of first stages may share a selective sensing input circuit, and 2N stages in a plurality of second stages may share a selective sensing input circuit, where N is an integer greater than 1.

[0012] In an embodiment, each of the plurality of first stages and the plurality of second stages may include: a control node input circuit that transmits a first carry signal to a control node in response to a first carry signal and transmits a low voltage to the control node in response to a next carry signal; an inverter circuit that performs an inversion operation such that the control node and the inverting control node have opposite voltages; a carry output circuit that outputs a carry signal based on the voltage of the control node and a carry clock signal; a sense output circuit that outputs a corresponding sense signal from the sense signals based on the voltage of the control node and a sense clock signal; a scan output circuit that outputs a corresponding scan signal from the scan signals based on the voltage of the control node and a scan clock signal; and a selective sense circuit that transmits a high voltage to the control node based on a sense start signal and the voltage of a selective sense input node. Two of the plurality of first stages may share a selective sense input circuit that provides a second carry signal to the selective sense input nodes of these two stages, and 2N of the plurality of second stages may share a selective sense input circuit that provides a third carry signal to the selective sense input nodes of the 2N stages, where N is an integer greater than 1.

[0013] In an embodiment, two of the plurality of first stages may share a selective sensing input circuit, and the scan driver may further include an extension switch that couples the selective sensing input nodes of the plurality of 2N stages of the plurality of second stages to each other in response to an extension signal, where N is an integer greater than 1, and the plurality of 2N stages of the plurality of second stages may share a selective sensing input circuit through the extension switch.

[0014] In an embodiment, each of the plurality of first stages may include a selective sensing input circuit, and N of the plurality of second stages may share a selective sensing input circuit, where N is an integer greater than 1.

[0015] In an embodiment, each of the plurality of first stages and the plurality of second stages may include: a control node input circuit that transmits a first carry signal to a control node in response to a first carry signal and transmits a low voltage to the control node in response to a next carry signal; an inverter circuit that performs an inversion operation such that the control node and the inverting control node have opposite voltages; a carry output circuit that outputs a carry signal based on the voltage of the control node and a carry clock signal; a sense output circuit that outputs a corresponding sense signal from the sense signals based on the voltage of the control node and a sense clock signal; a scan output circuit that outputs a corresponding scan signal from the scan signals based on the voltage of the control node and a scan clock signal; and a selective sense circuit that transmits a high voltage to the control node based on a sense start signal and the voltage of a selective sense input node. Each of the plurality of first stages may further include a selective sense input circuit that provides a second carry signal to a selective sense input node in the first stage, and the N stages of the plurality of second stages may share a selective sense input circuit that provides a third carry signal to a selective sense input node in the N stages, where N is an integer greater than 1.

[0016] In an embodiment, each of the plurality of first stages may include a selective sensing input circuit, and the scan driver may further include an extension switch that couples the selective sensing input nodes of N stages of the plurality of second stages to each other in response to an extension signal, where N is an integer greater than 1, and the N stages of the plurality of second stages may share a selective sensing input circuit through the extension switch.

[0017] According to an embodiment, an OLED display device is provided, comprising: a display panel including a first region and a second region; and a scan driver including a plurality of first stages and a plurality of second stages coupled to each other. The plurality of first stages are configured to provide scan signals and sensing signals to the first region, and the plurality of second stages are configured to provide scan signals and sensing signals to the second region. Two stages of the plurality of first stages share a selective sensing input circuit, and 2N stages of the plurality of second stages share a selective sensing input circuit, where N is an integer greater than 1.

[0018] In an embodiment, the first region may be a deteriorated and vulnerable region with a relatively high degree of degradation, and the second region may be a normal region with a relatively low degree of degradation.

[0019] In an embodiment, the first region may be the upper region and / or the lower region of the display panel, and the second region may be the middle region between the upper region and the lower region of the display panel.

[0020] In the embodiment, during the sensing period of each frame period, the sensing operation of each pixel in the first region can be performed, and the sensing operation of one pixel among the N×M pixels in the second region can be performed, where N is an integer greater than 1 and M is an integer greater than 0.

[0021] According to an embodiment, an OLED display device is provided, comprising: a display panel including a first region and a second region; and a scan driver including a plurality of first stages and a plurality of second stages coupled to each other. The plurality of first stages are configured to provide scan signals and sensing signals to the first region, and the plurality of second stages are configured to provide scan signals and sensing signals to the second region. Each of the plurality of first stages includes a selective sensing input circuit, and N stages of the plurality of second stages share a single selective sensing input circuit, where N is an integer greater than 1.

[0022] In an embodiment, the first region may be a deteriorated and vulnerable region with a relatively high degree of degradation, and the second region may be a normal region with a relatively low degree of degradation.

[0023] In an embodiment, the first region may be the upper region and / or the lower region of the display panel, and the second region may be the middle region between the upper region and the lower region of the display panel.

[0024] As described above, in the OLED display device according to the embodiments, the configuration of multiple first stages providing scan signals and sensing signals to a first region (e.g., a degraded and vulnerable region) of the display panel can differ from the configuration of multiple second stages providing scan signals and sensing signals to a second region (e.g., a normal region) of the display panel. Therefore, compared to sensing operations in the second region (e.g., the normal region), sensing operations in the first region (e.g., the degraded and vulnerable region) can be performed more finely (or precisely), and the size of the scan driver and the power consumption of the OLED display device can be effectively reduced. Attached Figure Description

[0025] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0026] Figure 1 This is a block diagram illustrating an organic light-emitting diode (OLED) display device according to an embodiment.

[0027] Figure 2 This is a circuit diagram illustrating an example of pixels included in an OLED display device according to an embodiment.

[0028] Figure 3 This is an illustration of an example display panel that includes both deteriorated and vulnerable areas as well as normal areas.

[0029] Figure 4 It is used to describe providing scanning signals and sensing signals to Figure 3 A timing diagram illustrating an example of the operation of the scan driver on the display panel.

[0030] Figure 5 This is a circuit diagram used to describe an example of the operation of each pixel during the active period.

[0031] Figure 6A This is a timing diagram used to describe an example of the sensing operation of a pixel during a sensing period, and Figure 6B This is a circuit diagram used to describe an example of the sensing operation of a pixel during a sensing period.

[0032] Figure 7 This is a block diagram illustrating a scan driver according to an embodiment.

[0033] Figure 8 It is used to describe Figure 7 A timing diagram of an example of the operation of the scan driver.

[0034] Figure 9 This is a circuit diagram illustrating an example of the Lth and L+1th stages included in a scan driver according to an embodiment.

[0035] Figure 10 It is used to describe Figure 9 The timing diagram shows an example of the operations at level L and level L+1.

[0036] Figure 11 This is a block diagram illustrating a scan driver according to another embodiment.

[0037] Figure 12 This is a block diagram illustrating a scan driver according to yet another embodiment.

[0038] Figure 13 This is a block diagram illustrating a scan driver according to another embodiment.

[0039] Figure 14 This is a block diagram illustrating an electronic device including an OLED display device according to an embodiment. Detailed Implementation

[0040] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part without departing from the teachings of this document.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. The singular forms “a” and “the (described)” as used herein are intended to include the plural forms, including “at least one”, unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or “including” as used in this specification indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof. Embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0042] Figure 1 This is a block diagram illustrating an organic light-emitting diode (“OLED”) display device according to an embodiment. Figure 2 This is a circuit diagram illustrating an example of pixels included in an OLED display device according to an embodiment. Figure 3 This is an illustration of an example display panel that includes both deteriorated and vulnerable areas as well as normal areas. Figure 4 It is used to describe providing scanning signals and sensing signals to Figure 3 A timing diagram illustrating an example of the operation of the scan driver for the display panel. Figure 5 This is a circuit diagram used to describe an example of the operation of each pixel during the activation period. Figure 6A This is a timing diagram used to describe an example of the sensing operation of a pixel during a sensing period, and Figure 6B This is a circuit diagram used to describe an example of the sensing operation of a pixel during a sensing period.

[0043] refer to Figure 1 According to an embodiment, the OLED display device 100 may include a display panel 110, a scan driver 120, a data driver 130, a sensor driver 140, and a controller 150.

[0044] Display panel 110 may include multiple data lines DL, multiple sensing lines SL1 and SL2, and multiple pixels PX coupled to the multiple data lines DL and the multiple sensing lines SL1 and SL2. In some embodiments, display panel 110 may further include multiple sensing signal lines for transmitting sensing signals SS to the multiple pixels PX and multiple scanning signal lines for transmitting scanning signals SC to the multiple pixels PX. In some embodiments, each pixel PX may include an organic light-emitting diode (OLED), and display panel 110 may be an OLED display panel.

[0045] In an embodiment, for example, such as Figure 2 As shown, each pixel PX may include a capacitor CST, a first transistor PXT1, a second transistor PXT2, a third transistor PXT3, and an organic light-emitting diode EL.

[0046] The capacitor CST can store the data voltage VDAT transmitted via the data line DL. The capacitor CST can be referred to as a storage capacitor for storing the data voltage VDAT. In some embodiments, the capacitor CST may include a first electrode coupled to the gate node NG and a second electrode coupled to the source node NS.

[0047] The first transistor PXT1 can generate a drive current based on the data voltage VDAT stored in the capacitor CST. The first transistor PXT1 can be referred to as a drive transistor for driving an organic light-emitting diode EL. In some embodiments, the first transistor PXT1 may include a gate coupled to a gate node NG, a drain receiving a first power supply voltage ELVDD (e.g., a high power supply voltage), and a source coupled to a source node NS.

[0048] The second transistor PXT2 can couple the data line DL to the gate node NG in response to the scan signal SC. Therefore, the second transistor PXT2 can transmit the data voltage VDAT or reference voltage VREF received from the data line DL to the gate node NG (i.e., the first electrode of the capacitor CST) in response to the scan signal SC. The second transistor PXT2 can be referred to as a switching transistor or a scan transistor. In some embodiments, the second transistor PXT2 may include a gate for receiving the scan signal SC, a drain coupled to the data line DL, and a source coupled to the gate node NG.

[0049] The third transistor PXT3 can couple the sensing line SL to the source node NS in response to the sensing signal SS. Therefore, the third transistor PXT3 can transmit the initialization voltage VINT of the sensing line SL in response to the sensing signal SS, or it can transmit the voltage or current at the source node NS to the sensing driver 140 via the sensing line SL. The third transistor PXT3 can be referred to as a sensing transistor. In some embodiments, the third transistor PXT3 may include a gate for receiving the sensing signal SS, a drain coupled to the source node NS, and a source coupled to the sensing line SL.

[0050] The organic light-emitting diode (OLED) EL can emit light based on the drive current generated by the first transistor PXT1. In some embodiments, the OLED EL may include an anode coupled to the source node NS and a cathode receiving a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0051] In some embodiments, such as Figure 2 As shown, the first transistor PXT1, the second transistor PXT2, and the third transistor PXT3 can be implemented using, but are not limited to, NMOS transistors. Furthermore, the configuration of the pixel PX according to the embodiment is not limited to... Figure 2 Examples. In other embodiments, the display panel 110 may be an inorganic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a liquid crystal display (“LCD”) panel, or any other suitable display panel.

[0052] The scan driver 120 can provide a scan signal SC and a sensing signal SS to a plurality of pixels PX based on a scan control signal SCTRL received from the controller 150. The scan control signal SCTRL according to the invention may include, but is not limited to, a scan clock signal, a sensing clock signal, and a carry clock signal. In some embodiments, the scan control signal SCTRL may further include a sensing start signal and a sensing end signal for each stage. In some embodiments, the scan driver 120 may be integrated or disposed in a peripheral portion of the display panel 110. In other embodiments, the scan driver 120 may be implemented using one or more integrated circuits.

[0053] Data driver 130 can generate a data voltage VDAT based on output image data ODAT received from controller 150 and a data control signal DCTRL, and can provide the data voltage VDAT to multiple pixels PX via multiple data lines DL. In some embodiments, the data control signal DCTRL according to the invention may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. Furthermore, in some embodiments, data driver 130 can provide a reference voltage VREF via multiple data lines DL during a sensing period. In some embodiments, data driver 130 and sensor driver 140 can be implemented using at least one single integrated circuit, and the single integrated circuit including data driver 130 and sensor driver 140 may be referred to as a readout-source driver integrated circuit (“RSIC”). In other embodiments, data driver 130 and controller 150 can be implemented using at least one single integrated circuit, and the single integrated circuit including data driver 130 and controller 150 may be referred to as a timing controller embedded data driver (“TED”) integrated circuit. In still other embodiments, data driver 130, sensor driver 140, and controller 150 may be implemented using separate integrated circuits.

[0054] The sense driver 140 can be coupled to multiple sense lines SL1 and SL2 of the display panel 110 and can sense characteristics of multiple pixels PX through the multiple sense lines SL1 and SL2, such as the driving characteristics of the first transistor PXT1 of the multiple pixels PX (e.g., threshold voltage VTH and / or mobility). In some embodiments, the sense driver 140 may include one or more precharge switches TPRE that transmit an initialization voltage VINT to the sense lines SL1 and SL2 in response to a precharge signal SPRE, and one or more analog-to-digital converters (ADCs) that convert the characteristics of the multiple pixels PX sensed through the sense lines SL1 and SL2 into digital sensed data. The sense driver 140 can provide the digital sensed data representing the characteristics of the multiple pixels PX to the controller 150. In some embodiments, the sense driver 140 may include one ADC for each sense line SL1 and SL2. In other embodiments, the sense driver 140 may include an analog-to-digital converter (ADC) for every two or more sense lines SL1 and SL2, and the sense driver 140 may further include a shared switch TSHARE that couples one of the two or more sense lines SL1 and SL2 to the ADC. In this case, the sense driver 140 can sense the characteristics of two or more pixels PX coupled to the two or more sense lines SL1 and SL2 in a time-division manner.

[0055] Controller 150 (e.g., a timing controller (“TCON”)) can receive input image data IDAT and control signal CTRL from an external host processor (e.g., a graphics processing unit (“GPU”), application processor (“AP”), or graphics card). In some embodiments, the input image data IDAT may be image data including red image data, green image data, and blue image data. In some embodiments, the control signal CTRL according to the invention may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 150 can receive digital sensing data representing the characteristics of a plurality of pixels PX from sense driver 140, and can generate output image data ODAT by correcting the input image data IDAT based on the digital sensing data. The data voltage VDAT generated based on the output image data ODAT can compensate for the degradation of the plurality of pixels PX or the degradation of the first transistor PXT1 of the plurality of pixels PX. Furthermore, controller 150 can control the operation of scan driver 120 by providing scan control signal SCTRL to scan driver 120, and can control the operation of data driver 130 by providing output image data ODAT and data control signal DCTRL to data driver 130.

[0056] Conventional OLED display devices may perform sensing operations on all pixels, and therefore the sensing operations may require a long sensing time. However, in the OLED display device 100 according to the embodiment, during the sensing period of each frame period, for a first region of the display panel 110, a sensing operation is performed on each pixel PX of the first region, and for a second region of the display panel 110, a sensing operation is performed on one pixel PX among N×M pixels of the second region, where N is an integer greater than 1 and M is an integer greater than 0.

[0057] In some embodiments, the first region targeted by performing a sensing operation on each pixel PX during the sensing period may be a deteriorated and vulnerable region with relatively high degradation, and the second region targeted by performing a sensing operation on one pixel PX out of N×M pixels during the sensing period may be a normal region with relatively low degradation. For example, in the case where the OLED display device 100 is a monitor, a fixed image may be mainly displayed in the upper (or top) or lower (or bottom) region of the display panel 110, and the upper and lower regions may degrade faster than the remaining areas of the display panel 110. Therefore, as Figure 3As shown, the upper and lower regions of the display panel 110 can be degraded and vulnerable regions (DVRs) with relatively high degradation, and the intermediate region between the upper and lower regions of the display panel 110 can be a normal region (NR) with relatively low degradation. In this case, during the sensing period, the OLED display device 100 can perform a sensing operation on each pixel PX for the degraded and vulnerable regions (DVRs) of the display panel 110 (e.g., the upper and / or lower regions). Furthermore, the OLED display device 100 can group multiple pixels PXs into pixel blocks PXBs for the normal region NR (e.g., the intermediate region) of the display panel 110, and can perform a sensing operation on one pixel PX in each pixel block PXB during the sensing period. For example, each pixel block PXB can include N×M pixels PXs located in N pixel rows and M pixel columns, where N is an integer greater than 1 and M is an integer greater than 0.

[0058] In order to perform sensing operations for each pixel PX in the degraded vulnerable area DVR and for each pixel block PXB in the normal area NR, during the sensing period, the scan driver 120 of the OLED display device 100 according to the embodiment can provide scan signals SC and sensing signals SS to all pixel rows in the pixel rows of the degraded vulnerable area DVR, and can also provide scan signals SC and sensing signals SS to a portion of the pixel rows in the pixel rows of the normal area NR. For example, as Figure 4 As shown, each frame period FP of the OLED display device 100 may include an activation period AP and a sensing period SP. In some embodiments, the sensing period SP may correspond to the vertical blank period between the activation periods AP.

[0059] During the active period AP, the scan driver 120 can sequentially provide scan signals SC and sensing signals SS to all pixel rows in the pixel rows of the degraded vulnerable area DVR and all pixel rows in the pixel rows of the normal area NR. For example, if the display panel 110 includes P pixel rows (i.e., the first pixel row to the Pth pixel row), where P is an integer greater than 1, the scan driver 120 can sequentially provide the first scan signals SC1 to the Pth scan signals SCP and the first sensing signals SS1 to the Pth sensing signals SSP to the first pixel row to the Pth pixel row of the display panel 110 on a pixel row basis during the active period AP.

[0060] Figure 5 The illustration shows an example of pixel PX's operation during the active period AP. For example... Figure 5As shown, during the active period AP, the second transistor PXT2 can transmit the data voltage VDAT of the data line DL to the gate node NG in response to the scan signal SC, and the third transistor PXT3 can transmit the initialization voltage VINT (e.g., ground voltage) received from the sensing line SL to the source node NS in response to the sensing signal SS. The capacitor CST can store the data voltage VDAT (or the difference between the data voltage VDAT and the initialization voltage VINT), the first transistor PXT1 can generate a drive current IDR based on the data voltage VDAT stored in the capacitor CST, and the organic light-emitting diode EL can emit light based on the drive current IDR generated by the first transistor PXT1.

[0061] During the sensing period SP, the scan driver 120 can provide scan signals SC1 to SCK and SCP-K+1 to SCP, as well as sensing signals SS1 to SSK and SSP-K+1 to SSP, to all pixel rows in the degraded and vulnerable area DVR. It can also provide scan signals SCK+1, SCK+N+1, ... and sensing signals SSK+1, SSK+N+1, ... to a portion of the pixel rows in the normal area NR. For example, K pixel rows in the upper region and K pixel rows in the lower region of the display panel 110, or the first pixel row to the Kth pixel row and the P-K+1th pixel row to the Pth pixel row, can be the degraded and vulnerable area DVR, where K is an integer greater than 0 and less than or equal to P. During the sensing period SP, the scan driver 120 can sequentially provide the first scan signal SC1 to the Kth scan signal SCK and the first sensing signal SS1 to the Kth sensing signal SSK to the first pixel row to the Kth pixel row on a pixel row basis. It can also sequentially provide the P-K+1 scan signal SCP-K+1 to the Pth scan signal SCP and the P-K+1 sensing signal SSP-K+1 to the Pth sensing signal SSP to the P-K+1 pixel row to the Pth pixel row on a pixel row basis. Furthermore, for the normal area NR of the display panel 110 (i.e., the K+1th pixel row to the PKth pixel row), the scan driver 120 can provide the scan signals SCK+1, SCK+N+1, ... and the sensing signals SSK+1, SSK+N+1, ... to one pixel row every N pixel rows during the sensing period SP, where N is an integer greater than 1. For example, during the sensing period SP, the scan driver 120 may provide only the scan signal SCK+1 and the sensing signal SSK+1 to the pixels in the (K+1)th pixel row from the (K+N)th pixel row to the pixels in the (K+2)th pixel row, and may provide only the scan signal SCK+N+1 and the sensing signal SSK+N+1 to the pixels in the (K+N+1)th pixel row from the (K+2N)th pixel row. Therefore, during the sensing period SP, a sensing operation can be performed on one pixel row of every N pixel rows in the normal region NR, thus effectively reducing the overall sensing time and power consumption of the OLED display device 100. Furthermore, in some embodiments, for the normal region NR, a sensing operation can be performed on one pixel PX of every M consecutive pixels PX in a pixel row. Therefore, a sensing operation can be performed on one pixel PX of each pixel block PXB comprising N×M pixels PX. In this case, the overall sensing time and power consumption of the OLED display device 100 can be effectively reduced.

[0062] Figure 6A The illustration shows an example of the signal / voltage for each pixel PX during the sensing operation performed within the sensing period SP, and Figure 6BThe illustration shows an example of an operation performed on pixel PX during a sensing operation. For example... Figure 6A and Figure 6B As shown, during the sensing period SP, the second power supply voltage ELVSS can be changed from a low voltage level (e.g., approximately 0V) to the voltage level of the first power supply voltage ELVDD. In this case, multiple pixels PX can remain non-illuminating during the sensing period SP. Before the scan signal SC and the sensing signal SS are applied to the pixels PX, the sensing driver 140 can provide an initialization voltage VINT (e.g., approximately 0V) to the sensing line SL in response to the precharge signal SPRE, and can precharge the voltage V_SL of the sensing line SL to the initialization voltage VINT. The data driver 130 can provide a reference voltage VREF as the voltage V_DL of the data line DL. If the scan signal SC and the sensing signal SS are applied to the pixels PX, the second transistor PXT2 can transfer the reference voltage VREF of the data line DL to the gate node NG in response to the scan signal SC, and the third transistor PXT3 can transfer the initialization voltage VINT of the sensing line SL to the source node NS in response to the sensing signal SS. When the scan signal SC and the sensing signal SS are applied to pixel PX, the first transistor PXT1 can be turned on based on the reference voltage VREF at the gate node NG, and the voltage of the source node NS can be increased to a voltage VREF-VTH corresponding to the value obtained by subtracting the threshold voltage VTH of the first transistor PXT1 from the reference voltage VREF. The voltage VREF-VTH of the source node NS can be provided to the sensing driver 140 through the third transistor PXT3 and the sensing line SL, and the sensing driver 140 can sense the threshold voltage VTH of the first transistor PXT1 by measuring the voltage VREF-VTH of the source node NS.

[0063] In order to generate Figure 4The scan signals SC1 to SCP and sensing signals SS1 to SSP shown in the illustration, according to an embodiment, the scan driver 120 of the OLED display device 100 may include a plurality of first stages and a plurality of second stages coupled to each other. The plurality of first stages can provide the scan signals SC1, SC2, ..., SCK and SCP-K+1, SCP-K+2, ..., SCP and the sensing signals SS1, SS2, ..., SSK and SSP-K+1, SSP-K+2, ..., SSP to a first region (e.g., a degraded and vulnerable area DVR), and the plurality of second stages can provide the scan signals SCK+1, SCK+2, ..., SCK+N, SCK+N+1, SCK+N+2, ..., SCK+2N, ... and the sensing signals SSK+1, SSK+2, ..., SSK+N, SSK+N+1, SSK+N+2, ..., SSK+2N, ... to a second region (e.g., a normal area NR). In some embodiments, a configuration that provides scan signals SC1, SC2, ..., SCK and SCP-K+1, SCP-K+2, ..., SCP and sensing signals SS1, SS2, ..., SSK and SSP-K+1, SSP-K+2, ..., SSP to a first region (e.g., a degraded and vulnerable area DVR) at multiple first levels can differ from a configuration that provides scan signals SCK+1, SCK+2, ..., SCK+N, SCK+N+1, ... and sensing signals SSK+1, SSK+2, ..., SSK+N, SSK+N+1, ... to a second region (e.g., a normal area NR). In some embodiments, such as Figure 7 or Figure 11 As shown, two of the multiple first stages can share a single selective sensing input circuit (SSIC) (see [reference]). Figure 9 In one embodiment, each of the plurality of first stages may include a selective sensing input circuit SSIC, and N of the plurality of second stages may share a single selective sensing input circuit SSIC, where N is an integer greater than 1. Therefore, since N or 2N second stages for the normal region NR can share a single selective sensing input circuit SSIC, the size of the scan driver 120 of the OLED display device 100 according to the embodiment can be effectively reduced compared to the size of a scan driver where each stage includes a single selective sensing input circuit.

[0064] As described above, in the OLED display device 100 according to the embodiment, a sensing operation can be performed on each pixel PX of the degraded and vulnerable area DVR, and a sensing operation can be performed on one pixel PX of each pixel block PXB of the normal area NR. Furthermore, in the OLED display device 100 according to the embodiment, the configuration of multiple first levels providing scan signals SC1, SC2, ..., SCK and SCP-K+1, SCP-K+2, ..., SCP and sensing signals SS1, SS2, ..., SSK and SSP-K+1, SSP-K+2, ..., SSP to a first area (e.g., the degraded and vulnerable area DVR) of the display panel 110 can differ from the configuration of multiple second levels providing scan signals SCK+1, SCK+2, ..., SCK+N, SCK+N+1 and sensing signals SSK+1, SSK+2, ..., SSK+N, SSK+N+1 to a second area (e.g., the normal area NR) of the display panel 110. Therefore, in the OLED display device 100 according to the embodiment, the sensing operation of the degraded and vulnerable area DVR can be performed more precisely compared with the sensing operation of the normal area NR, and the size of the scan driver 120 and the power consumption of the OLED display device 100 can be effectively reduced.

[0065] Figure 7 This is a block diagram illustrating a scan driver according to an embodiment. Figure 8 It is used to describe Figure 7 A timing diagram illustrating an example of scan driver operation. Figure 9 This is a circuit diagram illustrating an example of the Lth and L+1th stages included in a scan driver according to an embodiment, and Figure 10 It is used to describe Figure 9 The timing diagram shows an example of the operations at level L and level L+1.

[0066] refer to Figure 7 The scan driver 200 according to an embodiment may include a plurality of first-level STG1, STG2, ... and STGP-K+1, STGP-K+2, ... providing sensing signals SS1, SS2, ... and SSP-K+1, SSP-K+2, ... and scan signals SC1, SC2, ... and SCP-K+1, SCP-K+2, ... to the degraded and vulnerable area DVR of the display panel. The scan driver 200 according to an embodiment may also include a plurality of second-level STGK+1, STGK+2, STGK+3, STGK+4, ... providing scan signals SCK+1, SCK+2, SCK+3, SCK+4, ... and sensing signals SSK+1, SSK+2, SSK+3, SSK+4, ... to the normal area NR of the display panel.

[0067] Two stages among the multiple first-stage STG1, STG2, ... and STGP-K+1, STGP-K+2, ... used for degrading vulnerable areas of the DVR can share a single selective sensing input circuit SSIC. For example, the first-stage STG1 and the second-stage STG2 used for degrading vulnerable areas of the DVR can share a selective sensing input circuit 210, and the P-K+1 stage STGP-K+1 and the P-K+2 stage STGP-K+2 used for degrading vulnerable areas of the DVR can share a selective sensing input circuit 250. Furthermore, 2N (e.g., four) stages among the multiple second-stage STGK+1, STGK+2, STGK+3, STGK+4, ... used for normal areas of the NR can share a single selective sensing input circuit SSIC. For example, the K+1 stage STGK+1, the K+2 stage STGK+2, the K+3 stage STGK+3, and the K+4 stage STGK+4 used for normal areas of the NR can share a selective sensing input circuit 230. Therefore, the size of the scan driver 200 can be effectively reduced compared to the size of a scan driver in which each stage includes a selective sensing input circuit SSIC.

[0068] Multiple first and second stage STG1, STG2, ..., STGK+1, STGK+2, STGK+3, STGK+4, ..., STGP-K+1, STGP-K+2, ... can receive one or more sensing clock signals SS_CK1, SS_CK2, SS_CK3 and SS_CK4, one or more scan clock signals SC_CK1, SC_CK2, SC_CK3 and SC_CK4, and one or more carry clock signals CR_CK1, CR_CK2, CR_CK3 and CR_CK4. Multiple first and second level STG1, STG2, ..., STGK+1, STGK+2, STGK+3, STGK+4, ..., STGP-K+1, STGP-K+2, ... can further receive corresponding previous carry signals PCR_STG1, PCR_STG2, ..., PCR_STGK+1, PCR_STGK+2, PCR_STGK+3, PCR_STGK+4, ..., PCR_STGP-K+1, PCR_STGP-K+2, ... (or scan start signal). Each stage (e.g., STG1) can generate a carry signal (e.g., CR1) based on a previous carry signal (e.g., PCR_STG1) and a carry clock signal (e.g., CR_CK1), generate a sense signal (e.g., SS1) based on a previous carry signal (e.g., PCR_STG1) and a sense clock signal (e.g., SS_CK1), and generate a scan signal (e.g., SC1) based on a previous carry signal (e.g., PCR_STG1) and a scan clock signal (e.g., SC_CK1).

[0069] In addition, multiple first and second level STG1, STG2, ..., STGK+1, STGK+2, STGK+3, STGK+4, ..., STGP-K+1, STGP-K+2, ... can respectively receive the corresponding sensing start signals SSTA1, SSTA2, ..., SSTAK+1, SSTAK+2, SSTAK+3, SSTAK+4, ..., SSTAP-K+1, SSTAP-K+2, ... and the corresponding sensing end signals SEND1, SEND2, ..., SENDK+1, SENDK+2, SENDK+3, SENDK+4, ..., SENDP-K+1, SENDP-K+2, ... During the sensing period, each level (e.g., STG1) can generate a sensing signal (e.g., SS1) and a scan signal (e.g., SC1) based on a sensing clock signal (e.g., SS_CK1) and a scan clock signal (e.g., SC_CK1) during the period from the time point when the sensing start signal (e.g., SSTA1) is applied to the time point when the sensing end signal SEND1 is applied.

[0070] In an embodiment, for example, such as Figure 8 As shown, the sensing clock signals SS_CK1, SS_CK2, ... and the scan clock signals SC_CK1, SC_CK2, ... can be periodically switched within the active period AP and sensing period SP of each frame time period FP. The carry clock signals CR_CK1, CR_CK2, ... can be periodically switched within the active period AP of each frame time period FP, and the carry clock signals CR_CK1, CR_CK2, ... can have a substantially constant level, for example, a low level, within the sensing period SP of each frame time period FP.

[0071] During the active period AP, multiple first-level STG1, STG2, ... and STGP-K+1, STGP-K+2, ... used for degrading vulnerable areas of the DVR, and multiple second-level STGK+1, STGK+2, STGK+3, STGK+4, ... used for normal areas of the NR, can sequentially generate sensing signals SS1, SS2, ..., SSK+1, SSK+2, SSK+3, SSK+4, ..., scanning signals SC1, SC2, ..., SCK+1, SCK+2, SCK+3, SCK+4, ..., and carry signals CR1, CR2, ..., CRK+1, CRK+2, CRK+3, CRK+4, ..., CRP-K+1, CRP-K+2, ... based on sensing clock signals SS_CK1, SS_CK2, ..., scan clock signals SC_CK1, SC_CK2, ..., and carry clock signals CR_CK1, CR_CK2, ..., respectively. Multiple first-level STG1, STG2, ... and STGP-K+1, STGP-K+2, ... and multiple second-level STGK+1, STGK+2, STGK+3, STGK+4, ... can sequentially provide sensing signals SS1, SS2, ..., SSK+1, SSK+2, SSK+3, SSK+4, ... and scanning signals SC1, SC2, ..., SCK+1, SCK+2, SCK+3, SCK+4, ... to all pixel rows in the degraded and vulnerable area DVR and all pixel rows in the normal area NR during the active period AP.

[0072] During the sensing period SP, multiple first-level STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for degrading vulnerable areas of the DVR can provide sensing signals SS1, SS2, ... and scan signals SC1, SC2, ... to all pixel rows in the pixel rows of the degraded vulnerable area DVR. Multiple second-level STGK+1, STGK+2, STGK+3, STGK+4, ... for normal areas of the NR can provide sensing signals SSK+1, ... and scan signals SCK+1, ... to a portion of the pixel rows in the pixel rows of the normal area of ​​the NR during the sensing period SP.

[0073] In an embodiment, for example, stage STG1 among the plurality of first-stage STG1, STG2, ... and STGP-K+1, STGP-K+2, ... used for degrading vulnerable area DVRs can generate a first sensing signal SS1 and a first scan signal SC1 based on a first sensing clock signal SS_CK1 and a first scan clock signal SC_CK1 during the time period from the time point when the first sensing start signal SSTA1 is applied to the time point when the first sensing end signal SEND1 is applied. Stage STG2 among the plurality of first-stage STG1, STG2, ... and STGP-K+1, STGP-K+2, ... used for degrading vulnerable area DVRs can also generate a second sensing signal SS2 and a second scan signal SC2 based on a second sensing clock signal SS_CK2 and a second scan clock signal SC_CK2 during the time period from the time point when the second sensing start signal SSTA2 is applied to the time point when the second sensing end signal SEND2 is applied. Although Figure 8 The illustration shows an example in which the first sensing start signal SSTA1 and the second sensing start signal SSTA2 have substantially the same timing, and the first sensing end signal SEND1 and the second sensing end signal SEND2 have substantially the same timing. However, the timing of the sensing start signals and sensing end signals SSTA1, SSTA2, SEND1, and SEND2 according to the present invention may not be limited to these specific timings. Figure 8 Examples.

[0074] Conversely, in an embodiment, for example, for a plurality of second-level STGK+1, STGK+2, STGK+3, STGK+4, ... for the normal region NR, only one of the sensing start signals SSTAK+1, SSTAK+2, SSTAK+3, and SSTAK+4 and only one of the sensing end signals SENDK+1, SENDK+2, SENDK+3, and SENDK+4 among the 2N (e.g., four) levels of STGK+1, STGK+2, STGK+3, and STGK+4 can have a pulse during the sensing period SP, and the remaining sensing start signals SSTAK+2, SSTAK+3, and SSTAK+4 and the remaining sensing end signals SENDK+2, SENDK+3, and SENDK+4 can be simultaneously held at a low level LOW. Therefore, among the four stages STGK+1, STGK+2, STGK+3, and STGK+4, stage STGK+1 can generate the corresponding sensing signal SSK+1 and the corresponding scan signal SCK+1 based on the corresponding sensing clock signal SS_CK1 and the corresponding scan clock signal SC_CK1 during the time period from the time point when the corresponding sensing start signal SSTAK+1 is applied to the time point when the corresponding sensing end signal SENDK+1 is applied. However, the remaining stages STGK+2, STGK+3, and STGK+4 may not generate the corresponding sensing signals SSK+2, SSK+3, and SSK+4 and the corresponding scan signals SCK+2, SCK+3, and SCK+4. Therefore, during the sensing period SP, sensing operations can be performed on one pixel row of every four pixel rows in the normal region NR, thus effectively reducing the overall sensing time and power consumption. In some embodiments, one of the four levels STGK+1, STGK+2, STGK+3, and STGK+4 that generates the corresponding sensing signal and the corresponding scanning signal during the sensing period SP can be changed according to each frame period FP.

[0075] To perform these operations, in some embodiments, such as Figure 9 As shown, each of the multiple first-stage STG1, STG2, ... and STGP-K+1, STGP-K+2, ... and multiple second-stage STGK+1, STGK+2, STGK+3, STGK+4, ... may include a control node input circuit CNIC, an inverter circuit INVC, a carry output circuit CROC, a sensing output circuit SSOC, a scan output circuit SCOC, and a selective sensing circuit SSC. At least two stages STGL and STGL+1 may share or include a selective sensing input circuit SSIC. Figure 9The levels STGL and STGL+1 can be two consecutive levels from multiple first levels STG1, STG2, ... and STGP-K+1, STGP-K+2, ... used for deteriorating vulnerable areas of the DVR, or they can be two consecutive levels from multiple second levels STGK+1, STGK+2, STGK+3, STGK+4, ... used for normal areas of the NR.

[0076] The control node input circuit (CNIC) can transmit a previous carry signal (e.g., the first previous carry signal PCR1 or the third previous carry signal PCR3) to the control node NQL (or NQL+1) in response to a previous carry signal (e.g., the first previous carry signal PCR1 or the third previous carry signal PCR3), and can transmit a low voltage VSS1 (e.g., the first low voltage) to the control node NQL (or NQL+1) in response to a next carry signal NCR1 (or NCR2). For example, the first previous carry signal PCR1 of the Lth stage STGL according to the present invention can be, but is not limited to, the carry signal of the L-3rd stage; the next carry signal NCR1 of the Lth stage STGL can be, but is not limited to, the carry signal of the L+4th stage; the previous carry signal (the third previous carry signal PCR3) of the L+1st stage STGL+1 according to the present invention can be, but is not limited to, the carry signal of the L-2nd stage; and the next carry signal NCR2 of the L+1st stage STGL+1 can be, but is not limited to, the carry signal of the L+5th stage.

[0077] In some embodiments, such as Figure 9 As shown, the control node input circuit CNIC of the Lth stage STGL may include fourth transistors T4-1 and T4-2 that transmit the first carry signal PCR1 to the control node NQL in response to the first carry signal PCR1, fifth transistors T5-1 and T5-2 that transmit the low voltage VSS1 to the control node NQL in response to the next carry signal NCR1, and sixth transistors T6-1 and T6-2 that transmit the low voltage VSS1 to the control node NQL in response to the second control signal CS2. In some embodiments, each of the fourth transistors T4-1 and T4-2, the fifth transistors T5-1 and T5-2, and the sixth transistors T6-1 and T6-2 may be implemented using a dual transistor comprising two sub-transistors, and the control node input circuit CNIC of the Lth stage STGL may further include seventh transistors T7-1 and T7-2 that transmit the high voltage VGH (e.g., high gate voltage) to the node between these sub-transistors in response to the voltage of the control node NQL. In some embodiments, the seventh transistors T7-1 and T7-2 can also be implemented using a dual transistor comprising two sub-transistors.

[0078] The inverter circuit INVC performs an inversion operation, causing the control node NQL (or NQL+1) and the inverting control node NQBL (or NQBL+1) to have opposite voltages. Therefore, the inverter circuit INVC of stage L STGL allows the inverting control node NQBL to have a low voltage when control node NQL has a high voltage, and also allows control node NQL to have a low voltage when inverting control node NQBL has a high voltage. Furthermore, the inverter circuit INVC of stage L+1 STGL+1 allows the inverting control node NQBL+1 to have a low voltage when control node NQL+1 has a high voltage, and also allows control node NQL+1 to have a low voltage when inverting control node NQBL+1 has a high voltage.

[0079] In some embodiments, such as Figure 9 As shown, the inverter circuit INVC of the Lth stage STGL may include eighth transistors T8-1 and T8-2 that transmit a low voltage VSS1 to the control node NQL in response to the voltage of the inverting control node NQBL, and a ninth transistor T9 that transmits a low voltage VSS1 to the inverting control node NQBL in response to the voltage of the control node NQL. In some embodiments, the inverter circuit INVC of the Lth stage STGL may further include tenth transistors T10-1 and T10-2 that transmit a low voltage VSS1 to the control node NQL in response to the voltage of the inverting control node NQBL+1 of the (L+1)th stage STGL+1, and an eleventh transistor T11 that transmits a low voltage VSS1 to the inverting control node NQBL in response to the first carry signal PCR1. In some embodiments, each of the eighth transistors T8-1 and T8-2 and the tenth transistors T10-1 and T10-2 may be implemented using a dual transistor comprising two sub-transistors. In some embodiments, the inverter circuit INVC of the Lth stage STGL may further include a twelfth transistor T12-1 and T12-2, a thirteenth transistor T13, a fourteenth transistor T14, which is turned on in response to a voltage of the control node NQL, and a fifteenth transistor T15, which is turned on in response to a voltage of the control node NQL+1 of the L+1th stage STGL+1. The thirteenth transistor T13 may be turned off based on a low voltage VSS2 (e.g., a second low voltage) applied to the gate of the thirteenth transistor T13 when the fifteenth transistor T15 is turned on, and may deliver the high voltage VGH to the inverting control node NQBL when both the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0080] The carry output circuit CROC can output a carry signal CRL (or CRL+1) based on the voltage of the control node NQL (or NQL+1) and the carry clock signal CR_CK1 (or CR_CK2). Therefore, the carry output circuit CROC of the Lth stage STGL can output the carry signal CRL when the control node NQL has a high voltage and the carry clock signal CR_CK1 has a high voltage. The carry output circuit CROC of the (L+1)th stage STGL+1 can output the carry signal CRL+1 when the control node NQL+1 has a high voltage and the carry clock signal CR_CK2 has a high voltage.

[0081] In some embodiments, such as Figure 9 As shown, the carry output circuit CROC of the Lth stage STGL may include a sixteenth transistor T16 that outputs a carry clock signal CR_CK1 as a carry signal CRL based on the voltage of the control node NQL and the carry clock signal CR_CK1, and a first capacitor C1 for bootstrapping operation. The carry output circuit CROC of the Lth stage STGL may also include a seventeenth transistor T17 that outputs a low voltage VSS1 as a carry signal CRL in response to the voltage of the inverting control node NQBL+1 of the L+1th stage STGL+1, and an eighteenth transistor T18 that outputs a low voltage VSS1 as a carry signal CRL in response to the voltage of the inverting control node NQBL.

[0082] The sensing output circuit SSOC can output a sensing signal SSL (or SSL+1) based on the voltage of the control node NQL (or NQL+1) and the sensing clock signal SS_CK1 (or SS_CK2). Therefore, the sensing output circuit SSOC of the Lth stage STGL can output the sensing signal SSL when the control node NQL has a high voltage and the sensing clock signal SS_CK1 has a high voltage, and the sensing output circuit SSOC of the (L+1)th stage STGL+1 can output the sensing signal SSL+1 when the control node NQL+1 has a high voltage and the sensing clock signal SS_CK2 has a high voltage.

[0083] In some embodiments, such as Figure 9As shown, the sensing output circuit SSOC of the Lth stage STGL may include a nineteenth transistor T19 that outputs a sensing clock signal SS_CK1 as a sensing signal SSL based on the voltage of the control node NQL and the sensing clock signal SS_CK1, and a second capacitor C2 for bootstrapping operation. The sensing output circuit SSOC of the Lth stage STGL may also include a twentieth transistor T20 that outputs a low voltage VSS3 (e.g., a third low voltage) as a sensing signal SSL in response to the voltage of the inverting control node NQBL+1 of the L+1 stage STGL+1, and a twenty-first transistor T21 that outputs a low voltage VSS3 as a sensing signal SSL in response to the voltage of the inverting control node NQBL.

[0084] The scan output circuit SCOC can output the scan signal SCL (or SCL+1) based on the voltage of the control node NQL (or NQL+1) and the scan clock signal SC_CK1 (or SC_CK2). Therefore, the scan output circuit SCOC of the Lth stage STGL can output the scan signal SCL when the control node NQL has a high voltage and the scan clock signal SC_CK1 has a high voltage, and the scan output circuit SCOC of the (L+1)th stage STGL+1 can output the scan signal SCL+1 when the control node NQL+1 has a high voltage and the scan clock signal SC_CK2 has a high voltage.

[0085] In some embodiments, such as Figure 9 As shown, the scan output circuit SCOC of the Lth stage STGL may include a twenty-second transistor T22 that outputs the scan clock signal SC_CK1 as the scan signal SCL based on the voltage of the control node NQL and the scan clock signal SC_CK1, and a third capacitor C3 for bootstrapping operation. The scan output circuit SCOC of the Lth stage STGL may also include a twenty-third transistor T23 that outputs a low voltage VSS3 as the scan signal SCL in response to the voltage of the inverting control node NQBL+1 of the L+1 stage STGL+1, and a twenty-fourth transistor T24 that outputs a low voltage VSS3 as the scan signal SCL in response to the voltage of the inverting control node NQBL.

[0086] The selective sensing circuit SSC can transmit a high voltage VGH to the control node NQL (or NQL+1) based on the voltage of the selective sensing input node NSSIL (or NSSIL+1) and the sensing start signal SSTAL (or SSTAL+1). Furthermore, the selective sensing circuit SSC can transmit a low voltage VSS1 to the control node NQL (or NQL+1) based on the voltage of the selective sensing input node NSSIL (or NSSIL+1) and the sensing end signal SEND. For example... Figure 9As shown, the selective sensing input node NSSIL of the Lth stage STGL and the selective sensing input node NSSIL+1 of the (L+1)th stage STGL+1 can be coupled to each other. In some embodiments, the same sensing end signal SEND can be applied to the selective sensing circuit SSC of the Lth stage STGL and the selective sensing circuit SSC of the (L+1)th stage STGL+1.

[0087] In some embodiments, such as Figure 9 As shown, the selective sensing circuit SSC of the L-th stage STGL may include a twenty-fifth transistor T25 that is turned on in response to the voltage of the selective sensing input node NSSIL, a fourth capacitor C4 coupled between the line of high voltage VGH and the selective sensing input node NSSIL, and a twenty-sixth transistor T26 that is turned on in response to the sensing start signal SSTAL. The twenty-fifth transistor T25 and the twenty-sixth transistor T26 can transmit the high voltage VGH to the control node NQL when both the selective sensing input node NSSIL and the sensing start signal SSTAL are high. The selective sensing circuit SSC of the L-th stage STGL may further include a twenty-seventh transistor T27 that is turned on in response to the voltage of the selective sensing input node NSSIL and a twenty-eighth transistor T28 that is turned on in response to the sensing start signal SSTAL. The twenty-seventh transistor T27 and the twenty-eighth transistor T28 can transmit the low voltage VSS1 to the inverting control node NQBL when both the selective sensing input node NSSIL and the sensing start signal SSTAL are high. In some embodiments, the selective sensing circuit SSC of the Lth stage STGL may further include a twenty-ninth transistor T29 and a thirty-first transistor T31 that are turned on in response to a sensing end signal SEND, and a thirtieth transistor T30 that is turned on in response to the voltage of the selective sensing input node NSSIL. The twenty-seventh transistor T27, the twenty-ninth transistor T29, the thirtieth transistor T30, and the thirty-first transistor T31 may transmit a low voltage VSS1 to the control node NQL when the selective sensing input node NSSIL has a high voltage and the sensing end signal SEND has a high voltage.

[0088] The selective sensing input circuit SSIC can provide a second carry signal PCR2 to the selective sensing input nodes NSSIL and NSSIL+1 of the L-th stage STGL and the (L+1)-th stage STGL+1 in response to a first control signal CS1. In some embodiments, the second carry signal PCR2 according to the invention can be, but is not limited to, a carry signal of the (L-2)-th stage. In the scan driver 200 according to an embodiment, two stages (e.g., STG1 and STG2, or STGP-K+1 and STGP-K+2, ...) of a plurality of first stages STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for degrading vulnerable area DVRs can share or include a selective sensing input circuit SSIC that provides the second carry signal PCR2 to the selective sensing input nodes (e.g., NSSI1 and NSSI2, or NSSIP-K+1 and NSSIP-K+2) in these two stages. In the scan driver 200, 2N (e.g., four) levels (e.g., STGK+1, STGK+2, STGK+3, STGK+4, ...) of the multiple second-level STGK+1, STGK+2, STGK+3, STGK+4, ... for the normal region NR may share or include a selective sensing input circuit SSIC that provides the previous carry signal to the selective sensing input nodes (e.g., NSSIK+1, NSSIK+2, NSSIK+3, and NSSIK+4) in the 2N levels.

[0089] In some embodiments, such as Figure 9 As shown, the selective sensing input circuit SSIC may include a first transistor T1 and a second transistor T2 that are turned on in response to a first control signal CS1, and a third transistor T3 that applies a high voltage VGH to the node between the first transistor T1 and the second transistor T2 in response to the voltage of the selective sensing input node NSSIL.

[0090] In the following text, reference will be made to Figure 9 and Figure 10 To describe the operations of STGL at level L and STGL+1 at level L+1.

[0091] The sensing clock signals SS_CK1 and SS_CK2, and the scan clock signals SC_CK1 and SC_CK2, can be periodically switched within the active period AP and sensing period SP of each frame time period FP. The carry clock signals CR_CK1 and CR_CK2 can be periodically switched within the active period AP of each frame time period FP, and can have a substantially constant level, e.g., a low level, within the sensing period SP of each frame time period FP. In some embodiments, the second control signal CS2 can be applied to the Lth stage STGL and the (L+1)th stage STGL+1 at the start or end time of the frame time period FP. The control node input circuit CNIC of the Lth stage STGL can apply a low voltage VSS1 to the control node NQL in response to the second control signal CS2, and the control node input circuit CNIC of the (L+1)th stage STGL+1 can apply a low voltage VSS1 to the control node NQL+1 in response to the second control signal CS2.

[0092] During the first time period TM1 of the active period AP, a first carry signal PCR1 (e.g., the carry signal of level L-3) can be applied. The control node input circuit CNIC of level L STGL can transmit the first carry signal PCR1 to the control node NQL, and the control node NQL can have a high voltage.

[0093] During the second time period TM2 of the active period AP, the second / third carry signals PCR2 / PCR3 (e.g., carry signals of the (L-2)th stage) can be applied. The control node input circuit CNIC of the (L+1)th stage STGL+1 can transmit the third carry signal PCR3 to the control node NQL+1, and the control node NQL+1 can have a high voltage. Furthermore, during the second time period TM2, the first control signal CS1 can be applied, and the selective sensing input circuit SSIC can, in response to the first control signal CS1, transmit the second carry signal PCR2 to the selective sensing input nodes NSSIL and NSSIL+1, and the selective sensing input nodes NSSIL and NSSIL+1 can have a high voltage.

[0094] During the third time period TM3 of the active period AP, the first sensing clock signal SS_CK1, the first scan clock signal SC_CK1, and the first carry clock signal CR_CK1 can be applied. The voltage of the control node NQL in the L-th stage STGL can be bootstrapped by the first capacitor C1, the second capacitor C2, and / or the third capacitor C3. The carry output circuit CROC of the L-th stage STGL can output the carry signal CRL based on the bootstrap voltage, the sensing output circuit SSOC of the L-th stage STGL can output the sensing signal SSL based on the bootstrap voltage, and the scan output circuit SCOC of the L-th stage STGL can output the scan signal SCL based on the bootstrap voltage.

[0095] During the fourth time period TM4 of the active period AP, the second sensing clock signal SS_CK2, the second scan clock signal SC_CK2, and the second carry clock signal CR_CK2 can be applied. The voltage of the control node NQL+1 in stage L+1 STGL+1 can be bootstrapped. The carry output circuit CROC of stage L+1 STGL+1 can output the carry signal CRL+1 based on the bootstrap voltage, the sensing output circuit SSOC of stage L+1 STGL+1 can output the sensing signal SSL+1 based on the bootstrap voltage, and the scan output circuit SCOC of stage L+1 STGL+1 can output the scan signal SCL+1 based on the bootstrap voltage.

[0096] During the fifth time period TM5 of the sensing period SP, the sensing start signal SSTAL can be applied to the Lth stage STGL. The selective sensing circuit SSC of the Lth stage STGL can transmit a high voltage VGH to the control node NQL in response to the high voltage of the selective sensing input node NSSIL and the sensing start signal SSTAL.

[0097] During the sixth time period TM6 of the sensing period SP, the first sensing clock signal SS_CK1 and the first scan clock signal SC_CK1 can be applied. The voltage of the control node NQL in the L-th stage STGL can be bootstrapped by the second capacitor C2 and / or the third capacitor C3. The sensing output circuit SSOC of the L-th stage STGL can output the sensing signal SSL based on the bootstrap voltage, and the scan output circuit SCOC of the L-th stage STGL can output the scan signal SCL based on the bootstrap voltage.

[0098] In some embodiments, when the Lth level STGL and the L+1th level STGL+1 are levels used for the normal region NR, the sensing start signal SSTAL+1 may not be applied to the L+1th level STGL+1, and the L+1th level STGL+1 may not output the sensing signal SSL+1 and the scan signal SCL+1 during the sensing period SP.

[0099] In other embodiments, where the Lth stage STGL and the (L+1)th stage STGL+1 are stages used to degrade the vulnerable region DVR, the sensing start signal SSTAL+1 can be applied to the (L+1)th stage STGL+1 during the sixth time TM6. The selective sensing circuit SSC of the (L+1)th stage STGL+1 can transmit a high voltage VGH to the control node NQL+1 in response to the high voltage of the selective sensing input node NSSIL+1 and the sensing start signal SSTAL+1. Subsequently, during the seventh time TM7, the second sensing clock signal SS_CK2 and the second scan clock signal SC_CK2 can be applied, and the voltage of the control node NQL+1 in the (L+1)th stage STGL+1 can be bootstrapped. The sensing output circuit SSOC of the (L+1)th stage STGL+1 can output the sensing signal SSL+1 based on the bootstrap voltage, and the scan output circuit SCOC of the (L+1)th stage STGL+1 can output the scan signal SCL+1 based on the bootstrap voltage.

[0100] During the eighth time TM8 of the sensing period SP, the sensing end signal SEND can be applied. The selective sensing circuit SSC of stage L STGL and stage L+1 STGL+1 can transmit a low voltage VSS1 to the control nodes NQL and NQL+1 in response to the high voltage of the selective sensing input nodes NSSIL and NSSIL+1 and the sensing end signal SEND.

[0101] During the ninth time TM9 of the sensing period SP, the first control signal CS1 may be applied again, for example, at the end of the sensing period SP. The selective sensing input circuit SSIC may, in response to the first control signal CS1, transmit a second carry signal PCR2 with a low voltage to the selective sensing input nodes NSSIL and NSSIL+1, and the selective sensing input nodes NSSIL and NSSIL+1 may be initialized to a low voltage.

[0102] In this manner, stage L STGL and stage L+1 STGL+1 can sequentially output carry signals CRL and CRL+1, sensing signals SSL and SSL+1, and scan signals SCL and SCL+1 during the active period AP. When stage L STGL and stage L+1 STGL+1 are stages used for the normal region NR, only one stage STGL of stage L STGL and stage L+1 STGL+1 can output the sensing signal SSL and the scan signal SCL during the sensing period SP. Furthermore, when stage L STGL and stage L+1 STGL+1 are stages used for the degraded vulnerable region DVR, stage L STGL and stage L+1 STGL+1 can sequentially output the sensing signals SSL and SSL+1 and the scan signals SCL and SCL+1 during the sensing period SP.

[0103] As described above, in the scan driver 200 according to the embodiment, two stages (e.g., STG1 and STG2) among the plurality of first stages STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for degrading the vulnerable area DVR can share a single selective sensing input circuit SSIC. In the scan driver 200 according to the embodiment, 2N stages (e.g., STGK+1, STGK+2, STGK+3, STGK+4, ...) among the plurality of second stages STGK+1, STGK+2, STGK+3, STGK+4 for the normal area NR can share a single selective sensing input circuit SSIC. Therefore, compared to sensing operations for the normal area NR, sensing operations for degrading the vulnerable area DVR can be performed more finely (or precisely), and the size and power consumption of the scan driver 200 can be effectively reduced.

[0104] Figure 11 This is a block diagram illustrating a scan driver according to another embodiment.

[0105] refer to Figure 11 According to the embodiment, the scan driver 300 may include a plurality of first-level STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for the deteriorated and vulnerable area DVR of the display panel, a plurality of second-level STGK+1, STGK+2, STGK+3, STGK+4, ... for the normal area NR of the display panel, and at least one extended switch TEXT. Figure 11 The scan driver 300 can have the same as Figure 7 The scan driver 200 has a similar configuration and similar operation, except that the scan driver 300 may further include an extension switch TEXT.

[0106] Two of the multiple first-stage STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for degrading vulnerable areas of the DVR (e.g., STG1 and STG2, or STGP-K+1 and STGP-K+2) can share a selective sensing input circuit (e.g., 310 or 350) coupled to the selective sensing input nodes (e.g., NSSI1 and NSSI2, or NSSIP-K+1 and NSSIP-K+2) in these two stages.

[0107] 2N stages (e.g., STGK+1, STGK+2, STGK+3, STGK+4, ...) for the normal region NR can share a single selective sensing input circuit (e.g., 330) coupled to the selective sensing input nodes (e.g., NSSIK+1, NSSIK+2, NSSIK+3, and NSSIK+4) in these 2N stages via an extension switch TEXT. This effectively reduces the size and power consumption of the scan driver 300. In some embodiments, the extension switch TEXT can selectively couple the selective sensing input nodes (e.g., NSSIK+1, NSSIK+2, NSSIK+3, and NSSIK+4) of these 2N stages to each other in response to the extension signal SEXT.

[0108] Figure 12 This is a block diagram illustrating a scan driver according to yet another embodiment.

[0109] refer to Figure 12 According to the embodiment, the scan driver 400 may include a plurality of first-level STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for the deteriorated and vulnerable area DVR of the display panel, and a plurality of second-level STGK+1, STGK+2, STGK+3, STGK+4, ... for the normal area NR of the display panel. Figure 12 The scan driver 400 can have with Figure 7 The scan driver 200 has a similar configuration and similar operation, except that each of the multiple first-stage STG1, STG2, ... and STGP-K+1, STGP-K+2, ... may include a selective sensing input circuit 410, 420, 440 or 450.

[0110] Each of the multiple first-stage STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for the DVR used to degrade vulnerable areas may include a selective sensing input circuit 410, 420, 440, or 450. The N stages (e.g., STGK+1, STGK+2, STGK+3, STGK+4, ...) of the multiple second-stage STGK+1, STGK+2, STGK+3, STGK+4 for the normal area NR may share or include a single selective sensing input circuit (e.g., 430). Therefore, the size and power consumption of the scan driver 400 can be effectively reduced.

[0111] Figure 13 This is a block diagram illustrating a scan driver according to another embodiment.

[0112] refer to Figure 13According to the embodiment, the scan driver 500 may include a plurality of first-level STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for the deteriorated and vulnerable area DVR of the display panel, a plurality of second-level STGK+1, STGK+2, STGK+3, STGK+4, ... for the normal area NR of the display panel, and at least one extended switch TEXT. Figure 13 The scan driver 500 can have the same characteristics as... Figure 12 The scan driver 400 has a similar configuration and similar operation, except that the scan driver 500 may further include an extension switch TEXT.

[0113] Each of the multiple first-stage STG1, STG2, ... and STGP-K+1, STGP-K+2, ... for the degraded vulnerable area DVR can include a selective sensing input circuit 510, 520, 540, or 550. The N stages (e.g., STGK+1, STGK+2, STGK+3, STGK+4, ...) of the multiple second-stage STGK+1, STGK+2, STGK+3, STGK+4 for the normal area NR can share a single selective sensing input circuit (e.g., 530) coupled to the selective sensing input nodes (e.g., NSSIK+1, NSSIK+2, NSSIK+3, and NSSIK+4) in these N stages via an extended switch TEXT. Therefore, the size and power consumption of the scan driver 500 can be effectively reduced. In some embodiments, the extended switch TEXT can selectively couple selective sensing input nodes (e.g., NSSIK+1, NSSIK+2, NSSIK+3, and NSSIK+4) in these N stages to each other in response to the extended signal SEXT.

[0114] Figure 14 This is a block diagram illustrating an electronic device including an OLED display device according to an embodiment.

[0115] refer to Figure 14 Electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (“I / O”) device 1140, a power supply 1150, and an OLED display device 1160. Electronic device 1100 may further include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electronic devices, etc.

[0116] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. Processor 1110 can be coupled to other components via address buses, control buses, data buses, etc. In addition, in some embodiments, processor 1110 can be further coupled to an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0117] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (mobile “DRAM”) device, and so on.

[0118] Storage device 1130 may be a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 can supply power for the operation of electronic device 1100. OLED display device 1160 can be coupled to other components via a bus or other communication link.

[0119] In the OLED display device 1160, the configuration of multiple first stages providing scan signals and sensing signals to a first region (e.g., a degraded or vulnerable region) of the display panel can differ from the configuration of multiple second stages providing scan signals and sensing signals to a second region (e.g., a normal region) of the display panel. Therefore, compared to sensing operations in the second region (e.g., the normal region), sensing operations in the first region (e.g., the degraded or vulnerable region) can be performed more finely (or precisely), and the size of the scan driver and the power consumption of the OLED display device 1160 can be effectively reduced.

[0120] The inventive concept can be applied to any electronic device 1100, including the OLED display device 1160. For example, the inventive concept can be applied to televisions (“TV”), digital TVs, 3D TVs, smartphones, wearable electronic devices, tablet computers, mobile phones, personal computers (“PC”), home appliances, laptop computers, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0121] The foregoing is a description of embodiments and should not be construed as limiting the embodiments. Although some embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the embodiments without departing from the novel teachings and advantages of the inventive concept. Thus, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is an illustrative description of different exemplary embodiments and should not be construed as limiting oneself to the specific embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. An organic light-emitting diode (OLED) display device, comprising: Including the display panels of the first and second areas; as well as Includes multiple first-stage and multiple second-stage scan drivers coupled to each other. The plurality of first stages are configured to provide scanning signals and sensing signals to the first region, and the plurality of second stages are configured to provide the scanning signals and sensing signals to the second region. The configurations of the plurality of first-level units differ from the configurations of the plurality of second-level units. Within each frame's sensing period, the sensing operation for each pixel in the first region is executed, and the sensing operation for one pixel out of the N×M pixels in the second region is executed. Where N is an integer greater than 1, and M is an integer greater than 0.

2. The organic light-emitting diode display device according to claim 1, wherein, The first region is a vulnerable region with a relatively high degree of degradation, and The second region is a normal region with relatively low degradation.

3. The organic light-emitting diode display device according to claim 1, wherein, The first region is the upper and / or lower region of the display panel, and The second region is the middle region between the upper region and the lower region of the display panel.

4. The organic light-emitting diode display device of claim 1, wherein each of a plurality of pixels in the first region and the second region comprises: This includes a capacitor coupled to a first electrode at the gate node and a second electrode coupled to the source node; A first transistor that generates a drive current based on the voltage stored in the capacitor; A second transistor coupled to the gate node in response to a corresponding scan signal in the scan signals; A third transistor is coupled to the source node in response to a corresponding sensing signal in the sensing signals; as well as Organic light-emitting diode that emits light based on the driving current.

5. The organic light-emitting diode display device according to any one of claims 1 to 4, wherein, Two of the multiple first stages share a selective sensing input circuit, and The 2N stages of the plurality of second stages share a single selective sensing input circuit. Where N is an integer greater than 1.

6. The organic light-emitting diode display device according to any one of claims 1 to 4, wherein each of the plurality of first stages and the plurality of second stages comprises: The control node input circuit transmits the first previous carry signal to the control node in response to the first previous carry signal and transmits a low voltage to the control node in response to the next carry signal. An inverter circuit performs an inversion operation so that the control node and the inverting control node have opposite voltages; The carry output circuit outputs a carry signal based on the voltage of the control node and the carry clock signal; The sensing output circuit outputs a corresponding sensing signal from the sensing signals based on the voltage and sensing clock signal of the control node. The scan output circuit outputs a corresponding scan signal from the scan signals based on the voltage and scan clock signal of the control node; as well as The selective sensing circuit transmits a high voltage to the control node based on the sensing start signal and the voltage of the selective sensing input node. Wherein two of the plurality of first stages share a selective sensing input circuit that provides a second prior carry signal to the selective sensing input node of the two stages, and The 2N stages of the plurality of second stages share a selective sensing input circuit that provides a third previous carry signal to the selective sensing input node of the 2N stages, and N is an integer greater than 1.

7. The organic light-emitting diode display device according to any one of claims 1 to 4, wherein, Two of the multiple first stages share a single selective sensing input circuit. The scan driver further includes an extension switch that couples selective sensing input nodes in 2N of the plurality of second stages to each other in response to an extension signal, where N is an integer greater than 1. The 2N stages of the plurality of second stages share a selective sensing input circuit through the extended switch.

8. An organic light-emitting diode display device, comprising: Including the display panels of the first and second areas; as well as Includes multiple first-stage and multiple second-stage scan drivers coupled to each other. The plurality of first stages are configured to provide scanning signals and sensing signals to the first region, and the plurality of second stages are configured to provide the scanning signals and sensing signals to the second region. Two of the plurality of first stages share a single selective sensing input circuit. The 2N stages of the plurality of second stages share a single selective sensing input circuit, and N is an integer greater than 1. Within each frame's sensing period, the sensing operation for each pixel in the first region is executed, and the sensing operation for one pixel out of the N×M pixels in the second region is executed. Where N is an integer greater than 1, and M is an integer greater than 0.

9. An organic light-emitting diode display device, comprising: Including the display panels of the first and second areas; as well as Includes multiple first-stage and multiple second-stage scan drivers coupled to each other. The plurality of first stages are configured to provide scanning signals and sensing signals to the first region, and the plurality of second stages are configured to provide the scanning signals and sensing signals to the second region. Each of the plurality of first stages includes a selective sensing input circuit. The N stages of the plurality of second stages share a single selective sensing input circuit, and N is an integer greater than 1. Within each frame's sensing period, the sensing operation for each pixel in the first region is executed, and the sensing operation for one pixel out of the N×M pixels in the second region is executed. Where N is an integer greater than 1, and M is an integer greater than 0.

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