Glucose sensor with improved accuracy and long-term stability

Abstract

Short pulse glitch detection in microelectronic devices and related methods, apparatus, and systems are described herein. An apparatus can detect a number of pulses of a signal and compare them to a timing aperture to determine whether any of the number of pulses is a short pulse glitch. The timing aperture, which can be based on a timing signal and / or one or more pulse width thresholds, can define whether a pulse is an acceptable pulse or a problematic short pulse glitch.

Description

[0001] Priority application

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 17 / 129,596, filed on December 21, 2020, entitled “Glitch Detection in Microelectronic Devices, and Related Devices, Systems, and Methods”. Technical Field

[0003] Embodiments of this disclosure relate to short-time pulse interference detection. More specifically, various embodiments of this disclosure relate to short-time pulse interference detection in microelectronic devices and related methods, apparatus, and systems. Background Technology

[0004] Memory devices are typically provided as internal semiconductor-based integrated circuits in computers or other electronic systems. Many different types of memory exist, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low-power double data rate memory (LPDDR), phase-change memory (PCM), and flash memory. Summary of the Invention

[0005] One or more embodiments of this disclosure include an apparatus. The apparatus may include a pulse detector configured to detect one or more pulses of a received signal. The apparatus may further include a circuitry coupled to the pulse detector and configured to receive from the pulse detector one or more captured signals indicating the width of the one or more pulses of the received signal. The circuitry may also be configured to compare the width of the one or more pulses of the received signal with a timing aperture defining a pulse width range. Furthermore, the circuitry may be configured to generate a signal indicating short-duration pulse wave interference in response to the width of the one or more pulses of the received signal being outside the pulse width range of the timing aperture.

[0006] Other embodiments of this disclosure include a method. The method may include detecting at least one pulse of a signal from a microelectronic device. The method may also include comparing the width of the at least one pulse of the signal with a predetermined timing aperture. Furthermore, the method may include detecting short-time pulse wave interference based on the comparison of the width of the at least one pulse with the predetermined timing aperture. The method may also include performing one or more operations via the microelectronic device in response to detecting the short-time pulse wave interference.

[0007] Additional embodiments of this disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory system operatively coupled to the at least one processor device. The memory system may include a memory device. The memory device may include a pulse detector configured to detect the width of a plurality of pulses of a test signal. The memory device may also include a filter coupled to the pulse detector. The filter may be configured to receive a timing signal defining a timing period. The filter may also be configured to receive a signal indicating the width of the plurality of pulses of the test signal. Furthermore, the filter may be configured to compare the width of the plurality of pulses of the signal with the timing period to detect short-time pulse wave interference. Additionally, the filter may be configured to generate a marker in response to detecting the short-time pulse wave interference. Attached Figure Description

[0008] Figure 1 This is a functional block diagram of an example memory device according to various embodiments of the present disclosure.

[0009] Figure 2 This is a diagram of example streams that can be used to detect short-time pulse wave interference according to various embodiments of this disclosure.

[0010] Figure 3A and 3B Example timing diagrams depicting the expected operation of a semiconductor device according to one or more embodiments of the present disclosure.

[0011] Figure 4 This is a block diagram depicting a portion of an example apparatus comprising a pulse detector and a filter according to various embodiments of the present disclosure.

[0012] Figure 5 This is a block diagram depicting a portion of another example apparatus comprising a positive pulse detector, a negative pulse detector, and a filter, according to various embodiments of the present disclosure.

[0013] Figure 6This is a block diagram depicting a portion of another example apparatus comprising a positive pulse detector and a negative pulse detector, two filters, and logic, according to various embodiments of the present disclosure.

[0014] Figure 7 This is a block diagram depicting a portion of another example apparatus comprising a positive pulse detector and a negative pulse detector, a filter, and logic, according to various embodiments of the present disclosure.

[0015] Figure 8 This is a block diagram depicting a portion of yet another example apparatus comprising a positive pulse detector and a negative pulse detector, a plurality of filters and logic, according to various embodiments of the present disclosure.

[0016] Figure 9 Example circuit diagrams are depicted according to various embodiments of the present disclosure.

[0017] Figure 10 and 11 Curves depicting several signals of a device according to various embodiments of the present disclosure.

[0018] Figure 12 This is a flowchart illustrating example methods of operating a microelectronic device according to various embodiments of the present disclosure.

[0019] Figure 13 This is a simplified block diagram of an example memory system according to one or more embodiments of the present disclosure.

[0020] Figure 14 This is a simplified block diagram of an example electronic system according to one or more embodiments of the present disclosure. Detailed Implementation

[0021] Semiconductor memory devices typically comprise an array of memory cells. Memory cells in the array are selected for reading and writing using row and column address signals input to the memory device. The row and column address signals are processed by an address decoding circuitry system to select the row and column lines in the array to access one or more desired memory cells. As described in more detail below, various signals, such as address signals, command signals (e.g., action commands, read / write signals, refresh commands), data signals, strobe signals, and other signals, can be transmitted within the semiconductor memory device. These and other signals may include pulses (i.e., a change in signal amplitude from a baseline value to another value (i.e., a higher or lower value) and back to the baseline value). As described herein, signal pulses that are too short (e.g., less than a quarter of a clock cycle) or too long (e.g., more than three-quarters of a clock cycle) may be due to faults and / or design errors, which could affect various functions (e.g., but not limited to command, read, and / or write operations) and / or cause associated device malfunctions.

[0022] As will be understood, some signal pulses (e.g., short pulses) in circuits (e.g., microelectronic circuits, such as semiconductor circuits) can produce nondeterministic characteristics. As will be understood, various problems and / or events (e.g., temporary metastability (e.g., timing hazards due to flip-flops (FFs) or latches) and / or asynchronous or poorly controlled timing of signals entering logic gates) can lead to downstream short pulses or “short-time pulse wave interference” (e.g., in semiconductor circuits).

[0023] It will also be understood that semiconductor devices may be simulated and / or tested in ideal environments (e.g., by design and / or inspection personnel), making it difficult to detect many unexpected short-time pulse interferences on the die. Furthermore, in some conventional systems and / or methods, short-time pulse interference problems are identified during system testing (e.g., close to the time of shipment to the customer), which can adversely increase time-to-market (TTM) (i.e., due to the need for commissioning and / or additional simulation and computational verification processes).

[0024] As disclosed herein, various embodiments may relate to detecting short-time pulse interference within a semiconductor device. More specifically, for example, in some embodiments, a signal (e.g., a “test signal,” “signal of interest,” or “signal under test”) may be monitored to determine if any pulses in the signal constitute short-time pulse interference. According to various embodiments, the width of the signal pulse may be detected and compared to a selectable width range (also referred to herein as a “timing aperture” or “timing window”) to determine whether the pulse is short-time pulse interference. According to some embodiments, the timing aperture may be set (e.g., by a user) via, for example, one or more fuses (e.g., test mode fuses).

[0025] More specifically, according to a non-limiting example, the pulse width of a data strobe signal (DQS) can be detected and compared with a timing signal (e.g., a pulse and / or a clock signal (e.g., a system clock signal)) that can define and / or be used to define a timing aperture. In at least some embodiments, the timing aperture can be selected to be between, for example, one-quarter and three-quarters of the period of the clock signal. In this example, if the pulse width of the DQS signal is less than one-quarter or greater than three-quarters of the clock signal period, then the pulse can be determined to be problematic short-time pulse wave interference. Otherwise, the pulse can be determined to be an acceptable pulse. As another example, if the pulse width of the DQS signal is less than half or greater than half of the clock signal period, then the pulse can be determined to be problematic short-time pulse wave interference. In yet another example, if the pulse width of the DQS signal is less than half or greater than three-quarters of the clock signal period, then the pulse can be determined to be problematic short-time pulse wave interference.

[0026] In some embodiments, in response to the detection of short-duration pulse interference, an indication (e.g., a warning) of the short-duration pulse interference can be provided. More specifically, a warning pin or another available pin of the semiconductor device can be used to indicate the detected short-duration pulse interference. Furthermore, according to some embodiments, one or more operations (e.g., enabling and / or disabling events) can be performed in response to the detection of short-duration pulse interference. For example, in response to the detection of short-duration pulse interference (e.g., of the DQS signal) in the semiconductor device, one or more input / output operations can be performed and / or modified based on one or more predefined mode register settings of the semiconductor device. More specifically, for example, one or more mode register settings can be configured to disable one or more read and / or write operations in response to the detection of short-duration pulse interference. More specifically, for example, one or more mode register bits can be configured to prevent a write operation if the DQS signal associated with the write operation contains short-duration pulse interference. As another example, one or more mode register bits can be configured such that if the DQS signal associated with a write operation contains short-duration pulse interference, the associated read operation (i.e., for reading data associated with the write operation) can be disabled (i.e., via a read block). In another example, one or more mode register bits can be configured such that if the DQS signal associated with a write operation contains short-duration pulse interference, the write operation and the associated read operation (i.e., for reading data associated with the write operation) can be enabled (e.g., to compare the written data with the read data).

[0027] As will be understood, various embodiments of this disclosure can help verify functionality and performance in silicon. It will also be understood that various embodiments can enable some problems (e.g., short-time pulse interference / ringing issues) to be identified at the component level (i.e., prior to system testing), thus reducing the amount of subsequent testing (e.g., debugging and / or additional simulation and computational verification processes).

[0028] Although various embodiments are described herein with reference to semiconductor and / or memory devices, this disclosure is not limited thereto, and the embodiments are generally applicable to microelectronic systems and / or devices that may or may not include semiconductor and / or memory devices. Embodiments of this disclosure will now be explained with reference to the accompanying drawings.

[0029] Figure 1This is a functional block diagram illustrating an example memory device 100 according to at least one embodiment of the present disclosure. The memory device 100 may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), dual data rate SDRAM (DDR SDRAM, such as DDR4 SDRAM, etc.), or synchronous graphics random access memory (SGRAM). The memory device 100, which can be integrated on a semiconductor chip, may include a memory array 102.

[0030] exist Figure 1 In one embodiment, memory array 102 is shown as comprising eight memory groups BANK0-7. Memory array 102 in other embodiments may comprise more or fewer groups. Each memory group comprises several access lines (word lines WL), several data lines (bit lines BL and / or BL), and several memory cells MC arranged at the intersections of the word lines WL and the bit lines BL and / or BL. The selection of word lines WL may be performed by row decoder 104, and the selection of bit lines BL and / or BL may be performed by column decoder 106. Figure 1 In one embodiment, row decoder 104 may include a corresponding row decoder for each memory group BANK0-7, and column decoder 106 may include a corresponding column decoder for each memory group BANK0-7.

[0031] Bit lines BL and / BL are coupled to their respective sense amplifiers SAMP. Read data from bit line BL or / BL is amplified by the sense amplifier SAMP and transferred to the read / write amplifier 160 via the complementary local data line (LIOT / B), the transfer gate (TG), and the complementary main data line (MIOT / B). Conversely, write data output from the read / write amplifier 160 is transferred to the sense amplifier SAMP via the complementary main data line MIOT / B, the transfer gate TG, and the complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0032] The memory device 100 may be generally configured to receive various inputs via various terminals (e.g., from an external controller), such as address and command terminals 108, clock terminal 110, and data terminal 122. The memory device 100 may include additional terminals that can be coupled to the voltage generator 120, such as power supply terminals 124 and 126.

[0033] During expected operation, one or more command signals COM received via address and command terminals 108 can be transmitted to command decoder 116 via command / address input circuitry 112. Command decoder 116 may include circuitry configured to generate various internal commands by decoding the one or more command signals COM. Examples of internal commands include action command ACT and read / write signal R / W.

[0034] Furthermore, one or more address signals ADD received via address and command terminals 108 can be transmitted to address decoder 114 via command / address input circuitry 112. Address decoder 114 can be configured to supply row address XADD to row decoder 104 and column address YADD to column decoder 106. Although command / address input circuitry 112 is shown as a single circuit, in some embodiments, command / address input circuitry 112 may include more than one circuit.

[0035] The action command ACT may include a pulse signal activated in response to a command signal COM (e.g., an action command) indicating row access. In response to the action signal ACT, the row decoder 104 specifying the group address can be activated. Therefore, the word line WL specified by the row address XADD can be selected and activated.

[0036] The read / write signal R / W may include a pulse signal activated in response to a command signal COM (e.g., a read command or a write command) indicating column access. In response to the read / write signal R / W, the column decoder 106 can be activated, and the bit line BL specified by the column address YADD can be selected.

[0037] In response to the action command ACT, the read signal, the row address XADD, and the column address YADD, data can be read from the memory cell MC specified by the row address XADD and the column address YADD. The read data can be output via the sense amplifier SAMP, the transfer gate TG, the read / write amplifier 160, the input / output circuit 162, and the data terminal 122. Furthermore, in response to the action command ACT, the write signal, the row address XADD, and the column address YADD, write data can be supplied to the memory array 102 via the data terminal 122, the input / output circuit 162, the read / write amplifier 160, the transfer gate TG, and the sense amplifier SAMP. The write data can be written to the memory cell MC specified by the row address XADD and the column address YADD.

[0038] Additionally, memory device 100 may include fuse / register 164, which may include one or more fuse circuits and / or one or more registers (e.g., but not limited to, test mode fuses, mode registers (MR)). For example, one or more settings of the mode register (e.g., of fuse / register 164) may be used to define one or more operations to be performed in response to the detection of short-duration pulse wave interference. Furthermore, according to some embodiments, one or more thresholds (e.g., for defining timing apertures) may be set (e.g., by a user) via one or more fuses (e.g., test mode fuses) in fuse / register 164. As will be understood, fuse / register 164 may be coupled to one or more other components of memory device 100, such as, but not limited to, column decoder 106, row decoder 104, memory cell array 102, read / write amplifier 160, input / output circuitry 162, circuitry system 166, and possibly other components.

[0039] Clock signals CK and / or CK can be received via clock terminal 110. Clock input circuit 118 can generate an internal clock signal ICK based on clock signals CK and / or CK. The internal clock signal ICK can be transmitted to various components of memory device 100, such as input / output circuit 162 (e.g., for controlling the operating timing of input / output circuit 162).

[0040] The memory device 100 may further include a circuit system 166 configured to implement various embodiments of the present disclosure. For example, the circuit system 166 may include one or more pulse detectors, filters (also referred to herein as “detection apertures”), and / or logic, as at least referenced below. Figure 2 and 4 -9 describes this more fully. As will be understood, circuitry 166 may be coupled to one or more other components of memory device 100, such as, but not limited to, command / address input circuitry 112, address decoder 114, command decoder 116, column decoder 106, row decoder 104, memory cell array 102, read / write amplifier 160, input / output circuitry 162, fuse / register 164, clock input circuitry 118, and possibly other components. In some embodiments, at least a portion of circuitry 166 may be included within at least one other component of memory device 100 (e.g., within input / output circuitry 162).

[0041] Figure 2 This is a diagram of an example flow 200 that can be used to detect short-time pulse wave interference according to various embodiments of the present disclosure. In some embodiments, at least a portion of flow 200 may be an example of the intended operation of a semiconductor device. Figure 3A and 3BExample timing diagrams 300 and 350, respectively, depicting the expected operation of a semiconductor device according to one or more embodiments of the present disclosure.

[0042] refer to Figure 2 , 3A In conjunction with 3B, stream 200 may begin at block 202, where the pulse width of the received signal (e.g., but not limited to, command, data signal, data strobe (DQS)) 204 is detected and / or measured. For example, signal 204 may be a DQS signal, such as a signal containing a true component "signal_t" and a complementary component "signal_c", as shown below. Figure 3A and Figure 3B As shown in the diagram. Furthermore, at block 206, the pulse width of signal 204 can be compared with comparison element 208. As described more fully herein, comparison element 208 may include, for example, control signals and / or timing signals (e.g., pulse and / or clock signals). In some embodiments, comparison element 208 may define and / or be used to define a timing aperture (also referred to herein as a “timing window”) (e.g., having an upper pulse width threshold and / or a lower pulse width threshold), which can be used to determine whether the pulse width (e.g., of signal 204) is acceptable (e.g., a non-short-time pulse wave interference pulse) or unacceptable (e.g., short-time pulse wave interference).

[0043] In at least one instance, the comparator 208 may be or define a timing aperture, such as at least a portion (e.g., a clock cycle) of a clock signal having a true component “CK_t” and a complementary component “CK_c”, as... Figure 3A and Figure 3B As shown in the diagram. As a more specific example, the comparator 208 may be or be defined as a timing aperture between one-quarter (e.g., 0.25CK) and three-quarters (e.g., 0.75CK) of the clock cycle of the clock signal. In this example, the pulse width of signal 204 can be compared to the upper and lower limits of the timing aperture. More precisely, for example, in the case where the timing aperture is 0.25CK-0.75CK, the width of signal 204 can be compared to the lower limit (i.e., 0.25CK) and upper limit (i.e., 0.75CK) of the timing aperture (e.g., at box 206). Short-duration pulse wave interference can be detected when the pulse width of signal 204 is less than the lower limit (i.e., 0.25CK in this example) or greater than the upper limit (i.e., 0.75CK in this example), as depicted in box 210. As an example, as... Figure 3A As shown, at time T A The pulse width W1 of signal_t ​​is greater than 0.75CK, and therefore short-duration pulse wave interference can be detected. As another example, such as... Figure 3B As shown, at time TB The pulse width W2 of signal_t ​​is less than 0.25CK, and therefore short-time pulse wave interference can be detected.

[0044] If the pulse width of signal 204 is neither less than the lower limit (i.e., 0.25CK in this example) nor greater than the upper limit (i.e., 0.75CK in this example), short-time pulse interference may not be detected. For example, if no short-time pulse interference is detected, flow 200 may return to block 202 (i.e., from block 206), where the width of another pulse of the measured signal (e.g., signal 204 or another signal) may be used.

[0045] According to at least some embodiments, in response to the detection of short-time pulse interference (e.g., at block 210), a short-time pulse interference indicator (also referred to herein as a “warning indicator” or “warning”) can be generated (e.g., affirmatively) at block 212, and flow 200 can proceed to block 214. For example, the indication of short-time pulse interference (e.g., a warning) can be provided via a warning signal (ALERT_n) and / or via a warning pin of the semiconductor device or another available pin.

[0046] Furthermore, according to some embodiments, at block 214, one or more operations can be performed in response to the detection of short-duration pulse wave interference. For example, in response to the detection of short-duration pulse wave interference (e.g., of the DQS signal), one or more input / output operations (e.g., enabling and / or disabling operations) can be performed and / or modified based on one or more mode register settings, as described above.

[0047] Figure 4 This is a block diagram depicting a portion of an example apparatus 400 according to various embodiments of the present disclosure. It may include semiconductor devices (e.g., in...). Figure 1 The device 400 (within or part of the circuitry 166 of the memory device 100) includes a pulse detector 402 and a filter 404. For example, the pulse detector 402 and other pulse detectors described herein may also be referred to herein as a “pulse detection module,” a “pulse detector block,” or a variation thereof. The filter 404 and other filters described herein may also be referred to herein as a “timing filter,” a “detection aperture,” a “short-time pulse interference detector,” a “short-time pulse interference detection module,” a variation thereof, or simply as a “circuitry system.”

[0048] According to various embodiments, pulse detector 402 may be configured to receive signal (e.g., "test signal") 406, which may contain any signal from device 400. By way of example only, signal 406 may contain any timing-critical signal sensitive to short-duration pulse wave interference and / or truncated pulses. As a more specific example, signal 406 may contain a DQS signal, an address signal (e.g., a decoded address signal), a command signal (e.g., a decoded command), a clock signal, a read delay calculation signal, another timing-critical signal, or another suitable signal. Pulse detector 402 may be configured to receive signal 406, detect and transmit pulse 408 (i.e., the pulse of signal 406) to filter 404. For example, pulse detector 402 may detect the rising and falling edges of the pulse of signal 406. Those skilled in the art will understand pulse detection, and pulse detector 402 may detect pulses via any known and suitable means (e.g., differential pair, direct edge detection, etc.).

[0049] Filter 404 may include any suitable circuit system (e.g., logic circuit system (e.g., logic gate) or other circuit system such as comparators, latches, flip-flops, sense amplifiers, but not limited thereto). Filter 404 may be configured to receive pulse 408 and aperture timing control signal 410, which may indicate and / or define a timing aperture and / or be used to define a timing aperture (i.e., for filter 404). For example, aperture timing control signal 410 may include one or more signals (e.g., one or more control signals and / or timing signals (e.g., clock signals and / or pulses)) indicating the size of the desired timing aperture (i.e., an acceptable pulse width range).

[0050] According to some embodiments, the aperture timing control signal 410 can be determined based on the signal of interest. For example, the command decoding signal can operate on a full-cycle clock and therefore can sustain for a full clock cycle. In this case, the timing aperture can be set to a suitable range using the system clock or a delay generator (e.g., via the aperture timing control signal 410). For delay calculation signals, critical short-pulse interference-sensitive timing is typically near the start / end of the calculated delay; therefore, in this example, the signal determining the delay is used as the aperture timing control signal 410 (i.e., enabling and disabling short-pulse interference detection near the start and end of the calculation), and the timing aperture can be associated with the start / end of the calculated timing.

[0051] In one instance where the aperture timing control signal 410 or another signal comprises one or more control signals, in response to receiving said one or more control signals, the filter 404 may be set with one or more thresholds that can be used to distinguish acceptable pulses from problematic short-duration pulse interference. For example, in response to the aperture timing control signal 410, the filter 404 may set a lower limit pulse width threshold (“lower limit”) to, for example, a percentage of clock cycles and / or duration (e.g., in nanoseconds or picoseconds). Alternatively or additionally, in response to the aperture timing control signal 410, the filter 404 may set an upper limit pulse width threshold (“upper limit”) to, for example, a percentage of clock cycles and / or duration (e.g., in nanoseconds or picoseconds).

[0052] Furthermore, in some embodiments, the aperture timing control signal 410 may include a timing signal (e.g., a pulse and / or a clock signal (e.g., a system clock signal or a derivative of a system clock signal)). In these embodiments, the pulse (e.g., signal 408) may be compared with the timing signal to determine whether the pulse is a short-time pulse wave interference. For example, refer to... Figure 3B At time T B The signal_t ​​(i.e., the actual part of the signal of interest) rises and falls during the "high time" of the clock signal CK_t (i.e., the actual part of the timing signal), therefore it can be determined that the pulse of signal_t ​​is a short-time pulse wave interference. Furthermore, refer to... Figure 3A Around time T C The pulse of signal_t ​​falls and rises during the "low time" of the clock signal CK_t, so it can be determined that the pulse of signal_t ​​is a short-time pulse wave interference.

[0053] As will be described more fully below, the true and complementary components of the test signal (e.g., signal_t ​​and signal_c) can be compared with the true and complementary components of the timing signal (e.g., clock signal CK_t and clock signal CK_c) to detect short-time pulse wave interference in several pulses of the test signal. Furthermore, as will be understood, in embodiments where the control signal 410 is a clock signal, the timing aperture can be adjusted with the frequency of the clock signal. For example, when the clock frequency decreases, the timing aperture (i.e., the acceptable pulse width range) can be automatically adjusted (e.g., increased) with the clock frequency.

[0054] Refer again Figure 4Filter 404 can be configured to compare pulse 408 with one or more defined thresholds and / or aperture timing control signals 410. For example, in at least one embodiment, filter 404 can compare the width of pulse 408 with one or more defined thresholds (e.g., via one or more logic circuits). In response to the comparison of the width of pulse 408 with the one or more defined thresholds, filter 404 can generate a signal 412 indicating whether pulse 408 is an acceptable pulse or a short-duration pulse wave interference. In a particular instance, if the width of pulse 408 is greater than an upper threshold width or less than a lower threshold width, signal 412 can be affirmed to indicate that pulse 408 is a short-duration pulse wave interference. Alternatively, if the width of pulse 408 is neither greater than the upper threshold width nor less than the lower threshold width, signal 412 can be denied to indicate that pulse 408 is an acceptable pulse.

[0055] In other embodiments where the aperture timing control signal 410 includes a timing signal (e.g., a pulse and / or clock signal), the filter 404 can compare the timing signal with the width of the pulse 408. In response to the comparison of the pulse 408 width with the timing signal, the filter 404 can generate a signal 412 indicating whether the pulse 408 is an acceptable pulse or a short-time pulse wave interference. In one example, if both edges of the pulse 408 (i.e., falling and rising or rising and falling) occur during a “high time” or “low time” of the timing signal, then short-time pulse wave interference can be detected. In another example, if the width of the pulse 408 is greater than an upper pulse width threshold (e.g., 0.75CK) or less than a lower pulse width threshold (e.g., 0.25CK), then signal 412 can be used to indicate that the pulse 408 is a short-time pulse wave interference. Alternatively, if the width of pulse 408 is neither greater than the upper pulse width threshold nor less than the lower pulse width threshold (e.g., 0.25CK <= the width of pulse 408 <= 0.75CK), then signal 412 can be negated to indicate that pulse 408 is an acceptable pulse.

[0056] According to some embodiments, the pulse detector may include multiple polarities, which may increase the likelihood of detecting short-duration pulse wave interference in both the high and low directions. For example, Figure 5 This is a block diagram depicting a portion of another example device 500 according to various embodiments of the present disclosure. Device 500 is similar to Figure 4 The device 400; however, in Figure 5 In one embodiment, the pulse detector 502 includes a positive edge detector 502A for detecting positive edges and a negative edge detector 502B for detecting negative edges. The device 500 further includes a filter 504, which may include... Figure 4 Filter 404. By detecting each edge of the signal under test (i.e., individually), the control of filter 504 can be enhanced (e.g., compared to...). Figure 4 (Example).

[0057] According to various embodiments, each of the positive edge detector 502A and the negative edge detector 502B is configured to receive a signal (e.g., a "test signal") 506, which may contain any signal from the device 500. Similar to... Figure 4 Signal 406 and signal 506 may contain any timing-critical signal, for example, that is sensitive to short-duration pulse wave interference and / or truncated pulses. Positive edge detector 502A may be configured to receive signal 506, detect and capture the rising edge of signal 506, and transmit the captured signal (i.e., the result of detection) (e.g., a logic signal (HIGH or LOW) containing timing information) 508 to filter 504. Negative edge detector 502B may be configured to receive signal 506, detect the falling edge of signal 506, and transmit the captured signal (i.e., the result of detection) (e.g., a logic signal (LOW or HIGH) containing timing information) 509 to filter 504. Those skilled in the art will understand pulse detection via rising and falling edges, and that pulse detector 502 may detect the rising and falling edges of signal 506 via any known and suitable means.

[0058] Filter 504 may be configured to receive an aperture timing control signal 510, which may indicate and / or define a timing aperture and / or be used to define a timing aperture. In embodiments where the aperture timing control signal 510 includes a timing signal (e.g., a pulse and / or clock signal), filter 504 may compare the timing signal with captured signals 508 and 509. In response to the comparison of captured signals 508 and 509 with the timing signal, filter 504 may generate a signal 512 indicating whether short-duration pulse wave interference has been detected.

[0059] In some instances, the captured signal 508 can be compared with the "high time" of the first half of the clock cycle of the clock signal (i.e., the timing signal), and the captured signal 509 can be compared with the "low time" of the second half of the clock cycle of the clock signal (i.e., the timing signal). In this instance, if the captured signal 508 rises and falls during the "high time" of the first half of the clock cycle of the clock signal, then short-time pulse wave interference can be detected. Furthermore, if the captured signal 509 falls and rises during the "low time" of the second half of the clock cycle of the clock signal, then short-time pulse wave interference can be detected.

[0060] In another example where the aperture timing control signal 510 includes a pulse, the first (e.g., rising) edge of the pulse can be the start of the timing aperture, and the second (e.g., falling) edge can be the end of the timing aperture. In this example, if the captured signal (e.g., captured signal 508) rises and falls during the timing aperture, then short-time pulse wave interference can be detected.

[0061] As another example, if the width of the captured signal 508 or the captured signal 509 is greater than the upper pulse width threshold (e.g., 0.75CK) or less than the lower pulse width threshold (e.g., 0.25CK), then signal 512 can be affirmed to indicate short-time pulse wave interference. Alternatively, if the width of the captured signal 508 is neither greater than the upper pulse width threshold nor less than the lower pulse width threshold (e.g., 0.25CK <= width of pulse 508 <= 0.75CK), and the width of the captured signal 509 is neither greater than the upper pulse width threshold nor less than the lower pulse width threshold (e.g., 0.25CK <= width of pulse 509 <= 0.75CK), then signal 512 can be negated to indicate that signal 506 does not contain short-time pulse wave interference.

[0062] Furthermore, according to some embodiments, the filter (i.e., the detection aperture) may include more than one filter component (i.e., more than one detection aperture). For example, Figure 6 This is a block diagram depicting a portion of another example device 600 according to various embodiments of the present disclosure. Device 600 is similar to... Figure 5 The device 500; however, in Figure 6 In the embodiments described, filter 604 includes filter 604A and filter 604B. Each of filter 604A and filter 604B may include any suitable circuit system (e.g., logic circuit system (e.g., logic gate) or other circuit systems such as comparators, latches, flip-flops, sense amplifiers, but not limited thereto). Device 600 further includes logic 614. By way of example only, logic 614 may include OR gates and / or one or more other logic circuits. Similar to device 500, device 600 further includes pulse detector 602, including positive edge detector 602A and negative edge detector 602B.

[0063] According to various embodiments, each of the positive edge detector 602A and the negative edge detector 602B is configured to receive a signal (e.g., a "test signal") 606, which may contain any signal from the device 600. Similar to... Figure 4Signal 406 and signal 606 may contain any timing-critical signal, such as one sensitive to short-duration pulse wave interference and / or truncated pulses. Positive edge detector 602A is configured to receive signal 606, detect and capture the rising edge of signal 606, and transmit the captured signal (i.e., the result of detection) (e.g., a logic signal (HIGH or LOW) containing timing information) 608 to filter 604A. Negative edge detector 602B is configured to receive signal 606, detect the falling edge of signal 606, and transmit the captured signal (i.e., the result of detection) (e.g., a logic signal (LOW or HIGH) containing timing information) 609 to filter 604B.

[0064] Each of filters 604A and 604B is configured to receive an aperture timing control signal 610, which may indicate and / or define a timing aperture and / or may be used to define a timing aperture (i.e., for each of filters 604A and 604B). It should be noted that the input of filter 604B configured to receive the aperture timing control signal 610 includes an inversion bubble, such that filter 604B is configured to compare the captured signal 609 with a LOW timing signal, while filter 604A is configured to compare the captured signal 608 with a HIGH timing signal.

[0065] In embodiments where the aperture timing control signal 610 includes a timing signal (e.g., a pulse and / or a clock signal), filter 604A can compare at least a portion of the timing signal with the captured signal 608, and filter 604B can compare at least a portion of the timing signal with the captured signal 609.

[0066] In response to a comparison between the captured signal 608 and the timing signal, filter 604A can generate a signal 612A indicating whether the captured signal 608 is subject to acceptable pulse or short-duration pulse wave interference. Furthermore, in response to a comparison between the captured signal 609 and the timing signal, filter 604B can generate a signal 612B indicating whether the captured signal 609 is subject to acceptable pulse or short-duration pulse wave interference.

[0067] In at least one instance, filter 604A compares the captured signal 608 with the "high time" of the first half of the clock cycle of the clock signal (i.e., the timing signal), and filter 604B compares the captured signal 609 with the "low time" of the second half of the clock cycle of the clock signal (i.e., the timing signal). In this instance, if the captured signal 608 rises and falls during the "high time" of the first half of the clock cycle of the clock signal, then filter 604A can confirm signal 612A (e.g., indicating that the captured signal 608 contains short-time pulse wave interference). Furthermore, if the captured signal 609 falls and rises during the "low time" of the second half of the clock cycle of the clock signal, then filter 604B can confirm signal 612B (e.g., indicating that the captured signal 609 contains short-time pulse wave interference).

[0068] As another example, if the width of the captured signal 608 is greater than the upper pulse width threshold (e.g., 0.75CK) or less than the lower pulse width threshold (e.g., 0.25CK), then signal 612A can be affirmed. Similarly, if the width of the captured signal 609 is greater than the upper pulse width threshold (e.g., 0.75CK) or less than the lower pulse width threshold (e.g., 0.25CK), then signal 612B can be affirmed. Alternatively, if the width of the captured signal 608 is neither greater than the upper pulse width threshold nor less than the lower pulse width threshold (e.g., 0.25CK <= width of pulse 608 <= 0.75CK), and the width of the captured signal 609 is neither greater than the upper pulse width threshold nor less than the lower pulse width threshold (e.g., 0.25CK <= width of pulse 608 <= 0.75CK), then each of signals 612A and 612B can be rejected (e.g., indicating that captured signals 608 and 609 are acceptable).

[0069] Logic 614 can be configured to receive signals 612A and 612B and generate signal 616. According to some embodiments, signal 616 can be affirmed (e.g., a HIGH signal) in response to either signal 612A or signal 612B being affirmed (e.g., HIGH). Furthermore, signal 616 can be negated (e.g., a LOW signal) in response to both signals 612A and 612B being negated (e.g., LOW).

[0070] In other embodiments, multiphase aperture timing control can be used, wherein the filter can compare a positive pulse with a positive signal (e.g., a clock signal) during one phase and compare a negative pulse with a negative signal (e.g., a clock signal) during another phase. For example, Figure 7 This is a block diagram depicting a portion of another example apparatus 700 including multiphase aperture timing control, according to various embodiments of the present disclosure. Similar to... Figure 6The apparatus 600 and apparatus 700 include a pulse detector 702, which includes a positive edge detector 702A and a negative edge detector 702B. Furthermore, apparatus 700 includes a filter 704, which may include any suitable circuitry (e.g., logic circuitry (e.g., logic gates) or other circuitry such as comparators, latches, flip-flops, sense amplifiers, but not limited thereto). In some embodiments, apparatus 700 may include a reset block 714, which may be configured to clear short-duration pulse interference markers (e.g., periodically and / or after a data burst is read and / or written).

[0071] According to various embodiments, each of the positive edge detector 702A and the negative edge detector 702B is configured to receive a signal (e.g., a "test signal") 706, which may contain any signal of the device 700. Similar to signals 406, 506, and 606 described above, signal 706 may contain any timing-critical signal, for example, sensitive to short-time pulse wave interference and / or truncated pulses. Positive edge detector 702A is configured to receive signal 706, detect and capture the rising edge of signal 706, and transmit the captured signal (i.e., the result of detection) (e.g., a logic signal (HIGH or LOW) containing timing information) 708 to filter 704. Negative edge detector 702B is configured to receive signal 706, detect the falling edge of signal 706, and transmit the captured signal (i.e., the result of detection) (e.g., a logic signal (LOW or HIGH) containing timing information) 709 to filter 704.

[0072] Filter 704 can be configured to receive an N-bit aperture timing control signal 710, which can indicate and / or define a timing aperture and / or can be used to define a timing aperture (i.e., for each of several phases). In embodiments where the N-bit aperture timing control signal 710 includes a timing signal (e.g., a pulse and / or a clock signal), during one phase (e.g., a first phase), filter 704 can be configured to compare the timing signal with a captured signal 708 (i.e., for a first timing aperture). Furthermore, during another phase (e.g., a second phase), filter 704 can be configured to compare the timing signal with a captured signal 709 (i.e., for a second timing aperture). In response to the comparison of the captured signals 708 and 709 with the timing, filter 704 can transmit a signal 712, which can indicate whether the captured signals 708 and 709 are both acceptable pulses or whether the captured signals 708 and / or 709 are short-duration pulse wave interference.

[0073] In some instances, the captured signal 708 can be compared with the "high time" of the first half of the clock cycle of the clock signal (i.e., the timing signal), and the captured signal 709 can be compared with the "low time" of the second half of the clock cycle of the clock signal (i.e., the timing signal). In this instance, if the captured signal 708 rises and falls during the "high time" of the first half of the clock cycle of the clock signal, then short-time pulse wave interference can be detected. Furthermore, if the captured signal 709 falls and rises during the "low time" of the second half of the clock cycle of the clock signal, then short-time pulse wave interference can be detected.

[0074] In another example where the N-bit aperture timing control signal 710 includes a pulse, the first (e.g., rising) edge of the pulse can be the start point of the timing aperture, and the second (e.g., falling) edge can be the end point of the timing aperture. In this example, if the captured signal (e.g., captured signal 708) rises and falls during the timing aperture, then short-time pulse wave interference can be detected.

[0075] As another example, if the width of the captured signal 708 or the captured signal 709 is greater than the upper pulse width threshold (e.g., 0.75CK) or less than the lower pulse width threshold (e.g., 0.25CK), then signal 712 can be affirmed to indicate short-time pulse wave interference. Alternatively, if the width of the captured signal 708 is neither greater than the upper pulse width threshold nor less than the lower pulse width threshold (e.g., 0.25CK <= width of pulse 708 <= 0.75CK), and the width of the captured signal 709 is neither greater than the upper pulse width threshold nor less than the lower pulse width threshold (e.g., 0.25CK <= width of pulse 709 <= 0.75CK), then signal 712 can be negated to indicate that signal 706 does not contain short-time pulse wave interference.

[0076] According to various embodiments, signal 712 may be received at reset block 714, wherein short-time pulse wave interference flag 716 may be reset (e.g., periodically, in response to an event (e.g., a timing event), and / or after a data burst is read and / or written).

[0077] Figure 8 This is a block diagram depicting a portion of another example apparatus 800 according to various embodiments of the present disclosure. Figure 8 In one embodiment, the rising and falling edges of signal 806 can be analyzed (e.g., compared with the real and complementary signals of the clock signal) to detect short-time pulse wave interference.

[0078] Device 800 includes a pulse detector 802, comprising a positive edge detector 802A and a negative edge detector 802B. Device 800 further includes a first filter 804A, a second filter 804B, a third filter 804C, and a fourth filter 804D. Each of filters 804A-804D may include any suitable circuit system (e.g., a logic circuit system (e.g., a logic gate) or other circuit systems such as comparators, latches, flip-flops, sense amplifiers, but not limited thereto). Device 800 further includes logic 814. By way of example only, logic 814 may include an OR gate and / or one or more other logic circuits.

[0079] According to various embodiments, each of the positive edge detector 802A and the negative edge detector 802B is configured to receive a signal (e.g., a "test signal") 806, which may contain any signal of the device 800. Similar to signals 406, 506, 606, and 706, signal 806 may contain any timing-critical signal, for example, that is sensitive to short-time pulse wave interference and / or truncated pulses. Positive edge detector 802A may be configured to receive signal 806, detect and capture the rising edge of signal 806, and transmit the captured signal (i.e., the detection result) (e.g., a logic signal (HIGH or LOW) containing timing information) 808 to filters 804A and 804C. Negative edge detector 802B may be configured to receive signal 806, detect the falling edge of signal 806, and transmit the captured signal (i.e., the detection result) (e.g., a logic signal (LOW or HIGH) containing timing information) 809 to filters 804B and 804D.

[0080] Each of filters 804A, 804B, 804C, and 804D is configurable to receive an aperture timing control signal 810, which may indicate and / or define a timing aperture and / or may be used to define a timing aperture (i.e., for each of filters 804A, 804B, 804C, and 804D). It should be noted that the inputs of filters 804B and 804C, configured to receive the aperture timing control signal 810, include an inverting loop, such that filters 804B and 804C are configured to compare the captured signal with a LOW timing signal, while filters 804A and 804D are configured to compare the captured signal with a HIGH timing signal.

[0081] In embodiments where the aperture timing control signal 810 includes a timing signal (e.g., a pulse and / or clock signal), filter 804A can compare at least a portion of the timing signal with the captured signal 808, filter 804B can compare at least a portion of the timing signal with the captured signal 809, filter 804C can compare at least a portion of the timing signal with the captured signal 808, and filter 804D can compare at least a portion of the timing signal with the captured signal 809.

[0082] Filter 804A compares the rising edge of the true portion of the timing signal with the captured signal 808. In response to the comparison of the captured signal 808 with the timing signal, filter 804A generates a signal 812A indicating whether short-duration pulse interference has been detected. More specifically, in at least one instance, filter 804A compares the captured signal 808 with the "high time" of the first half of the clock cycle of the true portion of the clock signal (i.e., the timing signal). In this instance, if the captured signal 808 rises and falls during the "high time" of the first half of the clock cycle of the true portion of the clock signal, then filter 804A can confirm signal 812A.

[0083] Furthermore, filter 804B can compare the falling edge of the true portion of the timing signal with the captured signal 809. In response to the comparison of the captured signal 809 with the timing signal, filter 804B can generate a signal 812B indicating whether short-duration pulse interference has been detected. More specifically, in at least one instance, filter 804B can compare the captured signal 809 with the "low time" of the second half of the clock cycle of the true portion of the clock signal (i.e., the timing signal). In this instance, if the captured signal 809 falls and rises during the "low time" of the second half of the clock cycle of the true portion of the clock signal, then filter 804B can confirm signal 812B.

[0084] Furthermore, filter 804C can compare the rising edge of the complementary portion of the timing signal with the captured signal 808. In response to the comparison between the captured signal 808 and the timing signal, filter 804C can generate a signal 812C indicating whether short-duration pulse wave interference has been detected. More specifically, in at least one instance, filter 804C can compare the captured signal 808 with the "high time" of the second half of the clock cycle of the complementary portion of the clock signal (i.e., the timing signal). In this instance, if the captured signal 808 rises and falls during the "high time" of the second half of the clock cycle of the complementary portion of the clock signal, then filter 804C can confirm signal 812C.

[0085] Additionally, filter 804D can compare the falling edge of the complementary portion of the timing signal with the captured signal 809. In response to the comparison of the captured signal 809 with the timing signal, filter 804D can generate a signal 812D indicating whether short-duration pulse interference has been detected. More specifically, in at least one instance, filter 804D can compare the captured signal 809 with the "low time" of the first half of the clock cycle of the complementary portion of the clock signal (i.e., the timing signal). In this instance, if the captured signal 809 falls and rises during the "low time" of the first half of the clock cycle of the complementary portion of the clock signal, then filter 804D can confirm signal 812D.

[0086] Logic 814 can be configured to receive signals 812A-812D and generate signal 816. According to some embodiments, signal 816 (e.g., HIGH) can be affirmed in response to at least one of signals 812A-812D being affirmed (e.g., HIGH). Furthermore, signal 816 (e.g., LOW) can be negated in response to each of signals 812A-812D being negated (e.g., LOW).

[0087] It should be noted that the difference between signal 808 captured at 804A and signal 808 captured at 804C lies in the timing of the aperture. In other words, short-time pulse interference of the same height / width can be captured, but the timing of the aperture is different (i.e., generated by filter 804A compared to filter 804C). Knowing the timing of the short-time pulse interference can be beneficial and can be decoded as needed (e.g., on logic 814).

[0088] Figure 9 This is a circuit diagram 900 according to various embodiments of the present disclosure. Circuit diagram 900 may be... Figure 8 An example implementation of device 800. Circuit diagram 900 includes several flip-flops 902, several AND gates 904, OR gates 906, inverters 908 and 910, and a set / reset (SR) latch 912.

[0089] Flip-flop 902A can be configured to generate a HIGH output (i.e., at Q) in response to detecting the rising edge of the test signal (“Test Signal”) 903 (“PulseD”) when the clock signal is HIGH. Furthermore, flip-flop 902B can be configured to generate a HIGH output (i.e., at Q) in response to detecting the falling edge of the test signal (“Test Signal”) 903 (“PulseD”) when the clock signal is HIGH. Flip-flop 902C can be configured to generate a HIGH output (i.e., at Q) in response to detecting the test signal (“Test Signal”) 903 (“PulseD”) when the clock signal is LOW. Additionally, flip-flop 902D can be configured to generate a HIGH output (i.e., at Q) in response to detecting the falling edge of the test signal (“Test Signal”) 903 (“PulseD”) when the clock signal is LOW.

[0090] AND gate 904A is configured to respond to a first aperture (e.g., by Figure 8 The rising and falling edges are detected during the period defined by filter 804A (i.e., the clock signal is HIGH for both the rising and falling edges of signal 903) and affirmatively marked. AND gate 904B is configured to respond to the second aperture (e.g., by...) Figure 8 The rising and falling edges are detected during the period defined by filter 804B (i.e., the clock signal is LOW for both rising and falling edges of signal 903) and affirmatively marked. AND gate 904C is configured to respond to the detection of rising and falling edges during the third aperture (e.g., by...). Figure 8 During the detection of rising and falling edges (i.e., the clock signal is HIGH for the rising edge and LOW for the falling edge) during the filter 804C (defined by the filter 804C), a positive flag is generated. Furthermore, the AND gate 904D is configured to respond to the detection of rising and falling edges during the fourth aperture (e.g., by the filter 804C). Figure 8 The rising and falling edges are detected during the period defined by the filter 804D (i.e., the clock signal is LOW for the rising edge of signal 903 and HIGH for the falling edge of signal 903) and affirmatively marked.

[0091] OR gate 906 is configured to affirm short-time pulse interference flag 907 in response to at least one AND gate 904 affirming a flag indicating short-time pulse interference. Furthermore, SR latch 912 is configured to capture short-time pulse interference flag 907. In some embodiments, SR latch 912 may (e.g., periodically) clear short-time pulse interference flag 907.

[0092] As will be understood from circuit diagram 900, flip-flop 902 can be used for rising and falling edge detection, and the system clock can be used as a RESET (or ENABLE) to set the timing aperture of flip-flop 902. It should be noted that by using the system clock, the timing aperture can be adjusted with the clock cycle.

[0093] It should be noted that circuit diagram 900 provides example circuit configurations for implementing various embodiments of this disclosure. However, this disclosure is not limited to circuit diagram 900, and those skilled in the art will understand that other circuit configurations can be used to implement various embodiments of this disclosure.

[0094] As will be understood, the various embodiments disclosed herein may include and / or utilize additional circuitry to perform various operations. More specifically, for example, additional circuitry may be used to regulate one or more signals and / or adjust the timing of one or more signals. More precisely, a multiplexer (not shown) that can be coupled to a pulse detector (e.g., pulse detector 402) may be used to select a specific test signal. As another example, various buffers and / or delay elements may be used to add and / or increase (e.g., delay of signals) and / or align two or more signals (e.g., align a comparison signal (e.g., a clock signal) and a test signal). As yet another example, a clock divider and / or circuitry may be used to clear a marker signal (e.g., after a confirmed short-time pulse interference marker).

[0095] Figure 10 and 11 Curves depicting several signals of a device according to various embodiments of the present disclosure. References Figure 10 Curve 1000 includes a clock signal (e.g., system clock signal) 1002, a test signal 1004, a short-time pulse interference detection signal 1006, and a short-time pulse interference marker 1008. For example... Figure 10 As shown, the first four pulses of test signal 1004 are less than one-quarter of the period of clock signal 1002. Therefore, for each of the first four pulses of test signal 1004, short-time pulse wave interference detection signal 1006 contains a pulse (i.e., a LOW pulse for negative edge detection), and short-time pulse wave interference flag 1008 is confirmed (i.e., approximately at time t1). Furthermore, as... Figure 10 As shown, the short-time pulse wave interference flag 1008 is reset (i.e., approximately at time t2) (e.g., after the complete data burst has been read out).

[0096] refer to Figure 11 Curve 1100 includes a clock signal (e.g., system clock signal) 1102, a test signal 1104, a short-time pulse interference detection signal 1106, and a short-time pulse interference marker 1108. For example... Figure 11As shown, at approximately times t3 and t4, the pulses of test signal 1104 are less than one-quarter of the period of clock signal 1102. Therefore, for each of these pulses of test signal 1104, short-time pulse interference detection signal 1106 contains a pulse (i.e., a LOW pulse for negative edge detection), and short-time pulse interference flag 1108 is confirmed (i.e., between times t3 and t4). Furthermore, as... Figure 11 As shown, the short-time pulse interference flag 1008 is reset (i.e., approximately at time t5). Furthermore, at approximately time t6, the pulse of the test signal 1104 is less than a quarter of the period of the clock signal 1102, and therefore the short-time pulse interference detection signal 1106 contains a pulse at approximately time t7 (i.e., a LOW pulse for negative edge detection), and the short-time pulse interference flag 1108 is confirmed (i.e., approximately at time t7).

[0097] Figure 12 This is a flowchart of an example method 1200 for operating a microelectronic device. Method 1200 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 1200 may be performed by a device or system, such as... Figure 1 Memory device 100 Figure 4 Device 400, Figure 5 Device 500, Figure 6 Device 600, Figure 7 Device 700, Figure 8 Device 800, Figure 9 Circuit diagram 900 Figure 13 Memory system 1300, Figure 14 The electronic system 1400 or another device or system. Although shown as discrete blocks, the individual blocks can be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0098] Method 1200 may begin at block 1202, wherein at least one pulse of a signal of a microelectronic circuit may be detected, and method 1200 may proceed to block 1204. For example, the at least one pulse of a signal (e.g., a DQS signal) may be detected via one or more pulse detectors (e.g., pulse detector 402, pulse detector 502, pulse detector 602, pulse detector 702, or pulse detector 802).

[0099] At block 1204, the width of the at least one pulse of the signal can be compared with a predetermined timing aperture, and method 1200 can proceed to block 1206. For example, the width of the at least one pulse of the signal can be compared with the predetermined timing aperture via one or more filters (e.g., filters 404, 504, 604A, 604B, 704, and 804A-804D). For example, the width of the at least one pulse can be compared with a timing signal defining the predetermined timing aperture. In another example, the width of the at least one pulse can be compared with one or more pulse width thresholds.

[0100] At block 1206, short-time pulse interference can be detected in response to a comparison of the width of the at least one pulse with a predetermined timing aperture, and method 1200 can proceed to block 1208. For example, short-time pulse interference can be detected in response to the at least one pulse containing both a falling edge and a rising edge during the predetermined timing aperture. As another example, short-time pulse interference can be detected in response to the at least one pulse having a width greater than an upper threshold width of the timing aperture or less than a lower threshold width of the timing aperture.

[0101] At box 1208, one or more operations can be performed in response to the detection of short-time pulse interference. For example, in response to the detection of short-time pulse interference and based on one or more mode register settings of the microelectronic device, one or more read and / or write operations can be enabled and / or disabled.

[0102] Modifications, additions, or omissions may be made to method 1200 without departing from the scope of this disclosure. For example, the operations of method 1200 may be performed in different orders. Furthermore, the operations and actions outlined are provided as examples only, and some of the operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without departing from the essence of the disclosed embodiments. For example, in various embodiments, method 1200 may include the operation of receiving a timing signal indicating a predetermined timing aperture at one or more filters (e.g., filters 404, 504, 604A, 604B, 704, and 804A-804D).

[0103] A memory system is also disclosed. The memory system may include a plurality of memory devices. Each memory device may include one or more arrays (e.g., memory arrays) and one or more output drivers, as described herein.

[0104] Figure 13This is a simplified block diagram of a memory system 1300 implemented according to one or more embodiments described herein. The memory system 1300 includes a plurality of memory devices 1302 and a controller 1304. For example, one or more of the memory devices 1302 may include pulse detectors, one or more filters, and / or other circuitry for detecting short-time pulse interference, as described herein. Each memory device 1302, which may include one or more memory cells, may include one or more output driver circuitry, including one or more cell drivers, as described herein.

[0105] An electronic system is also disclosed. The electronic system may include a memory system, which includes a plurality of memory devices. Figure 14 This is a simplified block diagram of an electronic system 1400 implemented according to one or more embodiments described herein. The electronic system 1400 includes at least one input device 1402. The input device 1402 may be a keyboard, mouse, or touchscreen. The electronic system 1400 further includes at least one output device 1404. The output device 1404 may be a monitor, touchscreen, or speaker. The input device 1402 and the output device 1404 are not necessarily separate from each other. The electronic system 1400 further includes a storage device 1406. The input device 1402, the output device 1404, and the storage device 1406 are coupled to a processor 1408.

[0106] The electronic system 1400 further includes a memory system 1410 coupled to the processor 1408. It may include... Figure 13 The memory system 1300 and the memory system 1410 include several memory devices (e.g., Figure 1 (Memory device 100). Electronic system 1400 may include computing, processing, industrial, or consumer products. For example, but not limitingly, electronic system 1400 may include personal computers or computer hardware components, servers or other networking hardware components, handheld devices, tablet computers, electronic notebooks, cameras, telephones, music players, wireless devices, displays, chipsets, games, vehicles, or other known systems.

[0107] One or more embodiments of this disclosure include an apparatus. The apparatus may include a pulse detector configured to detect one or more pulses of a received signal. The apparatus may further include a circuitry coupled to the pulse detector and configured to receive from the pulse detector one or more captured signals indicating the width of the one or more pulses of the received signal. The circuitry may also be configured to compare the width of the one or more pulses of the received signal with a timing aperture defining a pulse width range. Furthermore, the circuitry may be configured to generate a signal indicating short-duration pulse wave interference in response to the width of the one or more pulses of the received signal being outside the pulse width range of the timing aperture.

[0108] Other embodiments of this disclosure include a method. The method may include detecting at least one pulse of a signal from a microelectronic device. The method may also include comparing the width of the at least one pulse of the signal with a predetermined timing aperture. Furthermore, the method may include detecting short-time pulse wave interference based on the comparison of the width of the at least one pulse with the predetermined timing aperture. The method may also include performing one or more operations via the microelectronic device in response to detecting the short-time pulse wave interference.

[0109] Additional embodiments of this disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory system operatively coupled to the at least one processor device. The memory system may include a memory device. The memory device may include a pulse detector configured to detect the width of a plurality of pulses of a test signal. The memory device may also include a filter coupled to the pulse detector. The filter may be configured to receive a timing signal defining a timing period. The filter may also be configured to receive a signal indicating the width of the plurality of pulses of the test signal. Furthermore, the filter may be configured to compare the width of the plurality of pulses of the signal with the timing period to detect short-time pulse wave interference. Additionally, the filter may be configured to generate a marker in response to detecting the short-time pulse wave interference.

[0110] As is customary, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations for describing various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Additionally, some aspects of the drawings may be simplified for clarity. Consequently, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0111] The terms used herein, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0112] Furthermore, if the intention is to use a specific number of introduced claim statements, then this intention will be explicitly stated in the claims, and without such a statement, this intention does not exist. For example, to aid understanding, the appended claims may contain the introductory phrases “at least one” and “one or more” to introduce the claim statements. However, the use of such phrases should not be construed as implying that introducing the claim statements with the indefinite article “a / an” limits any particular claim containing such introduced claim statements to embodiments containing only one such statement, even if the same claim contains the introductory phrases “one or more” or “at least one” and an indefinite article such as “a” (e.g., “a” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles to introduce claim statements. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0113] Furthermore, even when a specific number of the introduced claims are explicitly stated, it should be understood that such a statement should generally be interpreted as referring to at least the number of statements (e.g., a simple statement of "two statements" without other modifiers means at least two statements, or two or more statements). Moreover, in cases where conventions such as "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, such structures are generally intended to include only A, only B, only C, A and B, A and C, B and C, or A, B, and C, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0114] Furthermore, it should be understood that any transitional word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, is intended to include the possibility of including one, any, or both of the stated terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0115] Furthermore, the use of the terms "first," "second," "third," etc., in this document does not necessarily imply a specific order or number of elements. Generally, the terms "first," "second," "third," etc., are used as general identifiers to distinguish different elements. Where the terms "first," "second," "third," etc., do not imply a specific order, they should not be construed as implying a specific order. Similarly, where the terms "first," "second," "third," etc., do not imply a specific number of elements, they should not be construed as implying a specific number of elements.

[0116] The embodiments of this disclosure described above and shown in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, various modifications to this disclosure will become apparent to those skilled in the art from the description, in addition to what is shown and described herein, such as alternative applicable combinations of the described elements. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. A device for detecting short-time pulse wave interference, comprising: A pulse detector configured to detect one or more pulses of a received signal; as well as A circuit system coupled to the pulse detector and configured as follows: Receive one or more captured signals from the pulse detector, indicating the width of the one or more pulses of the received signal; The width of the one or more pulses of the received signal is compared with a timing aperture that defines a pulse width range; and A signal indicating the short-time pulse wave interference is generated in response to the width of one or more pulses of the received signal being outside the pulse width range of the timing aperture.

2. The apparatus of claim 1, wherein the circuit system is further configured to receive a timing signal defining the timing aperture.

3. The apparatus according to claim 2, wherein the pulse detector comprises: A first edge detector is configured to detect a first edge of the signal and generate a first captured signal among the one or more captured signals; as well as A second edge detector is configured to detect a second edge of the signal and generate a second captured signal among the one or more captured signals.

4. The apparatus of claim 3, wherein the circuit system includes at least one filter, the filter being configured to: Compare the first captured signal with the high time of the first half of the clock cycle of the timing signal; Compare the second captured signal with the low time of the second half of the clock cycle of the timing signal; and In response to the first captured signal or the second captured signal containing the short-time pulse wave interference, the signal indicating the short-time pulse wave interference is generated.

5. The apparatus of claim 3, wherein the circuit system comprises: The first filter is configured as follows: Receive the first captured signal and the timing signal; and A first indicator signal is generated in response to the rise and fall of the first captured signal during the high time period of the first half of the clock cycle of the true component of the timing signal. and The second filter is configured as follows: Receive the second captured signal and the timing signal; and In response to the second captured signal falling and rising during the low time period of the second half of the clock cycle of the true component of the timing signal, a second indicator signal is generated.

6. The apparatus of claim 5, further comprising logic coupled to the output of each of the first filter and the second filter, the logic being configured to generate a short-time pulse wave interference mark in response to receiving the first indicator signal or the second indicator signal.

7. The apparatus of claim 5, wherein the circuit system further comprises: The third filter is configured as follows: Receive the first captured signal and the timing signal; and A third indicator signal is generated in response to the rise and fall of the first captured signal during the high time period of the first half of the clock cycle of the complementary component of the timing signal; and The fourth filter is configured as follows: Receive the second captured signal and the timing signal; and A fourth indicator signal is generated in response to the second captured signal falling and rising during the low time period of the second half of the clock cycle of the complementary component of the timing signal.

8. The apparatus of claim 7, further comprising logic coupled to the output of each of the first filter, the second filter, the third filter, and the fourth filter, the logic being configured to generate a short-time pulse wave interference mark in response to receiving the first indicator signal, the second indicator signal, the third indicator signal, or the fourth indicator signal.

9. The apparatus of claim 1, wherein the circuit system is further configured to: The width of the one or more pulses of the received signal is compared with a first width threshold, a second width threshold, or both the first width threshold and the second width threshold; and In response to the width of one or more pulses of the received signal being less than the first width threshold or greater than the second width threshold, a signal indicating the short-time pulse wave interference is generated.

10. A method for operating a microelectronic device, comprising: Detect at least one pulse of the signal from the microelectronic device; Compare the width of the at least one pulse of the signal with a predetermined timing aperture; Short-time pulse wave interference is detected based on a comparison of the width of the at least one pulse with the predetermined timing aperture. as well as In response to the detection of the short-time pulse wave interference, one or more operations are performed via the microelectronic device.

11. The method of claim 10, wherein detecting the short-time pulse wave interference comprises detecting the short-time pulse wave interference in response to the width of the at least one pulse of the signal being greater than an upper limit pulse width threshold of the predetermined timing aperture or less than a lower limit pulse width threshold of the predetermined timing aperture.

12. The method of claim 10, further comprising receiving a timing signal indicating the predetermined timing aperture.

13. The method of claim 12, wherein receiving the timing signal includes receiving a pulse or clock signal.

14. The method of claim 13, wherein detecting the at least one pulse of the signal comprises capturing each of a positive pulse and a negative pulse of the signal.

15. The method of claim 14, wherein comparing the width of the pulse of the signal with a predetermined timing aperture comprises: Compare the positive pulse with the positive signal of the timing signal; and Compare the negative pulse with the negative signal of the timing signal.

16. The method of claim 10, wherein performing the one or more operations in response to detecting the short-time pulse wave interference includes performing the one or more operations in response to detecting the short-time pulse wave interference and based on one or more mode register settings.

17. An electronic system comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the input device and the output device; as well as At least one memory system operatively coupled to the at least one processor device, the memory system comprising: A memory device, the memory device comprising: A pulse detector configured to detect the width of several pulses of a test signal; as well as A filter, coupled to the pulse detector and configured to: Receive timing signals with a defined timing period; Receive a signal indicating the width of the plurality of pulses of the test signal; The widths of the plurality of pulses of the signal are compared with the timing period to detect short-time pulse wave interference; and A marker is generated in response to the detection of the short-time pulse wave interference.

18. The electronic system of claim 17, wherein the pulse detector comprises a plurality of triggers, wherein each of the plurality of triggers is configured to receive the test signal.

19. The electronic system of claim 18, wherein the filter comprises a plurality of AND gates, each of the plurality of AND gates being configured to receive signals from two of the plurality of flip-flops.

20. The electronic system of claim 19, further comprising an OR gate configured to receive an output from each of the plurality of AND gates.

21. The electronic system of claim 17, wherein the memory device further includes one or more mode registers, wherein one or more settings of the one or more mode registers are configured to define one or more operations performed in response to the detection of the short-time pulse wave interference.

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