Interleaved two-pass data programming technique to reduce write amplification

Abstract

This application relates to an interleaved two-pass data programming technique to reduce write amplification. In coarse programming, the threshold voltage of a memory cell is programmed to a first level representing N-1 bit values ​​based on a first mapping between combinations of N-1 possible bit values ​​and a threshold level. A group identifier indicates whether the first level is an odd or even level in the first mapping. For fine programming, based on the group identifier, the memory cell is read to obtain the N-1 bit values; and at least one additional bit is received to join the N-1 bit values ​​to form at least N bit values. Then, the threshold voltage of the memory cell is finely programmed to a second level representing the at least N bit values ​​based on a second mapping between combinations of the at least N possible bit values ​​and a threshold level.

Description

Technical Field

[0001] At least some of the embodiments disclosed herein generally relate to memory systems, and more specifically, but not limited to, techniques for programming voltage thresholds of memory cells in a memory system to store multiple data bits per memory cell. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this application relates to a method comprising: receiving a first number of data bits; programming a threshold voltage of a first memory cell to a first level representing a combination of bit values ​​from the first number of data bits, based on a first mapping between a combination of bit values ​​from the first number of data bits and a threshold level; calculating a group identifier indicating whether the first level is an odd or even level in the first mapping; reading the first memory cell having the threshold voltage programmed to the first level to obtain the first number of data bits based on the group identifier; receiving at least one additional data bit, wherein the at least one additional data bit and the first number of data bits obtained from the reading form a second number of data bits; and programming the threshold voltage of the first memory cell to a second level representing a combination of bit values ​​from the second number of data bits, based on a second mapping between a combination of bit values ​​from the second number of data bits and a threshold level.

[0004] Another aspect of this application relates to a memory device comprising: an integrated circuit package enclosing the memory device; a plurality of memory cell groups formed on at least one integrated circuit die; and a latch; wherein, in response to a command identifying a first memory cell group within the plurality of memory cell groups, the memory device is configured to receive a first number of data bit groups; program the first memory cell group to store the first number of data bit groups, wherein, based on a first mapping between combinations of bit values ​​in the first number of data bits and a threshold level, a threshold voltage of each corresponding memory cell in the first memory cell group is programmed to a first level representing a combination of bit values ​​in the first number of data bits; and calculate a group identifier for the corresponding memory cell, the group... The identifier indicates whether the first level is an odd or even level in the first mapping; the first memory cell group is read based on the group identifier to retrieve the first number of data bit groups into a first portion of the latch; an additional data bit group is received into a second portion of the latch, wherein the additional data bit group and the first number of data bit groups form a second number of data bit groups in the latch; and the first memory cell group is programmed to store the second number of data bit groups, wherein the threshold voltage of the corresponding memory cell in the first memory cell group is programmed to a second level representing the combination of bit values ​​in the second number of data bits according to a second mapping between the combination of bit values ​​in the second number of data bits and a threshold level.

[0005] Another aspect of this application relates to a memory subsystem comprising: a processing means; and at least one memory means having a plurality of page memory cells, including a first page memory cell and a second page memory cell; wherein the processing means is configured to provide a first number of data pages to the memory means and identify the first page memory cell; wherein, in response to the first number of data pages, the memory means is configured to: perform a first pass programming on a threshold voltage of a memory cell in the first page to store the first number of data pages according to a first mapping between the values ​​of bits in the first number of data bits and a threshold level; calculate a page group identifier, each corresponding group identifier in the page group identifier identifying a corresponding mapping to read the first page memory. The corresponding memory cell in the memory unit; caching the page group identifier in the second page memory cell; reading the first page memory cell using the page group identifier buffered in the second page memory cell; wherein the processing means is configured to provide additional data pages to the memory device; and wherein, in response to the additional data pages, the memory device is configured to: perform a second pass programming on the threshold voltage of the memory cell in the first page to store a second number of data pages, the second number of data pages including the additional data pages and the first number of data pages retrieved from the first page memory cell using the page group identifier buffered in the second page memory cell. Attached Figure Description

[0006] Embodiments are illustrated by way of example rather than limitation in the accompanying drawings, in which the same reference numerals indicate the same elements.

[0007] Figure 1 An instance computing system having a memory subsystem is described according to some embodiments of this disclosure.

[0008] Figure 2 According to one embodiment, an integrated circuit memory device having a programming manager configured to program threshold voltages of memory cells to store data is described.

[0009] Figure 3 One embodiment illustrates an instance of a programmable memory cell storing multiple bits per memory cell.

[0010] Figure 4 One embodiment illustrates a two-pass programming technique where multiple bits are stored per memory cell.

[0011] Figure 5 The voltage distribution for two-pass programming of a memory cell is illustrated according to one embodiment.

[0012] Figure 6 One embodiment illustrates mapping to threshold levels and group identifiers in two-pass programming of a memory cell to store data.

[0013] Figure 7 A method for two-pass programming of memory cells is shown according to some embodiments.

[0014] Figure 8 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0015] At least some aspects of this disclosure are directed to techniques for improving the storage of multiple bits per memory cell in a memory subsystem. The following are combined with... Figure 1 Describe examples of storage devices and memory modules. Typically, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] Integrated circuit memory cells (e.g., flash memory cells) can be programmed to store data by being in a predefined voltage state. For example, if a memory cell is configured / programmed to allow a large current to flow through it at a predefined voltage, then the memory cell stores a positive bit 1; otherwise, it stores a positive bit 0. Furthermore, a memory cell can store multiple data bits by being configured / programmed differently at multiple predefined voltages. For example, a memory cell can store multiple data bits through a combination of states with multiple predefined voltages; and different combinations of states of the memory cell at predefined voltages can be interpreted as representing different states of data bits stored in the memory cell.

[0017] While the threshold voltage of a memory cell can be adjusted / programmed by applying voltage pulses to the cell, it is typically difficult to precisely adjust / program the threshold voltage to a predefined voltage. A typical programming operation moves the threshold voltage of the memory cell to a voltage range where the probability level of the threshold voltage change actually lies at different voltages within the threshold distribution region.

[0018] Therefore, programming operations can move the threshold voltage of a memory cell to a threshold distribution region where the probability density level of any voltage within that region is higher than a predefined threshold density. Programming operations that produce a wide threshold distribution region are coarse and therefore less accurate than those that produce a narrow threshold distribution region. Coarse programming operations are generally faster than fine, accurate programming operations.

[0019] In order to store multiple bits per memory cell, the threshold voltage of the memory cell can be programmed into different regions so that each region represents a different combination of bit values.

[0020] To reduce the probability of errors when reading memory cells, it is desirable to reduce, minimize, and / or eliminate overlap in the threshold voltage region caused by programming operations. Increasing the number of bits stored per memory cell necessitates a reduction in the width of the threshold voltage distribution region, and consequently, a requirement for improved precision / accuracy of programming operations.

[0021] Improving the precision / accuracy of programming operations typically results in longer data programming timeframes. As the time spent programming the threshold voltage of a memory cell increases, the speed at which data is stored in the memory cell decreases.

[0022] By programming the threshold voltage of a memory cell to a narrow threshold distribution region, multiple programming passes can be used to accelerate data storage in the memory cell. An initial coarse programming pass can be used to quickly move the threshold voltage of the memory cell with lower precision. Therefore, the threshold voltage of the memory cell is moved to a relatively wide threshold distribution region. Subsequent fine programming passes can be used to fine-tune the threshold voltage of the memory cell and move it to a relatively narrower region of the threshold voltage distribution to reduce the probability of read errors. A combination of coarse and fine programming can be faster than directly programming the memory cell to a narrow threshold distribution region.

[0023] Multiple-pass programming can increase the complexity of circuit systems used for it. For example, in some implementations, buffers can be used to store input data for subsequent passes. Optionally, some memory cells in the memory device can be used in single-level cell (SLC) mode to temporarily store / buffer input data, one bit per memory cell, for subsequent use in the next pass. From the user's perspective, such an arrangement eliminates the need for a separate type of memory cell for buffering data, but increases write amplification of the memory device and / or reduces available memory / storage capacity.

[0024] At least some aspects of this disclosure address the aforementioned and other drawbacks by coarsely programming each memory cell to reduce the number of bits (e.g., 3 bits per cell) in a manner that allows the coarsely programmed memory cells to be reliably used as buffers. To improve the speed and / or accuracy of retrieving data from the coarsely programmed memory cells, an indicator is stored to identify the possible threshold level of the memory cell. The indicator may be stored in available memory in a single-level cell (SLC) mode (e.g., 1 bit per cell).

[0025] Because the indicator eliminates some threshold levels from the possibility of reading memory cells, coarsely programmed memory cells can be read accurately (e.g., in multi-level cell (MLC) mode (e.g., 2 bits per cell)), even when the threshold distribution region resulting from coarse programming is very wide for a reduction of several bits per cell (e.g., 3 bits per cell) in normal operation. In some embodiments, the indicator can be calculated based on an XOR or XNOR operation to eliminate the possibility of alternating threshold levels being programmed for storing a reduction of several bits per memory cell.

[0026] After retrieving a reduced number of data bits per memory cell from the coarsely programmed memory cells with the help of an indicator, additional data can be received to form a dataset of a predetermined number of bits per memory cell (e.g., 4 bits per cell); and then fine programming operations can be applied to store the entire dataset in a predetermined number of bits per memory cell (e.g., 4 bits per cell).

[0027] This type of programming technique can reduce the need for separate memory units to buffer data for fine-pass programming, reduce write amplification, and / or increase the memory / storage capacity available to the user.

[0028] Figure 1 An example computing system 100 including a memory subsystem 110 is described according to some embodiments of this disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transportation), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing devices.

[0031] The computing system 100 may include a host system 120, which is coupled to one or more memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes, for example, electrical, optical, magnetic, and other connections.

[0032] Host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., controller 116) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120, for example, uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0033] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Bus Attached (SATA) interfaces, PCIe interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Connected SCSI (SAS) interfaces, Dual Data Rate (DDR) memory bus interfaces, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR) interfaces, Low Power Dual Data Rate (LPDDR) interfaces, or any other interfaces. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize high-speed NVM (NVMe) interface access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Typically, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] The processing unit 118 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processor core, an execution unit, etc. In some cases, the controller 116 may be referred to as a memory controller, a memory management unit, and / or a starter. In one example, the controller 116 controls communication via a bus coupled between the host system 120 and the memory subsystem 110. Typically, the controller 116 may send commands or requests to the memory subsystem 110 to perform desired access to memory devices 130, 140. The controller 116 may further include an interface circuitry for communicating with the memory subsystem 110. The interface circuitry can translate responses received from the memory subsystem 110 into information for the host system 120.

[0035] The controller 116 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations such as reading, writing, or erasing data at memory devices 130, 140, and other such operations. In some cases, the controller 116 is integrated within the same package as the processing device 118. In other cases, the controller 116 is packaged separately from the processing device 118. The controller 116 and / or the processing device 118 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or combinations thereof. The controller 116 and / or the processing device 118 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] Memory devices 130 and 140 may include different types of non-volatile memory components and / or any combination of volatile memory components. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Some examples of non-volatile memory components include negative-AND (or NAND, NAND) type flash memory and in-situ write memory, such as three-dimensional crosspoint ("3D crosspoint") memory. Crosspoint arrays of non-volatile memory can be combined with stackable cross-grid data access arrays to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash memory-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without pre-erasing them. For example, NAND type flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0039] Although a non-volatile memory device is described as such as 3D cross-type and NAND type memory (e.g., 2D NAND, 3D NAND), the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0040] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled on the command bus via controller 116). Controller 115 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (e.g., hard-coded) logic to perform the operations described herein. Controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0041] Controller 115 may include processing means 117 (e.g., a processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of controller 115 includes embedded memory configured to store instructions for performing operations of control memory subsystem 110 (including handling communication between memory subsystem 110 and host system 120).

[0042] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetching data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including controller 115, but in other embodiments of the present disclosure, memory subsystem 110 does not include controller 115 and may instead rely on external control (e.g., via an external host, or via a processor or controller separate from the memory subsystem).

[0043] Typically, controller 115 receives commands or operations from host system 120 and translates these commands or operations into instructions or appropriate commands to enable desired access to memory device 130. Controller 115 may handle other operations such as wear leveling, garbage collection, error detection and correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. Controller 115 may further include host interface circuitry for communicating with host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into command instructions to access memory device 130 and translates responses associated with memory device 130 into information for host system 120.

[0044] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory device 130.

[0045] In some embodiments, memory device 130 includes a local media controller 150 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device contained within the same memory device package as the local controller for media management (e.g., local media controller 150). An example of a managed memory device is a managed NAND (MNAND) device.

[0046] Controller 115 and / or memory device 130 may include a programming manager 113 configured to perform interleaved two-pass data programming with reduced write amplification. In some embodiments, controller 115 in memory subsystem 110 and / or controller 150 in memory device 130 may include at least a portion of programming manager 113. In other embodiments, or in combination, controller 116 in host system 120 and / or processing device 118 includes at least a portion of programming manager 113. For example, controller 115, controller 116, and / or processing device 118 may include a logic circuitry system implementing programming manager 113. For example, controller 115 or processing device 118 of host system 120 (e.g., a processor) may be configured to execute instructions stored in memory to perform the operation of programming manager 113 as described herein. In some embodiments, programming manager 113 is implemented in an integrated circuit chip disposed in memory subsystem 110. In other embodiments, the programming manager 113 may be part of the firmware of the memory subsystem 110, the operating system of the host system 120, a device driver or application, or any combination thereof.

[0047] For example, a programming manager 113 implemented in controller 115 and / or controller 150 may initially receive a reduced number (e.g., N-1) data groups (e.g., pages) for programming into a group of memory cells in memory device 130, which will then be programmed to store a predetermined number (e.g., N) bits per memory cell. The programming manager 113 generates a set of (e.g., page) indicators by applying an XOR (or XNOR) operation to the reduced number of data groups. The programming manager 113 initiates coarse programming to store the reduced number (e.g., N-1) data groups (e.g., pages) into the group of memory cells, where each memory cell in the group stores one bit from each of the reduced number (e.g., N-1) data groups. Each memory cell in the group of memory cells has a corresponding indicator bit (e.g., generated based on an XOR or XNOR operation on its bits stored via coarse programming). The indicator identifies a set of possible threshold levels for the memory cell. When the indicator bit has a value, the possible threshold levels of the group of memory cells correspond to an even threshold level that stores a reduced number (e.g., N-1) bits per memory cell; and when the indicator bit has another value, the set of possible threshold levels of the memory cells corresponds to an odd threshold level that stores a reduced number (e.g., N-1) bits per memory cell. Memory cells with an indicator bit equal to 1 can be considered to be in a first group programmed with N-2 bits per memory cell; and memory cells with an indicator bit equal to 0 can be considered to be in a second group programmed with N-2 bits per memory cell; and the threshold distribution regions of the first and second groups are configured to be interleaved and correspond to threshold levels that store N-1 bits per memory cell. Therefore, the possible threshold levels of different indicator bits are interleaved. The indicator bit allows the memory device 130 to read coarsely programmed memory cells to retrieve a reduced number (e.g., N-1) bits by reading in an N-2 bit per memory cell mode based on the indicator value. After receiving another data set, fine programming operations can be performed to store a predetermined number (e.g., N) of data sets into a group of memory cells that have been coarsely programmed.

[0048] Figure 2 An integrated circuit memory device having a programming manager is described according to one embodiment. The programming manager is configured to program threshold voltages of memory cells to store data. For example, Figure 1 The memory device 130 in the memory subsystem 110 can be used Figure 2 The integrated circuit memory device 130 is used for implementation.

[0049] The integrated circuit memory device 130 may be encapsulated in a single integrated circuit package. The integrated circuit memory device 130 includes multiple sets of memory cells 131, ..., 133 that may be formed in one or more integrated circuit dies. A typical memory cell in set 131 (or set 133) may be programmed to store one or more data bits.

[0050] Some of the memory cells in the integrated circuit memory device 130 can be configured to operate together for specific types of operations. For example, memory cells on an integrated circuit die can be organized into planes, blocks, and pages. A plane contains multiple blocks; a block contains multiple pages; and a page can have multiple strings of memory cells. For example, an integrated circuit die can be the smallest unit capable of independently executing commands or reporting status; the same concurrent operation can be performed in parallel on multiple planes in the integrated circuit die; a block can be the smallest unit for performing an erase operation; and a page can be the smallest unit for performing a data programming operation (writing data into a memory cell). Each string connects its memory cells to a common bit line; and the control gates of memory cells at the same location in a string within a block or page are connected to a common word line. Control signals can be applied to the word line and bit line to address individual memory cells.

[0051] Integrated circuit memory device 130 has a communication interface 147 to receive a command with address 135 from controller 115 of memory subsystem 110, retrieve memory data 144 from the memory cell identified by memory address 135, and at least provide memory data 144 as part of a response to the command. Optionally, memory device 130 may decode memory data 144 (e.g., using error correction code (ECC) technology) and provide the decoded data as part of a response to the command. Address decoder 141 of integrated circuit memory device 130 translates address 135 into a control signal to select a set of memory cells in integrated circuit memory device 130; and read / write circuitry 143 of integrated circuit memory device 130 performs an operation to determine memory data 144 stored in the memory cell at address 135.

[0052] Integrated circuit memory device 130 has a set of latches 145 to temporarily hold memory data 144 while read / write circuitry 143 is programming a threshold voltage of a memory cell group (e.g., 131 or 133). For example, read / write circuitry 143 may program the threshold voltage of a memory cell in memory cell group 131 to store N bits per memory cell. The memory cell group (e.g., 131 or 133) has M memory cells. Latches 145 are configured to store N×M data bits in N data groups. Each data group has M data bits to be stored in the M memory cells of the memory cell group (e.g., 131 or 133).

[0053] When latch 145 has N data sets to be stored in a memory cell group (e.g., 131), programming manager 113 is configured to determine and program the threshold voltage levels of the memory cells in the memory cell group (e.g., 131). The threshold voltage levels can be determined based on the bit values ​​in memory data 144 and Gray code that maps combinations of bit values ​​to threshold levels, such that any two combinations of bit values ​​represented by two consecutive threshold levels differ by exactly one bit.

[0054] In one embodiment, memory device 130 initially receives N-1 data groups for coarsely programming threshold voltages of memory cells in a group of memory cells (e.g., 131). The coarse programming operation moves the threshold voltage of the memory cells to a voltage region close to the threshold level used to store the N data groups. The coarse programming is configured to store the N-1 data groups into the group of memory cells, where each memory cell stores one bit from each of the N-1 data groups. The coarse programming maps the N-1 bit values ​​to be stored in each memory cell to their coarsely programmed threshold level. The coarse threshold level is 2N-1 times the value of the N-1 bits. N-1 One of the possible combinations. An indicator is generated to identify whether the coarse threshold level for each memory cell is odd or even. Therefore, the value of the indicator reduces the possible voltage level of each memory cell to 2. N-2 This allows the read / write circuit 143 to distinguish 2 N-2 A threshold level is used to read N-1 bits of data stored in each memory cell. This arrangement reduces the precision requirements of coarse programming and the time required to perform coarse programming, and / or improves the accuracy of reading N-1 bits from each coarsely programmed memory cell. Group indicators can be stored in another group of memory cells (e.g., 133) used as buffers to eliminate the need to manufacture different types of memory cells as buffers. For example, in SLC mode, the indicators can be stored in a buffered group of memory cells (e.g., 133) to achieve improved speed and increased programming / erasing budget, compared to other modes that store more than one bit per memory cell. After coarse programming, memory device 130 receives additional data groups (e.g., from controller 115 of memory subsystem 110) and reads N-1 data groups from the coarsely programmed group of memory cells (e.g., 131) to form N data groups. A fine programming operation is performed to store the N data groups in the previously coarsely programmed group of memory cells (e.g., 131). Fine programming moves the threshold voltage of memory cells in a group (e.g., 131) to a region with a fine threshold distribution that allows N data sets to be read from the memory cell group (e.g., 131). NA threshold level. After reading N-1 data groups from a coarsely programmed group of memory cells (e.g., 131), the indicator group can be discarded.

[0055] In some implementations, the threshold levels for coarse and fine programming are determined using Gray code, such as in... Figure 6 As explained in [the document], Gray code maps combinations of bit values ​​to threshold levels such that when the threshold level represented by the bit value combination changes to the next larger or smaller threshold level, one and only one bit of the bit value changes. In some implementations, indicator groups can be computed by applying an XOR (or XNOR) to N-1 data groups.

[0056] Figure 3 An example is shown according to one embodiment, where a programmable memory cell stores multiple bits per memory cell. For example, Figure 3 Instances can be found Figure 1 and / or Figure 2 It is implemented in the memory device 130.

[0057] exist Figure 3 In this configuration, memory cell group 131 has memory cells 137, ..., 139. Multiple data groups 151, 157, ..., 159 provide data bits to be stored in memory cells 137, ..., 139. The number of bits provided in each data group (e.g., 157, 159, or 151) is equal to the number of memory cells 137 to 139 in memory cell group 131. Each memory cell (e.g., 139 or 137) stores a set of bits, one from each of data groups 151, 157, ..., and 159.

[0058] For example, data bits 161, 163, ..., 165 from data groups 151, 157, ..., 159 are stored in a memory cell 137; and the voltage threshold of memory cell 137 is programmed by read / write circuit 143 to be at a level representing the value of data bits 161, 163, ..., 165. Similarly, data bits 171, 173, ..., 175 from data groups 151, 157, ..., 159 are stored in another memory cell 139, and are represented by the voltage threshold level of memory cell 139.

[0059] Optionally, the data bits in the data group can be organized in codewords 153, ..., 155 according to error detection and data recovery techniques, such as error correction codes (ECC) (e.g., low-density parity-check (LDPC) codes).

[0060] For example, codeword 153 in data group 151 may contain data bits 161 to 162. When one of the data bits in codeword 153 is faulty, the fault can be detected and corrected (e.g., using low-density parity check (LDPC) technology).

[0061] When data groups 151, 157, ..., 159 are stored in latches 181, 183, ..., 185, the read / write circuit 143 reads 149 threshold values ​​of programmable memory cells 137, ..., 139 such that the voltage threshold values ​​of memory cells 137, ..., 139 represent the values ​​of the corresponding data bits from data groups 151, 157, ..., 159.

[0062] Based on Gray code, combinations of values ​​of data bits (e.g., 161, 163, ..., 165) to be stored in memory cells (e.g., 137) are mapped to the voltage threshold level of the memory cell (e.g., 137). For example, read / write circuit 143 may include a Gray code table (e.g., such as...). Figure 6 (As illustrated in the table) a threshold level of a set of data bits (e.g., 161, 163, ..., 165) in a memory cell (e.g., 137) and a memory cell (e.g., 137) representing the value of the set of data bits (e.g., 161, 163, ..., 165).

[0063] To expedite the programming of 149 threshold voltages for memory cells 137, ..., 139 to store data sets 151, 157, ..., 159, read / write circuitry 143 can be configured to use two programming operations. In the first coarse programming, the threshold voltages of memory cell set 131 are shifted to a relatively wide threshold distribution region near the fine threshold distribution region. The coarsely programmed threshold voltages are determined based on the threshold levels representing data sets 157, ..., 159. A set of threshold level indicators is temporarily calculated and stored / buffered to assist in accurately reading data sets 157 to 159 from the coarsely programmed memory cell set 131. After reading data groups 157 to 159 back into latches 183, ..., 185 and further receiving data group 151 into latch 181, the read / write circuit 143 can perform fine programming to move the threshold voltages of memory cells 137, ..., 139 to a fine threshold distribution region representing the data bits in data groups 151, ..., 157, 159, as described below. Figure 4 , 5 And / or 6, further detailed discussion.

[0064] Figure 4 One embodiment illustrates a two-pass programming technique where multiple bits are stored per memory cell. For example, Figure 4 The technology can Figure 1 In the memory subsystem 110 Figure 2 It is implemented in the memory device 130.

[0065] exist Figure 4 In this process, a reduced number of (N-1) data bits 163 to 165 are used to determine the coarse programming threshold level T 203 by mapping 201 between bit value combinations and coarse programming threshold levels.

[0066] All possible coarsely programmed threshold levels are classified into two groups. For example, the coarsely programmed threshold levels are numbered in ascending order. Classification 205 is configured to place even levels in the even array and odd levels in the odd array. Group identifier 207 indicates whether the threshold level 203 of memory cell 137 is in the even array or the odd array. The even and odd arrays can be programmed into an interleaved threshold distribution region close to the final threshold region.

[0067] The first pass of threshold programming 219 is performed to move the threshold voltage 221 of memory cell 137 in memory cell group 131 to a relatively wide threshold distribution region. Read / write circuitry 143 may store the group identifier 207 of memory cell 137 in another memory cell 191 (e.g., in a different memory cell group 133 in SLC mode).

[0068] To finely program memory cell 137 to store data bits 161, 163, ..., 165, read / write circuit 143 can read 211 the group identifier of memory cell 137 from memory cell 191 to assist in the operation of retrieving data bits 163 to 165 from memory cell 137. Group identifier 207 eliminates half of the possible threshold levels representing the values ​​of data bits 163 to 165. Therefore, the group identifier allows read / write circuit 143 to determine the values ​​of data bits 163, ..., 165 based on threshold voltage 221, which is coarsely programmed into a relatively wide threshold distribution region, such as in... Figure 5 As explained in the document, the read / write circuit 143 can read data bits 163, ..., 165 from memory cell 137 into latches 183, ..., 185, respectively.

[0069] In order to fine-program memory cell 137, memory device 130 will further receive 215 data bits 161 from controller 115 of memory subsystem 110. When data bits 161, 163, ..., 165 are in latches 181, 183, ..., 185 respectively, read / write circuit 143 can determine fine-programming threshold level 223 by mapping 217 between bit value combination and fine-programming threshold level.

[0070] A second pass of threshold programming 229 is performed to move the threshold voltage 225 of memory cell 137 in memory cell group 131 to a relatively narrow threshold distribution region. The region is narrow enough to allow read / write circuitry 143 to determine data bits 161, 163, ..., 165 based on the sensed threshold voltage 225 of memory cell 137.

[0071] Figure 4 This illustrates an example where N-1 bits are programmed in the first pass and N bits are programmed in the second pass. Typically, the first pass can be configured to program Nj bits; and the second pass is used to program an additional j bits, so that a total of N bits are programmed through the two passes.

[0072] Figure 5 The voltage distribution for two-pass programming of a memory cell is illustrated according to one embodiment. For example, it can be based on... Figure 5 To implement the distribution described in the document Figure 4 Two-pass programming techniques are used to store data in QLC mode (four bits per memory cell).

[0073] exist Figure 5 In order to program memory cell 137 to store data in QLC mode, the threshold voltage of the memory cell is shifted to a voltage range of V0, V2, ..., V... 15 The threshold voltage is one of 16 QLC threshold levels 0, 1, ..., 15 centered at V0. For example, when memory cell 137 is programmed to QLC threshold level 0, curve 241 centered at V0 illustrates the probability level of the threshold voltage of memory cell 137 being close to V0. The voltage range of curve 241 represents the threshold distribution region at QLC threshold level 0.

[0074] Similarly, when memory cell 137 is programmed to QLC threshold level 1, curve 243 centered on V1 illustrates that the probability level of the threshold voltage of memory cell 137 is close to V1. The voltage range of curve 243 represents the threshold distribution region at QLC threshold level 1.

[0075] At voltage region 249, curves 241 and 243 overlap, indicating an ambiguity regarding whether memory cell 137 is programmed to be at threshold level 0 to represent one set of bit values ​​or at threshold level 1 to represent another set of bit values ​​when the threshold voltage of memory cell 137 is found in region 249. When the mapping between bit value combinations and threshold levels is based on Gray code, the bit values ​​represented by threshold level 0 and threshold level 1 differ by one bit. Therefore, the probability of this bit, determined based on the threshold voltage of memory cell 137, being read incorrectly is small. Errors in such bits can typically be detected and corrected via ECC / LPDC decoding of the codeword (e.g., 153) in the data group (e.g., 151) containing the bit. Reducing the overlapping region improves the accuracy of reading memory cell 137. However, reducing the width of distribution curves 241 and 243 requires higher accuracy and therefore a longer time to program the threshold voltage of memory cell 137.

[0076] exist Figure 5 In order to program the threshold voltage of memory cell 137 to a QLC level with narrow distribution curves 241, 243, etc., the read / write circuit 143 of memory device 130 initially coarsely programs the memory cell to TLC levels 0, 1, ..., 7 based on three data bits (e.g., 163, ..., 165) of the four data bits (e.g., 161, 163, ..., 165) to be stored in memory cell 137.

[0077] For example, when the three data bits of memory cell 137 are coarsely programmed to the TLC threshold level 0, curve 251 centered on the TLC level V0 illustrates that the probability level of the threshold voltage of memory cell 137 is close to V0. The voltage range of curve 251 represents the threshold distribution region at the TLC threshold level 0.

[0078] Similarly, when the three data bits of memory cell 137 are coarsely programmed to TLC threshold level 1, curve 253, centered on TLC level V1, illustrates that the probability level of the threshold voltage of memory cell 137 is close to V1. The voltage range of curve 253 represents the threshold distribution region of TLC threshold level 1.

[0079] At voltage region 259, TLC curves 251 and 253 overlap. Reducing the overlap between TLC curves 251 and 253 can result in a longer time to perform coarse programming.

[0080] To reduce coarse programming time without compromising the accuracy of reading the three data bits programmed using TLC levels, a memory group identifier 207 is calculated and / or used to indicate whether memory cell 137 is programmed to an odd TLC threshold level or an even TLC threshold level.

[0081] When group identifier 207 indicates that memory cell 137 has been coarsely programmed to an even TLC threshold level, the possible threshold voltage distribution is represented by alternating curves 251, 255, etc. A distribution curve for odd TLC threshold levels (e.g., curve 253 centered on V1) is not possible. Therefore, when the threshold voltage of memory cell 137 is found in region 259, there is no ambiguity in the values ​​of the three bits programmed via the threshold voltage of memory cell 137.

[0082] Similarly, when group identifier 207 indicates that memory cell 137 is coarsely programmed to an odd TLC threshold level, the possible threshold voltage distribution is represented by alternating curves 253, 257, etc. A distribution curve for an even TLC threshold level (e.g., curve 251 centered on V1) is not possible. Therefore, when a threshold voltage of memory cell 137 is found in region 259, there is no ambiguity in the values ​​of the three data bits programmed via the threshold voltage of memory cell 137.

[0083] Group identifier 207 allows read / write circuitry 143 to distinguish alternating TLC profiles 251, 255, ... for memory cells coarsely programmed based on even-array levels, or alternating TLC profiles 253, 257, ... for memory cells coarsely programmed based on odd-array levels. Since reading even-array levels (or odd-array levels) corresponds to determining one of four possible states, the profiles (251, 255, ...; 253, 257, ...) can be as coarse as those for programming in MLC mode; and coarsely programmed memory cells 137 can be read in the MLC mode identified by group identifier 207.

[0084] For example, based on group identifier 207 to identify memory cell 137 coarsely programmed according to even array levels, read / write circuit 143 can use MLC read mode to determine the coarsely programmed threshold level of memory cell 137 and thus the three data bits (e.g., 163, ..., 165) stored in memory cell 137 by coarse programming.

[0085] Similarly, based on group identifier 207 to identify memory cell 137 coarsely programmed according to odd array levels, read / write circuit 143 can use MLC read mode to determine the coarsely programmed threshold level of memory cell 137 and thus the three data bits (e.g., 163, ..., 165) stored in memory cell 137 by coarse programming.

[0086] From another perspective, even-array levels can be seen as the result of programming the corresponding data to even-array levels in the first MLC mode; and even-array levels can be seen as the result of programming the corresponding data to odd-array levels in the second MLC mode. The first MLC mode and the second MLC mode are configured such that their threshold distribution regions are interleaved as in TLC levels and consistent with TCL levels. Therefore, based on group identifier 207, memory cell 137 will be read according to either the first MLC mode or the second MLC mode.

[0087] After the threshold voltage of memory cell 137 is coarsely programmed to the TLC level, the threshold voltage of memory cell 137 can be further finely programmed to the nearby QLC level identified by the four data bits (e.g., 161, 163, ..., 165) to be stored in memory cell 137.

[0088] For example, when memory cell 137 is initially programmed to a TLC level of 0 with distribution curve 251, additional data bits (e.g., 161) of memory cell 137 can further identify whether memory cell 137 will be programmed to a QLC level of 0 or 1, respectively, represented by distribution curves 241 or 243. Since memory cell 137 has already been coarsely programmed to have a probability level of voltage close to V0, which is close to the TLC level represented by the wide distribution curve 251, it takes less time to further finely program it to a QLC threshold level of 0 or 1 with a narrow distribution curve 241 or 243 (less than the threshold voltage of directly programming memory cell 137 based on the erased state).

[0089] Figure 6 One embodiment illustrates mapping threshold levels and group identifiers to store data during two-pass programming of a memory cell. For example, Figure 6 The mapping can be compared with Figure 5 Use it together with the distribution curves described in the document.

[0090] Figure 6 This illustrates an example of data programming in QLC mode, where the threshold voltage of a memory cell (e.g., 137) is programmed to represent a four-bit value. A page of memory cells is programmed (written) together. Since each cell stores four bits, the page memory cell can store the data bits of four data pages, where the number of data bits in a data page equals the number of memory cells in the memory cell page. For example, each data page is... Figure 3 The examples of the data groups described herein; and memory cell pages are Figure 3 Examples of memory cell groups described herein.

[0091] Conventionally and / or for convenience, the four data pages in QLC mode are named Lower Page (LP), Upper Page (UP), Extra Page (XP), and Previous Page (TP), respectively. A memory cell (e.g., 137) in QLC mode stores one bit from each of the four pages. Since the values ​​of the four data bits stored in the memory cell (e.g., 137) have 16 different combinations, as in... Figure 6 As illustrated in the table shown, the threshold voltage of the memory cell (e.g., 137) is programmed to one of 16 QLC threshold levels to represent the corresponding combination of bit values.

[0092] Figure 6 The table shown illustrates an example of Gray code, which maps the values ​​of four data bits (e.g., 161, 163, ..., 165) stored in a QLC memory cell (e.g., 137) to a threshold level 203 of the memory cell (e.g., 137). For example, when a memory cell (e.g., 137) is determined to have a QLC threshold level of 0, the memory cell (e.g., 137) is considered to store 1 as a TP bit, 1 as an XP bit, 1 as an UP bit, and 1 as an LP bit. Similarly, in order to store 0, 1, 1, and 1 as TP, XP, UP, and LP bits in the memory cell (e.g., 137), the threshold voltage is programmed to level 1. An increased threshold level represents an increased threshold voltage to be programmed for the memory cell (e.g., 137).

[0093] Gray code (e.g., as in...) Figure 6 (As illustrated in the table) has characteristics / properties where one and only one bit value changes between two consecutive threshold levels. For example, when the QLC threshold level changes from 0 to 1, in Figure 6 In the table, only the TP bit changes from 1 to 0. Similarly, when the QLC threshold level changes between 1 and 2 (or, 2 and 3, 3 and 4, 4 and 5, etc.), only the LP bit changes (or, the TP bit, UP bit, TP bit, etc., respectively).

[0094] exist Figure 6 In this configuration, each pair of adjacent odd and even QLC levels shares the same set of XP, UP, and LP bits. This allows combinations of XP, UP, and LP bits to be mapped to TLC levels 0, 1, ..., 7. Since QLC levels 0 and 1 share TLC level 0, coarsely programming memory cell 137 to TLC level 0 results in a memory threshold voltage close to both QLC levels 0 and 1. Similarly, since QLC levels 2 and 3 share TLC level 1, coarsely programming memory cell 137 to TLC level 1 results in a memory threshold voltage close to both QLC levels 2 and 3.

[0095] exist Figure 6In the diagram, the group identifier has a value of 1 to indicate that memory cell 137 has an even number of TLC levels (e.g., 0, 2, 4, 6), and the group identifier has a value of 0 to indicate that memory cell 137 has an odd number of TLC levels (e.g., 1, 3, 5, 7). The group identifier can be calculated based on the "XOR" or "XNOR" of the XP, UP, and LP bits (or based on the number of TLC levels).

[0096] Since the group identifier is calculated based on the XOR (or XNOR) of the UP, UP, and LP bits (or based on the number of TLC levels), one of the XP, UP, and LP bits can be calculated by the XOR (or XNOR) of the group identifier with the other bits. For example, the XP bit can be calculated by the XOR (or XNOR) of the group ID, UP, and LP bits.

[0097] The XP, UP, and LP bits of group identifier 207, which are equal to 1, are not independent of each other. This is because any one of these bits can be calculated by XORing (or XORing) the group identifier 207 (which is 1) with the remaining bits. Any two of the XP, UP, and LP bits can be considered as being calculated in MLC mode based on their bit values. Figure 6 The even-numbered MLC levels shown in the table are mapped and programmed, where the voltage range of even-numbered MLC levels is in... Figure 5 The even-numbered array levels V0, V2, V4, and V6 are centered around this. Therefore, a coarsely programmed memory cell (e.g., 137) with a group identifier 207 equal to 1 can utilize the mapping of even-numbered MLC levels in MLC mode (as in...). Figure 6 (From the table) to read.

[0098] Similarly, the XP, UP, and LP bits of group identifier 207, which are equal to 0, are not independent of each other. This is because any two of the XP, UP, and LP bits can be calculated by XORing (or XNORing) the group identifier 207 (which is 0) with the remaining bits, and can be considered as being in MLC mode based on their bit values. Figure 6 The table shows the mapping of odd-numbered MLC levels, which are then mapped and programmed, with the voltage region of odd-numbered MLC levels being... Figure 5 The system centers on odd-numbered MLC levels V1, V3, V5, and V7. Therefore, a coarsely programmed memory cell (e.g., 137) with a group identifier 207 equal to 0 can utilize the mapping of odd-numbered MLC levels in MLC mode (as in...). Figure 6 (From the table) to read.

[0099] Figure 7 A method for two-pass programming of memory cells is shown according to some embodiments. Figure 7The method can be executed through processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software / firmware (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, Figure 7 The method is at least in part by Figure 1 Controller 115 or Figure 2 The processing logic in the memory device 130 is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0100] For example, Figure 7 The method can be found Figure 1 The memory subsystem 110 described herein uses Figure 2 Integrated circuit memory device 130 and Figures 3 to 6 It uses data programming techniques to execute.

[0101] At block 301, memory device 130 receives a first number of data bits (e.g., 163, ..., 165) for a first pass programming into memory cell (e.g., 137).

[0102] Typically, a group of memory cells (e.g., a page) are programmed together. Therefore, a memory device can receive a first number of data bit groups from the group of memory cells, wherein each data bit group has one data bit for each of the memory cells, and each memory cell will store one data bit from the data bit group.

[0103] The first programming pass is performed after the memory cell (e.g., 137) has been previously erased; and the memory cell (e.g., 137) has not been programmed to store data since the most recent erase operation. The first programming pass is performed to move the threshold voltage of the memory cell (e.g., 137) closer to the level to which it will be programmed in the second pass to store more bits than the first number.

[0104] At block 303, based on a first mapping between the combination of bit values ​​in the first number of data bits and a threshold level, the read / write circuit 143 of memory device 130 programs the threshold voltage of the first memory cell (e.g., 137) to a first level representing the combination of bit values ​​in the first number of data bits.

[0105] For example, the first number is 3; and three bits are used in the first mapping to identify the threshold level of a specific combination of the values ​​of the three bits. In such an instance, the first mapping associates eight threshold levels with eight possible combinations of the values ​​of the three bits. The eight threshold levels are similar to or the same as the threshold levels used to store three bits per memory cell (e.g., a three-level cell (TLC) pattern). However, the first pass of TLC pattern programming can be coarse because the threshold distribution regions of adjacent threshold levels can have significant overlap. Based on the coarsely programmed threshold levels, significant overlap can result in a high probability of reading the level of the memory cell (e.g., 137). However, coarse programming can reduce the time spent completing coarse programming. To speed up the reading of coarsely programmed memory cells and / or avoid read errors, a group identifier can be used to indicate the possible groups of threshold levels that have been coarsely programmed for the memory cell (e.g., 137). The group identifier identifies whether the memory cell (e.g., 137) is programmed to four odd-numbered TLC levels or four even-numbered TLC levels. Four odd-numbered TLC levels can be considered as a set of Multilevel Cell (MLC) threshold levels, representing an odd-numbered subset of eight possible combinations of bit values; and four even-numbered TLC levels can be considered as another set of Multilevel Cell (MLC) threshold levels, representing an even-numbered subset of eight possible combinations of bit values. Therefore, the group identifier allows the read / write circuitry 143 of memory device 130 to use MLC technology to read coarsely programmed memory cells.

[0106] Typically, such group identifiers can be used to read memory cells (e.g., 137) that have been coarsely programmed to store a first number of data bits.

[0107] At block 305, memory device 130 calculates group identifier 207 indicating whether the first level is an odd level or an even level in the first mapping.

[0108] To reduce buffer requirements, memory device 130 can store group identifier 207 in a second memory cell (e.g., 191) by programming a threshold voltage of the second memory cell to represent the data bits representing group identifier 207. For example, the second memory cell (e.g., 191) can be programmed in single-level cell (SLC) mode to store group identifier 207.

[0109] For example, when a TLC page memory cell is coarsely programmed to store three pages of data (e.g., XP, UP, LP), a page group identifier can be calculated and stored / buffered in an SLC page to assist in reading the coarsely programmed TLC page.

[0110] For example, group identifier 207 can be calculated based on the "XOR" or "XNOR" of a first number of data bits (e.g., 163, ..., 165).

[0111] At block 307, the read / write circuit 143 of memory device 130 reads 211 a first memory cell (e.g., 137) having a threshold voltage coarsely programmed to a first level based on group identifier 207 to obtain back a first number of data bits (e.g., 163, ..., 165) from the first memory cell (e.g., 137).

[0112] For example, a first number of data bits (e.g., 163, ..., 165) can be read into a latch (e.g., 183, ..., 185) as input data for a second pass of fine programming for more data bits.

[0113] When the group identifier 207 is calculated based on the XOR (or XOR) of the first number of data bits (e.g., 163, ..., 165), one of the data bits (e.g., 163, ..., 165) can be calculated based on the XOR (or XOR) of the group identifier 207 with the other data bits.

[0114] At block 309, memory device 130 receives additional data bits (e.g., 161). The additional data bits (e.g., 161) together with a first number of data bits (e.g., 163, ..., 165) read from a first memory cell (e.g., 137) form a second number of data bits (e.g., 161, 163, ..., 165).

[0115] For example, a second number of data bits (e.g., 161, 163, ..., 165) may be received into a latch (e.g., 181, 183, ..., 185) to form input data for a second pass of programming of the first memory cell (e.g., 137).

[0116] At block 311, based on a second mapping between the combination of bit values ​​in the second number of data bits and a threshold level, the read / write circuit 143 of memory device 130 programs the threshold voltage of the first memory cell (e.g., 137) to a second level representing the combination of bit values ​​in the second number of data bits.

[0117] For example, the first mapping is for coarse programming of TLC; and the second mapping is for fine programming of QLC. After fine programming, the overlap between the threshold distribution regions of the QLC threshold level is reduced; and it is not necessary to use group indicators to assist in reading the first memory cell (e.g., 137) programmed in QLC mode.

[0118] The second mapping is configured such that two bit value combinations sharing the same first number of data bits are mapped to adjacent threshold levels. Therefore, the threshold voltage of the first memory cell (e.g., 137) coarsely programmed according to the first level is close to the threshold distribution region finely programmed to the second level.

[0119] Figure 8 An example machine illustrating computer system 400 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 400 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform operations of the programming manager 113 (e.g., execute instructions to perform operations corresponding to the reference). Figures 1 to 7 The operation of the described programming manager 113 is described. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0120] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be performed by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as encompassing any collection of machines that individually or jointly execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0121] Example computer system 400 includes processing devices 402 that communicate with each other via bus 430, main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and data storage system 418.

[0122] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include a network interface device 408 for communication via network 420.

[0123] Data storage system 418 may include machine-readable medium 424 (also referred to as computer-readable medium) storing instructions 426 or software embodying one or more sets of the methods or functions described herein. Instructions 426 may also reside wholly or at least partially within main memory 404 and / or processing device 402 during execution of the instructions by computer system 400, the main memory 404 and processing device 402 also constituting machine-readable storage media. Machine-readable medium 424, data storage system 418, and / or main memory 404 may correspond to... Figure 1 The memory subsystem 110.

[0124] In one embodiment, instruction 426 includes instructions for implementing the programming manager 113 (e.g., reference 113). Figures 1 to 7 The described programming manager 113) provides functional instructions. While machine-readable medium 424 is shown as a single medium in the exemplary embodiments, the term "machine-readable storage medium" should be considered as including a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as including any medium capable of storing or encoding sets of instructions for machine execution and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0125] Some parts of the foregoing detailed description have been presented in terms of the symbolic representation of algorithms and data bit operations within computer memory. These algorithms are described and represented in a manner used by those skilled in the art of data processing to communicate the nature of their work to others skilled in the art. Algorithms are hereby and generally considered to be a self-consistent sequence of operations that leads to a desired result. Operations are operations that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, or otherwise manipulated. Referring to these signals as bits, values, elements, symbols, characters, items, numbers, etc., has sometimes proven convenient (primarily for reasons of commonality).

[0126] However, it should be remembered that all these terms and similar terms are associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0127] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each media being coupled to a computer system bus.

[0128] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the program based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will be illustrated below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0129] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processing according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0130] In this description, various functions and operations are described as being executed or caused by computer instructions for the sake of simplicity. However, those skilled in the art will recognize that such expressions mean that the function is produced by one or more controllers or processors (e.g., microprocessors) executing computer instructions. Alternatively or in combination, functions and operations may be implemented using dedicated circuit systems with or without software instructions, such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Embodiments may be implemented using hard-wired circuit systems without software instructions or in combination with software instructions. Therefore, the techniques described are neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a data processing system.

[0131] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the embodiments of this disclosure without departing from the broader spirit and scope set forth in the appended claims. Therefore, this specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A method for a memory device, comprising: Receive the first number of data bits; Based on a first mapping between the combination of bit values ​​in the first number of data bits and a threshold level, the threshold voltage of the first memory cell is programmed to a first level representing the combination of bit values ​​in the first number of data bits; Calculate the group identifier indicating whether the first level is an odd level or an even level in the first mapping; Based on the group identifier, the first memory cell having the threshold voltage programmed to the first level is read to obtain the first number of data bits; Receive at least one additional data bit, wherein the at least one additional data bit and the first number of data bits obtained from the read form a second number of data bits; and Based on a second mapping between the combination of bit values ​​in the second number of data bits and a threshold level, the threshold voltage of the first memory cell is programmed to a second level representing the combination of bit values ​​in the second number of data bits.

2. The method according to claim 1, further comprising: The group identifier is stored in the second memory cell by programming a threshold voltage to represent the data bits representing the group identifier; and The second memory cell is read to retrieve the group identifier for reading the first memory cell having the threshold voltage programmed to the first level.

3. The method of claim 2, wherein calculating the group identifier includes determining the first number of data bits using an "XOR" or "XNOR" operation.

4. The method of claim 3, wherein the first number of data bits has a first data bit and a second data bit; and reading the first memory cell having the threshold voltage programmed to the first level comprises determining an XOR or XOR operation between the group identifier and the second data bit to obtain the first data bit.

5. The method of claim 3, wherein the first level is configured to be near the second level, regardless of the value of the additional data bits.

6. The method of claim 3, wherein the first number is 3; the second number is 4; and the first mapping is between a combination of three-bit values ​​and a three-level cell (TLC) threshold level; the second mapping is between a combination of four-bit values ​​and a combination of four-level cell (TLC) threshold levels; and the second memory cell is programmed to store the group identifier in a single-level cell (SLC) mode.

7. The method of claim 6, wherein reading the first memory cell comprises reading the first memory cell according to a multi-level cell (MLC) threshold level identified by the group identifier.

8. The method according to claim 3, wherein reading the first memory unit comprises: Based on the group identifier, a third mapping is identified between combinations of bit values ​​from a third number of data bits and a threshold level, wherein the third number is equal to the first number minus one; and The first memory cell is read according to the third mapping.

9. A memory device comprising: An integrated circuit package that encloses the memory device; Multiple memory cell groups are formed on at least one integrated circuit die; and latch; In response to a command identifying a first memory cell group within the plurality of memory cell groups, the memory device is configured to, Receive the first number of data bit groups; The first memory cell group is programmed to store the first number of data bit groups, wherein, according to a first mapping between the combination of bit values ​​in the first number of data bits and a threshold level, the threshold voltage of each corresponding memory cell in the first memory cell group is programmed to a first level representing the combination of bit values ​​in the first number of data bits; Calculate the group identifier of the corresponding memory cell, whereby the group identifier indicates whether the first level is an odd level or an even level in the first mapping; The first memory cell group is read based on the group identifier to retrieve the first number of data bit groups into the first part of the latch; An additional data bit group is received into a second portion of the latch, wherein the additional data bit group and the first number of data bit groups form a second number of data bit groups in the latch; and The first memory cell group is programmed to store the second number of data bit groups, wherein the threshold voltage of the corresponding memory cell in the first memory cell group is programmed to a second level representing the combination of bit values ​​in the second number of data bits, according to a second mapping between the combination of bit values ​​in the second number of data bits and a threshold level.

10. The memory device of claim 9, wherein the memory device is further configured to: In Single-Level Cell (SLC) mode, the group identifier of the corresponding memory cell is buffered in the second memory cell group within the plurality of memory cells; and the first memory cell group and the second memory cell group are of the same type.

11. The memory device of claim 10, wherein the threshold distribution region generated by programming with the second level is substantially consistent with the threshold distribution region generated by programming with the first level.

12. The memory device of claim 10, wherein the memory device is further configured to read the first memory cell group according to a third mapping between a combination of bit values ​​in a third number of data bits and a threshold level, the first memory cell group being programmed to store the first number of data groups, the third number being equal to the first number minus one, and the third mapping being identified by the group identifier of the corresponding memory cell.

13. The memory device of claim 12, wherein the first number is 3; the second number is 4; and the first mapping is between a combination of three bit values ​​and a three-level cell (TLC) threshold level; the second mapping is between a combination of four bit values ​​and a combination of four-level cell (QLC) threshold levels; and the second memory cell is programmed to store the group identifier in a single-level cell (SLC) mode.

14. The memory device of claim 13, wherein the third mapping is a combination of two bit values ​​and a multilevel cell (MLC) threshold level.

15. A memory subsystem comprising: Processing device; and At least one memory device having a plurality of page memory cells, including a first page memory cell and a second page memory cell; The processing device is configured to provide a first number of data pages to the memory device and identify the first page memory cell; In response to the first number of data pages, the memory device is configured to: Based on a first mapping between the bit values ​​in the first number of data pages and threshold levels, a first pass of programming is performed on the threshold voltage of the memory cells in the first page to store the first number of data pages; Calculate a page group identifier, where each corresponding group identifier in the page group identifier identifies a corresponding mapping to read the corresponding memory cell in the first page memory cell; The page group identifier is cached in the second page memory unit; The first page memory cell is read using the page group identifier buffered in the second page memory cell; The processing device is configured to provide additional data pages to the memory device; and In response to the additional data page, the memory device is configured to: Based on a second mapping between the bit values ​​in the second number of data pages and threshold levels, a second pass is performed on the threshold voltage of the memory cell in the first page to store the second number of data pages, the second number of data pages including the additional data pages and the first number of data pages retrieved from the first page memory cell using the page group identifier buffered in the second page memory cell.

16. The memory subsystem of claim 15, wherein the memory device is further configured to calculate the page group identifier in a single-level cell (SLC) mode based on an XOR or XNOR operation of the first number of data groups and store the page group identifier in the second page memory cell.

17. The memory subsystem of claim 16, wherein the first number is 3; the second number is 4; and the first mapping is between a combination of three bit values ​​and a three-level cell (TLC) threshold level; and the second mapping is between a combination of four bit values ​​and a combination of four-level cell (QLC) threshold levels.

18. The memory subsystem of claim 17, wherein when the corresponding group identifier has a zero value, the memory device is configured to read the corresponding memory cell according to a third mapping between the first bit value and the first multilevel cell (MLC) threshold level; and when the corresponding group identifier has a zero value, the memory device is configured to read the corresponding memory cell according to a fourth mapping between the second bit value and the second multilevel cell (MLC) threshold level.

19. The memory subsystem of claim 18, wherein the combination of the third mapping and the fourth mapping corresponds to the first mapping; and the first multilevel cell (MLC) threshold level and the second multilevel cell (MLC) threshold level are interleaved in the first mapping.

20. The memory subsystem of claim 19, wherein the memory device is configured to read the first page memory cell according to the three-level cell TLC threshold level in the first mapping to retrieve two pages of the first number of data pages programmed into the first page memory cell, and to calculate a third page of the first number of data pages according to an XOR or XNOR operation between the page group identifier and the two pages.

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