Method and apparatus for preventing fast charge loss

Abstract

The present disclosure relates to methods and apparatus for preventing fast charge loss. Processing logic in a memory device initiates a program operation on a memory array, the program operation including a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a respective first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically to detrapping electrons during programming verification operations in a memory device to prevent rapid charge loss. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure relates to a memory device comprising: a memory array; and control logic operably coupled to the memory array to perform operations including: initiating a programming operation on the memory array, the programming operation including a programming phase and a programming verification phase; and causing a negative voltage signal to be applied to a first selected word line of a block of the memory array during the programming verification phase of the programming operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the programming operation.

[0004] Another aspect of this disclosure is a method comprising: initiating a programming operation on a memory array, the programming operation including a programming phase and a programming verification phase; and causing a negative voltage signal to be applied to a first selected word line of a block of the memory array during the programming verification phase of the programming operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the programming operation.

[0005] Another aspect of this disclosure is directed to a memory device comprising: a memory array; and control logic operably coupled to the memory array to perform operations including: receiving a programming command corresponding to a programming operation on the memory array; causing a programming voltage signal to be applied to a first selected word line of a block of the memory array during a programming phase of the programming operation to program a corresponding first memory cell in a string of memory cells in the block to a target voltage; and causing a negative voltage signal to be applied to the first selected word line during a programming verification phase of the programming operation before a positive pass voltage signal and a programming verification signal are applied to the first selected word line to verify that the first memory cell has reached the target voltage. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 Examples of computing systems including a memory subsystem are shown according to some embodiments of the present disclosure.

[0008] Figure 2A This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 2B This is a schematic diagram illustrating a string of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 3 This is a timing diagram of a memory device operated with a negative word line bias at the beginning of the programming verification recovery phase of a single-pass programming operation, according to some embodiments of the present disclosure.

[0011] Figure 4A This is a timing diagram of a memory device operated with negative word line bias at the beginning of the programming verification recovery phase of the first pass of a multi-pass programming operation, according to some embodiments of the present disclosure.

[0012] Figure 4B This is a timing diagram of a memory device operated with negative word line bias at the beginning of the programming verification recovery phase of the second pass of a multi-pass programming operation, according to some embodiments of the present disclosure.

[0013] Figure 5 This is a timing diagram of a memory device operated with a negative word line bias at the end of the programming verification recovery phase of a single-pass programming operation, according to some embodiments of the present disclosure.

[0014] Figure 6 This is a flowchart of an example method for detrapping electrons during a programming verification operation in a memory device to prevent rapid charge loss, according to some embodiments of the present disclosure.

[0015] Figure 7 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0016] This disclosure relates to the detrapping of electrons during programming verification operations in a memory device within a memory subsystem to prevent rapid charge loss. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. The following is combined with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0017] The memory subsystem may include high-density non-volatile memory devices where data retention is required when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die containing one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit for storing information. Hereinafter, a block refers to a cell of a memory device used to store data and may include groups of memory cells, groups of word lines, word lines, or individual memory cells. Each block may contain several sub-blocks, each sub-block being defined by associated pillars (e.g., vertical conductive traces) extending from a shared bit line. A memory page (also referred to herein as a “page”) stores one or more bits of binary data corresponding to data received from the host system. To achieve high density, strings of memory cells in non-volatile memory devices can be configured to comprise several memory cells comprising pillars at least partially surrounding a polysilicon channel material (i.e., the channel region). The memory cells can be coupled to access lines, often referred to as "word lines," which are typically fabricated together with the memory cells to form a string array within a memory block. The compactness of some non-volatile memory devices, such as 3D flash NAND memory, means that word lines are common to many memory cells within a memory block.

[0018] During a programming operation, a selected memory cell can be programmed by applying a programming voltage to a selected word line. In some cases, a series of incremental voltage programming pulses are applied to the selected word line to increase the charge level of each memory cell connected to that word line, thereby increasing the threshold voltage of each memory cell. After each programming pulse, or after several programming pulses, a programming check operation is performed to determine whether the threshold voltage of the memory cell has increased to the desired programming level. After the programming operation is complete, the programmed memory cell may experience various forms of charge loss, which may lead to defects in the data retention characteristics of the memory cell, such as unity charge loss, intrinsic charge loss, and quick charge loss. Quick charge loss (QLC) is a result of electrons being trapped in the tunnel oxide layer (also referred to herein as the "band engineering (BE)" layer) after the applied programming pulse moves back into the channel region of the memory cell string. When the cell passes the programming check operation, the programmed threshold voltage appears higher due to the charge trapped in the tunnel oxide layer. However, when the memory cell is read later after the programming operation has been completed, the cell may have a threshold voltage lower than the threshold voltage obtained during the programming verification operation. This is attributed to charge leakage from the tunnel oxide layer to the channel region. This may require increasing the threshold voltage distribution to accommodate all possible threshold voltages for a given state, and could result in a higher error rate during any subsequent read operation.

[0019] Some memory devices attempt to mitigate rapid charge loss by applying a negative gate bias voltage before the programming and verification operation. This voltage detraps some electrons trapped in the tunnel oxide layer (i.e., allows those electrons to flow out into the channel region), causing some rapid charge loss to occur during the programming and verification operation before sensing. However, the application of the negative gate bias voltage can also cause detrapping of electrons within the channel region itself. Detrapping in the channel region causes a change in the threshold voltage of the memory cells in the string, thereby adversely affecting the read window budget (RWB) between the voltage distributions of the memory cells and leading to an increased read error rate. These devices do not isolate the detrapping of electrons from the tunnel oxide layer and from the channel region so that they do not occur simultaneously before or during the programming and verification operation.

[0020] This disclosure addresses the above and other drawbacks by preventing rapid charge loss through electron detrapping during programming and verification operations in a memory device. In one embodiment, processing logic in the memory device causes a negative voltage signal (e.g., -1 volt) to be applied to a selected word line (i.e., the word line being programmed (WLn)) of a block of the memory array of the memory device during a specific interval of the programming and verification phase of the programming operation to enhance electron detrapping from the tunnel oxide layer of the memory device. In one embodiment, a negative voltage signal is applied at the beginning of the programming and verification phase, for example, before a positive pass voltage (i.e., Vpassr) is applied to the selected word line. Shortly after detrapping, the voltage signal applied to the selected word line, the unselected word line, and the selected gate device ramps up to the pass voltage, which not only causes channel boost discharge due to the ramping of the pass voltage but also causes electron trapping within the polysilicon channel region of the memory device. The magnitude of the pass voltage is typically insufficient to cause electron trapping in the tunnel oxide layer. In another embodiment, a negative voltage signal is applied at the end of the programming and verification phase, for example, after the pass voltage and one or more verification voltages are applied to the selected word line. A negative voltage signal causes electrons to be detrapped from the tunnel oxide layer and from the channel region. During subsequent programming operations, the additional electron injection due to the previous detrapping can program some electrons into the storage nitride layer instead of completely filling the tunnel oxide layer traps. Therefore, at the end of the programming operation, there are fewer electrons in the tunnel oxide layer traps, and because no negative voltage signal is applied between the programming and programming verification phases, the channel region traps remain filled.

[0021] The advantages of this method include (but are not limited to) improved performance in the memory subsystem. By increasing the read window budget between the voltage distributions in the memory array in the manner described herein, the time interval between electrons leaving the tunnel oxide layer and being detrapped from the channel region is increased. This results in a lower error rate during subsequent read operations, as well as improved reliability and data retention in the memory device. Consequently, the overall quality of service level of the memory subsystem is improved.

[0022] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is shown. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such devices.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0027] Host system 120 can be coupled to memory system 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM Fast (NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance by combining a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages that can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is shown to include a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory device 130 may represent a single die having some control logic embodied thereon (e.g., local media controller 135). In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0038] In one embodiment, the memory subsystem 110 includes a memory device programming management component 113 that can monitor, control, and / or manage data access operations (e.g., programming operations) performed on a non-volatile memory device (e.g., memory device 130) of the memory subsystem 110. For example, a programming operation may include several phases, such as a programming phase and a programming verification phase. The programming management component 113 is responsible for applying (or indicating which voltages are applied) a specific voltage to the memory device 130 during the programming operation. For example, during the programming phase, the programming management component 113 may cause a programming voltage to be applied to a first selected word line (i.e., the word line being programmed (WLn)) of a block of memory array of the memory device 130 to program a corresponding first memory cell in the string of memory cells in the block to a target voltage (i.e., a voltage representing data to be stored in the memory cell). During the programming verification phase, the programming management component 113 may cause a programming verification voltage to be applied to the first selected word line to sense the voltage level of the corresponding memory cell. In one embodiment, to enhance the detrapping of electrons from the tunnel oxide layer of the memory device, the programming management component 113 may further cause a negative voltage signal to be applied to the first selected word line during the programming verification phase. Depending on the embodiment, the negative voltage signal may be applied at the beginning of the programming verification phase (i.e., before the positive pass voltage signal is applied to the first selected word line) or at the end of the programming verification phase (i.e., after the positive pass voltage signal and one or more programming verification voltage signals are applied to the selected word line). Further details regarding the operation of the programming management component 113 are described below.

[0039] Figure 2A The first device and the present memory subsystem (e.g., in the form of a present memory device 130 according to the embodiment) are... Figure 1A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0040] Memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 204 ( Figure 2A (Not shown in the text) can be programmed to be one of at least two target data states.

[0041] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 204. The memory device 130 also includes an input / output (I / O) control circuitry 260 to manage the input of commands, addresses, and data to the memory device 130, as well as the output of data and status information from the memory device 130. Address register 214 communicates with I / O control circuitry 260, row decoding circuitry 208, and column decoding circuitry 210 to latch the address signal before decoding. Command register 224 communicates with I / O control circuitry 260 and local media controller 135 to latch incoming commands.

[0042] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 204 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to addresses. In one embodiment, the local media controller 134 includes a programming management component 113 that can perform electron detrapping during programming verification operations in memory device 130 to prevent rapid charge loss.

[0043] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 270 for transfer to memory cell array 204; then, new data can be latched from I / O control circuitry 260 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 260 for output to memory subsystem controller 115; then, new data can be transferred from data register 270 to cache register 218. Cache register 218 and / or data register 270 may form a page buffer of memory device 130 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 2A (Not shown in the diagram) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines of the memory cells connected to the memory cell array 204. The status register 222 can communicate with the I / O control circuitry system 260 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0044] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 236, and outputs data to memory subsystem controller 115 via I / O bus 236.

[0045] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 236 at the I / O control circuitry system 260, and then written to the command register 224. Addresses can be received via the input / output (I / O) pins [7:0] of the I / O bus 236 at the I / O control circuitry system 260, and then written to the address register 214. Data can be received via the input / output (I / O) pins [7:0] for 8-bit devices or the input / output (I / O) pins [15:0] for 16-bit devices at the I / O control circuitry system 260, and then written to the cache register 218. The data can then be written to the data register 270 for programming the memory cell array 204.

[0046] In this embodiment, the cache register 218 may be omitted, and data may be written directly to the data register 270. Data may also be output on the input / output (I / O) pins [7:0] for an 8-bit device or the input / output (I / O) pins [15:0] for a 16-bit device. Although references may be made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0047] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 2A The memory device 130. It should be understood that, reference Figure 2A The functionality of the various block components described may not necessarily be separate from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2A The functionality of one or more block components. Alternatively, one or more components or component portions of an integrated circuit device may be combined to perform... Figure 2A The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that combinations of other I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0048] Figure 2B This is a schematic diagram illustrating a string 200 of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, string 200 represents, for example, a portion of a memory device 130 from a memory cell array 204, such as... Figure 2AAs shown. String 200 includes a plurality of memory cells 212 (i.e., charge storage devices), for example, up to 32 memory cells (or more) in some embodiments. String 200 includes a source-side select transistor, referred to as source-select gate 220 (SGS) (typically an n-channel transistor), coupled between the memory cells 212 and a common source 226 at one end of string 200. The common source 226 may comprise, for example, a co-doped semiconductor material and / or other conductive material. At the other end of string 200, a drain-side select transistor, referred to as drain-select gate 230 (SGD) (typically an n-channel transistor), and a gate-induced drain leakage (GIDL) generator 240 (GG) (typically an n-channel transistor) are coupled between one of the memory cells 212 and a data line 234, which is typically referred to as a "bit line" in this art. The common source 226 can be coupled to a reference voltage (e.g., ground voltage or simply "ground" [Gnd]) or a voltage source (e.g., a charge pump circuit or power supply, which may be selectively configured to a specific voltage suitable for optimizing programming operations).

[0049] Each memory cell 212 may include, for example, a floating gate transistor or a charge trapping transistor, and may include a single-level memory cell or a multi-level memory cell. The floating gate may be referred to as charge storage structure 235. The memory cell 212, source-select gate 220, drain-select gate 230, and GIDL generator 240 may be controlled by signals on their respective control gates 250.

[0050] Control signals may be applied by or at the instruction of the programming management component 113, for example, applied to a select line (not shown) to select a string, or applied to an access line (not shown) to select a memory cell 212. In some cases, control gates may form portions of a select line (for selecting a device) or an access line (for a cell). Drain select gate 230 receives a voltage that causes drain select gate 230 to select or deselect string 200. In one embodiment, each corresponding control gate 250 is connected to a separate word line (i.e., an access line) such that each device or memory cell can be controlled individually.

[0051] In one embodiment, to enhance electron detrapping from the tunnel oxide layer forming a portion of string 200, programming management component 113 may cause a negative voltage signal to be applied to a first selected word line during the programming verification phase of the programming operation. This negative voltage signal is received at a corresponding control gate 250 to which the first selected word line is connected. Depending on the embodiment, the negative voltage signal may be applied at the beginning of the programming verification phase (i.e., before a positive pass voltage signal is applied to the first selected word line) or at the end of the programming verification phase (i.e., after a positive pass voltage signal and one or more programming verification voltage signals are applied to the selected word line). The application of this negative voltage signal enhances electron detrapping from the tunnel oxide layer during the programming verification phase without causing detrapping of electrons in the polysilicon channel region of string 200. The specific application of the negative voltage signal may vary depending on whether a single-pass or multi-pass programming operation is being performed, as described in more detail below.

[0052] Figure 3 This is a timing diagram 300 of some embodiments of the present disclosure for operating a memory device with a negative word line bias at the beginning of the program verification recovery phase of a single-pass programming operation. During a programming operation performed on a non-volatile memory device, such as memory device 130, specific phases may be encountered, including a programming phase and a program verification phase. During the programming phase, a programming voltage is applied to a selected word line of memory device 130 to program a specific charge level representing a desired value to a selected memory cell on the word line. During the program verification phase, a read voltage is applied to the selected word line to read the charge level stored at the selected memory cell to confirm that the desired value has been properly programmed. Because relatively high voltages are applied during the programming and program verification operations, the program recovery and program verification recovery phases can be implemented to allow memory device 130 to recover.

[0053] Timing diagram 300 illustrates a programming verification phase according to one embodiment. In this embodiment, the programming verification phase comprises four time intervals during which different voltage signals are applied to various devices in the memory device 130. During a first time interval 310, a reset pass voltage (i.e., Vpass_rst) is applied to all data word lines, including the selected word line (SelWL) and any unselected word lines (UnselWL), as well as the drain-select gate (SGD) of the string 200. During a second time interval 320, the programming management component 113 causes a negative voltage signal (Vneg) to be applied to the selected word line (SelWL). In one embodiment, the programming management component 113 sends a signal to the word line driver (or some other component) instructing the driver to apply the negative voltage signal to the word line. The voltage signal applied to the unselected word line remains at the reset pass voltage, and the select gate pass voltage (Vpassr) is applied to the drain-select gate. The negative voltage signal enhances de-trapping in the tunnel oxide layer and channel region of the memory string 200. After a specific time period (e.g., a few microseconds), a third time interval 330 may begin. During the third time interval 330, a pass voltage (Vpassr) spike is applied to the selected word line, and the voltage signal on the unselected word lines ramps up to the pass voltage (Vpassr / Vpass1r). The pass voltage causes channel boost discharge and also causes electron trapping in the polysilicon channel region. During the fourth time interval 340, one or more programming verification voltage signals (pv_1, pv_2, ... pv_n) are applied to the selected word line. These voltages sense the charge level stored at the selected memory cell to confirm that the desired value has been properly programmed. Because electron detrapping of the tunnel oxide layer has already been performed during the second time interval 320, the shallow traps in the tunnel oxide layer will be empty and will not affect the sensing of the programming verification operation performed during the fourth time interval 340. The voltage signals applied to the unselected word line and drain-select gate can be held at the pass voltage or optionally ramped down to ground (gnd), and all voltage signals eventually ramp down to the reset pass voltage (Vpassr_rst) and ground at the end of the programming verification recovery phase 300.

[0054] Figure 4AThis is a timing diagram 400 for operating a memory device with a negative word line bias at the beginning of the programming verification recovery phase of the first pass of a multi-pass programming operation, according to some embodiments of this disclosure. Certain memory subsystems, such as memory subsystems implementing QLC memory, use multi-pass programming algorithms, such as a coarse-fine two-pass programming algorithm. In this embodiment, word line programming begins with a coarse programming of the memory cells in the first pass. The goal of this "coarse" first pass is to quickly program all cells to a level slightly below their final target programming level. During the slower "fine" second pass, the memory cells are programmed to a slightly higher final target programming voltage. This type of two-pass programming minimizes cell-to-cell (C2C) interference because when the fine programming pass is performed, each cell and its neighboring cells are almost at their final target programming voltage, requiring only "slight modifications." The combination of precision programming in the first pass and minimized C2C coupling enables fast programming with a high RWB.

[0055] Timing diagram 400 illustrates a programming verification phase following a first programming pass according to one embodiment. In this embodiment, the programming verification phase comprises four time intervals during which different voltage signals are applied to various devices in memory device 130. During a first time interval 410, a reset pass voltage (i.e., Vpass_rst) is applied to all data word lines of string 200. During a second time interval 420, programming management component 113 causes a negative voltage signal (Vneg) to be applied to a selected word line (Sel WL) and a second word line (WLn-1) adjacent to the selected word line on one side of the selected word line. The second word line may be a word line connected to a previously coarsely programmed memory cell. In one embodiment, programming management component 113 sends a signal to a word line driver (or some other component) instructing the driver to apply the negative voltage signal to the word line. The voltage signal applied to the unselected word line remains at the reset pass voltage, and a select gate pass voltage (Vpassr) is applied to the drain select gate. The negative voltage signal enhances de-trapping in the tunnel oxide layer and channel region of memory string 200. After a specific time period (e.g., a few microseconds), a third time interval 430 may begin. During the third time interval 430, a pass voltage (Vpassr) spike is applied to the selected word line and the selected gate, and the voltage signals on the second word line (WLn-1) and any unselected word lines (including the third word line (WLn+1) adjacent to the selected word line on the second side of the selected word line) ramp up to the pass voltage (Vpassr / Vpass1r). The pass voltage on the selected gate causes channel boost discharge, and the pass voltage on the selected word line causes electron trapping in the polysilicon channel region. During the fourth time interval 440, one or more programming verification voltage signals (pv_1, pv_2, ... pv_n) are applied to the selected word line. These voltages sense the charge level stored at the selected memory cell to confirm that the desired value has been properly programmed. Because electron detrapping of the tunnel oxide layer has been performed during the second time interval 420, the shallow traps in the tunnel oxide layer will be empty and will not affect the sensing of the programming verification operation performed during the fourth time interval 440. The voltage signals applied to the second word line and the unselected word line can be maintained at the pass voltage, and all voltage signals eventually slope down to the reset pass voltage (Vpassr_rst) and the ground voltage (gnd) at the end of the programming verification recovery phase 400.

[0056] Figure 4BThis is a timing diagram 450 of some embodiments of the present disclosure for operating a memory device with a negative word line bias at the beginning of the programming verification recovery phase of the second pass of a multi-pass programming operation. Timing diagram 450 illustrates a programming verification phase following the second programming pass according to one embodiment. In this embodiment, the programming verification phase comprises four time intervals during which different voltage signals are applied to various devices in the memory device 130. During a first time interval 460, a reset pass voltage (i.e., Vpass_rst) is applied to all data word lines of string 200. During a second time interval 470, programming management component 113 causes a negative voltage signal (Vneg) to be applied to a selected word line (Sel WL) and a third word line (WLn+1) adjacent to the selected word line on a second side of the selected word line. The third word line may be a word line connected to a memory cell that has been coarsely programmed but not yet finely programmed. In one embodiment, programming management component 113 sends a signal to a word line driver (or some other component) instructing the driver to apply the negative voltage signal to the word line. The voltage signal applied to the unselected word line is maintained at the reset pass voltage, and the select gate pass voltage (Vpassr) is applied to the drain select gate. The negative voltage signal enhances detrapping in the tunnel oxide layer and channel region of the memory string 200. After a specific time period (e.g., a few microseconds), a third time interval 480 may begin. During the third time interval 480, a pass voltage (Vpassr) spike is applied to the selected word line and the select gate, and the voltage signal on the third word line (WLn+1) and any unselected word line (including the second word line (WLn-1)) ramps up to the pass voltage (Vpassr / Vpass1r). The pass voltage on the select gate causes channel boost discharge, and the pass voltage on the selected word line causes electron trapping in the polysilicon channel region. During the fourth time interval 490, one or more programming verification voltage signals (pv_1, pv_2, ... pv_n) are applied to the selected word line. These voltages sense the charge level stored at the selected memory cell to confirm that the desired value has been properly programmed. Because electron detrapping of the tunnel oxide layer has already been performed during the second time interval 470, the shallow traps in the tunnel oxide layer will be empty and will not affect the sensing of the programming verification operation performed during the fourth time interval 490. The voltage signals applied to the third word line and the unselected word line can be maintained at the pass voltage, and all voltage signals eventually slope down to the reset pass voltage (Vpassr_rst) and the ground voltage (gnd) at the end of the programming verification recovery phase 450.

[0057] Figure 5This is a timing diagram 500 for operating a memory device with a negative word line bias at the end of the program verification recovery phase of a single-pass programming operation, according to some embodiments of the present disclosure. In this embodiment, the program verification phase comprises five time intervals during which different voltage signals are applied to various devices in the memory device 130. During a first time interval 510, a reset pass voltage (i.e., Vpass_rst) is applied to all data word lines, including the selected word line (Sel WL) and any unselected word line (Unsel WL) as well as the drain-select gate (SGD) of string 200. During a second time interval 520, a pass voltage (Vpassr) spike is applied to the selected word line and the select gate, and the voltage signals on the unselected word line and the drain-select gate ramp up to the pass voltage (Vpassr / Vpass1r). The pass voltage on the select gate can cause channel boost discharge, and the pass voltage on the selected word line can cause electron trapping in the polysilicon channel region. During the third time interval 530, one or more programming verification voltage signals (pv_1, pv_2, ... pv_n) are applied to selected word lines. These voltages sense the charge level stored at the selected memory cells to confirm that the desired value has been properly programmed. Voltage signals applied to unselected word lines and drain-select gates may be held at the pass voltage or optionally ramped down to ground (gnd), and all voltage signals eventually ramp down to the reset pass voltage (Vpassr_rst). During the fourth time interval 540, programming management component 113 causes a negative voltage signal (Vneg) to be applied to the selected word line (Sel WL). In one embodiment, programming management component 113 sends a signal to a word line driver (or some other component) instructing the driver to apply the negative voltage signal to the word line. Voltage signals applied to unselected word lines and drain-select gates are held at the reset pass voltage. The negative voltage signal detraps electrons in the tunnel oxide layer and channel region of the memory string 200. After a specific time period (e.g., a few microseconds), a fifth time interval 550 may begin. During the fifth time interval 550, all voltage signals are ramped down to ground at the end of the programming verification recovery phase 500. During subsequent programming operations, the additional electron injection due to the previous detrapping may program some electrons into the storage nitride layer rather than completely filling the tunnel oxide layer traps. Therefore, at the end of the programming operation, there are fewer electrons in the tunnel oxide layer traps, and because no negative voltage signal is applied between the programming and programming verification phases, the channel traps remain filled.

[0058] In another embodiment, the programming management component 113 may cause a negative voltage signal to be applied at the end of the programming verification recovery phase of a multi-pass programming operation. For example, the programming management component 113 may cause a negative voltage signal to be applied to a selected word line and to one or more adjacent word lines after a pass voltage (e.g., Vpassr) and one or more programming verification voltages (e.g., pv_1-pv_n) have been applied. In one embodiment, during the first programming pass of the multi-pass programming operation, a negative voltage signal is applied to the selected word line and to a second word line (e.g., WLn-1) adjacent to the selected word line on one side of the selected word line. Then, during the second programming pass of the multi-pass programming operation, a negative voltage signal is applied to the selected word line and to a third word line (e.g., WLn+1) adjacent to the selected word line on the other side of the selected word line. The application of this negative voltage signal can detrap electrons in the tunnel oxide layer and channel region of the memory string, so that these electrons will not affect subsequent read operations performed on the memory cells of the memory string.

[0059] Figure 6 This is a flowchart illustrating an example method for detrapping electrons during a programming verification operation in a memory device to prevent rapid charge loss, according to some embodiments of this disclosure. Method 600 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 600 is performed by… Figure 1 The programming management component 113 executes. Although shown in a specific sequence or order, the order of processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0060] At operation 605, a command is received. For example, processing logic (e.g., programming management component 113) may receive from a requesting party (e.g., memory subsystem controller 115) a command to perform a memory access operation on a memory array (e.g., memory array 204) of a memory device (e.g., memory device 130). In one embodiment, the command includes a programming command, and the memory access operation includes a programming operation. For example, the memory access operation may include a QLC programming operation associated with multiple pages (e.g., four pages) of host data to be written to the memory device.

[0061] At operation 610, a memory access operation is initiated. For example, processing logic may initiate a programming operation associated with a received command on memory device 130. In one embodiment, the programming operation includes a programming phase and a programming verification phase. In some embodiments, each of these phases may be repeated multiple times in a loop during a single programming operation.

[0062] At operation 615, a programming voltage signal is applied. For example, the processing logic may cause the programming voltage signal to be applied to a first selected word line of a block of the memory array during the programming phase of the programming operation. The programming voltage signal is applied to the selected word line of the memory device 130 to program a specific charge level (i.e., target voltage) representing a desired value to a selected memory cell in the string of memory cells on the word line.

[0063] At operation 620, a negative voltage signal is applied. For example, the processing logic may cause the negative voltage signal to be applied to a first selected word line during the programming verification phase of a programming operation. In one embodiment, the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in a block, and the first selected word line is associated with a programming operation (i.e., connected to the memory cell being programmed).

[0064] At operation 625, a determination is made. For example, the processing logic may determine whether the programming operation involves multiple programming passes. In one embodiment, the programming operation is a single-pass programming operation, wherein memory cells connected to a selected word line are programmed in a single programming pass. In other embodiments, the programming operation is a multi-pass programming operation, wherein memory cells of a memory array are programmed in two or more programming passes. In one embodiment, during the first pass of the multi-pass programming operation, the processing logic coarsely programs the memory cells to an initial value representing a host data page. In one embodiment, the programming management component 113 may cause one or more programming pulses to be applied to the selected word line to store a host data page in the memory cell. The initial value may be slightly lower than the final target value, such that the first programming pass can be performed with minimal latency. In one embodiment, during the second pass of the multi-pass programming operation, the processing logic reads the coarsely programmed initial value from the first pass and finely programs the memory cells to the final value representing a host data page. In one embodiment, the programming management component 113 may cause one or more programming voltage pulses to be applied to a memory cell to increase an initial value to a final value representing a host data page.

[0065] If the programming operation is not a multi-pass operation (i.e., the programming operation is a single-pass programming operation), an additional voltage signal is applied at operation 630. Depending on the embodiment, a positive pass voltage signal (e.g., Vpassr) and one or more programming verification voltage signals (e.g., pv_1-pv_n) are applied before or after the negative voltage signal during the programming verification phase. In one embodiment, the processing logic causes the negative voltage signal to be applied to the first selected word line at the beginning of the programming verification phase of the programming operation (i.e., before the positive pass voltage signal is applied to the first selected word line). In another embodiment, the processing logic causes the negative voltage signal to be applied to the selected word line at the end of the programming verification phase of the programming operation (i.e., after the positive pass voltage signal and one or more programming verification voltage signals are applied to the selected word line).

[0066] If the programming operation is a multi-pass operation, a negative voltage signal is applied during the first programming pass at operation 635. For example, the processing logic may cause a negative voltage signal to be applied to a first selected word line (e.g., WLn) and a second word line (e.g., WLn-1) adjacent to the first selected word line during the first programming verification phase of a multi-pass programming verification phase. The second word line is coupled to a second memory cell in the multi-pass programming string on a first side of a first memory cell.

[0067] At operation 640, a negative voltage signal is applied during the second programming pass. For example, the processing logic may cause a negative voltage signal to be applied to a first selected word line (e.g., WLn) and a third word line adjacent to the first selected word line (e.g., WLn+1) during the second programming verification phase of the plurality of programming verification phases. The third word line is coupled to a third memory cell in the plurality of memory cells on a second side of a first memory cell in the memory cell string.

[0068] Figure 7 An example machine of computer system 700 is shown, within which an instruction set executable for causing the machine to perform any one or more of the methods discussed herein is provided. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1(Operation of the programming management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0069] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0070] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0071] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication on network 720.

[0072] The data storage system 718 may include a machine-readable storage medium 724 (also called a computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0073] In one embodiment, instruction 726 includes instructions for implementing the corresponding Figure 1 The programming management component 113 contains functional instructions. While machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding instruction sets executable by a machine and causing the machine to perform any one or more methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0074] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0075] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0076] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0077] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0078] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine-readable storage medium, such as a read-only memory (“ROM”), random access memory (“RAM”), disk storage medium, optical storage medium, flash memory components, etc.

[0079] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: Memory array; as well as Control logic, which is operatively coupled to the memory array, performs operations including: A programming operation is initiated on the memory array, the programming operation including a programming phase and a programming verification phase; as well as This causes a negative voltage signal to be applied to the first selected word line of the block of the memory array after a positive pass voltage signal and one or more programming verification voltage signals are applied to the first selected word line during the programming verification phase of the programming operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, and wherein the first selected word line is associated with the programming operation.

2. The memory device of claim 1, wherein the negative voltage signal is applied to the first selected word line before the positive pass voltage signal is applied to the first selected word line during the programming verification phase of the programming operation.

3. The memory device according to claim 2, wherein the programming operation includes a multi-pass programming operation comprising multiple programming stages and multiple programming verification stages.

4. The memory device of claim 3, wherein the control logic is configured to perform operations further including: This causes the negative voltage signal to be applied to the first selected word line and a second word line adjacent to the first selected word line during the first programming verification phase of the plurality of programming verification phases, wherein the second word line is coupled to a second memory cell of the first memory cell in the memory cell string on a first side.

5. The memory device of claim 4, wherein the control logic is configured to perform operations further including: This causes the negative voltage signal to be applied to the first selected word line and a third word line adjacent to the first selected word line during the second programming verification phase of the plurality of programming verification phases, wherein the third word line is coupled to a third memory cell of the first plurality of memory cells on a second side of the first memory cell in the memory cell string.

6. The memory device of claim 1, wherein the programming operation includes a plurality of programming stages and a plurality of programming verification stages, each associated with a different programming voltage, and wherein the negative voltage is applied to the first selected word line only during a subset of the plurality of programming verification stages that are associated with programming voltages exceeding a predefined threshold voltage level.

7. A method comprising: Initiate a programming operation on the memory array, the programming operation including a programming phase and a programming verification phase; as well as This causes a negative voltage signal to be applied to the first selected word line of the block of the memory array after a positive pass voltage signal and one or more programming verification voltage signals are applied to the first selected word line during the programming verification phase of the programming operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, and wherein the first selected word line is associated with the programming operation.

8. The method of claim 7, wherein the negative voltage signal is applied to the first selected word line before the positive pass voltage signal is applied to the first selected word line during the programming verification phase of the programming operation.

9. The method according to claim 8, wherein the programming operation includes a multi-pass programming operation comprising multiple programming stages and multiple programming verification stages.

10. The method of claim 9, further comprising: This causes the negative voltage signal to be applied to the first selected word line and a second word line adjacent to the first selected word line during the first programming verification phase of the plurality of programming verification phases, wherein the second word line is coupled to a second memory cell of the first memory cell in the memory cell string on a first side.

11. The method of claim 10, further comprising: This causes the negative voltage signal to be applied to the first selected word line and a third word line adjacent to the first selected word line during the second programming verification phase of the plurality of programming verification phases, wherein the third word line is coupled to a third memory cell of the first plurality of memory cells on a second side of the first memory cell in the memory cell string.

12. The method of claim 7, wherein the programming operation includes a plurality of programming stages and a plurality of programming verification stages, each associated with a different programming voltage, and wherein the negative voltage is applied to the first selected word line only during a subset of the plurality of programming verification stages associated with programming voltages exceeding a predefined threshold voltage level.

13. A memory device comprising: Memory array; as well as Control logic, which is operatively coupled to the memory array, performs operations including: Receive programming commands corresponding to programming operations on the memory array; This causes a programming voltage signal to be applied to a first selected word line of the block of the memory array during the programming phase of the programming operation to program a first memory cell of a first plurality of memory cells in the memory cell string of the block to a target voltage; as well as This causes a negative voltage signal to be applied to the first selected word line after a positive pass voltage signal and a programming verification signal are applied to the first selected word line to verify that the first memory cell has reached the target voltage during the programming verification phase of the programming operation.

14. The memory device of claim 13, wherein the programming operation includes a multi-pass programming operation comprising a plurality of programming stages and a plurality of programming verification stages.

15. The memory device of claim 14, wherein the control logic is configured to perform operations further including: This causes the negative voltage signal to be applied to the first selected word line and a second word line adjacent to the first selected word line during the first programming verification phase of the plurality of programming verification phases, wherein the second word line is coupled to a second memory cell of the first memory cell in the memory cell string on a first side.

16. The memory device of claim 15, wherein the control logic is configured to perform operations further including: This causes the negative voltage signal to be applied to the first selected word line and a third word line adjacent to the first selected word line during the second programming verification phase of the plurality of programming verification phases, wherein the third word line is coupled to a third memory cell of the first plurality of memory cells on a second side of the first memory cell in the memory cell string.

17. The memory device of claim 13, wherein the programming operation includes a plurality of programming stages and a plurality of programming verification stages, each associated with a different programming voltage, and wherein the negative voltage is applied to the first selected word line only during a subset of the plurality of programming verification stages associated with programming voltages exceeding a predefined threshold voltage level.

18. The memory device of claim 13, wherein the positive pass voltage signal has a higher magnitude than the programming verification signal.

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