Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, a gate structure, a source-drain doped region and a dielectric layer; forming a sacrificial layer on the dielectric layer; forming an initial source-drain contact structure penetrating through the dielectric layer and the sacrificial layer on top of the source-drain doped region, a part of the initial source-drain contact structure in the sacrificial layer serving as a sacrificial source-drain contact structure; forming an initial gate plug penetrating through the dielectric layer and the sacrificial layer on top of the gate structure, a part of the initial gate plug in the sacrificial layer serving as a sacrificial gate plug, with the initial source-drain contact structure as a lateral stop position; any one or both of the sacrificial source-drain contact structure and the sacrificial gate plug being a reverse trapezoidal structure in lateral section; removing the sacrificial source-drain contact structure and the sacrificial gate plug and the sacrificial layer by using a first planarization process to form a gate plug and a source-drain contact structure. The present application is advantageous in simplifying the process and reducing the probability of bridging of the gate plug and the source-drain contact structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and a substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped regions for connecting the source / drain doped regions to external circuitry.

[0004] However, the current semiconductor structure formation process still presents significant challenges. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which helps to simplify the process flow for forming gate plugs and source / drain contact structures and reduce the probability of bridging between gate plugs and source / drain contact structures.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source and drain doped regions are formed in the substrate on both sides of the gate structure, a dielectric layer is formed on the substrate covering the sidewalls and top of the gate structure and the source and drain doped regions, the gate structure extending longitudinally, and the direction perpendicular to the longitudinal direction being transverse; forming a sacrificial layer on the dielectric layer; forming an initial source and drain contact structure penetrating the top of the source and drain doped regions through the dielectric layer and the sacrificial layer, contacting the source and drain doped regions, wherein the portion of the initial source and drain contact structure located in the sacrificial layer serves as a sacrificial source and drain contact structure; and using the initial source and drain contact structure as the sacrificial source and drain contact structure. The contact structure is a stop position along the lateral direction, forming an initial gate plug that penetrates the dielectric layer and sacrificial layer at the top of the gate structure and contacts the gate structure. The portion of the initial gate plug located in the sacrificial layer serves as a sacrificial gate plug. Either or both of the sacrificial source-drain contact structure and the sacrificial gate plug have an inverted trapezoidal cross-section along the lateral direction. A first planarization process is used to remove the sacrificial source-drain contact structure, the sacrificial gate plug, and the sacrificial layer, creating a gap between the initial gate plug and the initial source-drain contact structure. The remaining initial gate plug is used as a gate plug, and the remaining initial source-drain contact structure is used as a source-drain contact structure.

[0007] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate, the gate structure extending longitudinally, the direction perpendicular to the longitudinal direction being transverse; source / drain doped regions located in the substrate on both sides of the gate structure; a dielectric layer located on the substrate and covering the sidewalls and top of the gate structure, as well as the source / drain doped regions; a polishing stop layer located on the dielectric layer; a source / drain contact structure penetrating the dielectric layer and polishing stop layer at the top of the source / drain doped regions, the source / drain contact structure contacting the source / drain doped regions; a gate plug penetrating the dielectric layer and polishing stop layer at the top of the gate structure, the gate plug contacting the gate structure, a gap being present between the gate plug and the source / drain contact structure, and the gate plug being flush with the top surface of the source / drain contact structure and the polishing stop layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the formation method provided by this embodiment of the invention, an initial source-drain contact structure is first formed. Then, using the initial source-drain contact structure as the stopping position in the lateral direction, an initial gate plug penetrating the dielectric layer at the top of the gate structure is formed. This allows the initial gate plug to be self-aligned and positioned so that, in the lateral direction, the initial gate plug is located between adjacent initial source-drain contact structures. Furthermore, any one or both of the sacrificial source-drain contact structures and the sacrificial gate plug have an inverted trapezoidal cross-section in the lateral direction. That is, in the direction along the substrate normal, the closer to the substrate, the smaller the lateral dimension of any one or both of the sacrificial source-drain contact structures and the sacrificial gate plug. Correspondingly, when using the first planarization process... During the removal of the sacrificial source / drain contact structure, the sacrificial gate plug, and the sacrificial layer, as the thickness of the initial gate plug and the initial source / drain contact structure removed by the first planarization process increases, the initial gate plug and the initial source / drain contact structure can be gradually spaced apart, thereby achieving isolation between the gate plug and the source / drain contact structure. In summary, this embodiment of the invention utilizes the initial source / drain contact structure as the stopping position in the lateral direction to form the initial gate plug, and then uses the first planarization process to achieve the spacing between the gate plug and the source / drain contact structure, thereby simplifying the process flow for forming the gate plug and the source / drain contact structure, reducing the probability of bridging between the gate plug and the source / drain contact structure, thereby improving production efficiency and product yield, and optimizing the performance of the semiconductor structure. Attached Figure Description

[0010] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figures 4 to 5 This is a schematic diagram of the structure corresponding to each step in another method of forming a semiconductor structure;

[0012] Figures 6 to 24 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] As the background technology shows, the current semiconductor structure formation process still presents significant challenges. Specifically, the COAG process is particularly challenging. This paper will analyze a specific semiconductor structure formation method. Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1A substrate 1 is provided, on which a gate structure 2 is formed. A gate capping layer 3 is formed on the top surface of the gate structure 2. Sidewalls 4 are formed on the sidewalls of the gate structure 2 and the gate capping layer 3. Source and drain doped regions 5 are formed in the substrate 1 on both sides of the gate structure 2 and the sidewalls 4. A bottom dielectric layer (not shown) covering the source and drain doped regions 5 is formed on the exposed substrate 1 of the gate structure 2. The bottom dielectric layer is exposed on the top surface of the gate capping layer 3. A source and drain contact layer 6 is formed in the bottom dielectric layer that contacts the source and drain doped regions 5. The sidewalls of the source and drain contact layer 6 are in contact with the sidewalls 4.

[0015] refer to Figure 2 Remove a portion of the thickness of the source / drain contact layer 6 and the sidewall 4, and form a source / drain capping layer 7 on the source / drain contact layer 6. The sidewall of the source / drain capping layer 7 is in contact with the gate capping layer 3, and the source / drain capping layer 7 covers the top of the sidewall 4 and the source / drain contact layer 6.

[0016] refer to Figure 3 A top dielectric layer 8 is formed that covers the bottom dielectric layer 6, the gate cap layer 3, and the source / drain cap layer 7; a source / drain plug 9 is formed that penetrates the source / drain cap layer 7 and the top dielectric layer 8 and is in contact with the source / drain contact layer 6.

[0017] In the process of forming the source / drain plug 9, the above method requires first forming a source / drain via that penetrates the source / drain cap layer 7 and the top dielectric layer 8 and exposes the source / drain contact layer 6. Then, the source / drain plug 9 is formed in the source / drain via. During the formation of the source / drain via, it is easy to cause mis-etching of the sidewall 4 located on the sidewall of the source / drain contact layer 6, which can easily lead to the formation of a weak point at the top corner of the sidewall 4 (e.g., Figure 3 (As shown by the dotted coil in the middle), this causes the source / drain plug 9 to easily bridge or break down with the gate structure 2 at weak points, which in turn can easily reduce the performance of the semiconductor structure and the manufacturing yield.

[0018] Another formation method has been proposed. Figures 4 to 5 This is a schematic diagram of the steps involved in forming another semiconductor structure. The similarities between this method and the aforementioned method will not be repeated here; the differences are as follows: (Refer to...) Figure 4 A portion of the source / drain contact layer 6a is removed, and a source / drain cap layer 7a is formed on the source / drain contact layer 6a. The sidewall of the source / drain cap layer 7a is in contact with the sidewall of the sidewall 4a. (Reference) Figure 5 A top dielectric layer 8a is formed that covers the bottom dielectric layer, the gate cap layer 3a, and the source / drain cap layer 7a; a gate plug 9a is formed that penetrates the gate cap layer 3a and the top dielectric layer 8a and is in contact with the gate structure 2a.

[0019] In the process of forming the gate plug 9a, the above method requires first forming a gate via (not shown) that penetrates the gate cap layer 3a and the top dielectric layer 8a and exposes the gate structure 2a. Then, the gate plug 9a is formed in the gate via. During the formation of the gate via, the sidewalls 4a located on the sidewalls of the gate cap layer 3a and the gate structure 2a are easily etched incorrectly, which can lead to bridging or breakdown between the gate plug 9a and the source / drain contact layer 6a (e.g., Figure 5 (As shown by the dashed coil in the middle), this leads to poor performance of the semiconductor structure and reduced production yield. The semiconductor structure formation process still faces significant challenges.

[0020] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure. First, an initial gate plug is formed using an initial source-drain contact structure as a stop position in the lateral direction. Then, a first planarization process is used to achieve the spacing between the gate plug and the source-drain contact structure. This simplifies the process flow for forming the gate plug and the source-drain contact structure, reduces the probability of bridging between the gate plug and the source-drain contact structure, and thus helps improve production efficiency and product yield, as well as optimize the performance of the semiconductor structure.

[0021] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 6 to 24 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0022] refer to Figures 6 to 8 A substrate 100 is provided, on which a gate structure 110 is formed. Source / drain doped regions 140 are formed in the substrate 100 on both sides of the gate structure 110. A dielectric layer 200 is formed on the substrate 100, covering the sidewalls and top of the gate structure 110, as well as the source / drain doped regions 140. The gate structure 110 is located along the longitudinal direction (e.g., ...). Figure 6 Extending in the X direction (as shown in the middle), the direction perpendicular to the longitudinal direction is the transverse direction (as shown in the middle X direction). Figure 6 (As shown in the Y direction). In this embodiment, both the longitudinal and transverse directions are parallel to the surface of the substrate 100.

[0023] The substrate 100 provides a process platform for subsequent process fabrication. In this embodiment, the substrate 100 is used to form a fin field-effect transistor (FinFET). The substrate 100 is a three-dimensional substrate, including a substrate (not shown) and fins (not shown) protruding from the substrate. In this embodiment, the substrate is a silicon substrate, and the fins are made of the same material as the substrate. In other embodiments, the substrate may be other types of three-dimensional substrates. In some other embodiments, when forming a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0024] The gate structure 110 is used to control the opening or closing of the conductive channel. In this embodiment, the gate structure 110 spans the fin and covers part of the top surface and part of the sidewalls of the fin. In this embodiment, the gate structure 110 is a metal gate structure. In other embodiments, the gate structure may also be a polysilicon gate structure.

[0025] In this embodiment, a gate capping layer 120 is also formed on the top of the gate structure 110. The gate capping layer 120 serves to protect the top of the gate structure 110 in subsequent processes (e.g., forming source / drain contact structures that contact the source / drain doped regions 140). The gate capping layer 120 is made of a material that has etching selectivity with the dielectric layer 200. As an example, the material of the gate capping layer 120 is silicon nitride.

[0026] The source / drain doped regions 140 are used to provide a carrier source. In this embodiment, the source / drain doped regions 140 are also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped regions 140 are located in the fins on both sides of the gate structure 110.

[0027] The dielectric layer 200 is used to achieve isolation between adjacent devices, and also to achieve electrical isolation between the gate plug and the source / drain contact structure. The material of the dielectric layer 200 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride.

[0028] In this embodiment, the dielectric layer 200 covers the top of the gate cap layer 120.

[0029] In this embodiment, the step of providing the substrate 100 includes the following steps:

[0030] like Figure 6 and Figure 7 As shown, Figure 6 This is a top view. Figure 7 for Figure 6 A cross-sectional view along the x-direction shows a substrate 100, a gate structure 110 on the substrate 100, source / drain doped regions 140 located on both sides of the gate structure 110 in the substrate 100, and a bottom dielectric layer 150 located on the side portion of the substrate 100 of the gate structure 110, the bottom dielectric layer 150 covering the source / drain doped regions 140. In this embodiment, the bottom dielectric layer 150 is an interlayer dielectric (ILD). In this embodiment, the material of the bottom dielectric layer 150 is silicon oxide.

[0031] As an example, the steps of providing a substrate 100, a gate structure 110, source / drain doped regions 140, and a bottom dielectric layer 150 include: providing a substrate 100; forming a dummy gate structure (not shown) on the substrate 100; forming source / drain doped regions 140 in the substrate 100 on both sides of the dummy gate structure; forming a bottom dielectric layer 150 covering the source / drain doped regions 140 on the substrate 100 on the side of the dummy gate structure; removing the dummy gate structure and forming a gate opening (not shown) in the bottom dielectric layer 150; and forming a gate structure 110 in the gate opening.

[0032] In this embodiment, a sidewall 130 is also formed on the sidewall of the gate structure 110. Specifically, the sidewall 130 is formed on the sidewall of the dummy gate structure after the dummy gate structure is formed and before the source / drain doped regions 140 are formed.

[0033] Sidewall 130 is used to define the formation region of source / drain doped region 140 and to protect the sidewall of gate structure 110. In this embodiment, the material of sidewall 130 includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, and low-k dielectric materials.

[0034] In this embodiment, after forming the gate structure 110, a portion of the gate structure 110 thickness is removed, and a groove is formed on the top of the gate structure 110; a gate capping layer 120 is formed in the groove. In this embodiment, for ease of illustration and explanation, only the bottom dielectric layer 150 and the gate capping layer 120 are shown in the cross-sectional view.

[0035] like Figure 8 As shown, a top dielectric layer 160 is formed on the bottom dielectric layer 150, covering the top of the gate structure 110. The top dielectric layer 160 and the bottom dielectric layer 150 are used to form the dielectric layer 200.

[0036] The top dielectric layer 160 is used to achieve electrical isolation between the gate plug and the source / drain contact structure. The material of the top dielectric layer 160 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0037] In other embodiments, the formation method may further include: after providing the substrate, gate structure, source / drain doped regions, and bottom dielectric layer, and before forming the top dielectric layer, forming a source / drain contact layer that penetrates the top of the source / drain doped regions and contacts the source / drain doped regions. The source / drain contact layer is used to bring out the electrical properties of the source / drain doped regions, thereby enabling electrical connection between the source / drain doped regions and external circuits or other interconnect structures. The material of the source / drain contact layer may be a conductive material such as copper, tungsten, or cobalt.

[0038] refer to Figure 9 and Figure 10 , Figure 9 This is a top view. Figure 10 for Figure 9 The cross-sectional view along the xx direction, the method of forming also includes: after providing the substrate 100, forming a polishing stop layer 210 on the dielectric layer 200.

[0039] Subsequent steps include forming a sacrificial layer on the dielectric layer 200; forming an initial source / drain contact structure that penetrates the top of the source / drain doped region 140 through the dielectric layer 200 and the sacrificial layer, wherein the portion of the initial source / drain contact structure located in the sacrificial layer serves as the sacrificial source / drain contact structure; forming an initial gate plug that penetrates the top of the gate structure 110 through the dielectric layer 200 and the sacrificial layer, wherein the portion of the initial gate plug located in the sacrificial layer serves as the sacrificial gate plug; and removing the sacrificial source / drain contact structure, the sacrificial gate plug, and the sacrificial layer using a first planarization process.

[0040] By forming a polishing stop layer 210 on the dielectric layer 200 after it is formed and before the sacrificial layer is formed, the top surface of the polishing stop layer 210 can be used as the stop position for the first planarization process. This helps to reduce the difficulty of the first planarization process, accurately control the planarization thickness of the first planarization process, and improve the flatness and height consistency of the top surface of the initial gate plug and the initial source-drain contact structure after the first planarization process. This allows the top surface height of the formed gate plug and source-drain contact structure to be accurately controlled. In addition, the polishing stop layer 210 also helps to reduce the probability of damage to the top surface of the dielectric layer 200.

[0041] Therefore, the density and hardness of the material selected for the polishing stop layer 210 are higher than those of the dielectric layer 200, the subsequently formed sacrificial layer, the initial source / drain contact structure, and the initial gate plug material, thereby ensuring that the polishing stop layer 210 can define the stop position during the first planarization process. Specifically, the material of the polishing stop layer 210 includes one or more of silicon nitride, titanium nitride, silicon oxynitride, silicon carbonitride, and boron carbonitride.

[0042] In this embodiment, the polishing stop layer 210 is made of a dielectric material, which helps to reduce the impact of the polishing stop layer 210 on the semiconductor structure and improve the compatibility of the polishing stop layer 210 with subsequent processes. As an example, the polishing stop layer 210 is made of silicon nitride. Using silicon nitride is beneficial for improving process compatibility and reducing process costs. Furthermore, silicon nitride has high density and hardness, which helps to improve the effectiveness of the polishing stop layer 210 in defining the stop position of the first planarization process.

[0043] The grinding stop layer 210 should not be too thin, otherwise it will increase the risk of the grinding stop layer 210 being removed during the subsequent first planarization process, thereby reducing the effectiveness of the grinding stop layer 210 in defining the stop position of the first planarization process; the grinding stop layer 210 should also not be too thick, otherwise it will easily cause unnecessary waste of materials and time. In this embodiment, the thickness of the grinding stop layer 210 is 10nm to 100nm.

[0044] In this embodiment, the process for forming the grinding stop layer 210 includes one or more of chemical vapor deposition, atomic layer deposition, and physical vapor deposition. As an example, using atomic layer deposition to form the grinding stop layer 210 is beneficial for improving the thickness uniformity of the grinding stop layer 210, allowing for precise control of its thickness. Furthermore, atomic layer deposition also helps improve the density and film quality of the grinding stop layer 210 material.

[0045] Continue to refer to Figure 9 and Figure 10 , Figure 9 This is a top view. Figure 10 for Figure 9 A cross-sectional view along the xx direction shows that a sacrificial layer 220 is formed on the dielectric layer 200. Specifically, the sacrificial layer 220 is formed on the grinding stop layer 210.

[0046] The sacrificial layer 220, together with the dielectric layer 200, provides support for the formation of the initial source / drain contact structure and the initial gate plug. Subsequently, an initial source / drain contact structure is formed penetrating the top of the source / drain doped region 140 through the dielectric layer 200 and the sacrificial layer 220, with the portion of the initial source / drain contact structure located within the sacrificial layer 220 serving as the sacrificial source / drain contact structure. An initial gate plug is also formed penetrating the top of the gate structure 110 through the dielectric layer 200 and the sacrificial layer 210, with the portion of the initial gate plug located within the sacrificial layer serving as the sacrificial gate plug. The cross-section of either or both of the sacrificial source / drain contact structure and the sacrificial gate plug is an inverted trapezoidal structure. Then, a first planarization process is used to remove the sacrificial source / drain contact structure, the sacrificial gate plug, and the sacrificial layer 210, thereby allowing for a gap between the formed initial gate plug and the initial source / drain contact structure.

[0047] In this embodiment, the material of the sacrificial layer 220 is a dielectric material, which is beneficial to improve the compatibility between the sacrificial layer 220 and subsequent process steps. Moreover, the material of the sacrificial layer 220 is different from that of the grinding stop layer 210. In the subsequent first planarization process, the removal rate of the sacrificial layer 220 is different from that of the grinding stop layer 210, and the removal rate of the sacrificial layer 220 is faster, so that the first planarization process can stop on the grinding stop layer 210. In addition, since the sacrificial layer 220 will be removed later, the selection of the material of the sacrificial layer 220 is more flexible and free compared with the material of the dielectric layer 200.

[0048] In this embodiment, the material of the sacrificial layer 220 includes one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. As an example, the material of the sacrificial layer 220 is silicon oxide. The material of the sacrificial layer 220 is the same as that of the top dielectric layer 160, which is beneficial to further improve process compatibility.

[0049] The thickness of the sacrificial layer 220 should not be too small; otherwise, the thickness of the subsequent sacrificial source-drain contact structure and sacrificial gate plug will be too small. During the first planarization process, the thickness of the removed initial source-drain contact structure and initial gate plug will be relatively small, which may lead to an excessively small gap between the remaining initial source-drain contact structure and the remaining initial gate plug after the first planarization process. This is not conducive to reducing the parasitic capacitance between the source-drain contact structure and the gate plug. Conversely, the thickness of the sacrificial layer 220 should not be too large, as this may result in unnecessary material waste. Furthermore, an excessively large thickness of the subsequent sacrificial source-drain contact structure and sacrificial gate plug may increase the time required for the first planarization process, thereby reducing production capacity and increasing process risks and side effects. Therefore, in this embodiment, the thickness of the sacrificial layer 220 is between 10 nm and 1000 nm.

[0050] In this embodiment, a deposition process (e.g., chemical vapor deposition) is used to form the sacrificial layer 220.

[0051] refer to Figures 11 to 15 An initial source / drain contact structure 230 is formed, which penetrates the dielectric layer 200 and the sacrificial layer 220 at the top of the source / drain doped region 140 and is in contact with the source / drain doped region 140. The portion of the initial source / drain contact structure 230 located in the sacrificial layer 220 serves as the sacrificial source / drain contact structure 230(a).

[0052] refer to Figures 16 to 22With the initial source-drain contact structure 230 as the stopping position in the lateral direction, an initial gate plug 240 is formed, penetrating the dielectric layer 200 and the sacrificial layer 220 at the top of the gate structure 110, and is in contact with the gate structure 110. The portion of the initial gate plug 240 located in the sacrificial layer 220 is called the sacrificial gate plug 240(a). Either or both of the sacrificial source-drain contact structure 230(a) and the sacrificial gate plug 240(a) have an inverted trapezoidal cross-section in the lateral direction.

[0053] In this embodiment, after the initial source-drain contact structure 230 is formed, an initial gate plug 240 is formed through the dielectric layer 200 at the top of the gate structure 110, with the initial source-drain contact structure 230 as the stop position in the lateral direction. Thus, the formation position of the initial gate plug 240 is self-aligned through the initial source-drain contact structure 230, so that the initial gate plug 240 is located between adjacent initial source-drain contact structures 230 in the lateral direction. Moreover, the cross-section of any one or both of the sacrificial source-drain contact structure 230(a) and the sacrificial gate plug 240(a) in the lateral direction is an inverted trapezoidal structure. In the direction along the normal of the substrate 100, the lateral dimension of any one or both of the sacrificial source-drain contact structure 230(a) and the sacrificial gate plug 240(a) becomes smaller and smaller as they get closer to the substrate 100, so that there can be a gap between the initial source-drain contact structure 230 and the initial gate plug 240 near the top surface of the dielectric layer 200.

[0054] Accordingly, in the subsequent process of removing the sacrificial source-drain contact structure 230(a), the sacrificial gate plug 240(a), and the sacrificial layer 220 using the first planarization process, as the thickness of the initial gate plug 240 and the initial source-drain contact structure 230 removed by the first planarization process increases, the initial gate plug 240 and the initial source-drain contact structure 230 can be gradually separated, thereby achieving isolation between the gate plug and the source-drain contact structure and reducing the probability of bridging between the gate plug and the source-drain contact structure.

[0055] As an example, the cross-sections along the lateral direction of the sacrificial source-drain contact structure 230(a) and the sacrificial gate plug 240(a) are both inverted trapezoidal structures. In this embodiment, any one or both of the initial source-drain contact structure 230 and the initial gate plug 240 have inverted trapezoidal cross-sections along the lateral direction. As an example, the cross-sections along the lateral direction of the initial source-drain contact structure 230 and the initial gate plug 240 are both inverted trapezoidal structures.

[0056] In other embodiments, either the initial source / drain contact structure or the initial gate plug may have an inverted trapezoidal cross-section along the lateral direction, and the other may have a rectangular cross-section along the lateral direction. In still other embodiments, either or both of the portions of the initial source / drain contact structure located below the sacrificial source / drain contact structure and the portions of the initial gate plug located below the sacrificial gate plug may also have rectangular cross-sections along the lateral direction.

[0057] In this embodiment, the steps of forming the initial source-drain contact structure 230 and the initial gate plug 240 include:

[0058] refer to Figures 11 to 15 An initial source / drain contact structure 230 is formed, which penetrates the dielectric layer 200 and the sacrificial layer 220 at the top of the source / drain doped region 140 and is in contact with the source / drain doped region 140. The portion of the initial source / drain contact structure 230 located in the sacrificial layer 220 serves as the sacrificial source / drain contact structure 230(a).

[0059] In this embodiment, the initial source / drain contact structure 230 is made of copper. In other embodiments, the initial source / drain contact structure may also be made of conductive materials such as tungsten or cobalt.

[0060] As an example, the steps for forming the initial source-drain contact structure 230 include:

[0061] like Figures 11 to 12 As shown, a source / drain contact opening 250 is formed, penetrating the dielectric layer 200 and sacrificial layer 220 at the top of the source / drain doped region 140 and exposing the source / drain doped region 140.

[0062] The source / drain contact opening 250 provides space for forming the initial source / drain contact structure. In this embodiment, the source / drain contact opening 250 also extends through the polishing stop layer 210.

[0063] In this embodiment, the source / drain contact opening 250 penetrates the dielectric layer 200 and sacrificial layer 220 at the top of the source / drain doped region 140 and exposes the source / drain doped region 140. Subsequently, during the formation of the initial source / drain contact structure in the source / drain contact opening 250, the initial source / drain contact structure is a monolithic structure.

[0064] In this embodiment, the step of forming the source / drain contact opening 250 includes: as follows Figure 11 As shown, a source / drain contact mask layer 170 is formed on the sacrificial layer 220; as Figure 12 As shown, using the source / drain contact mask layer 170 as a mask, the sacrificial layer 220, the polishing stop layer 210, and the dielectric layer 200 are etched sequentially to form the source / drain contact opening 250; the source / drain contact mask layer 170 is then removed.

[0065] In this embodiment, the source / drain contact mask layer 170 is made of titanium nitride.

[0066] In this embodiment, an anisotropic etching process is used to sequentially etch the sacrificial layer 220, the polishing stop layer 210, and the dielectric layer 200. The anisotropic etching process has the characteristics of anisotropic etching, that is, the longitudinal etching rate is greater than the transverse etching rate, which is beneficial to improving the profile control of the source / drain contact opening 250 and improving the morphological quality of the source / drain contact opening 250.

[0067] After forming the source / drain contact opening 250, the source / drain contact mask layer 170 is removed.

[0068] like Figures 13 to 15 As shown, conductive material is filled into the source / drain contact opening 250 to form an initial source / drain contact structure 230. In this embodiment, the initial source / drain contact structure 230 is in contact with the source / drain doped region 140, and the initial source / drain contact structure 230 is a monolithic structure. This is beneficial for the initial source / drain structure 230 to have lower resistance and lower contact resistance with the source / drain doped region 140, thereby improving the subsequent RC delay and enhancing the performance of the semiconductor structure.

[0069] In this embodiment, the initial source-drain contact structure 230 extends longitudinally and is a long strip structure. Thus, in the transverse direction, the region between adjacent initial source-drain contact structures 230 locates the formation position of the initial gate plug, thereby realizing the self-alignment of the initial gate plug position. This is beneficial to improving the effect of the initial source-drain contact structure 230 as the self-alignment stop position of the gate plug 310 in the transverse direction, and further reducing the probability of bridging between the gate plug and the source-drain contact structure.

[0070] In this embodiment, the step of forming the initial source-drain contact structure 230 includes: as follows Figure 13 As shown, conductive material 260 is filled into the source / drain contact opening 250, and conductive material 260 is also formed on the sacrificial layer 220; as Figure 14 and Figure 15 As shown, Figure 14 This is a top view. Figure 15 for Figure 14 A cross-sectional view along the xx direction shows that the conductive material 260 on the sacrificial layer 220 has been removed, and the remaining conductive material 260 in the source-drain contact opening 250 is used as the initial source-drain contact structure 230.

[0071] In this embodiment, the process for forming the conductive material 260 includes one or more of physical vapor deposition, chemical vapor deposition, and electrochemical plating. In this embodiment, a chemical mechanical planarization process is used to remove the conductive material 260 located on the sacrificial layer 220.

[0072] In other embodiments, when a source / drain contact layer that contacts the source / drain doped region is formed in the bottom dielectric layer, the step of forming the initial source / drain contact structure includes: forming a source / drain contact hole that penetrates the top dielectric layer and the sacrificial layer on the source / drain contact layer to expose the source / drain contact layer; and forming an initial source / drain contact plug that contacts the source / drain contact layer in the source / drain contact hole to form the initial source / drain contact structure with the source / drain contact layer.

[0073] refer to Figures 16 to 20 With the initial source-drain contact structure 230 as the lateral stopping position, an initial gate plug 240 is formed, penetrating the dielectric layer 200 and sacrificial layer 220 at the top of the gate structure 110, and in contact with the gate structure 110. The portion of the initial gate plug 240 located in the sacrificial layer 220 serves as the sacrificial gate plug 240(a). The initial gate plug 240 is used to form the gate plug in a subsequent first planarization process.

[0074] In this embodiment, the initial gate plug 240 contacts the top of the gate structure 110 of the active area (AA), and the initial gate plug 240 penetrates the gate cap layer 120. Correspondingly, when the first planarization process is subsequently used to remove the sacrificial source-drain contact structure 230(a) and the sacrificial gate plug 240(a), the resulting gate plug is located above the gate structure 110 of the active area, and the gate plug is correspondingly an active gate contact hole plug (COAG). In this embodiment, the initial gate plug 240 is made of copper. In other embodiments, the initial gate plug can also be made of conductive materials such as tungsten or cobalt.

[0075] In this embodiment, the step of forming the initial gate plug 240 includes:

[0076] like Figures 16 to 19 As shown, with the initial source-drain contact structure 230 as the lateral stopping position, a gate contact hole 270 is formed in the dielectric layer 200 and sacrificial layer 220 on top of the gate structure 110, exposing the gate structure 110. The gate contact hole 270 is used to provide space for forming the gate plug.

[0077] In this embodiment, during the formation of the gate contact hole 270, since the sacrificial layer 220 and the initial source / drain contact structure 230, as well as the dielectric layer 200 and the initial source / drain contact structure 230, have a high etching selectivity, the etching process for forming the gate contact hole 270 has a low etching rate on the initial source / drain contact structure 230. As a result, the etching process for forming the gate contact hole 270 can use the initial source / drain contact structure 230 as the etching stop position in the lateral direction, thereby achieving self-alignment of the gate contact hole 270 in the lateral direction.

[0078] Specifically, the materials of the sacrificial layer 220 and the dielectric layer 200 are both dielectric materials, while the material of the initial source / drain contact structure 230 is a metallic material. A high etching selectivity can be easily achieved between the sacrificial layer 220 and the initial source / drain contact structure 230, as well as between the dielectric layer 200 and the initial source / drain contact structure 230. The etching process for forming the gate contact hole 270 has a low probability of causing mis-etching of the initial source / drain contact structure 230.

[0079] Specifically, the step of forming the gate contact hole 270 includes: as follows Figure 16 and Figure 17 As shown, Figure 16 This is a top view. Figure 17 for Figure 16 A cross-sectional view along the xx direction shows a hard mask layer 180 formed on the sacrificial layer 220 and the initial source / drain contact structure 230. A mask opening 185 is formed in the hard mask layer 180, located above the top of the gate structure 110 and laterally between the initial source / drain contact structures 230. Figure 18 and Figure 19 As shown, Figure 18 This is a top view. Figure 19 for Figure 18 A cross-sectional view along the xx direction shows that, with the hard mask layer 180 as the mask and the initial source / drain contact structure 230 as the stop position in the lateral direction, the sacrificial layer 220 and the dielectric layer 200 are etched along the mask opening 185 to form the gate contact hole 270.

[0080] The hard mask layer 180 is used as an etching mask for forming the gate contact hole. In this embodiment, the material of the hard mask layer 180 includes titanium nitride. The mask opening 185 is used to define the formation location of the gate contact hole.

[0081] As an example, the mask opening 185 also extends laterally to expose a portion of the top of the initial source / drain contact structure 230. In this embodiment, even though the mask opening 185 extends laterally above a portion of the initial source / drain contact structure 230, the initial source / drain contact structure 230 can be used as a laterally stopping position because there is a high etch selectivity between the sacrificial layer 220 and the initial source / drain contact structure 230, and between the dielectric layer 200 and the initial source / drain contact structure 230. This helps to reduce the dimensional accuracy requirements of the mask opening 185 and increase the process window for forming the mask opening 185 and the gate contact via.

[0082] The process for forming the gate contact hole 270 includes one or both of dry etching and wet etching processes. Specifically, along the mask opening 185, dry etching and wet etching processes are sequentially used to etch the sacrificial layer 220 and the dielectric layer 200 to form the gate contact hole 270.

[0083] In this embodiment, after forming the gate contact hole 270, the hard mask layer 180 is also removed.

[0084] like Figure 20 As shown, conductive material is filled into the gate contact hole 270 to form the initial gate plug 240.

[0085] In this embodiment, the initial gate plug 240 fills the gate contact hole 270 and is formed on the sacrificial layer 220 and the initial source / drain contact structure 230. In this embodiment, the process of filling the gate contact hole 270 with conductive material includes one or more of chemical vapor deposition, physical vapor deposition, and electrochemical plating.

[0086] refer to Figure 21 and Figure 22 , Figure 21 This is a top view. Figure 22 for Figure 21 In the cross-sectional view along the xx direction, the first planarization process is used to remove the sacrificial source-drain contact structure 230(a), the sacrificial gate plug 240(a), and the sacrificial layer 220, so that there is a gap between the initial gate plug 240 and the initial source-drain contact structure 230. The remaining initial gate plug 240 is used as the gate plug 310, and the remaining initial source-drain contact structure 230 is used as the source-drain contact structure 300.

[0087] One or both of the sacrificial source / drain contact structures 230(a) and sacrificial gate plugs 240(a) have an inverted trapezoidal cross-section in the lateral direction. In the direction along the normal to the substrate 100, the lateral dimension of one or both of the sacrificial source / drain contact structures 230(a) and sacrificial gate plugs 240(a) becomes smaller and smaller as they get closer to the substrate 100. As a result, there can be a gap between the initial source / drain contact structures 230 and the initial gate plugs 240 near the top surface of the dielectric layer 200. Correspondingly, after removing the sacrificial source / drain contact structures 230(a), the sacrificial gate plugs 240(a), and the sacrificial layer 220, there can be a gap between the remaining initial source / drain contact structures 230 and the initial gate plugs 240, thereby achieving isolation between the gate plugs 310 and the source / drain contact structures 300.

[0088] In summary, this embodiment utilizes the initial source-drain contact structure 230 as the stop position in the lateral direction to form the initial gate plug 240. Then, the spacing between the gate plug 310 and the source-drain contact structure 300 is realized through the first planarization process, which simplifies the process flow of forming the gate plug 310 and the source-drain contact structure 300, reduces the probability of bridging between the gate plug 310 and the source-drain contact structure 300, and thus improves production efficiency and product yield, as well as optimizes the performance of the semiconductor structure.

[0089] The gate plug 310 is used to realize the electrical connection between the gate structure 110 and the external circuit. In this embodiment, the gate plug 310 is formed above the gate structure 110 in the active region. The gate plug 310 is an active gate contact hole plug, which helps to save the chip area, thereby achieving further reduction in chip size.

[0090] The source / drain contact structure 300 contacts the source / drain doped region 140, thereby enabling electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures. In this embodiment, the source / drain contact structure 300 is a single-piece structure, which helps to reduce the resistance of the source / drain contact structure 300, thereby improving the subsequent RC delay and reducing power consumption. In this embodiment, the source / drain contact structure 300 is a long strip structure extending longitudinally.

[0091] In this embodiment, in the first planarization process, the top surface of the grinding stop layer 210 is used as the stop position to remove the sacrificial source / drain contact structure 230(a), the sacrificial gate plug 240(a), and the sacrificial layer 220. This helps to reduce the difficulty of the first planarization process, accurately control the planarization thickness of the first planarization process, and improve the flatness and height consistency of the top surface of the initial gate plug 240 and the initial source / drain contact structure 230 after the first planarization process. This allows the top surface height of the gate plug 310 and the source / drain contact structure 300 to be accurately controlled. In addition, it also helps to reduce the probability of damage to the top surface of the dielectric layer 200.

[0092] In this embodiment, the first planarization process includes a chemical mechanical planarization (CMP) process. CMP can achieve comprehensive planarization of various materials with different properties, improving planarization efficiency while also enhancing the flatness and height uniformity of the top surface of the planarized film.

[0093] refer to Figure 23 and Figure 24 , Figure 23 This is a top view. Figure 23 for Figure 23 The cross-sectional view along the xx direction shows that the formation method further includes: after removing the sacrificial source-drain contact structure 230(a), the sacrificial gate plug 240(b), and the sacrificial layer 220, removing the polishing stop layer 210 to expose the top surface of the dielectric layer 200. This prevents the polishing stop layer 210 from affecting the parasitic capacitance between the gate plug 310 and the source-drain contact structure 300, and facilitates the subsequent formation of a material with a low dielectric constant on the dielectric layer 200. This helps to reduce the parasitic capacitance of the semiconductor structure, thereby reducing RC delay and improving the performance of the semiconductor structure.

[0094] In this embodiment, a second planarization process is used to remove the polishing stop layer 210. During the removal of the polishing stop layer 210, a portion of the gate plug 310 and source / drain contact structure 300 are also removed. Accordingly, after removing the polishing stop layer 210 and a portion of the gate plug 310 and source / drain contact structure 300, the remaining gate plug 310 and source / drain contact structure 300 are flush with the top surface of the dielectric layer 200.

[0095] Accordingly, the present invention also provides a semiconductor structure. (See reference) Figure 21 and Figure 22 , Figure 21 This is a top view. Figure 22 for Figure 21 A cross-sectional view along the x-direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0096] In this embodiment, the semiconductor structure includes: a substrate 100; and a gate structure 110 located on the substrate 100, wherein the gate structure 110 is along the longitudinal direction (e.g., ...). Figure 21 Extending in the Y direction (as shown in the middle), the direction perpendicular to the longitudinal direction is the transverse direction (as shown in the middle Y direction). Figure 21 (As shown in the X direction); Source / drain doped regions 140 are located in the substrates 100 on both sides of the gate structure 110; a dielectric layer 200 is located on the substrate 100 and covers the sidewalls and top of the gate structure 110, as well as the source / drain doped regions 140; a polishing stop layer 210 is located on the dielectric layer 200; a source / drain contact structure 300 penetrates the dielectric layer 200 and polishing stop layer 210 at the top of the source / drain doped regions 140, and the source / drain contact structure 300 is in contact with the source / drain doped regions 140; a gate plug 310 penetrates the dielectric layer 200 and polishing stop layer 210 at the top of the gate structure 110, and the gate plug 310 is in contact with the gate structure 110, with a gap between the gate plug 310 and the source / drain contact structure 300, and the gate plug 310 is flush with the top surface of the source / drain contact structure 300 and the polishing stop layer 210.

[0097] In this embodiment, the semiconductor structure includes a polishing stop layer 210, and the gate plug 310 is flush with the top surface of the source / drain contact structure 300 and the polishing stop layer 210. This is because during the formation of the semiconductor structure, a sacrificial layer is also formed on the polishing stop layer 210. An initial source / drain contact structure is first formed, penetrating the sacrificial layer, the polishing stop layer 210, and the dielectric layer 200. Then, using the initial source / drain contact structure as the lateral stopping position, an initial gate plug is formed, penetrating the top of the dielectric layer 200 of the gate structure 110. This allows for self-alignment through the initial source / drain contact structure. The initial gate plug is positioned so that it is located between adjacent initial source / drain contact structures in the lateral direction. Then, the initial source / drain contact structure, the initial gate plug, and the sacrificial layer are planarized with the top surface of the grinding stop layer 210 as the stop position. This allows the initial gate plug and the initial source / drain contact structure to be gradually spaced apart, thereby achieving isolation between the gate plug 310 and the source / drain contact structure 300. This reduces the probability of bridging between the gate plug 310 and the source / drain contact structure 300, thereby optimizing the performance of the semiconductor structure.

[0098] In this embodiment, both the longitudinal and transverse directions are parallel to the surface of the substrate 100.

[0099] In this embodiment, substrate 100 is used to form a FinFET. Substrate 100 is a three-dimensional substrate, including a substrate and fins protruding from the substrate. In other embodiments, the substrate may be other types of three-dimensional substrates. In still other embodiments, when forming a planar field-effect transistor, the substrate is a planar substrate.

[0100] The gate structure 110 is used to control the opening or closing of the conductive channel. In this embodiment, the gate structure 110 spans the fin and covers part of the top surface and part of the sidewalls of the fin. In this embodiment, the gate structure 110 is a metal gate structure. In other embodiments, the gate structure may also be a polysilicon gate structure.

[0101] In this embodiment, the semiconductor structure further includes a gate cap layer 120, located between the top of the gate structure 110 and the dielectric layer 200. The gate cap layer 120 serves to protect the top of the gate structure 110 during the formation of the semiconductor structure. The gate cap layer 120 is made of a material that has etching selectivity with the dielectric layer 200. As an example, the material of the gate cap layer 120 is silicon nitride.

[0102] In this embodiment, the semiconductor structure further includes a sidewall 130 located on the sidewalls of the gate structure 110 and the gate cap layer 120. The sidewall 130 is used to define the formation region of the source / drain doped region 140 and to protect the sidewalls of the gate structure 110.

[0103] The source / drain doped regions 140 are used to provide a carrier source. In this embodiment, the source / drain doped regions 140 are also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped regions 140 are located in the fins on both sides of the gate structure 110.

[0104] The dielectric layer 200 is used to achieve isolation between adjacent devices and to achieve electrical isolation between the gate plug 310 and the source-drain contact structure 300. The dielectric layer 200 is made of a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the dielectric layer 200 covers the top of the gate cap layer 120.

[0105] In this embodiment, the dielectric layer 200 is a stacked structure, including: a bottom dielectric layer 150, located on the substrate 100 on the side of the gate structure 110 and covering the source / drain doped regions 140; and a top dielectric layer 160, located on the bottom dielectric layer 150 and covering the top of the gate structure 110. For a detailed description of the bottom dielectric layer 150 and the top dielectric layer 160, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0106] The grinding stop layer 210 is used to define the stop position during the first planarization process of forming the gate plug 310 and the source-drain contact structure 300. This helps to reduce the difficulty of the first planarization process, accurately control the planarization thickness of the first planarization process, improve the flatness and height consistency of the top surface of the gate plug 310 and the source-drain contact structure 300, and accurately control the height of the top surface of the gate plug 310 and the source-drain contact structure 300. The grinding stop layer 210 also helps to reduce the probability of damage to the top surface of the dielectric layer 200.

[0107] Therefore, the density and hardness of the polishing stop layer 210 material are higher than those of the dielectric layer 200, the source / drain contact structure 300, and the gate plug 310. In this embodiment, the polishing stop layer 210 is made of a dielectric material, thereby reducing the impact of the polishing stop layer 210 on the semiconductor structure and allowing the polishing stop layer 210 to remain within the semiconductor structure. Specifically, the polishing stop layer 210 material includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon boron carbonitride. As an example, the polishing stop layer 210 is made of silicon nitride. Using silicon nitride material is beneficial for improving process compatibility and reducing process costs, and silicon nitride material also has high density and hardness.

[0108] To ensure the effectiveness of the grinding stop layer 210 in defining the stop position during the first planarization process, and to avoid wasting process time and materials, in this embodiment, the thickness of the grinding stop layer 210 is 10nm to 100nm.

[0109] The source / drain contact structure 300 is used to electrically connect the source / drain doped region 140 to the external circuit. In this embodiment, the source / drain contact structure 300 is an integral structure, which helps to reduce the resistance of the source / drain contact structure 300, thereby improving the subsequent RC delay and reducing power consumption.

[0110] In other embodiments, the source / drain contact structure may not be a monolithic structure. The source / drain contact structure includes: a source / drain contact layer that penetrates the bottom dielectric layer on top of the source / drain doped region and is in contact with the source / drain doped region; and a source / drain contact plug that penetrates the top dielectric layer on the source / drain contact layer and is in contact with the source / drain contact layer.

[0111] In this embodiment, the source-drain contact structure 300 is a long strip structure extending longitudinally. Correspondingly, during the formation of the source-drain contact structure 300, the initial source-drain contact structure is also a long strip structure extending longitudinally. Thus, in the lateral direction, the area between adjacent initial source-drain contact structures is used to locate the formation position of the gate plug, thereby realizing the self-alignment of the gate plug 310. This is beneficial to improving the effect of the initial source-drain contact structure as the self-alignment stop position of the gate plug 310 in the lateral direction, and further reducing the probability of bridging between the gate plug 310 and the source-drain contact structure 300.

[0112] In this embodiment, the source / drain contact structure 300 is made of copper. In other embodiments, the source / drain contact structure may also be made of conductive materials such as tungsten or cobalt.

[0113] The gate plug 310 is used to realize the electrical connection between the gate structure 110 and the external circuit. In this embodiment, the gate plug 310 is in contact with the gate structure 110 of the active region. The gate plug 310 is an active gate contact hole plug, which helps to save chip area and further reduce chip size.

[0114] In this embodiment, the gate plug 310 penetrates the gate cap layer 120. In this embodiment, the gate plug 310 is made of copper. In other embodiments, the gate plug may also be made of conductive materials such as tungsten or cobalt.

[0115] In this embodiment, any one or both of the source / drain contact structures 300 and the gate plug 310 have an inverted trapezoidal cross-section in the lateral direction. That is, in the direction along the normal to the substrate 100, the closer to the substrate 100, the smaller the lateral dimension of any one or both of the gate plug 310 and the source / drain contact structures 300. During the formation of the gate plug 310 and the source / drain contact structures 300, there can be a gap between the initial source / drain contact structures and the initial gate plug near the top surface of the dielectric layer 200. After the initial source / drain contact structures and the initial gate plug above the top surface of the dielectric layer 200 are removed using the first planarization process, electrical isolation can be achieved between the formed source / drain contact structures 300 and the gate plug 310. As an example, both the source / drain contact structures 300 and the gate plug 310 have an inverted trapezoidal cross-section in the lateral direction.

[0116] In other embodiments, one of the source / drain contact structure and the gate plug may have an inverted trapezoidal cross-section along the lateral direction, while the other may have a rectangular cross-section along the lateral direction. In still other embodiments, both the source / drain contact structure and the gate plug may have rectangular cross-sections along the lateral direction.

[0117] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a gate structure is formed, and source / drain doped regions are formed in the substrate on both sides of the gate structure. A dielectric layer is formed on the substrate, covering the sidewalls and top of the gate structure and the source / drain doped regions. The gate structure extends longitudinally, and the direction perpendicular to the longitudinal direction is transverse. A sacrificial layer is formed on the dielectric layer; An initial source / drain contact structure is formed, which extends through the top of the source / drain doped region and the dielectric layer and the sacrificial layer, and is in contact with the source / drain doped region. The portion of the initial source / drain contact structure located in the sacrificial layer serves as a sacrificial source / drain contact structure. Using the initial source-drain contact structure as the stop position in the lateral direction, an initial gate plug is formed in a self-aligned manner, penetrating the dielectric layer and the sacrificial layer at the top of the gate structure, and in contact with the gate structure. The portion of the initial gate plug located in the sacrificial layer serves as the sacrificial gate plug. Wherein, along the lateral direction, the top of the sacrificial gate plug is directly adjacent to and in contact with the top of the sacrificial source / drain contact structure, and any one or both of the sacrificial source / drain contact structure and the sacrificial gate plug have an inverted trapezoidal cross-section along the lateral direction. A first planarization process is used to remove the sacrificial source-drain contact structure, the sacrificial gate plug, and the sacrificial layer, so that there is a gap between the initial gate plug and the initial source-drain contact structure. The remaining initial gate plug is used as a gate plug, and the remaining initial source-drain contact structure is used as a source-drain contact structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the initial source / drain contact structure includes: forming a source / drain contact opening that penetrates the dielectric layer and the sacrificial layer at the top of the source / drain doped region, wherein the source / drain contact opening exposes the source / drain doped region; The source-drain contact opening is filled with conductive material to form the initial source-drain contact structure.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of forming the initial source-drain contact structure, the initial source-drain contact structure extends along the longitudinal direction and is a long strip structure.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of providing a substrate, a gate structure, source / drain doped regions, and the dielectric layer include: providing a substrate, a gate structure located on the substrate, source / drain doped regions located in substrates on both sides of the gate structure, and a bottom dielectric layer located on a side substrate of the gate structure, the bottom dielectric layer covering the source / drain doped regions; forming a top dielectric layer on the bottom dielectric layer to cover the top of the gate structure, the top dielectric layer and the bottom dielectric layer constituting the dielectric layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method for forming the semiconductor structure further includes: after providing a substrate, a gate structure, source / drain doped regions, and a bottom dielectric layer, and before forming the top dielectric layer, forming a source / drain contact layer that penetrates the top of the source / drain doped regions and contacts the source / drain doped regions. The steps of forming the initial source-drain contact structure include: forming a source-drain contact hole through the top dielectric layer and the sacrificial layer on the source-drain contact layer to expose the source-drain contact layer; forming an initial source-drain contact plug in the source-drain contact hole to contact the source-drain contact layer, wherein the initial source-drain contact plug and the source-drain contact layer constitute the initial source-drain contact structure.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the initial gate plug includes: forming a gate contact hole in the dielectric layer and sacrificial layer on top of the gate structure, with the initial source-drain contact structure as the stopping position in the lateral direction, to expose the gate structure; and filling the gate contact hole with conductive material to form the initial gate plug.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The step of forming the gate contact hole includes: forming a hard mask layer on the sacrificial layer and the initial source / drain contact structure, wherein a mask opening is formed in the hard mask layer, the mask opening is located above the top of the gate structure and is laterally located between the initial source / drain contact structures; using the hard mask layer as a mask and the initial source / drain contact structure as the lateral stopping position, etching the sacrificial layer and the dielectric layer along the mask opening to form the gate contact hole.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of filling the gate contact hole with conductive material, the initial gate plug is filled in the gate contact hole and is also formed on the sacrificial layer and the initial source-drain contact structure.

9. The method for forming a semiconductor structure according to any one of claims 1 to 8, characterized in that, The method for forming the semiconductor structure further includes: after providing the substrate and before forming the sacrificial layer, forming a polishing stop layer on the dielectric layer; In the first planarization process, the sacrificial source-drain contact structure, the sacrificial gate plug, and the sacrificial layer are removed with the top surface of the grinding stop layer as the stop position.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the semiconductor structure further includes: after removing the sacrificial source-drain contact structure, the sacrificial gate plug, and the sacrificial layer using a first planarization process, removing the polishing stop layer to expose the top surface of the dielectric layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The step of removing the grinding stop layer includes: using a second planarization process to remove the grinding stop layer.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the polishing stop layer, the material of the polishing stop layer includes one or more of silicon nitride, titanium nitride, silicon oxynitride, silicon carbonitride, and boron carbonitride.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the sacrificial layer, the thickness of the sacrificial layer is from 10 nm to 1000 nm.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the sacrificial layer, the material of the sacrificial layer includes one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first planarization process includes a chemical mechanical planarization process.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The cross-section of either or both of the initial source / drain contact structure and the initial gate plug along the transverse direction is an inverted trapezoidal structure.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed by the method according to any one of claims 1 to 16, comprising: Base; A gate structure is located on the substrate, the gate structure extends longitudinally, and the direction perpendicular to the longitudinal direction is the lateral direction; The source and drain doped regions are located in the substrate on both sides of the gate structure; A dielectric layer is located on the substrate and covers the sidewalls and top of the gate structure, as well as the source and drain doped regions; A grinding stop layer is located on the dielectric layer; A source / drain contact structure extends through the dielectric layer and the polishing stop layer at the top of the source / drain doped region, and the source / drain contact structure is in contact with the source / drain doped region; A gate plug extends through the dielectric layer and the polishing stop layer at the top of the gate structure, the gate plug is in contact with the gate structure, there is a gap between the gate plug and the source / drain contact structure, and the gate plug is flush with the top surface of the source / drain contact structure and the polishing stop layer.

18. The semiconductor structure as claimed in claim 17, characterized in that, The source-drain contact structure is an integral structure.

19. The semiconductor structure as claimed in claim 18, characterized in that, The source / drain contact structure extends along the longitudinal direction and is a long strip structure.

20. The semiconductor structure as claimed in claim 18, characterized in that, The dielectric layer includes: a bottom dielectric layer located on the substrate on the side of the gate structure and covering the source / drain doped regions; and a top dielectric layer located on the bottom dielectric layer and covering the top of the gate structure.

21. The semiconductor structure as claimed in claim 20, characterized in that, The source / drain contact structure includes: a source / drain contact layer that penetrates the bottom dielectric layer on top of the source / drain doped region and is in contact with the source / drain doped region; and a source / drain contact plug that penetrates the top dielectric layer on the source / drain contact layer and is in contact with the source / drain contact layer.

22. The semiconductor structure as claimed in claim 17, characterized in that, The thickness of the grinding stop layer is 10 nm to 100 nm.

23. The semiconductor structure as claimed in claim 17, characterized in that, The material of the grinding stop layer is a dielectric material; the material of the grinding stop layer includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron carbonitride.

24. The semiconductor structure as claimed in claim 17, characterized in that, The cross-section of any one or both of the source / drain contact structure and the gate plug along the transverse direction is an inverted trapezoidal structure.

25. The semiconductor structure as claimed in claim 18, characterized in that, The semiconductor structure further includes: a gate cap layer, located between the top of the gate structure and the dielectric layer; The gate plug contacts the top of the gate structure in the active region, and the gate plug penetrates the gate cap layer.

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