Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure comprises: providing a substrate, the substrate comprising a first region, a second region and an isolation structure, the isolation structure being located between the first region and the second region; forming a first protrusion on a part of the surface of the isolation structure; forming a first gate dielectric layer on the first region, removing the first protrusion and forming a second gate dielectric layer on the second region; forming a first gate on the first gate dielectric layer; and forming a second gate on the second gate dielectric layer. The semiconductor structure comprises: a substrate comprising a first region, a second region and an isolation structure; a first gate dielectric layer and a second gate dielectric layer located above the first region and the second region respectively; and a first gate and a second gate located on the surface of the first gate dielectric layer and the second gate dielectric layer respectively. The present disclosure improves the technical problem of excessive etching of the isolation structure and standby leakage of the transistor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In the semiconductor field, leakage current has always been a significant factor reducing processor yield, hindering performance improvements, and impacting power consumption reduction. As transistor manufacturing processes shrink, processor core area decreases, leading to a substantial increase in energy density per unit area, making leakage current issues more pronounced. If not effectively addressed, power consumption may even increase. Traditional silicon dioxide gate dielectric processes have reached a bottleneck. Therefore, to effectively solve the leakage current problem, a new high-k metal gate structure (HKMG) is employed. Compared to traditional processes, HKMG significantly reduces leakage current while effectively controlling power consumption, resulting in a significant increase in transistor density, and simultaneously providing higher performance and lower power consumption. Summary of the Invention

[0003] This disclosure provides a method for preparing a semiconductor structure and the semiconductor structure itself.

[0004] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including a first region, a second region, and an isolation structure, the isolation structure being located between the first region and the second region; forming a first protrusion on a portion of the surface of the isolation structure; forming a first gate dielectric layer on the first region; removing the first protrusion; forming a second gate dielectric layer on the second region; forming a first gate on the first gate dielectric layer; and forming a second gate on the second gate dielectric layer.

[0005] In some disclosed embodiments, the process includes: forming a first hard mask layer on the surfaces of the first region and the second region; forming a first mask layer on the surface of the substrate, the first mask layer covering the first region and a portion of the isolation structure; etching the isolation structure and the first hard mask layer using the first mask layer as a mask, forming a first protrusion on the surface of the isolation structure; and removing the first mask layer and the first hard mask layer.

[0006] In some disclosed embodiments, a third gate dielectric layer is formed on the surfaces of the first and second regions, the third gate dielectric layer being located below the first hard mask layer.

[0007] In some disclosed embodiments, the isolation structure, the first hard mask layer, and the third gate dielectric layer are etched using the first mask layer as a mask to form a first protrusion on the surface of the isolation structure; the first mask layer, the first hard mask layer, and the third gate dielectric layer are then removed.

[0008] In some disclosed embodiments, after a first protrusion is formed on a portion of the surface of the isolation structure, a second initial gate dielectric layer is formed on the surfaces of the first region, the first protrusion, and the second region; a second mask layer is formed over the second initial gate dielectric layer, the second mask layer covering the second region and a portion of the isolation structure, exposing the first protrusion and the first region; the second initial gate dielectric layer is etched with the second mask layer to form a second gate dielectric layer, the second gate dielectric layer covering the surface of the second region.

[0009] In some disclosed embodiments, the second initial gate dielectric layer and the first protrusion in the first region are etched using the second mask layer as a mask to remove the second initial gate dielectric layer and the first protrusion on the first region.

[0010] In some disclosed embodiments, forming the first gate dielectric layer on the first region includes forming the first gate dielectric layer by an epitaxial growth process.

[0011] In some disclosed embodiments, the material used for the first gate dielectric layer includes a strained material.

[0012] In some disclosed embodiments, the first gate and / or the second gate include: a second hard mask layer, a metal layer, a buffer layer, and a high dielectric constant layer.

[0013] In some disclosed embodiments, the first mask layer is removed using a dry etching process.

[0014] In some disclosed embodiments, the isolation structure is made of materials including SiO2 and / or SiON.

[0015] In some disclosed embodiments, the material used for the second gate dielectric layer includes oxide materials.

[0016] In some disclosed embodiments, a pre-cleaning step is included before forming the first gate dielectric layer.

[0017] In some disclosed embodiments, the first gate dielectric layer and the second gate dielectric layer are flush in height.

[0018] This disclosure also provides a semiconductor structure, comprising: a substrate including a first region, a second region, and an isolation structure, the isolation structure being located between the first region and the second region; a first gate dielectric layer being located above the first region; a second gate dielectric layer being located above the second region; a first gate being located on the surface of the first gate dielectric layer; and a second gate being located on the surface of the second gate dielectric layer.

[0019] In some disclosed embodiments, the first gate and / or the second gate include: a second hard mask layer, a metal layer, a buffer layer, and a high dielectric constant layer.

[0020] In some disclosed embodiments, the first gate dielectric layer and the second gate dielectric layer are flush in height.

[0021] In some disclosed embodiments, the material used for the first gate dielectric layer includes a strained material.

[0022] In some disclosed embodiments, the isolation structure is made of materials including SiO2 and / or SiON.

[0023] In some disclosed embodiments, the material used for the second gate dielectric layer includes oxide materials.

[0024] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself, which effectively improves the problem of excessive etching of the isolation structure during semiconductor structure fabrication and the technical problem of transistor standby leakage. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the specific embodiments of this disclosure, the drawings used in the specific embodiments of this disclosure will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Appendix Figure 1 The diagram shows the steps of a method for fabricating a semiconductor structure according to a specific embodiment of this disclosure.

[0027] Appendix Figure 2A-2D The attached image shows... Figure 1 A schematic diagram of the process steps S10-S13.

[0028] Appendix Figure 3 The diagram shows the steps of the method for forming the first protrusion of this disclosure.

[0029] Appendix Figures 4A-4D The attached image shows... Figure 3 Process diagram of steps S31-S34.

[0030] Appendix Figure 5 The diagram shows the steps of the method for forming the first gate dielectric layer and the second gate dielectric layer of this disclosure.

[0031] Appendix Figures 6A-6E The attached image shows... Figure 5 Process diagram of steps S51-S55. Detailed Implementation

[0032] The technical solutions of the specific embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described specific embodiments are only a part of the specific embodiments of this disclosure, and not all of them. Based on the specific embodiments in this disclosure, all other specific embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0033] In order to improve the over-etching phenomenon of isolation structure and substrate during semiconductor structure fabrication, and the technical problem of transistor leakage, this disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure.

[0034] Appendix Figure 1 The diagram shows the steps of a method for fabricating a semiconductor structure according to a specific embodiment of this disclosure.

[0035] The method for fabricating the semiconductor structure includes: step S10, providing a substrate 20, the substrate 20 including a first region 201, a second region 202 and an isolation structure 203, the isolation structure 203 being located between the first region 201 and the second region 202; step S11, forming a first protrusion 207 on a portion of the surface of the isolation structure 203; step S12, forming a first gate dielectric layer 211 on the first region 201, removing the first protrusion 207, and forming a second gate dielectric layer 212 on the second region 202; step S13, forming a first gate 220 on the first gate dielectric layer 211; and forming a second gate 230 on the second gate dielectric layer 212.

[0036] Appendix Figure 2A-2D The attached image shows... Figure 1 A schematic diagram of steps S10-S13. See attached diagram for reference. Figure 2A-2D As shown, the steps of the method for preparing a semiconductor structure according to a specific embodiment of the present disclosure will be described in detail.

[0037] Please see the appendix Figure 2A and attached Figure 1 As shown, in step S10, a substrate 20 is provided. The substrate 20 includes a first region 201, a second region 202, and an isolation structure 203, wherein the isolation structure 203 is located between the first region 201 and the second region 202. Further, a first hard mask layer 205 is disposed on the surfaces of the first region 201 and the second region 202. The steps for setting the first hard mask layer 205 will be described in detail later.

[0038] In one specific embodiment of this disclosure, the substrate 20 may be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be other materials, such as gallium arsenide or other III-V group compounds. In this embodiment, the substrate 20 is made of single-crystal silicon (Si).

[0039] Furthermore, the isolation structure 203 is made of materials including SiO2 and / or SiON, and has the functions of forming isolation regions for transistors and dividing P-wells and N-wells. In one specific embodiment of this disclosure, the first region 201 is used to form a P-type field-effect transistor, and the second region 202 is used to form an N-type field-effect transistor. In other specific embodiments of this disclosure, the first region 201 may be used to form an N-type field-effect transistor, and the second region 202 may be used to form a P-type field-effect transistor. Optionally, a third gate dielectric layer 204 is formed on the surfaces of the first region 201 and the second region 202. The third gate dielectric layer 204 is made of materials including SiO2 and / or SiON. The third gate dielectric layer 204 is disposed around the isolation structure 203 and has the function of preventing excessive etching of the substrate 20. Furthermore, a first hard mask layer 205 is disposed on the surface of the third gate dielectric layer 204.

[0040] Please see the appendix Figure 2B and attached Figure 1 As shown, in step S11, a first protrusion 207 is formed on a portion of the surface of the isolation structure 203. If the gate dielectric layer is formed directly on the surface of the substrate, the isolation structure can easily be damaged during etching and photoresist cleaning, leading to over-etching of the substrate and leakage current in the subsequently formed transistor. In this embodiment, the first protrusion 207 serves as a step, which can protect the substrate and isolation structure from over-etching during the subsequent formation of the first gate dielectric layer, avoiding trenches around the gate and preventing leakage current. In this specific embodiment, a step is formed on the surface of the isolation structure 203 by etching a portion of the isolation structure 203; this step is the first protrusion 207. Optionally, after forming the first protrusion 207, the third gate dielectric layer 204 is removed.

[0041] In this specific embodiment, the first protrusion 207 is formed on the isolation structure 203 near the first region 201; in other specific embodiments of the present invention, the first protrusion 207 may also be formed on the isolation structure 203 near the second region 202. The following description continues with the example of the first protrusion 207 being formed on the isolation structure 203 near the first region 201.

[0042] Furthermore, this disclosure describes a method for forming the first protrusion 207. (See attached document.) Figure 3 The step diagram shown further includes the following steps: Step S31, forming a first protrusion 207 on a portion of the surface of the isolation structure 203; Step S32, forming a first hard mask layer 205 on the surfaces of the first region 201 and the second region 202; Step S33, forming a first mask layer 206 on the surface of the substrate 20, the first mask layer 206 covering the first region 201 and a portion of the isolation structure 203; Step S34, etching the isolation structure 203 and the first hard mask layer 205 using the first mask layer 206 as a mask, forming the first protrusion 207 on the surface of the isolation structure 203; Step S35, removing the first mask layer 206 and the first hard mask layer 205.

[0043] Appendix Figures 4A-4D The attached image shows... Figure 3 Process diagrams for steps S31-S33. (See attached diagram) Figures 4A-4D As shown, the method for forming the first protrusion 207 listed in this disclosure will be described in detail.

[0044] Please see the appendix Figure 4A and attached Figure 3 As shown, in step S31, a first hard mask layer 205 is formed on the surfaces of the first region 201 and the second region 202. In one specific embodiment of this disclosure, a third gate dielectric layer 204 is formed on the surfaces of the first region 201 and the second region 202, and the third gate dielectric layer 204 is located below the first hard mask layer 205. The material used for the third gate dielectric layer 204 includes SiO2 and / or SiON. The material used for the first hard mask layer 205 is selected from one or more hard materials such as SiN and SiCN, and is used to protect the substrate 20 and the isolation structure 203 in subsequent etching steps. In other specific embodiments of this disclosure, the first hard mask layer 205 may also be a stacked layer.

[0045] Please see the appendix Figure 4B and attached Figure 3 As shown, in step S32, a first mask layer 206 is formed on the surface of the substrate 20, the first mask layer 206 covering the first region 201 and part of the isolation structure 203. In a specific embodiment of this disclosure, the first mask layer 206 is a patterned mask layer, which is used as a mask in subsequent etching steps.

[0046] Please see the appendix Figure 4C and attached Figure 3As shown, in step S33, the isolation structure 203 and the first hard mask layer 205 are etched using the first mask layer 206 as a mask, forming a first protrusion 207 on the surface of the isolation structure 203. In a specific embodiment of this disclosure, the isolation structure 203, the first hard mask layer 205, and the third gate dielectric layer 204 are etched using the first mask layer 206 as a mask, forming a first protrusion 207 on the surface of the isolation structure 203. Using the first protrusion 207 as a step, the substrate and isolation structure can be protected from excessive etching during the subsequent formation of the first gate dielectric layer, avoiding leakage. In this specific embodiment, by etching the isolation structure 203 and the first hard mask layer 205 not covered by the first mask layer 206, a step is formed on the surface of the isolation structure 203; this step is the first protrusion 207.

[0047] Please see the appendix Figure 4D and attached Figure 3 As shown, in step S34, the first mask layer 206 and the first hard mask layer 205 are removed. In one specific embodiment of this disclosure, the first mask layer 206 is removed using a dry etching process. Using a dry etching process allows for precise removal of the first mask layer 206, avoiding corrosion of other structures. In one specific embodiment of this disclosure, the first mask layer 206, the first hard mask layer 205, and the third gate dielectric layer 204 are removed. During this step, while removing the first hard mask layer 205, the first protrusion 207 is also etched to a certain extent, but this does not etch the structures that need to be retained in subsequent steps.

[0048] After the above steps are completed, an attachment is formed. Figure 2B The first protrusion 207 is shown.

[0049] Please continue to refer to the appendix. Figure 2C and attached Figure 1 As shown, in step S12, a first gate dielectric layer 211 is formed on the first region 201, the first protrusion 207 is removed, and a second gate dielectric layer 212 is formed on the second region 202. In a specific embodiment of this disclosure, the first gate dielectric layer 211 is located above the first region 201; the second gate dielectric layer 212 is located above the second region 202. The gate dielectric materials used in the first gate dielectric layer 211 and the second gate dielectric layer 212 include strained materials and high dielectric constant materials to improve the breakdown voltage and reduce the gate leakage current. The heights of the first gate dielectric layer 211 and the second gate dielectric layer 212 are flush.

[0050] Furthermore, this disclosure describes a method for forming the first gate dielectric layer 211 and the second gate dielectric layer 212. (See attached document.) Figure 5The step diagram of the method for forming the first gate dielectric layer and the second gate dielectric layer shown further includes: step S51, after forming a first protrusion 207 on a portion of the surface of the isolation structure 203, forming a second initial gate dielectric layer 208 on the surfaces of the first region 201, the first protrusion 207, and the second region 202; step S52, forming a second mask layer 209 above the second initial gate dielectric layer 208, the second mask layer 209 covering the second region 202 and a portion of the isolation structure 203, exposing the first protrusion 207 and the first region 201; step S53, etching the second initial gate dielectric layer 208 with the second mask layer 209 to form a second gate dielectric layer 212, the second gate dielectric layer 212 covering the surface of the second region 202; step S54, forming a first gate dielectric layer 211 on the first region 201; step S55, removing the second mask layer.

[0051] Appendix Figures 6A-6E The attached image shows... Figure 5 Process diagrams for steps S51-S55. (See attached document for reference.) Figures 6A-6E As shown, the steps of the method for forming the first gate dielectric layer and the second gate dielectric layer of this disclosure will be described in detail.

[0052] Please see the appendix Figure 6A and attached Figure 5 As shown, in step S51, after the first protrusion 207 is formed on a portion of the surface of the isolation structure 203, a second initial gate dielectric layer 208 is formed on the surfaces of the first region 201, the first protrusion 207, and the second region 202. In a specific embodiment of this disclosure, the second initial gate dielectric layer 208 is formed using processes such as ISSG, and the second initial gate dielectric layer 208 has a dense structure, and a dense second gate dielectric layer 212 continues to be formed in subsequent processes.

[0053] Please see the appendix Figure 6B and attached Figure 5 As shown, in step S52, a second mask layer 209 is formed above the second initial gate dielectric layer 208. The second mask layer 209 covers the second region 202 and part of the isolation structure 203, exposing the first protrusion 207 and the first region 201. The second mask layer 209 is disposed in the area not covered by the first mask layer 206.

[0054] Please see the appendix Figure 6C and attached Figure 5As shown, in step S53, the second initial gate dielectric layer 208 is etched using the second mask layer 209 as a mask to form a second gate dielectric layer 212, which covers the surface of the second region 202. In one specific embodiment of this disclosure, the second initial gate dielectric layer 208 and the first protrusion 207 of the first region 201 are etched using the second mask layer 209 as a mask to remove the second initial gate dielectric layer 208 and the first protrusion 207 from the first region 201. In one specific embodiment of this disclosure, the material used for the second gate dielectric layer 212 includes an oxide material. The second mask layer 209 acts as a mask during etching to define the formation area of ​​the first gate dielectric layer 211.

[0055] Please see the appendix Figure 6D and attached Figure 5 As shown, in step S54, a first gate dielectric layer 211 is formed on the first region 201. In this specific embodiment, the first gate dielectric layer 211 covers the surface of the first region 201 and a portion of the isolation structure 203; the second gate dielectric layer 212 covers the second region 202, a portion of the isolation structure 203, and a portion of the substrate 20 surface. In other specific embodiments of this disclosure, the first gate dielectric layer 211 may only cover the surface of the first region 201, and the second gate dielectric layer 212 may only cover the surface of the second region 202.

[0056] Furthermore, forming the first gate dielectric layer 211 on the first region 201 includes forming the first gate dielectric layer 211 by an epitaxial growth process. In one specific embodiment of this disclosure, the material used for the first gate dielectric layer 211 includes a strained material.

[0057] The strain material includes SiGe. The SiGe strain material generates uniaxial compressive stress in the channel manufacturing direction. This compressive stress can cause the valence band to split, with the heavy hole band leaving the top of the valence band and the light hole band occupying the top of the valence band, thereby reducing the effective mass of hole conduction in the channel direction and thus effectively improving the speed of PMOS.

[0058] In other embodiments of this disclosure, the strain material may also be C-doped SiGe. Furthermore, SiGe possesses the characteristics and advantages of a high dielectric constant material, exhibiting good insulation and better field-effect properties, which can reduce leakage current consumption and improve transistor performance.

[0059] In one specific embodiment of this disclosure, the first gate dielectric layer 211 and the second gate dielectric layer 212 are flush in height. While the first gate dielectric layer 211 and the second gate dielectric layer 212 are flush in height, the intermediate isolation structure 203 is not excessively etched, thus preventing standby leakage in the transistor structure.

[0060] In one specific embodiment of this disclosure, a pre-cleaning step is included before forming the first gate dielectric layer 211. The pre-cleaning step includes thermal oxidation annealing, purging, and other steps to remove particles and etchants from the surface of the first gate dielectric layer 211, thereby optimizing the contact between the first gate and the first gate dielectric layer 211. In conventional thermal oxidation annealing steps, over-etching of the isolation structure is prone to occur, even resulting in trenches around the gate. The first protrusion 207 introduced in this disclosure can act as a shield during thermal oxidation annealing and purging steps, effectively improving the over-etching phenomenon of the isolation structure during semiconductor structure fabrication and preventing trenches around the gate.

[0061] Please see the appendix Figure 6E and attached Figure 5 As shown, in step S55, the second mask layer 209 is removed.

[0062] After completing the above steps, you will obtain the attached document. Figure 2C The structure shown includes the first gate dielectric layer 211 and the second gate dielectric layer 212.

[0063] Please continue to refer to the appendix. Figure 2D and attached Figure 1 As shown, in step S13, a first gate 220 is formed on the first gate dielectric layer 211; a second gate 230 is formed on the second gate dielectric layer 212. The first gate 220 includes: a second hard mask layer 221, metal layers 222 and 224, a buffer layer 223, and a high dielectric constant layer 225; the second gate 230 includes: a second hard mask layer 231, metal layers 232 and 234, a buffer layer 233, and a high dielectric constant layer 235.

[0064] In the semiconductor structure provided in this disclosure, either the first gate 220 or the second gate 230 may be used alone, or both may be used simultaneously. If either the first gate 220 or the second gate 230 is used alone, the other gate may employ other common gate structures.

[0065] The second hard mask layers 221 and 231 can be made of SiN; the metal layers 222 and 232 can be made of W; the metal layers 224 and 234 can be made of La or other La-based metals; the buffer layers 223 and 233 can be made of TiN; and the high dielectric constant layers 225 and 235 can be made of HfO. Because the high dielectric constant layers 225 and 235 are made of high dielectric constant materials, which are semiconductor materials with a dielectric constant greater than that of SiO2, they possess good insulation properties and better field-effect characteristics, thus reducing leakage current consumption and improving transistor performance.

[0066] The above-mentioned technical solution relates to a method for fabricating a semiconductor structure. By setting protrusions on the isolation structure, the excessive etching phenomenon of the isolation structure during the semiconductor structure fabrication process is effectively improved, trenches are avoided around the gate, and the technical problem of transistor standby leakage is improved.

[0067] This disclosure also provides a semiconductor structure, such as Figure 2D As shown, the semiconductor structure includes: a substrate 20, the substrate 20 including a first region 201, a second region 202 and an isolation structure 203, the isolation structure 203 being located between the first region 201 and the second region 202; a first gate dielectric layer 211, the first gate dielectric layer 211 being located above the first region 201; a second gate dielectric layer 212, the second gate dielectric layer 212 being located above the second region 202; a first gate 220, the first gate 220 being located on the surface of the first gate dielectric layer 211; and a second gate 230, the second gate 230 being located on the surface of the second gate dielectric layer 212.

[0068] In one specific embodiment of this disclosure, the isolation structure is made of SiO2 and / or SiON. The first gate dielectric layer is made of a strained material; the second gate dielectric layer is made of an oxide material. The strained material includes SiGe, which generates uniaxial compressive stress in the channel fabrication direction. This compressive stress can cause the valence band to split, with the heavy hole band leaving the top of the valence band and the light hole band occupying the top of the valence band, thereby reducing the effective mass of hole conductance in the channel direction and effectively improving the speed of the PMOS. In other specific embodiments of this disclosure, the strained material can also be C-doped SiGe. In addition, SiGe has the characteristics and advantages of a high dielectric constant material, good insulation, and better field-effect characteristics, which can reduce leakage power consumption and improve transistor performance. Furthermore, the first gate dielectric layer and the second gate dielectric layer are flush in height. While the first gate dielectric layer 211 and the second gate dielectric layer 212 are flush in height, the intermediate isolation structure 203 is not over-etched, which can prevent leakage current in the transistor structure.

[0069] In one specific embodiment of this disclosure, the first gate 220 includes: a second hard mask layer 221, metal layers 222 and 224, a buffer layer 223, and a high-dielectric-constant layer 225. The second gate 230 includes: a second hard mask layer 231, metal layers 232 and 234, a buffer layer 233, and a high-dielectric-constant layer 235. In the semiconductor structure provided in this disclosure, the first gate 220 or the second gate 230 can be used alone, or both can be used simultaneously. If the first gate 220 or the second gate 230 is used alone, the other gate can adopt other common gate structures.

[0070] The materials of the second hard mask layers 221 and 231 can be SiN, the materials of the metal layers 222 and 232 can be W, the materials of the metal layers 224 and 234 can be La or other La-based metals, the materials of the buffer layers 223 and 233 can be TiN, and the materials of the high dielectric constant layers 225 and 235 can be HfO.

[0071] Since the high dielectric constant layer 225 is made of a high dielectric constant material, which is a semiconductor material with a dielectric constant greater than that of SiO2, it has good insulation and better field effect characteristics, which can reduce leakage current consumption and improve transistor performance.

[0072] The above-mentioned technical solution involves a semiconductor structure that effectively improves the excessive etching phenomenon of the isolation structure during the semiconductor structure fabrication process, avoids the formation of trenches around the gate, and improves the technical problem of transistor standby leakage.

[0073] It should be noted that, in this document, relational terms such as "second" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "also includes a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0074] The various specific embodiments in this specification are described in a related manner. Similar or identical parts between the different embodiments can be referred to interchangeably. Each specific embodiment focuses on its differences from other embodiments. In particular, the specific embodiments for semiconductor structures are relatively simple in description because they are fundamentally similar to the specific embodiments for the preparation method of semiconductor structures; relevant parts can be found in the descriptions of the specific embodiments for the preparation method of semiconductor structures.

[0075] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region, a second region, and an isolation structure located between the first region and the second region; A first protrusion is formed on a portion of the surface of the isolation structure; A first gate dielectric layer is formed on the first region, the first protrusion is removed, and a second gate dielectric layer is formed on the second region; A first gate is formed in the first gate dielectric layer; a second gate is formed in the second gate dielectric layer; A first hard mask layer is formed on the surfaces of the first and second regions; A first mask layer is formed on the surface of the substrate, the first mask layer covering the first region and part of the isolation structure; The isolation structure and the first hard mask layer are etched using the first mask layer as a mask, and a first protrusion is formed on the surface of the isolation structure. Remove the first mask layer and the first hard mask layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: A third gate dielectric layer is formed on the surface of the first region and the second region, and the third gate dielectric layer is located below the first hard mask layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The isolation structure, the first hard mask layer, and the third gate dielectric layer are etched using the first mask layer as a mask, and a first protrusion is formed on the surface of the isolation structure. Remove the first mask layer, the first hard mask layer, and the third gate dielectric layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: After a first protrusion is formed on a portion of the surface of the isolation structure, a second initial gate dielectric layer is formed on the surfaces of the first region, the first protrusion, and the second region. A second mask layer is formed above the second initial gate dielectric layer, the second mask layer covering the second region and part of the isolation structure, exposing the first protrusion and the first region; The second initial gate dielectric layer is etched with the second mask layer to form a second gate dielectric layer, which covers the surface of the second region.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: Using the second mask layer as a mask, the second initial gate dielectric layer and the first protrusion in the first region are etched to remove the second initial gate dielectric layer and the first protrusion in the first region.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: Forming a first gate dielectric layer on the first region includes forming the first gate dielectric layer by an epitaxial growth process.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The material used in the first gate dielectric layer includes strain material.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first gate and / or the second gate include: a second hard mask layer, a metal layer, a buffer layer, and a high dielectric constant layer.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first mask layer was removed using a dry etching process.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The materials used in the isolation structure include SiO2 and / or SiON.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, The material used for the second gate dielectric layer includes oxide materials.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process includes a pre-cleaning step before forming the first gate dielectric layer.

13. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first gate dielectric layer and the second gate dielectric layer are at the same height.

14. A semiconductor structure, characterized in that, include: A substrate, the substrate including a first region, a second region, and an isolation structure located between the first region and the second region; A first gate dielectric layer is located above the first region; A second gate dielectric layer is located above the second region; A first gate, the first gate being located on the surface of the first gate dielectric layer; The second gate is located on the surface of the second gate dielectric layer.

15. The semiconductor structure according to claim 14, characterized in that, The first gate and / or the second gate include: a second hard mask layer, a metal layer, a buffer layer, and a high dielectric constant layer.

16. The method for preparing a semiconductor structure according to claim 14, characterized in that, The first gate dielectric layer and the second gate dielectric layer are at the same height.

17. The semiconductor structure according to claim 14, characterized in that, The material used in the first gate dielectric layer includes strain material.

18. The semiconductor structure according to claim 14, characterized in that, The materials used in the isolation structure include SiO2 and / or SiON.

19. The semiconductor structure according to claim 14, characterized in that, The material used for the second gate dielectric layer includes oxide materials.

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