Size test structure and method

Abstract

This invention discloses a size testing structure and method. The size testing structure is used to test the size of a first type of shallow trench isolation (STI) structure. The size testing structure includes: a source and a drain of a transistor located in a substrate; a first type of shallow trench isolation (STI) structure located between the source and the drain of the transistor; the first type of shallow trench isolation (STI) structure includes an oxide layer, the top surface of which is higher than the surface of the substrate; a gate structure located on the top surface of the oxide layer; and a channel region located between the source and the drain.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a size testing structure and method. Background Technology

[0002] The dimensions of shallow trench isolation (STI) structures have a significant impact on the electrical properties and yield of semiconductor devices. As the critical dimensions of semiconductor devices shrink, the size of the STI structure becomes increasingly sensitive to the electrical properties of the semiconductor devices, and may even cause out-of-specification abrupt changes.

[0003] Currently, the size of STI structures is mainly detected by scanning electron microscopy (SEM) sections. However, this method requires destroying the semiconductor device structure, has poor timeliness, and has high labor and material costs. Summary of the Invention

[0004] In view of this, embodiments of the present invention aim to provide a size testing structure and method.

[0005] According to one aspect of the present invention, a dimensional testing structure is used to test the dimensions of a first type of STI structure, the dimensional testing structure comprising:

[0006] The source and drain of a transistor located in a substrate;

[0007] The first type of STI structure is located between the source and drain of the transistor; the first type of STI structure includes an oxide layer, the top surface of which is higher than the surface of the substrate;

[0008] The gate structure located on the top surface of the oxide layer; and

[0009] The channel region located between the source and the drain.

[0010] In the above scheme, the gate structure, the first type of STI structure, the source of the transistor, and the drain of the transistor form a field-effect transistor; wherein,

[0011] A first dimension is obtained by measuring the first turn-on voltage of the field-effect transistor; the first dimension is used to characterize the thickness of the first type of STI structure.

[0012] And / or,

[0013] The source, channel region, and drain of the transistor form a parasitic transistor; wherein,

[0014] A second dimension is obtained by measuring the second turn-on voltage of the parasitic transistor; the second dimension is used to characterize the thickness of the oxide layer in the substrate in the first type of STI structure.

[0015] In the above scheme, multiple chip regions and dicing channels located between the multiple chip regions are formed on the substrate;

[0016] The dimensional testing structure is located in the cutting channel.

[0017] In the above scheme, a second type of STI structure is also formed in the substrate; the second type of STI structure is used to isolate adjacent transistors in the substrate; the first type of STI structure and the second type of STI structure are formed using the same manufacturing parameters.

[0018] In the above scheme, the area of ​​the top surface of the oxide layer is smaller than the area of ​​the bottom surface of the gate structure; the size test structure also includes an insulating layer located on the substrate; the gate structure covers the oxide layer and the insulating layer.

[0019] In the above scheme, the transistor includes a high-voltage field-effect transistor, and the maximum gate-source voltage of the high-voltage field-effect transistor is greater than 20 volts.

[0020] According to a second aspect of the present invention, embodiments of the present invention also provide a size testing method, comprising:

[0021] Multiple size testing structures as described in the embodiments of the present invention are formed on the substrate;

[0022] Measure the first turn-on voltage of the field-effect transistor in the size test structure; determine the first dimension based on the measured first turn-on voltage; the first dimension is used to characterize the thickness of the first type of STI structure;

[0023] And / or,

[0024] Measure the second turn-on voltage of the parasitic transistor in the dimensional test structure; determine the second dimension based on the measured second turn-on voltage; the second dimension is used to characterize the thickness of the oxide layer in the substrate in the first type of STI structure.

[0025] In the above scheme, determining the second dimension based on the measured second turn-on voltage includes:

[0026] The base width of the parasitic transistor is obtained based on the measured second turn-on voltage.

[0027] The second dimension is determined based on the base region width of the parasitic transistor.

[0028] In the above scheme, multiple dimensional test structures are formed at different locations on the substrate; each of the multiple dimensional test structures includes a field-effect transistor and a parasitic transistor;

[0029] The method further includes:

[0030] Measure the first turn-on voltage of the field-effect transistor at different locations; compare the first turn-on voltages of the field-effect transistor at different locations to obtain a first comparison result; determine the consistency of the thickness of the first type STI structure at different locations based on the first comparison result.

[0031] And / or,

[0032] Measure the second turn-on voltage of the parasitic transistor at different locations; compare the second turn-on voltages of the parasitic transistor at different locations to obtain the second comparison result;

[0033] Based on the second comparison result, the consistency of the thickness of the first type STI structure oxide layer in the substrate at different locations is determined.

[0034] In the above scheme, the transistor includes a high-voltage field-effect transistor, and the maximum gate-source voltage of the high-voltage field-effect transistor is greater than 20 volts.

[0035] This invention provides a size testing structure and method. The size testing structure is used to test the dimensions of a first type of STI structure. The structure includes: a source and drain of a transistor located in a substrate; the first type of STI structure located between the source and drain of the transistor; the first type of STI structure including an oxide layer, the top surface of which is higher than the surface of the substrate; a gate structure located on the top surface of the oxide layer; and a channel region located between the source and drain. The testing structure provided by this invention uses the first type of STI structure as the gate oxide layer and forms a gate structure on the top surface of the first type of STI structure, thereby forming a field-effect transistor and a parasitic transistor around the first type of STI structure. Then, by measuring the electrical parameters of the field-effect transistor and the parasitic transistor, the dimensions of the STI structure are obtained. This avoids the problems of semiconductor device damage or high testing costs caused by slicing and testing STI structure dimensions in related technologies; it achieves the effects of improving the compatibility of STI structure size measurement with substrate processing technology, realizing online measurement, and enhancing timeliness. Attached Figure Description

[0036] Figure 1 A cross-sectional schematic diagram of a dimensional testing structure for measuring the thickness of a first type of STI structure, provided in an embodiment of the present invention;

[0037] Figure 2A cross-sectional schematic diagram of a size testing structure provided in an embodiment of the present invention for measuring the thickness of the oxide layer in the substrate of a first type STI structure;

[0038] Figure 3 This is a schematic diagram of the layout of a size testing structure provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram illustrating the implementation steps of a size testing method provided in an embodiment of the present invention. Detailed Implementation

[0040] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0041] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0042] It is understood that the meanings of “on”, “above” and “over” in this invention should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0043] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0044] In embodiments of the invention, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire substrate.

[0045] In embodiments of the invention, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0046] In this embodiment of the invention, the terms "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0047] It should be noted that the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.

[0048] In related technologies, the STI structure uses silicon nitride as a protective layer. Trenches are etched into a silicon single-crystal substrate using photolithography and etching, and then filled with high-density silicon oxide (HDP) via plasma-enhanced chemical vapor deposition (PECVD) as the dielectric material to achieve electrical isolation between devices in integrated circuits. The fabrication process of an STI structure generally includes: first, forming an isolation oxide layer, an etch barrier layer, and patterned photoresist sequentially on a semiconductor substrate; then, using the patterned photoresist as a mask, etching the etch barrier layer, isolation oxide layer, and semiconductor substrate to a certain depth to form shallow trenches. Next, a pad oxide layer is formed on the surface of the shallow trenches: insulating material is filled into the shallow trenches and covers the sidewalls of the pad oxide layer and the entire etch barrier layer to form a filling oxide layer. Then, the filling oxide layer is planarized until the etch barrier layer is exposed; finally, acid etching is used to remove the etch barrier layer and the pad oxide layer.

[0049] In the manufacturing process of STI structures, the dimensions of the STI structure, such as its thickness and the thickness of the oxide layer within the substrate, are crucial parameters. These parameters significantly impact the performance of semiconductor devices and even the design and manufacturing of the entire integrated circuit. Therefore, the measurement of STI structure dimensions has always been an important research topic in the field of semiconductor technology. In particular, as semiconductor device dimensions continue to shrink, the accurate measurement of STI structure dimensions has an increasingly significant impact on the performance evaluation of semiconductor devices and circuits, as well as on semiconductor device simulation modeling and design optimization. The importance of STI structure dimension measurement is becoming increasingly prominent.

[0050] This invention provides a dimensional testing structure and method. By using a first-type STI structure as the gate oxide layer and forming a gate structure on the top surface of the first-type STI structure, a field-effect transistor and a parasitic transistor are formed around the first-type STI structure. Then, the dimensions of the STI structure are obtained by measuring the electrical parameters of the field-effect transistor and the parasitic transistor. This avoids the problems of semiconductor device damage or high testing costs caused by slicing and testing STI structure dimensions in related technologies. It achieves the effects of improving the compatibility of STI structure dimension measurement with substrate processing technology, realizing online measurement, and enhancing timeliness.

[0051] This invention provides a dimensional testing structure for testing the dimensions of a first type of shallow trench isolation (STI) structure. Figure 1 This is a schematic diagram of a size testing structure provided in an embodiment of this application. Figure 1 As shown, the size test structure includes:

[0052] The source 1 and drain 2 of the transistor located in the substrate;

[0053] The first type of STI structure 3 is located between the source 1 and the drain 2 of the transistor; the first type of STI structure 3 includes an oxide layer, the top surface of which is higher than the surface of the substrate;

[0054] The gate structure 4 located on the top surface of the oxide layer; and

[0055] The channel region located between the source 1 and the drain 2.

[0056] Here, the substrate may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0057] In one embodiment, the substrate further includes a deep implanted P-well layer (HVPW) and a deep N-well layer (DNW); the HVPW surrounds the source 1, the first type STI structure 3, and the drain 2; the DNW surrounds the HVPW. In practical applications, HVPW and DNW are commonly used in high-voltage devices, primarily for noise isolation. Here, the DNW is used to isolate the P-type substrate, reducing substrate coupling noise.

[0058] In one embodiment, the transistor includes a high-voltage field-effect transistor (FET) with a maximum gate-source voltage greater than 20 volts. Here, the maximum gate-source voltage, also known as the gate-source rated voltage, is the maximum voltage that can be applied between the gate and source terminals, thereby preventing damage to the gate oxide layer due to excessive voltage. In practical applications, the gate oxide layer can withstand voltages much higher than the gate-source rated voltage. In practical applications, the high-voltage field-effect transistor may include a laterally diffused metal-oxide-semiconductor (LDMOS).

[0059] In one embodiment, the transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET, or MOS transistor for short).

[0060] In one embodiment, the gate structure 4 includes a metal gate or a polysilicon gate.

[0061] For example, the source 1 may include a first N-well, the drain 2 may include a second N-well, and the substrate may be P-type doped. Figure 1 An example of this is shown in the figure.

[0062] For example, the source 1 may include a first P-well, the drain 2 may include a second P-well, and the substrate may be N-type doped.

[0063] In practical applications, the gate structure 4 is connected to a test pad 6; the source 1 is connected to a test pad 8; and the drain 2 is connected to a test pad 7. The test pads 6, 7, and 8 are used for subsequent testing. Specifically, the test pads 6, 7, and 8 are connected to testing instruments, thereby enabling the dimensional testing of the STI structure in a semiconductor device using the dimensional testing structure of this invention.

[0064] In one embodiment, when forming the first type of STI structure 3, a trench is first formed on the substrate. The bottom and sides of the trench also include an isolation oxide layer. The isolation oxide layer may include a silicon dioxide monolayer, a silicon dioxide-silicon nitride bilayer, or a silicon dioxide-silicon nitride-silicon dioxide trilayer structure.

[0065] In practical applications, an oxide layer is filled within the trenches where an isolation oxide layer is formed. The material of the oxide layer includes, but is not limited to, silicon oxide. In practical applications, the oxide layer can be formed using a high-density plasma chemical vapor deposition (HDPCVD) process. It should be noted that the top surface of the oxide layer is higher than the surface of the substrate.

[0066] In practical applications, the channel region is located between the source 1 and the drain 2. Specifically, the channel region is located in the substrate surrounding the first type of STI structure 3, and is also located below the gate structure 4 in the substrate, distributed along the side and bottom surfaces of the trench.

[0067] In one embodiment, the gate structure 4, the first type STI structure 3, the source 1 of the transistor, and the drain 2 of the transistor form a field-effect transistor; wherein, a first dimension is obtained by measuring the first turn-on voltage of the field-effect transistor; the first dimension is used to characterize the thickness H1 of the first type STI structure 3.

[0068] Here, the first dimension is used to characterize the thickness H1 of the oxide layer in the first type of STI structure. It should be noted that the first dimension can be either the actual size of the thickness H1 of the first type of STI structure 3, or an equivalent that can characterize the thickness H1 of the first type of STI structure 3. This equivalent has no unit and is only used for horizontal comparison with multiple other equivalents.

[0069] For example, the source 1 includes a first N-well, the drain 2 includes a second N-well, the substrate is P-type doped, the gate structure 4 includes a metal gate, the field-effect transistor is an N-channel enhancement-mode MOS transistor, and the first turn-on voltage is the voltage at which the N-channel enhancement-mode MOS transistor forms its channel.

[0070] In practical applications, the first turn-on voltage of a MOS transistor can be varied due to changes in the manufacturing process. Specifically, the first turn-on voltage of a MOS transistor can be adjusted by variations in the physical parameters of the MOS transistor during manufacturing, such as body thickness, radius, and source / drain implantation / doping.

[0071] In practical applications, factors affecting the first turn-on voltage of a MOS transistor include the gate oxide layer used beneath the gate structure. Typically, a thicker gate oxide layer weakens the electric field by separating the charges over a larger distance; therefore, in a MOS transistor, a thicker gate oxide layer increases the first turn-on voltage, while a thinner gate oxide layer decreases it. Theoretically, the material of the gate oxide layer beneath the gate structure also affects the electric field, thus influencing the first turn-on voltage of the MOS transistor.

[0072] In the above embodiments, the oxide layer filled in the trench of the first type STI structure 3 is used as the gate oxide layer below the gate structure of the MOS transistor. Therefore, the thickness H1 of the first type STI structure 3 will affect the first turn-on voltage of the MOS transistor. Specifically, the greater the thickness H1 of the first type STI structure 3, the greater the first turn-on voltage of the MOS transistor. In practical applications, the change in the thickness H1 of the first type STI structure 3 can be reflected by the change in the first turn-on voltage of the MOS transistor.

[0073] In one embodiment, such as Figure 2 As shown, the source 1, the channel region, and the drain 2 of the transistor form a parasitic transistor, and the base region of the parasitic transistor is represented by the region where the line L is located; wherein, the second dimension is obtained by measuring the second turn-on voltage of the parasitic transistor; the second dimension is used to characterize the thickness H2 of the oxide layer in the substrate in the first type of STI structure 3.

[0074] It should be noted that the second dimension is used to characterize the thickness H2 of the oxide layer in the substrate in the first type of STI structure. It should also be noted that the second dimension can be either the actual thickness H2 of the oxide layer in the substrate in the first type of STI structure 3, or an equivalent that characterizes the thickness H2 of the oxide layer in the substrate in the first type of STI structure 3. This equivalent has no unit and is only used for lateral comparison with several other equivalents.

[0075] For example, the source 1 includes a first N-well, the drain 2 includes a second N-well, the substrate is P-type doped, the parasitic transistor is a parasitic NPN transistor, and the second turn-on voltage is the turn-on voltage of the parasitic NPN transistor.

[0076] In practical applications, since the base region width of the parasitic NPN transistor is a crucial factor affecting its characteristics, and this width can be reflected by its second turn-on voltage, the correspondence between the base region width and the second turn-on voltage can be obtained. Simultaneously, since the base region width of the parasitic NPN transistor corresponds to the thickness H2 of the oxide layer in the substrate of the first type of STI structure 3, the thickness H2 of the oxide layer in the substrate of the first type of STI structure 3 can be obtained from the base region width of the parasitic NPN transistor, thus revealing the correspondence between the thickness H2 of the oxide layer in the substrate of the first type of STI structure 3 and the second turn-on voltage of the NPN transistor. In other words, by monitoring the second turn-on voltage of the parasitic NPN transistor, a second dimension characterizing the thickness H2 of the oxide layer in the substrate of the first type of STI structure 3 can be obtained.

[0077] In one embodiment, a plurality of chip regions and cleavage channels are formed on the substrate; the dimensional testing structure is located in the cleavage channels.

[0078] In practical applications, after completing electrical tests on multiple chip regions on the substrate, multiple chips are obtained by dividing them through the dicing channel.

[0079] It is understandable that placing the size test structure in the cutting channel can improve the integration of the chip area without occupying the chip area, provided that normal testing is completed.

[0080] In one embodiment, a second type of STI structure is also formed in the substrate; the second type of STI structure is used to isolate adjacent transistors in the substrate; the first type of STI structure 3 and the second type of STI structure are formed using the same manufacturing parameters.

[0081] Here, the second type of STI structure is used to isolate the active region in the substrate. In practical applications, the top surface of the second type of STI structure does not have a gate structure 4 formed, but is instead covered with an insulating material.

[0082] In practical applications, the substrate includes multiple STI structures, including a first type STI structure 3 and a second type STI structure. The first type STI structure 3 is used to form the dimensional testing structure; the second type STI structure is used to isolate adjacent transistors in the substrate.

[0083] It should be noted that the first type of STI structure and the second type of STI structure are formed using the same manufacturing process. The design dimensions of the first type of STI structure and the second type of STI structure are completely identical. However, the actual dimensions of the first type of STI structure and the second type of STI structure differ slightly due to local differences in the manufacturing process. The case of the first type of STI structure can be used as a representative to reflect the actual dimensions of the second type of STI structure.

[0084] In practical applications, the substrate can contain STI structures of various sizes, with each size corresponding to multiple STI structures. Each size's multiple STI structures include a small number of the aforementioned first-type STI structures 3 and a large number of the aforementioned second-type STI structures. For each size of STI structure, the size of the corresponding second-type STI structure can be measured using the corresponding first-type STI structure as a test structure, thus obtaining the size of the STI structure of that size.

[0085] In one embodiment, the area of ​​the top surface of the oxide layer is smaller than the area of ​​the bottom surface of the gate structure 4; the dimensional testing structure further includes an insulating layer 5 located on the substrate; the gate structure 4 covers the oxide layer and the insulating layer.

[0086] It is understood that the first type of STI structure 3 and the second type of STI structure are formed using the same manufacturing parameters. Therefore, the area of ​​the top surface of the oxide layer is fixed before the dimensional testing structure is formed. In practical applications, when forming the gate structure 4 on the top surface of the oxide layer, the area of ​​the bottom surface of the gate structure 4 can be set to be larger than the area of ​​the top surface of the oxide layer in order to better perform dimensional testing. In this case, an insulating layer needs to be added around the oxide layer, so that the oxide layer and the insulating layer together serve as the gate oxide layer of the gate structure 4.

[0087] Figure 3 This is a schematic diagram of the layout of a size testing structure provided in an embodiment of the present invention. Figure 3 As shown, the gate structure 4, the source 1, and the drain 2 are respectively connected to multiple test pads 6, 8, and 7, thereby better reflecting the actual test voltages of the gate structure 4, the source 1, and the drain 2. Here, the specific number of test pads 6, 8, and 7 is not limited.

[0088] The present invention also provides a method for size testing. Figure 4 This is a schematic diagram illustrating the implementation process of the dimensional testing method provided in the embodiments of this application, as shown below. Figure 4 As shown, the method includes the following steps:

[0089] Step 401: Form a plurality of the size testing structures provided in the embodiments of the present invention on a substrate;

[0090] Step 402: Measure the first turn-on voltage of the field effect transistor in the size test structure; determine the first dimension based on the measured first turn-on voltage; the first dimension is used to characterize the thickness of the first type of STI structure; and / or, measure the second turn-on voltage of the parasitic transistor in the size test structure; determine the second dimension based on the measured second turn-on voltage; the second dimension is used to characterize the thickness of the oxide layer in the substrate of the first type of STI structure.

[0091] First, step 401 is performed to form the structure to be tested on the substrate.

[0092] In one embodiment, a gate structure 4 is formed on the first type STI structure 3; a test pad 6 is connected to the gate structure 4; a test pad 8 is connected to the source 1; and a test pad 7 is connected to the drain 2.

[0093] Then, in step 402, the first turn-on voltage of the field-effect transistor in the size test structure is measured; based on the measured first turn-on voltage, a first dimension is determined; the first dimension is used to characterize the thickness H1 of the first type of STI structure 3; and / or, the second turn-on voltage of the parasitic transistor in the size test structure is measured; based on the measured second turn-on voltage, a second dimension is determined; the second dimension is used to characterize the thickness H2 of the oxide layer in the first type of STI structure 3 located in the substrate.

[0094] In one embodiment, the base width of the parasitic transistor is obtained based on the measured second turn-on voltage; the second dimension is determined based on the base width of the parasitic transistor.

[0095] In one embodiment, multiple size test structures are formed at different locations on the substrate; each of the multiple size test structures includes a field-effect transistor (FET) and a parasitic transistor; a first turn-on voltage of the FET at different locations is measured; the first turn-on voltages of the FETs at different locations are compared to obtain a first comparison result; based on the first comparison result, the consistency of the thickness H1 of the first type STI structure 3 at different locations is determined; and / or a second turn-on voltage of the parasitic transistor at different locations is measured; the second turn-on voltages of the parasitic transistor at different locations are compared to obtain a second comparison result; based on the second comparison result, the consistency of the thickness of the oxide layer of the first type STI structure 3 in the substrate at different locations is determined.

[0096] Here, consistency refers to the dimensional uniformity of different locations on the same substrate or the dimensional uniformity of different substrates from different batches. It can be understood that the better the consistency of different locations on the same substrate, the more stable the electrical properties of the substrate; the better the consistency fluctuation of different substrates from different batches, the more stable the quality of the substrate.

[0097] It is understood that, based on the consistency of the thickness H1 of the first type of STI structure 3 and / or the consistency of the thickness of the oxide layer of the first type of STI structure 3 in the substrate, the consistency of the STI structure at different locations on the same substrate, or the consistency of different batches and different substrates, can be obtained. This can then be used to monitor the manufacturing process of the STI structure, improve the compatibility of STI structure size measurement with substrate processing technology, achieve online measurement, and enhance timeliness.

[0098] In practical applications, the dimensional information of the first type STI structure 3 can be obtained by detecting the first turn-on voltage of the field-effect transistor and the second turn-on voltage of the parasitic transistor in multiple dimensional test structures. Since the first type STI structure 3 and the second type STI structure are formed using the same manufacturing parameters and have the same design dimensions, the dimensional information of the second type STI structure can be obtained through the multiple dimensional test structures.

[0099] In one embodiment, the transistor is a high-voltage field-effect transistor (FET) with a maximum gate-source voltage greater than 20 volts.

[0100] This invention provides a dimensional testing structure and method. The dimensional testing structure is used to test the thickness of a first-type shallow trench isolation (STI) structure or the thickness of the oxide layer of the first-type STI structure located in the substrate. The dimensional testing structure includes: a source and drain of a transistor located in the substrate; the first-type STI structure located between the source and drain of the transistor; the first-type STI structure including an oxide layer, the top surface of which is higher than the surface of the substrate; a gate structure located on the top surface of the oxide layer; and a channel region located between the source and drain. The testing structure provided by this invention uses the first-type STI structure as the gate oxide layer and forms a gate structure on the top surface of the first-type STI structure, thereby forming a field-effect transistor (FET) and a parasitic transistor around the first-type STI structure. Then, by measuring the electrical parameters of the FET and the parasitic transistor, the dimensions of the STI structure are obtained. This avoids the problems of semiconductor device damage or high testing costs caused by slicing and testing STI structure dimensions in related technologies; it achieves the effects of improving the compatibility of STI structure dimension measurement with substrate processing technology, realizing online measurement, and enhancing timeliness.

[0101] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A size testing structure, characterized in that, A dimensional test structure for testing the dimensions of a first-type shallow trench isolation (STI) structure includes: The source and drain of a transistor located in a substrate; multiple chip regions are formed on the substrate and dicing channels are located between the multiple chip regions, and the dimensional testing structure is located in the dicing channels; The first type of shallow trench isolation (STI) structure is located between the source and drain of the transistor; the first type of shallow trench isolation (STI) structure includes an oxide layer, the top surface of which is higher than the surface of the substrate; The gate structure located on the top surface of the oxide layer; and The channel region located between the source and the drain; A second type of shallow trench isolation (STI) structure is also formed in the substrate; the second type of shallow trench isolation (STI) structure is used to isolate adjacent transistors in the substrate; the first type of shallow trench isolation (STI) structure and the second type of shallow trench isolation (STI) structure are formed using the same manufacturing parameters.

2. The size testing structure according to claim 1, characterized in that, The gate structure, the first type of shallow trench isolation (STI) structure, and the source and drain of the transistor form a field-effect transistor; wherein, a first dimension is obtained by measuring the first turn-on voltage of the field-effect transistor; the first dimension is used to characterize the thickness of the first type of shallow trench isolation (STI) structure. And / or, The source, the channel region, and the drain of the transistor form a parasitic transistor; wherein a second dimension is obtained by measuring the second turn-on voltage of the parasitic transistor; the second dimension is used to characterize the thickness of the oxide layer in the substrate in the first type of shallow trench isolation (STI) structure.

3. The size testing structure according to claim 1, characterized in that, The area of ​​the top surface of the oxide layer is smaller than the area of ​​the bottom surface of the gate structure; the dimensional testing structure also includes an insulating layer located on the substrate; the gate structure covers the oxide layer and the insulating layer.

4. The size testing structure according to claim 1, characterized in that, The transistor includes a high-voltage field-effect transistor, wherein the maximum gate-source voltage of the high-voltage field-effect transistor is greater than 20 volts.

5. A method for testing dimensions, characterized in that, include: A plurality of dimensional test structures as described in any one of claims 1 to 4 are formed on a substrate; Measure the first turn-on voltage of the field-effect transistor in the test structure of the specified dimensions; The first dimension is determined based on the measured first turn-on voltage; The first dimension is used to characterize the thickness of the first type of shallow trench isolation STI structure; And / or, Measure the second turn-on voltage of the parasitic transistor in the dimensional test structure; determine the second dimension based on the measured second turn-on voltage; The second dimension is used to characterize the thickness of the oxide layer in the substrate in the first type of shallow trench isolation STI structure.

6. The size testing method according to claim 5, characterized in that, The step of determining the second dimension based on the measured second turn-on voltage includes: The base width of the parasitic transistor is obtained based on the measured second turn-on voltage. The second dimension is determined based on the base region width of the parasitic transistor.

7. The size testing method according to claim 5, characterized in that, Multiple dimensional test structures are formed at different locations on the substrate; each of the multiple dimensional test structures includes a field-effect transistor and a parasitic transistor; The method further includes: Measure the first turn-on voltage of the field-effect transistor at different locations; compare the first turn-on voltage of the field-effect transistor at different locations to obtain a first comparison result; determine the consistency of the thickness of the first type of shallow trench isolation STI structure at different locations based on the first comparison result. And / or, The second turn-on voltage of the parasitic transistor at different locations is measured; the second turn-on voltage of the parasitic transistor at different locations is compared to obtain a second comparison result; based on the second comparison result, the consistency of the thickness of the oxide layer of the first type shallow trench isolation STI structure in the substrate at different locations is determined.

8. The size testing method according to claim 7, characterized in that, The transistor is a high-voltage field-effect transistor, and the maximum gate-source voltage of the high-voltage field-effect transistor is greater than 20 volts.

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