Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device according to the present embodiment includes a plurality of first semiconductor chips stacked. A first columnar electrode is connected to electrode pads of the plurality of first semiconductor chips and extends in a stacking direction of the plurality of first semiconductor chips. A plurality of second semiconductor chips are stacked above the first semiconductor chips. A second columnar electrode is connected to electrode pads of the plurality of second semiconductor chips and extends in a stacking direction of the plurality of second semiconductor chips. A third columnar electrode is electrically connected to a front end of the first columnar electrode and extends in the stacking direction of the plurality of second semiconductor chips. A resin layer covers the first semiconductor chips, the second semiconductor chips, the second columnar electrode, and the third columnar electrode, and exposes front ends of the second columnar electrode and the third columnar electrode.

Description

[0001] Related applications

[0002] This application claims priority to and benefits from the prior art application No. 2020-211473, filed on December 21, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] In a semiconductor package formed by encapsulating multiple semiconductor chips in resin, it is possible to provide columnar electrodes using metal wires on the electrode pads of each semiconductor chip. The metal wires are connected to the electrode pads of each semiconductor chip by wire bonding and are formed longitudinally by being pulled out longitudinally.

[0005] However, when multiple semiconductor chips are stacked, the metal wires connecting to the bottommost semiconductor chip need to be pulled out quite long longitudinally. If the metal wires are made longer, the leading edge of the wire may shift significantly, causing the wire to fall over during resin encapsulation. In this case, if the spacing between the electrode pads is narrowed, interference may occur between adjacent columnar electrodes. Summary of the Invention

[0006] One embodiment provides a semiconductor device capable of forming long columnar electrodes while suppressing collapse and interference.

[0007] The semiconductor device according to this embodiment has a plurality of first semiconductor chips stacked together. A first columnar electrode is connected to the electrode pads of the plurality of first semiconductor chips and extends along the stacking direction of the plurality of first semiconductor chips. A plurality of second semiconductor chips are stacked on top of the first semiconductor chips. A second columnar electrode is connected to the electrode pads of the plurality of second semiconductor chips and extends along the stacking direction of the plurality of second semiconductor chips. A third columnar electrode is connected to the front end of the first columnar electrode and extends along the stacking direction of the plurality of second semiconductor chips. A resin layer covers the first semiconductor chips, the second semiconductor chips, the second columnar electrode, and the third columnar electrode, exposing the front ends of the second columnar electrode and the third columnar electrode.

[0008] Based on the above configuration, a semiconductor device can be provided that forms a long columnar electrode while suppressing collapse and interference. Attached Figure Description

[0009] Figure 1A This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the first embodiment.

[0010] Figure 1B This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the first embodiment.

[0011] Figure 2A It means relative to Figure 1A The diagram shown is a cross-sectional view of a semiconductor device configuration example that also includes a rewiring layer and metal bumps.

[0012] Figure 2B It means relative to Figure 1B The diagram shown is a cross-sectional view of a semiconductor device configuration example that also includes a rewiring layer and metal bumps.

[0013] Figure 3 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0014] Figure 4 It is a continuation Figure 3 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0015] Figure 5 It is a continuation Figure 4 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0016] Figure 6 It is a continuation Figure 5 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0017] Figure 7 It is a continuation Figure 6 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0018] Figure 8 It is a continuation Figure 7 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0019] Figure 9 It is a continuation Figure 8 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0020] Figure 10 It is a continuation Figure 9 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0021] Figure 11 It is a continuation Figure 10 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0022] Figure 12 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the second embodiment.

[0023] Figure 13 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0024] Figure 14 It is a continuation Figure 13 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0025] Figure 15 It is a continuation Figure 14 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0026] Figure 16 It is a continuation Figure 15 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0027] Figure 17 yes Figure 16 A top view constructed in the middle.

[0028] Figure 18 It is a continuation Figure 17 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0029] Figure 19 It is a continuation Figure 18 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0030] Figure 20 It is a continuation Figure 19 A cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0031] Figure 21 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the third embodiment.

[0032] Figure 22 This is a schematic cross-sectional view showing an example of the configuration of the columnar electrode and the connecting part.

[0033] Figure 23 This is a cross-sectional view showing a configuration example of the semiconductor device according to the fourth embodiment.

[0034] Figure 24 This is a cross-sectional view showing a configuration example of the semiconductor device according to the fifth embodiment.

[0035] Figure 25 This is a cross-sectional view showing a configuration example of the semiconductor device according to the sixth embodiment.

[0036] Figure 26 This is a cross-sectional view showing a configuration example of the semiconductor device according to the seventh embodiment.

[0037] Figure 27 This is a schematic cross-sectional view showing an example of the configuration of the additional disk, the connecting part, and its surroundings.

[0038] Figure 28 This is a cross-sectional view showing a configuration example of the semiconductor device according to the eighth embodiment.

[0039] Figure 29 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 9th embodiment.

[0040] Figure 30 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 9th embodiment.

[0041] Figure 31 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 9th embodiment.

[0042] Figure 32 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 10th embodiment.

[0043] Figure 33 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 10th embodiment.

[0044] Figure 34 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 11th embodiment.

[0045] Figure 35 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 11th embodiment.

[0046] Figure 36 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 11th embodiment.

[0047] Figure 37 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 11th embodiment.

[0048] Figure 38 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 11th embodiment.

[0049] Figure 39 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 11th embodiment.

[0050] Figure 40A This is a cross-sectional view showing a configuration example of the semiconductor device according to the 12th embodiment.

[0051] Figure 40B This is a cross-sectional view showing a configuration example of the semiconductor device according to the 12th embodiment.

[0052] Figure 41 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 13th embodiment.

[0053] Figure 42 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 14th embodiment.

[0054] Figure 43 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 14th embodiment.

[0055] Figure 44 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 15th embodiment.

[0056] Figure 45 This is a cross-sectional view showing a configuration example of the semiconductor device according to the 16th embodiment. Detailed Implementation

[0057] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. In the following embodiments, the up-down direction refers to the relative direction when the stacking direction of the semiconductor chip is set to up or down, and may differ from the up-down direction along the acceleration due to gravity. The drawings are schematic or schematic, and the proportions of the parts are not necessarily the same as in reality. In the specification and drawings, elements that are the same as those described above in the drawings are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0058] (First Embodiment) Figure 1A and Figure 1B This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a semiconductor chip 10, an adhesive layer (DAF (Die Attachment Film)) 20, columnar electrodes 30, a resin layer 40, a semiconductor chip 50, an adhesive layer (DAF) 60, columnar electrodes 70, columnar electrodes 80, and a resin layer 90. The semiconductor device 1 may also be a semiconductor package such as a NAND flash memory or an LSI (Large Scale Integration).

[0059] Each of the multiple semiconductor chips 10 has a first surface F10a and a second surface F10b located on opposite sides of the first surface. Semiconductor elements (not shown), such as transistors and capacitors, are formed on the first surface F10a of each semiconductor chip 10. The semiconductor elements on the first surface F10a of the semiconductor chip 10 are covered and protected by an insulating film (not shown). This insulating film may be an inorganic insulating material, such as a silicon oxide film or a silicon nitride film. Alternatively, the insulating film may be made of a material on which an organic insulating material is formed on an inorganic insulating material. Examples of organic insulating materials include phenolic resins, polyimide resins, polyamide resins, acrylic resins, epoxy resins, PBO (p-phenylene benzobisoxazole) resins, silicon resins, benzocyclobutene resins, or mixtures or composites thereof. The semiconductor chip 10 may also be a NAND flash memory chip or a semiconductor chip equipped with any LSI. Semiconductor chips 10 can be semiconductor chips with the same structure as each other, or they can be semiconductor chips with different structures as each other.

[0060] Multiple semiconductor chips 10 are stacked and bonded together by an adhesive layer 20. The adhesive layer 20 may be an organic insulating material, such as a phenolic resin, polyimide resin, polyamide resin, acrylic resin, epoxy resin, PBO (p-phenylenebenzobisoxazole) resin, silicone resin, benzocyclobutene resin, or a mixture or composite thereof. Each of the multiple semiconductor chips 10 has an electrode pad 15 exposed on a first surface F10a. Other semiconductor chips 10 (upper semiconductor chips 10) stacked on top of the lower semiconductor chip 10 are offset in a substantially vertical direction (X direction) from the edge of the lower semiconductor chip 10 where the electrode pad 15 is located, so as not to overlap with the electrode pad 15 of the lower semiconductor chip 10.

[0061] The electrode disk 15 is electrically connected to one of the semiconductor elements disposed on the semiconductor chip 10. The electrode disk 15 is, for example, a low-resistivity metal such as a monomer of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, Ti, Ta, TiN, TaN, CrN, etc., a composite film of two or more of them, or an alloy of two or more of them.

[0062] The columnar electrode 30 is connected to the electrode pad 15 of the semiconductor chip 10 and extends along the stacking direction (Z direction) of the plurality of semiconductor chips 10. The adhesive layer 20 is partially removed to expose a portion of the electrode pad 15, so that the columnar electrode 30 can be connected to the electrode pad 15. Alternatively, the adhesive layer 20 is configured to be adhered to the second surface F10b of the upper semiconductor chip 10 and not overlap with the electrode pad 15 of the lower semiconductor chip 10. The lower end of the columnar electrode 30 is connected to the electrode pad 15 by wire bonding, and its connection portion 35 is formed into a spherical shape that is thicker than the diameter (thickness) of the columnar electrode 30 in the X or Y direction. The upper end of the columnar electrode 30 reaches the upper surface of the resin layer 40 and is exposed on the upper surface.

[0063] A resin layer 40 encapsulates (packages) multiple semiconductor chips 10 and columnar electrodes 30, with the front end of the columnar electrodes 30 exposed on the upper surface.

[0064] Each of the multiple semiconductor chips 50 has a first surface F50a and a second surface F50b located opposite the first surface F50a. Semiconductor elements (not shown), such as memory cell arrays, transistors, or capacitors, are formed on the first surface F50a of each semiconductor chip 50. The semiconductor elements on the first surface F50a of the semiconductor chip 50 are protected by an insulating film (not shown). This insulating film may be an inorganic insulating material, such as a silicon oxide film or a silicon nitride film. Alternatively, the insulating film may be a material on which an organic insulating material is formed on an inorganic insulating material. Examples of organic insulating materials include phenolic resins, polyimide resins, polyamide resins, acrylic resins, epoxy resins, PBO (p-phenylenebenzobisoxazole) resins, silicon resins, benzocyclobutene resins, or mixtures or composites thereof. The semiconductor chip 50 may be, for example, a NAND flash memory chip or a semiconductor chip equipped with any LSI. Semiconductor chips 50 can be semiconductor chips with the same structure as each other, or they can be semiconductor chips with different structures. Furthermore, semiconductor chip 50 can be a semiconductor chip with the same structure as semiconductor chip 10, or it can be a semiconductor chip with a different structure than semiconductor chip 10.

[0065] Multiple semiconductor chips 50 are stacked and bonded together by an adhesive layer 60. Each semiconductor chip 50 has an electrode pad 55 exposed on a first surface F50a. Semiconductor chips 50 stacked on top of other semiconductor chips 50 are offset in a substantially perpendicular direction (X direction) relative to the edge where the electrode pad 55 is located, so as not to overlap with the electrode pads 55 of other semiconductor chips 50. The bottom semiconductor chip 50 is disposed on a resin layer 40, and a resin layer 40 is located between the top semiconductor chip 10 and the bottom semiconductor chip 50.

[0066] The electrode disk 55 is electrically connected to one of the semiconductor elements disposed on the semiconductor chip 50. The electrode disk 55 is made of a low-resistivity metal, such as a monomer of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, Ti, Ta, TiN, TaN, CrN, etc., a composite film of two or more of them, or an alloy of two or more of them.

[0067] The columnar electrode 70 is connected to the electrode pad 55 of the semiconductor chip 50 and extends along the stacking direction (Z direction) of the plurality of semiconductor chips 50. The adhesive layer 60 is partially removed to expose a portion of the electrode pad 55, so that the columnar electrode 70 can be connected to the electrode pad 55. Alternatively, the adhesive layer 60 is configured to be adhered to the second surface F50b of the upper semiconductor chip 50 and not overlap with the electrode pad 55 of the lower semiconductor chip 50. The lower end of the columnar electrode 70 is connected to the electrode pad 55 by wire bonding, and its connection portion 75 is formed into a spherical shape that is thicker than the diameter (thickness) of the columnar electrode 70 in the X or Y direction. The upper end of the columnar electrode 70 reaches the upper surface of the resin layer 90 and is exposed on the upper surface.

[0068] Furthermore, the columnar electrode 80 is connected to the front end of the columnar electrode 30 exposed on the upper surface of the resin layer 40, extending along the stacking direction (Z direction) of the plurality of semiconductor chips 50. The lower end of the columnar electrode 80 is connected to the upper end of the columnar electrode 30 by a wire bonding method, and its connection portion 85 is formed into a spherical state that is thicker than the diameter (thickness) of the columnar electrodes 30 and 80 in the X or Y direction. That is, the connection portion 85 between the columnar electrodes 30 and 80 is larger than the cross-section of the columnar electrodes 30 and 80 in the direction perpendicular to the extending direction of the columnar electrodes 30 and 80 (X or Y direction).

[0069] The resin layer 90 encapsulates (packages) multiple semiconductor chips 50, columnar electrodes 30 and 80, with the front ends of the columnar electrodes 30 and 80 exposed on the upper surface.

[0070] Resin layers 40 and 90 may be made of organic insulating materials such as phenolic resins, polyimide resins, polyamide resins, acrylic resins, epoxy resins, PBO (p-phenylene benzobisoxazole) resins, silicone resins, benzocyclobutene resins, or mixtures or composites thereof.

[0071] Figure 2A and Figure 2B They respectively represent targeting Figure 1A and Figure 1B The diagram shown is a cross-sectional view of a semiconductor device 1 configuration example, which includes a semiconductor chip 200, a columnar electrode 210, a redistribution layer 100, and metal bumps 150.

[0072] Semiconductor chip 200 has a first surface F200a and a second surface F200b located on opposite sides of the first surface. Semiconductor elements (not shown), such as transistors and capacitors, are formed on the first surface F200a of each semiconductor chip 200. The semiconductor elements on the first surface F200a of the semiconductor chip 200 are protected by an insulating film (not shown). This insulating film uses an inorganic insulating material, such as a silicon oxide film or a silicon nitride film. Alternatively, the insulating film can also be made of a material on which an organic insulating material is formed on an inorganic insulating material. Examples of organic insulating materials include phenolic resins, polyimide resins, polyamide resins, acrylic resins, epoxy resins, PBO (p-phenylene benzobisoxazole) resins, silicon resins, benzocyclobutene resins, or mixtures or composites thereof. Semiconductor chip 200 can also be, for example, a controller chip controlling a memory chip (semiconductor chip 10, 50) or a semiconductor chip equipped with any LSI.

[0073] Semiconductor chip 200 is stacked on semiconductor chip 50 and bonded to semiconductor chip 50 by adhesive layer 60. Each semiconductor chip 200 has an electrode pad (not shown) exposed on the first surface F200a.

[0074] The columnar electrode 210 is connected to the electrode pad of the semiconductor chip 200 and extends along the Z direction. The adhesive layer 60 is partially removed to expose a portion of the electrode pad, allowing the columnar electrode 210 to connect to the electrode pad. Alternatively, the adhesive layer 20 is configured to adhere to the second surface F10b of the upper semiconductor chip 10, without overlapping with the electrode pad 15 of the lower semiconductor chip 10. The lower end of the columnar electrode 210 is connected to the electrode pad of the semiconductor chip 200 via a wire bonding method, and its connection portion forms a spherical shape that is thicker than the diameter (thickness) of the columnar electrode 210 in the X direction. The upper end of the columnar electrode 210 reaches the upper surface of the resin layer 90 and is exposed on this surface. The columnar electrode 210 can use the same material as the columnar electrodes 30, 70, and 80 described above.

[0075] Re-wiring layer (RDL)<Re Distribution Layer> The rewiring layer 100 is disposed on the resin layer 90 and electrically connected to the columnar electrodes 70, 80 and 210. The rewiring layer 100 is a multilayer wiring layer composed of multiple wiring layers and multiple insulating layers, and electrically connects the columnar electrodes 70, 80 and 210 to the metal bumps 150 respectively.

[0076] Metal bumps 150 are disposed on the redistribution layer 100 and electrically connected to the wiring layer of the redistribution layer 100. Metal bumps 150 are used for connection to external devices (not shown). Metal bumps 150 may be made of, for example, monomers of Sn, Ag, Cu, Au, Pd, Bi, Zn, Ni, Sb, In, or Ge, composite films of two or more of these materials, or alloys.

[0077] The manufacturing method of the semiconductor device 1 according to the first embodiment will now be described.

[0078] Figures 3 to 11 This is a cross-sectional view showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment.

[0079] First, such as Figure 3 As shown, multiple semiconductor chips 10 are stacked on the support substrate 2. At this time, the semiconductor chips 10 are bonded to other semiconductor chips 10 via an adhesive layer 20. The support substrate 2 can be a metal plate made of silicon, glass, ceramic, resin, lead frames, etc.

[0080] Then, as Figure 4As shown, a metal wire (conductive wire) is bonded to the electrode pad 15 of the semiconductor chip 10 using a wire bonding method. This metal wire is pulled out in a direction approximately perpendicular to the first surface F10a to form a columnar electrode 30. Since the columnar electrode 30 is formed using a wire bonding method, its lower end is soldered onto the electrode pad 15 in a spherical state that is thicker than its diameter (thickness) in the X or Y direction. Consequently, a connection portion 35, thicker than the diameter (thickness) of the columnar electrode 30 in the X or Y direction, is formed between the electrode pad 15 and the columnar electrode 30. This improves the connection strength between the electrode pad 15 and the columnar electrode 30. Furthermore, the columnar electrode 30 is cut off at its upper end, maintaining an upright state due to the rigidity of the columnar electrode 30 itself.

[0081] The columnar electrode 30 may be made of, for example, monomers of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, Ti, or Ta, composite materials of two or more of these materials, or alloys of two or more of these materials. Preferably, the columnar electrode 30 is made of monomers of Au, Ag, Cu, or Pd, composite materials of two or more of these materials, or alloys of two or more of these materials. More preferably, the columnar electrode 30 is made of a material with high hardness among the aforementioned materials, such as Cu, CuPd alloys, or materials in which Pd is coated on Cu. Therefore, the columnar electrode 30 is less prone to bending and tipping over when covered by the resin layer 40.

[0082] Then, as Figure 5 As shown, a resin layer 40 is used to coat the laminate of the semiconductor chip 10 and the columnar electrode 30. The resin layer 40 may be made of epoxy, phenolic, polyimide, polyamide, acrylic, PBO, silicone, benzocyclobutene, or other resins, as well as mixtures and composites thereof. Examples of epoxy resins are not particularly limited, but examples include bisphenol-type epoxy resins such as bisphenol A, bisphenol F, bisphenol AD, and bisphenol S; phenolic varnish-type epoxy resins such as phenolic resins and cresol-phenolic resins; resorcinol-type epoxy resins; aromatic epoxy resins such as triphenol methane triglycidyl ether; naphthalene-type epoxy resins; fluorene-type epoxy resins; dicyclopentadiene-type epoxy resins; polyether-modified epoxy resins; benzophenone-type epoxy resins; aniline-type epoxy resins; NBR-modified epoxy resins; CTBN-modified epoxy resins; and their hydrides. From the perspective of good adhesion to silicon, naphthalene-type epoxy resin and dicyclopentadiene-type epoxy resin are preferred. Furthermore, from the perspective of easy and rapid curing, benzophenone-type epoxy resin is preferred. The above-mentioned epoxy resins can be used alone or in combination of two or more. Additionally, the resin layer 40 may contain fillers such as silica.

[0083] After the resin layer 40 is formed, the resin layer 40 is heated by an oven or the like, or the resin layer 40 is hardened by irradiating the resin layer 40 with UV light.

[0084] Then, using chemical mechanical polishing (CMP) and mechanical polishing methods, the resin layer 40 is polished until the columnar electrode 30 is exposed. This yields... Figure 5 The structure shown.

[0085] Then, as Figure 6 As shown, multiple semiconductor chips 50 are stacked on the resin layer 40. At this time, the semiconductor chips 50 are bonded to the other semiconductor chips 50 by the adhesive layer 60.

[0086] Then, as Figure 7 As shown, a metal wire is bonded to the electrode pad 55 of the semiconductor chip 50 using a wire bonding method. This metal wire is pulled out in a direction approximately perpendicular to the first surface F50a (Z direction) to form a columnar electrode 70. Additionally, a metal wire is bonded to the upper end of the columnar electrode 30 exposed from the resin layer 40 using a wire bonding method. This metal wire is pulled out in the Z direction to form a columnar electrode 80. Since the columnar electrodes 70 and 80 are formed using a wire bonding method, the lower ends of the columnar electrodes 70 and 80 are soldered to the upper end of the electrode pad 55 or the columnar electrode 30 in a spherical state that is thicker than the diameter (thickness) of the columnar electrodes 70 and 80 in the X or Y direction. Consequently, a connecting portion 75, thicker than the diameter (thickness) of the columnar electrode 70 in the X or Y direction, is formed between the electrode pad 55 and the columnar electrode 70. A connecting portion 85, which is thicker than the diameter (thickness) of the columnar electrode 80 in the X or Y direction, is formed between the columnar electrode 30 and the columnar electrode 80. As a result, the connection strength between the electrode disk 55 and the columnar electrode 70, as well as the connection strength between the columnar electrode 30 and the columnar electrode 80, can be improved. In addition, the columnar electrodes 70 and 80 are cut off at their upper ends, and their upright state is maintained by the rigidity of the columnar electrodes 70 and 80 themselves.

[0087] The columnar electrodes 70 and 80 can be made of materials selected from the same range as those used for the columnar electrode 30. The materials of the columnar electrodes 70 and 80 can be the same as those of the columnar electrode 30, or they can be different materials. By using high-hardness materials, such as Cu, CuPd alloys, or materials that coat Pd onto Cu, the columnar electrodes 70 and 80 are less prone to bending and falling over when covered by the resin layer 90.

[0088] Then, as Figure 8As shown, a resin layer 90 is used to coat the laminate of the semiconductor chip 50 and the columnar electrodes 70 and 80. The resin layer 90 can be selected from the same material as the resin layer 40 described above. The material of the resin layer 90 can be the same as that of the resin layer 40, or it can be a different material. After the resin layer 90 is formed, it is hardened by heating the resin layer 90 in an oven or by irradiating the resin layer 90 with UV light.

[0089] Then, using CMP and mechanical polishing methods, the resin layer is polished to expose the columnar electrodes at 70-80°. This yields... Figure 8 The structure is shown. Then, the support substrate 2 is removed using heat, laser, or other optical methods. Alternatively, the support substrate 2 can be removed by grinding. Furthermore, it can be removed by cutting... Figure 8 The shown structure is monolithized. Therefore, we obtain... Figure 1A The semiconductor device 1 shown. On the other hand, cutting is performed while the support substrate 2 remains, thereby obtaining... Figure 1B Semiconductor device 1 is shown.

[0090] exist Figure 2A and Figure 2B In the control method of the semiconductor device 1 shown, in such a way... Figure 6 After the semiconductor chip 50 is stacked as shown, as Figure 9 As shown, a semiconductor chip 200 is then stacked on top of the uppermost semiconductor chip 50.

[0091] Then, as Figure 10 As shown, a metal wire is bonded to the electrode pad 55 of the semiconductor chip 50 using a wire bonding method. The metal wire is pulled out in a direction approximately perpendicular to the first surface F50a (Z direction) to form a columnar electrode 70. Additionally, a metal wire is bonded to the upper end of the columnar electrode 30 exposed from the resin layer 40 using a wire bonding method. The metal wire is pulled out in the Z direction to form a columnar electrode 80. Then, a columnar electrode 210 is formed on the semiconductor chip 200 using a plating method. Alternatively, a metal wire can be bonded to the electrode pad on the semiconductor chip 200 using a wire bonding method, and pulled out in a direction approximately perpendicular to the first surface F200a to form a columnar electrode 210. In this case, the columnar electrode 210 is also formed using a wire bonding method. Therefore, the lower end of the columnar electrode 210 is soldered to the electrode pad of the semiconductor chip 200 as a ball with a diameter (thickness) compared to the X or Y direction of the columnar electrode 210. This improves the connection strength. In addition, the columnar electrode 210 is cut off at the upper end, and the columnar electrode 210 itself is rigid enough to maintain an upright state.

[0092] The columnar electrode 210 can be made of a material selected from the same range as that of the columnar electrode 30 described above. The material of the columnar electrode 210 can be the same as that of the columnar electrodes 30, 70, and 80, or it can be a different material. By using a high-hardness material, such as Cu, CuPd alloy, or a material with Pd coated on Cu, the columnar electrode 210 is less prone to bending and falling over when covered by the resin layer 90.

[0093] Then, as Figure 11 As shown, the semiconductor chip 50 and the columnar electrodes 70, 80, and 210 are encapsulated by a resin layer 90. After the resin layer 90 is formed, it is hardened by heating it in an oven or by irradiating it with UV light.

[0094] Then, using CMP and mechanical polishing methods, the resin layer 90 is polished until the columnar electrodes 70, 80, and 210 are exposed. Thus, [the desired result is...] Figure 11 The structure shown.

[0095] Then, a rewiring layer 100 is formed on the resin layer 90. The insulating layer of the rewiring layer 100 may use, for example, epoxy, phenolic, polyimide, polyamide, acrylic, PBO, silicone, benzocyclobutene, or other resins, mixtures thereof, or composite materials. The wiring layer of the rewiring layer 100 may use, for example, monomers of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, Ti, Ta, TiN, TaN, CrN, or other monomers, composite materials of two or more of these, or alloys of two or more of these.

[0096] Then, the support substrate 2 is removed using light methods such as heat or laser. Alternatively, the support substrate 2 can be removed by grinding.

[0097] Then, metal bumps 150 are formed on the rewiring layer 100. The metal bumps 150 can be formed, for example, using ball-mount, plating, or printing methods. The metal bumps 150 can be made, for example, using monomers of Sn, Ag, Cu, Au, Pd, Bi, Zn, Ni, Sb, In, and Ge, composite films of two or more of them, or alloys.

[0098] Then, by cutting Figure 11 The structure shown is monolithized. Therefore, Figure 2A The semiconductor device 1 shown is now complete. Alternatively, it can be cut while the supporting substrate 2 remains, thereby obtaining... Figure 2B Semiconductor device 1 is shown.

[0099] The semiconductor device 1 having the above configuration was mounted on a wiring board and subjected to a temperature cycling test. The temperature cycling test was performed for 3000 cycles, with each cycle consisting of 30 minutes at -55°C, 5 minutes at 25°C, and 30 minutes at 125°C. However, no abnormalities were found in the connection points of the semiconductor device 1 according to this embodiment after 3000 cycles.

[0100] In the above embodiments, the columnar electrodes 30, 70, 80, and 210 are formed using a wire bonding method as an example, but they can also be formed using a plating method. For example, after the resin layers 40 and 90 form spheres reaching the electrode disks 15 and 55, metal material is embedded in the holes using a plating method. Thus, the columnar electrodes 30, 70, 80, and 210 can be formed using a plating method. The columnar electrodes 30, 70, 80, and 210 can also be formed using both the plating method and the wire bonding method described above.

[0101] The columnar electrodes 30, 70, 80, and 210 involved in this embodiment may also coexist with lines that directly connect the electrode pads of a semiconductor chip formed using a conventional wire bonding method. Alternatively, lines that directly connect semiconductor chips, columnar electrodes formed using a wire bonding method, and columnar electrodes formed using a plating method may coexist.

[0102] According to the first embodiment described above, the columnar electrodes 30 and 80, which are electrically connected to the electrode pads 15 of the plurality of semiconductor chips 10 stacked on the lower layer, are formed as lower columnar electrodes 30 and upper columnar electrodes 80 together with the stacking process of the semiconductor chips 10 and 50. Therefore, this embodiment can form substantially long columnar electrodes 30 and 80 while suppressing tilting and interference during the formation of resin layers 40 and 90.

[0103] The columnar electrode 30 is connected to the semiconductor chip 10 and is covered by a resin layer 40. Then, the semiconductor chip 50 is stacked on the planarized resin layer 40, and the columnar electrodes 80 are formed in a manner that connects to each columnar electrode 30. Thus, after the lower columnar electrode 30 is encapsulated by the resin layer 40, the upper columnar electrode 80 is formed. Therefore, the columnar electrode 30 will not fall over or tilt due to the formation of the columnar electrode 80. Furthermore, since the columnar electrode 80 stands upright from the planarized and hardened resin layer 40, it is also less prone to falling over or tilting. The upper end of the columnar electrode 80 is stable, and its positional displacement is less likely to occur. Furthermore, a thicker connection portion 85 than the columnar electrodes 30 and 80 is formed at the lower end of the columnar electrode 80. This reduces the connection impedance between the columnar electrodes 30 and 80. Therefore, the columnar electrodes 30 and 80 can be electrically connected with low impedance from the upper end of the columnar electrode 80 to the electrode pad 15 of the semiconductor chip 10. In addition, the connecting part 85 can also improve the mechanical connection strength between the columnar electrode 30 and the columnar electrode 80.

[0104] As a result, the columnar electrodes 30 and 80 can suppress the falling and interference of these columnar electrodes, and can be formed using substantially long wires.

[0105] Furthermore, in the case where the materials of resin layer 40 and resin layer 90 are different, and resin layer 40 and resin layer 90 have opposite stresses, it is related to the suppression of warpage in the semiconductor device 1. Regarding the difference in stress between resin layer 40 and resin layer 90, it can be adjusted according to their thicknesses. For example, if resin layer 40 and resin layer 90 have opposite stresses, and the stress of resin layer 40 is less than that of resin layer 90, then the thickness of resin layer 40 can be made thicker than that of resin layer 90 accordingly. Alternatively, for example, by reducing the value of the "elastic modulus × coefficient of thermal expansion" of the upper resin layer 90 relative to the value of the "elastic modulus × coefficient of thermal expansion" of resin layer 40, warpage can also be suppressed.

[0106] Alternatively, the support substrate 2 can be left unremoved, and instead... Figure 11 The remaining support substrate 2 is shown. In this case, the package of the semiconductor device 1 is cut together with the support substrate 2. The second surface F10b of the bottommost semiconductor chip 10 can be protected by the support substrate 2.

[0107] (Second Implementation) Figure 12This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the second embodiment. In the second embodiment, a plurality of semiconductor chips 10 and a plurality of semiconductor chips 50 are continuously stacked. The lowest semiconductor chip 50 is stacked on the uppermost semiconductor chip 10. An adhesive layer 60 is provided between the uppermost semiconductor chip 10 and the lowest semiconductor chip 50, but resin layers 40 and 90 are not present.

[0108] Semiconductor chips 10 and 50 are entirely covered by resin layer 40. However, a groove TR is provided in the resin layer 40 above the electrode disk 15 of semiconductor chip 10, and a resin layer 90 is disposed in the groove TR.

[0109] The resin layer 90 is the same as in the first embodiment in that it covers the columnar electrode 80 and exposes the front end of the columnar electrode 80. However, the resin layer 90 only fills the trench TR and does not cover the semiconductor chip 50 and the columnar electrode 70.

[0110] On the other hand, resin layer 40 covers semiconductor chips 10 and 50 and columnar electrodes 30 and 70. The upper surface of resin layer 40 exposes the tip of columnar electrode 70. Additionally, resin layer 40 exposes the tip of columnar electrode 30 at the bottom of the trench TR. Thus, at the bottom of the trench TR, columnar electrode 80 is electrically connected to the tip of columnar electrode 30 via connecting portion 85.

[0111] The configuration of columnar electrodes 30, 70, and 80 can also be the same as that of the corresponding columnar electrodes in the first embodiment. Thus, columnar electrode 30 is connected to the electrode disk 15 of the semiconductor chip 10 and extends along the stacking direction (Z direction) of the semiconductor chip 10. Columnar electrode 70 is connected to the electrode disk 55 of the semiconductor chip 50 and extends along the stacking direction (Z direction) of the semiconductor chip 50. Columnar electrode 80 is connected to the front end of columnar electrode 30 exposed in the groove TR of the resin layer 40 and extends along the Z direction.

[0112] Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment. Figure 12 The semiconductor device 1 shown has a similar Figure 2A The corresponding configuration also includes a semiconductor chip 200, a rewiring layer 100, and metal bumps 150. The configuration of the semiconductor chip 200, the rewiring layer 100, and the metal bumps 150 can be compared with... Figure 2A The corresponding components shown have the same structure. If from... Figure 12 In the configuration shown, the semiconductor chip 200, the rewiring layer 100, and the metal bump 150 are omitted, so the semiconductor device 1 becomes... Figure 1A The corresponding configuration. Furthermore, the semiconductor device 1 according to the second embodiment may also have, as... Figure 1B or Figure 2BThe supporting substrate 2 shown.

[0113] The manufacturing method of the semiconductor device 1 according to the second embodiment will now be described.

[0114] Figures 13-20 This is a cross-sectional view showing an example of a method for manufacturing the semiconductor device 1 according to the second embodiment.

[0115] First, such as Figure 13 As shown, multiple semiconductor chips 10 are stacked on a support substrate 2. At this time, semiconductor chips 10 are bonded to other semiconductor chips 10 via an adhesive layer 20. Then, multiple semiconductor chips 50 are stacked on the semiconductor chips 10. At this time, semiconductor chips 50 are bonded to other semiconductor chips 10 or 50 via an adhesive layer 60. Furthermore, the bottommost semiconductor chip 50 is bonded to the topmost semiconductor chip 10 via the adhesive layer 60. Then, semiconductor chip 200 is bonded to the topmost semiconductor chip 50 via the adhesive layer 60. The semiconductor chips 10, 50, and 200 are stacked offset along the X direction in a manner that does not coincide with the respective electrode disks 15 and 55 of the semiconductor chips located below them. Thus, a... Figure 13 The structure shown.

[0116] Then, as Figure 14 As shown, metal wires are bonded to the electrode pads 15 and 55 of semiconductor chips 10 and 50 using a wire bonding method. The metal wires are drawn out in a direction approximately perpendicular to the first surfaces F10a and F50a to form columnar electrodes 30 and 70. Since the columnar electrodes 30 and 70 are formed using a wire bonding method, their lower ends are soldered onto the electrode pads 15 and 55 in a spherical state that is thicker than the diameter (thickness) of the columnar electrodes 30 and 70 in the X or Y direction. Consequently, a connecting portion 35, thicker than the diameter (thickness) of the columnar electrode 30 in the X or Y direction, is formed between the electrode pad 15 and the columnar electrode 30. Similarly, a connecting portion 75, thicker than the diameter (thickness) of the columnar electrode 70 in the X or Y direction, is formed between the electrode pad 75 and the columnar electrode 70. As a result, the connection strength between the electrode pad 15 and the columnar electrode 30, and between the electrode pad 55 and the columnar electrode 70, can be improved. In addition, the columnar electrodes 30 and 70 are cut off at the upper end, and the columnar electrodes 30 and 70 maintain an upright state by utilizing their own rigidity.

[0117] Then, metal wires are bonded to the electrode pads of the semiconductor chip 200 using a wire bonding method, and the metal wires are pulled out in a direction approximately perpendicular to the first surface F200a (Z direction) to form a columnar electrode 210. Alternatively, the columnar electrode 210 can be pre-formed as a metal pillar on the semiconductor chip 200, and the semiconductor chip 200 with the columnar electrode 210 is bonded to the uppermost semiconductor chip 50.

[0118] Then, as Figure 15 As shown, semiconductor chips 10, 50, 200 and columnar electrodes 30, 70, 210 are coated with resin layer 40. Then, the resin layer 40 is hardened by heating it in an oven or by irradiating it with UV light.

[0119] Then, using CMP and mechanical polishing methods, the resin layer 40 is polished until the columnar electrodes 70 and 210 are exposed. Thus, the desired result is obtained. Figure 15 The structure shown.

[0120] Then, as Figure 16 As shown, a groove TR is formed in the resin layer 40 by grinding the portion above the electrode disk 15 and the columnar electrode 30 using a cutting tool or laser. The groove TR extends in a direction (Y direction) that is substantially parallel to the edge of the semiconductor chip 10, 50 on which the electrode disks 15, 55 are disposed, and is continuously formed with other semiconductor packages (not shown) adjacent in the Y direction.

[0121] Figure 17 yes Figure 16 A schematic top view of the structure formed during the process. For example... Figure 17 As shown, the groove TR is formed in a direction that is substantially parallel to the extension direction (Y direction) of the edge of the semiconductor chips 10 and 50 on which the electrode disks 15 and 55 are disposed. That is, the groove TR is formed to extend in a direction (Y direction) orthogonal to the offset direction of the semiconductor chips 10 and 50.

[0122] like Figure 16 As shown, the upper end of the cylindrical electrode 30 is exposed at the bottom of the groove TR. When using a cutting tool, the groove TR is as follows... Figure 17 The groove TR is formed as shown. When using a laser, the groove TR can be formed only in the area where the semiconductor chips 10 and 50 are present.

[0123] In this embodiment, the resin layer 40 is ground as a whole using CMP or mechanical polishing to form the groove TR. However, the resin layer 40 can also be ground as a whole using CMP or mechanical polishing after the groove TR is formed.

[0124] Then, as Figure 18As shown, a metal wire is bonded to the upper end of the columnar electrode 30 exposed at the bottom of the groove TR using a wire bonding method. This metal wire is pulled out along the Z direction to form a columnar electrode 80. Since the columnar electrode 80 is formed using a wire bonding method, the lower end of the columnar electrode 80 is welded to the upper end of the columnar electrode 30 in a spherical shape, thicker than the diameter (thickness) of the columnar electrode 80 in the X or Y direction. Consequently, a connecting portion 85, thicker than the diameter (thickness) of the columnar electrode 80 in the X or Y direction, is formed between the columnar electrode 30 and the columnar electrode 80. This improves the connection strength between the columnar electrode 30 and the columnar electrode 80. Furthermore, the columnar electrode 80 is cut off at its upper end, maintaining an upright state due to its own rigidity. As described above, the material of the columnar electrode 80 is such that it is not easily bent or tilted when covered by the resin layer 90.

[0125] Then, as Figure 19 As shown, the resin layer 90 material is filled into the groove TR to cover the columnar electrode 80. Then, the resin layer 90 is hardened by heating it in an oven or similar means, or by irradiating it with UV light.

[0126] Then, using CMP and mechanical polishing methods, the resin layer 90 is polished until the columnar electrodes 70, 80, and 210 are exposed. Thus, [the desired result is...] Figure 19 The structure shown.

[0127] Then, as Figure 20 As shown, a rewiring layer 100 is formed on the resin layer 90. Then, the support substrate 2 is removed using light methods such as heat or laser. Alternatively, the support substrate 2 can be removed by grinding.

[0128] Then, metal bumps 150 are formed on the rewiring layer 100. The metal bumps 150 can be formed, for example, by ball-mount, plating, or printing.

[0129] Then, by cutting Figure 20 The structure shown is monolithized. Therefore, Figure 12 The semiconductor device 1 shown is now complete.

[0130] In addition, it can also be with Figure 1A or Figure 1B Similarly shown, the rewiring layer 100 and the metal bump 150 are omitted.

[0131] In the second embodiment, the resin layer 90 fills a groove TR provided in a portion of the resin layer 40. Therefore, the volume of the resin layer 90 can be adjusted by adjusting the width and depth of the groove TR. By adjusting the volume of the resin layer 90, warping of the resin layer 40 can be suppressed.

[0132] Other configurations of the second embodiment may be the same as those of the first embodiment.

[0133] The second embodiment also divides the columnar electrodes 30 and 80, which are electrically connected to the electrode disks 15 of the plurality of semiconductor chips 10 stacked on the lower layer, into a lower columnar electrode 30 and an upper columnar electrode 80. Therefore, this embodiment can form substantially long columnar electrodes 30 and 80 while suppressing tilting and interference during the formation of the resin layers 40 and 90. The second embodiment also achieves other effects of the first embodiment.

[0134] (Third Implementation) Figure 21 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the third embodiment. In the third embodiment, the columnar electrode 80 is thicker than that in the first embodiment. Furthermore, the cross-sectional area of ​​the columnar electrode 80 in the direction perpendicular to its extension direction (X or Y direction) differs between the columnar electrode 80 and the columnar electrodes 30 and 70. The columnar electrode 80 is thicker than the columnar electrodes 30 and 70, and therefore has a larger cross-sectional area.

[0135] Figure 22 This is a schematic cross-sectional view showing an example of the configuration of the columnar electrodes 30 and 80 and the connecting portion 85. The columnar electrode 80 is thicker than the columnar electrode 30 and thinner than the connecting portion 85. That is, the cross-sectional area of ​​the columnar electrode 80 in the X-Y plane is larger than the cross-sectional area of ​​the columnar electrode 30 and smaller than the cross-sectional area of ​​the connecting portion 85.

[0136] By thickening the columnar electrode 80, its impedance value can be reduced. This reduces the impedance values ​​of the columnar electrodes 80 and 30 from the redistribution layer 100 to the electrode disk 15, improving the electrical characteristics of the semiconductor device 1. Other configurations in the third embodiment can be the same as those in the corresponding configuration of the first embodiment. Therefore, the third embodiment can also achieve the effects of the first embodiment.

[0137] (Fourth implementation) Figure 23 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the fourth embodiment. The fourth embodiment is an embodiment in which the columnar electrode 80 of the third embodiment is applied in the second embodiment. That is, for the cross-sectional area of ​​the X-Y plane, the cross-sectional area of ​​the columnar electrode 80 is larger than that of the columnar electrodes 30 and 70 and smaller than that of the connecting portion 85. As a result, the impedance value of the columnar electrodes 80 and 30 from the redistribution layer 100 to the electrode disk 15 can be reduced, thereby improving the electrical characteristics of the semiconductor device 1. Other configurations of the fourth embodiment can be the same as the corresponding configuration of the second embodiment. As a result, the fourth embodiment can also obtain the effects of the second embodiment.

[0138] Furthermore, in the third and fourth embodiments, the impedance value of the columnar electrode 80 is reduced by thickening the columnar electrode 80. However, the impedance value of the columnar electrode 80 can also be reduced by using a material with lower impedance compared to the materials of the columnar electrodes 30 and 70.

[0139] (Fifth Implementation) Figure 24 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the fifth embodiment. The semiconductor device 1 according to the fifth embodiment differs from the first embodiment in that an additional disk 83 is provided between the connection portion 85 and the columnar electrode 30. The additional disk 83 is provided at the front end of the columnar electrode 30 exposed from the resin layer 40, and has a larger area on the X-Y plane than the exposed area of ​​the front end of the columnar electrode 30.

[0140] The additional disk 83 can be made of conductive metals such as monomers of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, Ti, TiN, Cr, CrN, Ta, and TaN, composite films of two or more of these, or alloys of two or more of these. The additional disk 83 can improve the connection strength between the columnar electrode 30 and the columnar electrode 80, thereby improving reliability. The additional disk 83 can be formed on the columnar electrode 30 and the resin layer 40 using methods such as vapor deposition, sputtering, electroplating, or electroless plating. For example, composite films such as Ti-Ni-Au can be formed using sputtering. Composite films such as Ni-Pd-Au can be formed using electroless plating.

[0141] The additional disk 83 can be provided between the connection portions 85 of all columnar electrodes 30 and all columnar electrodes 80. Alternatively, the additional disk 83 can also be applied to the second to fourth embodiments.

[0142] (Sixth Embodiment) Figure 25This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the sixth embodiment. In the semiconductor device 1 according to the sixth embodiment, a plurality of columnar electrodes 80_1 and 80_2 are connected to one columnar electrode 30. The plurality of columnar electrodes 80_1 and 80_2 is not limited to two, but may be three or more. Each columnar electrode 80_1 and 80_2 is connected to an additional disk 83 via a connecting portion 85_1 and 85_2, and is electrically connected to one columnar electrode 30. The additional disk 83 is connected to the plurality of connecting portions 85_1 and 85_2 in a common manner. As a result, the additional disk 83 has an area on the X-Y plane that is larger than the exposed area of ​​the front end of the columnar electrode 30, and has an area that is larger than the cross-sectional area of ​​the connecting portions 85_1 and 85_2 on the X-Y plane. Alternatively, it may be configured such that one columnar electrode is connected to a plurality of columnar electrodes 80_1 and 80_2. It can also be constructed by connecting a cylindrical electrode via an additional disk 83.

[0143] Multiple columnar electrodes 80_1 and 80_2 can also be set in correspondence with each columnar electrode 30 or each additional disk 83.

[0144] (Seventh Embodiment) Figure 26 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the seventh embodiment. The semiconductor device 1 according to the seventh embodiment also includes an insulating layer 120 disposed between the resin layer 40 and the resin layer 90 or the semiconductor chip 50. The insulating layer 120 is disposed on the resin layer 40, but is removed in the areas of the additional pad 83 and the connecting portion 85.

[0145] Figure 27 This is a schematic cross-sectional view showing an example of the configuration of the additional disk 83, the connecting portion 85, and its surroundings. The insulating layer 120 covers the end of the additional disk 83 and is not located at the center of the additional disk 83. Therefore, the connecting portion 85 can be connected to the surface of the additional disk 83. The insulating layer 120 may be made of resins such as phenolic resins, polyimide resins, polyamide resins, acrylic resins, epoxy resins, PBO resins, silicone resins, benzocyclobutene resins, or mixtures or composite materials thereof.

[0146] After exposing the columnar electrodes and forming the additional disks 83, an insulating layer 120 is formed. The insulating layer 120 can maintain electrical insulation between adjacent additional disks 83, thereby improving the reliability of the semiconductor device 1.

[0147] By providing an insulating layer 120 between resin layers 40 and 90, the adhesion between resin layers 40 and 90 can be improved. Furthermore, the insulating layer 120 can improve the adhesion of the adhesive layer 60 adhered to the second surface F50b of the bottommost semiconductor chip 50. Preferably, the elastic modulus of the insulating layer 120 is lower than that of the resin layers 40 and 90. Therefore, the insulating layer 120 can absorb the stretching and contraction of the resin layers 40 and 90, thus suppressing warping of the semiconductor device 1.

[0148] The other configurations of the seventh embodiment can be the same as the corresponding configurations of the first embodiment. Therefore, the seventh embodiment can also achieve the effects of the first embodiment.

[0149] (Eighth Embodiment) Figure 28 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the eighth embodiment. The semiconductor device 1 according to the eighth embodiment also includes an insulating layer 130 disposed between the resin layer 40 and the redistribution layer 100 and between the resin layer 40 and the resin layer 90. The insulating layer 130 covers the inner surface of the trench TR, is disposed on the resin layer 40 between the resin layer 40 and the resin layer 90, but is removed in the areas of the additional pad 83 and the connecting portion 85.

[0150] Like insulating layer 120, insulating layer 130 covers the end of the supplementary tray 83 and is not located at the center of the supplementary tray 83. Therefore, the connecting portion 85 can be connected to the surface of the supplementary tray 83. Insulating layer 130 may be made of resins such as phenolic resins, polyimide resins, polyamide resins, acrylic resins, epoxy resins, PBO resins, silicone resins, benzocyclobutene resins, or mixtures or composite materials thereof.

[0151] After the trench TR is formed, the upper end of the columnar electrode 30 is exposed. After the additional disk 83 is formed, an insulating layer 130 is formed. The insulating layer 130 can maintain electrical isolation between adjacent additional disks 83, thereby improving the reliability of the semiconductor device 1.

[0152] By disposing the insulating layer 130 between the resin layer 40 and the resin layer 90, the adhesion between the resin layers 40 and 90 can be improved. Furthermore, the insulating layer 130 can improve the adhesion between the resin layer 40 and the redistribution layer 100. Preferably, the elastic modulus of the insulating layer 130 is lower than that of the resin layers 40, 90, and the redistribution layer 100. Therefore, the insulating layer 130 can absorb the stretching and contraction of the resin layers 40, 90, and the redistribution layer 100, thereby suppressing warping of the semiconductor device 1.

[0153] The other configurations of the eighth embodiment can be the same as the corresponding configurations of the second embodiment. Therefore, the eighth embodiment can also achieve the effects of the second embodiment.

[0154] (9th embodiment) Figures 29-31 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the ninth embodiment. The semiconductor device 1 according to the ninth embodiment further includes a rewiring layer 170 disposed between resin layer 40 and resin layer 90, and between resin layer 40 and the lowermost semiconductor chip 50. The wiring layer of the rewiring layer 170 is electrically connected to the pillar electrode 30 on the resin layer 40 side. That is, the front end of the pillar electrode 30 is electrically connected to the wiring layer on the back side of the rewiring layer 170. Additionally, the wiring layer of the rewiring layer 170 is electrically connected to the pillar electrode 80 on the resin layer 90 side. That is, the lower end of the pillar electrode 80 is electrically connected to the wiring layer on the surface side of the rewiring layer 170. The material of the rewiring layer 170 can be the same as the material of the rewiring layer 100.

[0155] The rewiring layer 170 rewirings the columnar electrodes 30 and electrically connects them to the columnar electrodes 80. Therefore, the spacing between adjacent columnar electrodes 80 is not limited by the spacing between adjacent columnar electrodes 30. That is, the arrangement of the columnar electrodes 80 relative to the columnar electrodes 30 has increased freedom, and the design freedom is increased. Thus, when viewed along the Z-direction, the columnar electrodes 80 can be positioned differently from the columnar electrodes 30. Furthermore, by placing the rewiring layer 170 between the resin layers 40 and 90, the adhesion between the resin layers 40 and 90 can be improved.

[0156] In addition, such as Figure 30 As shown, by providing a rewiring layer 170 between resin layer 40 and resin layer 90, the spacing of the columnar electrodes 30 can be changed to connect with the columnar electrodes 80. That is, the spacing between the plurality of columnar electrodes 80 can be different from the spacing between the plurality of columnar electrodes 30 when viewed along the Z direction. As a result, a semiconductor chip 50 can be stacked on top of the columnar electrodes 30. That is, the semiconductor chip 50 can overlap with the columnar electrodes 30 when viewed along the Z direction. As a result, the package size of the semiconductor device 1 can be reduced.

[0157] In addition, it can also be like Figure 31 As shown, the electrode pads 55 of the semiconductor chip 50 are positioned opposite to the electrode pads 15 of the semiconductor chip 10. In this case, the offset direction (X direction) of the stacked semiconductor chips 50 is opposite to the offset direction (-X direction) of the stacked semiconductor chips 10. Therefore, it is possible to reduce the size of the package of the semiconductor device 1 while also reducing the warpage of the package.

[0158] The other configurations of the ninth embodiment can be the same as the corresponding configurations of the first embodiment. Therefore, the ninth embodiment can also achieve the effects of the first embodiment.

[0159] (10th Embodiment) Figure 32 , Figure 33 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the tenth embodiment. In the semiconductor device 1 according to the tenth embodiment, slits ST are provided in the resin layers 40 on both sides of the stacked semiconductor chip 10, and resin layers 95 are embedded within the slits ST. The slits ST extend along the Y direction. Figure 33 In this process, the resin layer 95 is exposed on the side by cutting the slit ST portion. Alternatively, the slit ST can be configured such that, when viewed along the Z direction, the slit ST surrounds the stacked semiconductor chip 10 on all four sides.

[0160] Resin layer 95 can also be integrally formed from the same material as resin layer 90. In this case, after resin layer 40 is formed, slits ST can be formed using photolithography, etching, or cutting techniques, or by depositing the material of resin layer 90, thus simultaneously forming resin layers 90 and 95. Alternatively, warping can be suppressed, for example, by reducing the value of the elastic modulus × thermal expansion coefficient of the upper resin layers 90 and 95 compared to the value of the elastic modulus × thermal expansion coefficient of resin layer 40.

[0161] The slit ST can suppress warping of the package of semiconductor device 1. In addition, the resin layer 95 within the slit ST can improve the adhesion between resin layers 40 and 90.

[0162] The other configurations of the tenth embodiment can be the same as the corresponding configurations of the first embodiment. Therefore, the tenth embodiment can also achieve the same effects as the first embodiment. Furthermore, the tenth embodiment can also be combined with the second embodiment.

[0163] (11th Embodiment) Figure 34 , Figure 35 , Figure 36 , Figure 37 , Figure 38 and Figure 39This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the 11th embodiment. The semiconductor device 1 according to the 11th embodiment does not have a redistribution layer 100, but has metal bumps 155 provided at the upper ends of the pillar electrode 70 and the pillar electrode 210. The material of the metal bumps 155 can be the same as the material of the metal bumps 150. That is, the metal bumps 155 use conductive metals such as monomers of Sn, Ag, Cu, Au, Pd, Bi, Zn, Ni, Sb, In, and Ge, composite films of two or more of them, or alloys thereof.

[0164] When the spacing between adjacent columnar electrodes 70 and adjacent columnar electrodes 210 is large, a rewiring layer 100 is not required; the metal bumps 155 can be directly formed on the upper ends (exposed surfaces) of the columnar electrodes 70 and 210. Therefore, the process of installing a rewiring layer 100 is unnecessary. Furthermore, since a rewiring layer 100 is not required, the cost of the semiconductor device 1 is reduced.

[0165] Alternatively, an electrode disk (not shown) can be formed on the upper end of the columnar electrodes 70 and 210, and a metal bump 155 can be formed on the electrode disk.

[0166] It can also be like Figure 36 As shown, it is mounted on the wiring substrate 300, and encapsulated between the resin body and the wiring substrate by a resin layer 310. Alternatively, it can be as follows... Figure 37 As shown, it is mounted on the wiring substrate 300, encapsulated between the resin body and the wiring substrate by a resin layer 310, and then covered by a resin layer 320. Alternatively, it can be as follows... Figure 38 As shown, it is mounted on the wiring board 300, and the resin body and the wiring board, as well as the entire resin body, are covered by a resin layer 320. Alternatively, it can be as follows... Figure 39 The support 2 is shown. Resin layers 310 and 320 can use the same material as resin layer 40. Additionally, metal bumps 155 can also be formed on the pads of the wiring substrate.

[0167] The other configurations of the 11th embodiment can be the same as the corresponding configurations of the 1st embodiment. Therefore, the 11th embodiment can also achieve the same effects as the 1st embodiment. Alternatively, it can be as follows... Figure 35 As shown, the 11th embodiment is combined with the 2nd embodiment.

[0168] (12th implementation) Figure 40A This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the 12th embodiment. According to the 12th embodiment, the semiconductor chips 10 and 50 are divided into four types: semiconductor chips 10, 50_1, 50_2, and 50_3, and are stacked offset along the X direction.

[0169] Multiple stacked semiconductor chips 10 are covered by a resin layer 40. A columnar electrode 30 is connected to the electrode pad 15 of the semiconductor chip 10 via a connecting portion 35 and extends in the Z direction. The upper end of the columnar electrode 30 is exposed from the resin layer 40.

[0170] Multiple semiconductor chips 50_1 are stacked on resin layer 40. The stacked semiconductor chips 50_1 are covered by resin layer 90_1. A columnar electrode 70_1 is connected to the electrode pad 55_1 of the semiconductor chip 50_1 via a connecting portion 75_1 and extends in the Z direction. Additionally, a columnar electrode 80_1 is connected to the upper end of a columnar electrode 30 exposed from resin layer 40 via a connecting portion 85_1 and extends in the Z direction. Resin layer 90_1 covers the semiconductor chip 50_1, columnar electrodes 70_1, and 80_1, exposing the front ends of columnar electrodes 70_1 and 80_1.

[0171] Multiple semiconductor chips 50_2 are stacked on a resin layer 90_1. The stacked semiconductor chips 50_2 are covered by the resin layer 90_2. A columnar electrode 70_2 is connected to the electrode pad 55_2 of the semiconductor chip 50_2 via a connecting portion 75_2 and extends in the Z direction. In addition, a columnar electrode 80_2 is connected to the upper end of the columnar electrode 80_1 exposed from the resin layer 90_1 via a connecting portion 85_2 and extends in the Z direction. The resin layer 90_2 covers the semiconductor chip 50_2, the columnar electrodes 70_2 and 80_2, leaving the front ends of the columnar electrodes 70_2 and 80_2 exposed.

[0172] Multiple semiconductor chips 50_3 are stacked on a resin layer 90_2. A semiconductor chip 200 is stacked on the topmost semiconductor chip 50_3. The stacked semiconductor chips 50_3 and semiconductor chip 200 are covered by the resin layer 90_3. A columnar electrode 70_3 is connected to the electrode pad 55_3 of the semiconductor chip 50_3 via a connecting portion 75_3 and extends in the Z direction. In addition, a columnar electrode 80_3 is connected to the upper end of the columnar electrode 80_2 exposed from the resin layer 90_2 via a connecting portion 85_3 and extends in the Z direction. The resin layer 90_3 covers the semiconductor chip 50_3, columnar electrodes 70_3, and 80_3, exposing the front ends of the columnar electrodes 70_3 and 80_3.

[0173] The rewiring layer 100 is disposed on the resin layer 90_3 and electrically connected to the columnar electrodes 70_3, 80_3 and 210. The rewiring layer 100 is a multilayer wiring layer composed of multiple wiring layers and multiple insulating layers, and electrically connects the columnar electrodes 70, 80 and 210 to the metal bumps 150 respectively.

[0174] As shown in the 12th embodiment, the stacked structures of semiconductor chips 10, 50_1 to 50_3 can also be stacked as four semiconductor packages. The number of stacked semiconductor packages is not limited to four; it can be three or fewer or five or more.

[0175] Figure 40B It is Figure 40A A schematic cross-sectional view of the semiconductor chip, columnar electrode, and resin layer after extraction. Based on Figure 40B The 12th embodiment will be further described. The description will focus on the case where there are two semiconductor packages. It includes a plurality of stacked first semiconductor chips 10 and a plurality of first columnar electrodes 30 connected to electrode pads of the plurality of semiconductor chips 10 and extending along the stacking direction. It also includes a first resin layer 40 that covers the plurality of first semiconductor chips 10 and the plurality of first columnar electrodes 30, exposing the upper ends of the plurality of first columnar electrodes 30. It also includes a plurality of second semiconductor chips 50_1 stacked on a plurality of first semiconductor chips 10, a plurality of second columnar electrodes 70_1 connected to electrode disks 55_1 of the plurality of second semiconductor chips 50_1 and extending along the stacking direction of the plurality of second semiconductor chips 50_1, a plurality of third columnar electrodes 80_1 connected to a plurality of first columnar electrodes 30, and a second resin layer 90_1 covering the plurality of second semiconductor chips 50_1, the plurality of second columnar electrodes 70_1 and the plurality of third columnar electrodes 80_1 and exposing the upper ends of the plurality of second columnar electrodes 70_1 and the plurality of third columnar electrodes 80_1.

[0176] The following explanation addresses the case where there are three semiconductor packages. Here, the natural number k is set to 3 or increased from 3 to any natural number n (n >= 4). The case with three stacks is equivalent to k=3. In this case, compared to the case with two stacks, there are also multiple k-th semiconductor chips (3rd semiconductor chips 50_2) stacked on multiple (k-1)-th semiconductor chips (i.e., 2nd semiconductor chips 50_1), multiple 2k-2 columnar electrodes (4th columnar electrodes 70_2) connected to the electrode disks 55_2 of the multiple k-th semiconductor chips 50_2 and extending along the stacking direction of the multiple k-th semiconductor chips 50_2, and multiple 2k-4 columnar electrodes (2nd columnar electrodes 70_2). The package includes multiple 2k-1 columnar electrodes (5th columnar electrodes 80_2) connected to multiple 2k-3 columnar electrodes (3rd columnar electrode 80_1), and a k-th resin layer (3rd resin layer 90_2) covering multiple k-th semiconductor chips 50_2, multiple 2k-2 columnar electrodes 70_2, and multiple 2k-1 columnar electrodes 80_2, with the upper ends of the multiple 2k-2 columnar electrodes 70_2 and multiple 2k-1 columnar electrodes 80_2 exposed. When the number of semiconductor packages is 4, 5, or further increased, in addition to k=3, cases are added where k is increased to k=4, 5, or larger. Thus, regardless of how many semiconductor packages are added, the value of the natural number k can be used to explain the process.

[0177] The rewiring layer 100 is disposed on the k-th resin layer (k = 3 or n) and electrically connected to a plurality of 2k-2-th columnar electrodes, a plurality of 2k-1-th columnar electrodes, and columnar electrode 210. The rewiring layer 100 is a multilayer wiring layer formed by stacking multiple wiring layers and multiple insulating layers, and electrically connects the plurality of 2k-2-th columnar electrodes, the plurality of 2k-1-th columnar electrodes, and columnar electrode 210 to the metal bump 150 respectively.

[0178] The materials of the first resin layer 40, the second resin layer 90_1, and the subsequent k-th resin layer (k = 3 or n) can be the same or different. By making the first resin layer 40, the second resin layer 90_1, and the subsequent k-th resin layer (k = 3 or n) different, warping of the semiconductor package as a whole can be suppressed. Alternatively, the upper end of the columnar electrode may not be exposed from the first, second, or k-th resin layer (k ≥ 3), as long as at least a portion is exposed in some form.

[0179] (13th implementation) Figure 41 This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the 13th embodiment. According to the 13th embodiment, the resin layer 90 is disposed not only within the trench TR, but also between the resin layer 40 and the redistribution layer 100. Other configurations of the 13th embodiment may be the same as the corresponding configuration of the 2nd embodiment.

[0180] By making the stresses of resin layer 40 and resin layer 90 opposite, the warpage of the package of semiconductor device 1 can be adjusted, thereby improving reliability.

[0181] (14th embodiment) Figure 42 and Figure 43 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the 14th embodiment. According to the 14th embodiment, a groove TR is provided on a side surface extending to at least one end of the package of the semiconductor device 1, with the front end of the columnar electrode 30 exposed at its bottom. A resin layer 90 is also provided extending to one end of the package of the semiconductor device 1. Thus, the resin layer 90 is also exposed on the side surface of the package of the semiconductor device 1. The resin layer 40 is exposed on the side surface of the package, while the resin layer 90 is exposed on its upper portion.

[0182] exist Figure 42 In this configuration, the resin layer 90 is disposed only at one end of the package of the semiconductor device 1. Figure 43 In this embodiment, resin layers 90 are disposed at both ends of the package of semiconductor device 1. Other configurations of the 14th embodiment may be the same as the corresponding configurations of the 2nd embodiment.

[0183] When grinding the resin layer 40, the width of the groove TR can be increased by widening the grinding width. In addition, by grinding the resin layer 40 on both sides of each package, groove TR and resin layer 90 can be provided on both sides of the package.

[0184] By making the stresses of resin layer 40 and resin layer 90 opposite, and adjusting the volume of resin layer 90, the warpage of the package of semiconductor device 1 can be adjusted. This improves the reliability of semiconductor device 1. Other configurations of the 14th embodiment can be the same as the corresponding configuration of the 2nd embodiment.

[0185] (15th implementation) Figure 44 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the 15th embodiment. According to the 15th embodiment, the trench TR is formed in a stepped manner within the resin layer 40. Subsequently, the resin layer 90 embedded in the trench TR is also disposed in a stepped manner within the trench TR. The semiconductor device 1 of this embodiment is formed by repeatedly performing the formation of the trench TR, the formation of the columnar electrode 80, and the embedding of the resin layer 90. Therefore, since the columnar electrodes 30 and 80 can be formed sequentially, the long columnar electrodes 30 and 80 can be formed approximately linearly in the vertical direction. As a result, the reliability of the semiconductor device 1 is increased.

[0186] The other configurations of the 15th embodiment can be the same as the corresponding configurations of the 14th embodiment. Therefore, the 15th embodiment can also obtain the effects of the 14th embodiment.

[0187] (16th embodiment) Figure 45 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the 16th embodiment. According to the 16th embodiment, the bottom surface of the trench TR and the resin layer 90 is inclined relative to the X-Y planes (planes F10a, F10b). Preferably, the bottom surface of the trench TR and the resin layer 90 is inclined approximately parallel to the offset of the side surfaces of the stack of semiconductor chips 10, 50 (the inclination of the side surfaces of the stack). That is, the semiconductor chips 10, 50 are stacked with an offset in a certain inclined direction relative to planes F10a, F10b, F50a, F50b. Furthermore, the bottom surface of the trench TR is inclined along the inclined direction of the stack of semiconductor chips 10, 50. This allows the lengths of the columnar electrodes 30 to be approximately equal, suppressing bending or falling of the columnar electrodes 30. Additionally, the volume of the resin layer 90 can be made relatively small. Sometimes, a smaller volume of the resin layer 90 further reduces the warpage of the package. In this case, by reducing the volume of the resin layer 90 as shown in the 16th embodiment, the reliability of the semiconductor device 1 can be improved. Other configurations of the 16th embodiment can be the same as the corresponding configuration of the 2nd embodiment. Therefore, the 16th embodiment can also achieve the effects of the 2nd embodiment.

[0188] While several embodiments have been described above, these embodiments are merely illustrative and not intended to limit the scope of the invention. The new apparatus and method described herein can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the new apparatus and method described herein without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention described in the patent claims and its equivalents.

Claims

1. A semiconductor device comprising: Multiple stacked first semiconductor chips; The first columnar electrode is connected to the electrode disk of the plurality of first semiconductor chips and extends along the stacking direction of the plurality of first semiconductor chips. Multiple second semiconductor chips are stacked on top of the first semiconductor chip; The second columnar electrode is connected to the electrode disk of the plurality of second semiconductor chips and extends along the stacking direction of the plurality of second semiconductor chips. The third columnar electrode is electrically connected to the first columnar electrode and extends along the stacking direction of the plurality of second semiconductor chips; as well as The resin layer has the following characteristics: The first resin layer covers the first semiconductor chip, the second semiconductor chip, the first columnar electrode, and the second columnar electrode. The front end of the second columnar electrode is exposed on the upper surface of the first resin layer, and the front end of the first columnar electrode is exposed at the bottom of the groove or step provided in the first resin layer. as well as The second resin layer, disposed within the groove or step, is made of a different material than the first resin layer and has opposite stresses to the first resin layer. The third columnar electrode is connected to the front end of the first columnar electrode exposed within the groove or step of the first resin layer, and extends along the stacking direction of the plurality of second semiconductor chips. The second resin layer covers the third columnar electrode, exposing the front end of the third columnar electrode.

2. The semiconductor device according to claim 1, wherein, The groove extends in a direction substantially parallel to the edge of the plurality of first semiconductor chips or the plurality of second semiconductor chips on which the electrode disk is disposed.

3. The semiconductor device according to claim 1, wherein, A connecting portion is also provided between the first columnar electrode and the third columnar electrode, the cross-sectional dimension of which in the direction perpendicular to the extending direction of the third columnar electrode is larger than that of the first columnar electrode and the third columnar electrode.

4. The semiconductor device according to claim 1, wherein, It also has: A wiring layer, disposed on the resin layer, is electrically connected to the second columnar electrode and the third columnar electrode; and A bump is disposed on the wiring layer and electrically connected to the wiring layer.

5. The semiconductor device according to claim 1, wherein, The dimensions of the cross-section of the third columnar electrode in the direction perpendicular to its extension direction are different from the dimensions of the cross-sections of the first and second columnar electrodes in the direction perpendicular to their extension directions.

6. The semiconductor device according to claim 1, wherein, The material of the third columnar electrode is different from the materials of the first columnar electrode and the second columnar electrode.

7. The semiconductor device according to claim 1, wherein, It also includes an additional disk, which is disposed at the front end of the first columnar electrode and has a larger area than the exposed area of ​​the front end of the first columnar electrode.

8. The semiconductor device according to claim 1, wherein, A plurality of third columnar electrodes are connected to one of the plurality of first columnar electrodes.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The first resin layer and the second resin layer are made of different materials.

10. The semiconductor device according to claim 1, wherein, It also includes other semiconductor chips disposed on the second semiconductor chip.

11. The semiconductor device according to claim 1, wherein, The groove or the bottom is provided up to the side of the first resin layer, with the front end of the first columnar electrode exposed at its bottom.

12. The semiconductor device according to claim 1, wherein, The first semiconductor chip and the second semiconductor chip are stacked with an offset direction relative to the first surface of the first semiconductor chip and the second semiconductor chip. The bottom surface of the groove is inclined along the tilting direction of the first semiconductor chip and the second semiconductor chip.

13. The semiconductor device according to claim 1, wherein, The first to third columnar electrodes use conductive wires.

14. The semiconductor device according to claim 1, wherein, The first semiconductor chip and the second semiconductor chip are memory chips.

15. The semiconductor device according to claim 10, wherein, The other semiconductor chips are controller chips.

16. A method for manufacturing a semiconductor device, comprising: Multiple semiconductor chips are stacked on a support substrate. Multiple first columnar electrodes are formed on multiple electrode disks of the multiple semiconductor chips. The plurality of semiconductor chips and the plurality of first columnar electrodes are coated with a first resin layer. A groove is formed by grinding a portion of the plurality of first columnar electrodes and a portion of the first resin layer, exposing the upper ends of the plurality of first columnar electrodes at the bottom of the groove. A second columnar electrode is formed on the upper end of the plurality of first columnar electrodes exposed within the groove. The second columnar electrode is covered with a second resin layer inside the groove.

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