Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate including a peripheral region; a first active pattern on the peripheral region; a first source / drain pattern on the first active pattern; a first channel pattern formed on the first active pattern and connected to the first source / drain pattern, wherein the first channel pattern includes semiconductor patterns stacked on each other and spaced apart; a first gate electrode extending in a first direction and crossing the first channel pattern; a gate insulating layer interposed between the first gate electrode and the first channel pattern; a first gate contact provided on the first gate electrode and extending in the first direction; and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2020-0179249, filed on December 21, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor. Background Technology

[0003] A semiconductor device includes an integrated circuit made of a metal-oxide-semiconductor field-effect transistor (MOS-FET). To meet the growing demand for semiconductor devices with smaller pattern sizes and reduced design rules, MOS-FETs are being actively scaled down. This scaling down of MOS-FETs leads to a deterioration in the operational properties of the semiconductor device. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor device with improved electrical and reliability characteristics.

[0005] According to an embodiment of the inventive concept, a semiconductor device includes: a substrate including a peripheral region; a first active pattern disposed on the peripheral region; a first source / drain pattern disposed on the first active pattern; a first channel pattern formed on the first active pattern and connected to the first source / drain pattern, wherein the first channel pattern includes semiconductor patterns stacked and spaced apart from each other; a first gate electrode extending in a first direction and intersecting the first channel pattern; a gate insulating layer disposed between the first gate electrode and the first channel pattern; a first gate contact disposed on the first gate electrode and extending in the first direction; and a first dielectric layer disposed between the first gate electrode and the first gate contact. The first dielectric layer is disposed between the bottom surface of the first gate contact and the top surface of the first gate electrode and extends in the first direction.

[0006] According to an embodiment of the inventive concept, a semiconductor device includes: a substrate including a peripheral region and a logic cell region; a first active pattern and a second active pattern disposed on the peripheral region and the logic cell region, respectively; a first source / drain pattern and a second source / drain pattern disposed on the first active pattern and the second active pattern, respectively; a first channel pattern and a second channel pattern formed on the first active pattern and the second active pattern, respectively, and respectively connected to the first source / drain pattern and the second source / drain pattern, wherein each of the first channel pattern and the second channel pattern includes semiconductor patterns stacked and spaced apart from each other; a first gate electrode and a second gate electrode extending in a first direction and intersecting the first channel pattern and the second channel pattern, respectively; a first gate contact disposed on the first gate electrode; a second gate contact electrically connected to the second gate electrode; and a dielectric layer between the first gate contact and the first gate electrode. The width of the first gate contact in the first direction is greater than the width of the first channel pattern in the first direction.

[0007] According to an embodiment of the inventive concept, a semiconductor device includes: a substrate including a peripheral region and a logic cell region; a first active pattern and a second active pattern disposed on the peripheral region, spaced apart from each other in a first direction, and extending in a second direction intersecting the first direction; a device isolation layer disposed on the substrate, and the device isolation layer separating the first active pattern and the second active pattern; a first source / drain pattern and a second source / drain pattern respectively disposed on the first active pattern and the second active pattern; a first channel pattern and a second channel pattern respectively formed on the first active pattern and the second active pattern, and respectively connected to the first source / drain pattern and the second source / drain pattern, each of the first channel pattern and the second channel pattern including semiconductor patterns stacked and spaced apart from each other, the semiconductor patterns including a first semiconductor pattern at the lowest level, a second semiconductor pattern on the first semiconductor pattern, and a third semiconductor pattern on the second semiconductor pattern; a first gate electrode extending in the first direction and intersecting the first channel pattern and the second channel pattern, the first gate electrode including a substrate and a first... The system comprises: a first portion between semiconductor patterns; a second portion between the first semiconductor pattern and the second semiconductor pattern; a third portion between the second semiconductor pattern and the third semiconductor pattern; and a fourth portion on the third semiconductor pattern; a first gate insulating layer disposed between the first gate electrode and the first channel pattern and between the first gate electrode and the second channel pattern, the first gate insulating layer comprising a high-k dielectric layer and an insulating layer on the high-k dielectric layer; a pair of gate spacers disposed on opposite sides of the first gate electrode; a gate cap pattern disposed on the first gate electrode; a first interlayer insulating layer disposed on the gate cap pattern; an active contact penetrating the first interlayer insulating layer and electrically connected to at least one of the first source / drain pattern and the second source / drain pattern; a first gate contact disposed on the first gate electrode and penetrating the first interlayer insulating layer and the gate cap pattern; a first dielectric layer disposed between the first gate contact and the first gate electrode; a second interlayer insulating layer disposed on the first interlayer insulating layer; and a first metal layer formed in the second interlayer insulating layer and on the first gate contact, and electrically connected to the active contact. The first gate contact may extend in a first direction. The first dielectric layer may be disposed between the bottom surface of the first gate contact and the top surface of the first gate electrode and extend in a first direction. Attached Figure Description

[0008] Figure 1 This is a plan view of a semiconductor device according to an embodiment of the inventive concept.

[0009] Figures 2A to 2H They are along Figure 1 The sectional views taken from lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H'.

[0010] Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 This is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0011] Figure 4A , Figure 6A , Figure 8A , Figure 10A , Figure 12A and Figure 14A They are along Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken by line A-A'.

[0012] Figure 4B , Figure 6B , Figure 8B , Figure 10B , Figure 12B and Figure 14B They are along Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 The sectional view taken by line B-B'.

[0013] Figure 4C , Figure 8C , Figure 10C , Figure 12C and Figure 14C They are along Figure 3 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken by line C-C'.

[0014] Figure 4D , Figure 8D , Figure 10D , Figure 12D and Figure 14D They are along Figure 3 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken by line D-D'.

[0015] Figure 8E , Figure 10E , Figure 12E and Figure 14E They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken from line E-E'.

[0016] Figure 8F , Figure 10F and Figure 12F They are along Figure 7 , Figure 9 and Figure 11 The sectional view taken by line F-F'.

[0017] Figure 15A , Figure 15B and Figure 15C These are respectively the edges of a semiconductor device used to illustrate an embodiment according to the inventive concept. Figure 1 A sectional view taken from lines A-A', B-B', and C-C'.

[0018] Figure 16A , Figure 16B and Figure 16C These are respectively the edges of a semiconductor device used to illustrate an embodiment according to the inventive concept. Figure 1 A sectional view taken from lines A-A', B-B', and C-C'.

[0019] Figure 17 It is used to illustrate a semiconductor device according to an embodiment of the inventive concept. Figure 1 A sectional view taken by line C-C'.

[0020] Figure 18 This is a plan view of a semiconductor device according to an embodiment of the inventive concept.

[0021] Figure 19 It is along Figure 18 A sectional view taken by line A-A'.

[0022] Figure 20 This is a plan view of a semiconductor device according to an embodiment of the inventive concept.

[0023] Figure 21 It is along Figure 20 A sectional view taken by line A-A'. Detailed Implementation

[0024] Figure 1 This is a plan view of a semiconductor device according to an embodiment of the inventive concept. Figures 2A to 2H They are along Figure 1 The sectional views taken from lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H'.

[0025] Reference Figure 1According to an embodiment, a substrate 100 including a peripheral region PER and a logic cell region LGC is provided. The substrate 100 is a semiconductor substrate formed of or including silicon, germanium, silicon-germanium, or compound semiconductor materials. In this embodiment, the substrate 100 is a silicon substrate. The peripheral region PER is a region where transistors or I / O terminals constituting a processor core are disposed. The logic cell region LGC is a region where standard cells constituting a logic circuit are disposed. Compared to the transistors in the logic cell region LGC, the transistors in the peripheral region PER operate under high power conditions. In the following, reference will be made to… Figure 1 as well as Figures 2A to 2D A more detailed description of the transistors in the peripheral region PER.

[0026] In this embodiment, the peripheral region PER includes a first PMOSFET region PR1 and a first NMOSFET region NR1. The first PMOSFET region PR1 and the first NMOSFET region NR1 are separated by a second trench TR2 formed in the upper portion of the substrate 100. In other words, the second trench TR2 is located between the first PMOSFET region PR1 and the first NMOSFET region NR1. The first PMOSFET region PR1 and the first NMOSFET region NR1 are spaced apart from each other in a first direction D1, with the second trench TR2 positioned therebetween.

[0027] In an embodiment, the first active pattern AP1 and the second active pattern AP2 are separated by a first trench TR1 formed in the upper portion of the substrate 100. The first active pattern AP1 and the second active pattern AP2 are formed on the first PMOSFET region PR1 and the first NMOSFET region NR1, respectively. The first trench TR1 is shallower than the second trench TR2. The first trench TR1 is formed above the second trench TR2 and is wider than the second trench TR2. The first active pattern AP1 and the second active pattern AP2 extend in a second direction D2 intersecting the first direction D1. The first active pattern AP1 and the second active pattern AP2 may be vertically protruding portions of the substrate 100.

[0028] In this embodiment, the device isolation layer ST fills the first trench TR1 and the second trench TR2. The device isolation layer ST is formed of or includes silicon oxide. The upper portions of the first active pattern AP1 and the second active pattern AP2 protrude vertically above the device isolation layer ST (e.g., see...). Figure 2C The device isolation layer ST does not cover the upper part of the first active pattern AP1 and the second active pattern AP2, but the device isolation layer ST may cover the lower surface of the first active pattern AP1 and the second active pattern AP2.

[0029] In an embodiment, the first active pattern AP1 includes a first channel pattern CH1 formed on its upper portion. The second active pattern AP2 includes a second channel pattern CH2 formed on its upper portion. Each of the first channel pattern CH1 and the second channel pattern CH2 includes a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are sequentially stacked. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 are spaced apart from each other in a vertical direction (i.e., the third direction D3) perpendicular to the plane defined by the first direction D1 and the second direction D2.

[0030] In an embodiment, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 is formed of or includes at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). In another embodiment, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 is formed of or includes crystalline silicon.

[0031] In this embodiment, a pair of first source / drain patterns SD1 are disposed on the upper part of the first active pattern AP1. The first source / drain patterns SD1 are first conductivity type (e.g., p-type) impurity regions. A first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 of the first channel pattern CH1 are disposed between the pair of first source / drain patterns SD1. In other words, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the first channel pattern CH1 connect the pair of first source / drain patterns SD1 to each other.

[0032] In this embodiment, a pair of second source / drain patterns SD2 are disposed on the upper portion of the second active pattern AP2. The second source / drain patterns SD2 are second conductivity type (e.g., n-type) impurity regions. A first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 of the second channel pattern CH2 are positioned between the pair of second source / drain patterns SD2. In other words, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the second channel pattern CH2 connect the pair of second source / drain patterns SD2 to each other.

[0033] In an embodiment, the first source / drain pattern SD1 and the second source / drain pattern SD2 are epitaxial patterns formed by a selective epitaxial growth process. In an embodiment, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 has a top surface that is substantially coplanar with the top surface of the third semiconductor pattern SP3. In an embodiment, the top surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 is located at a position higher than the top surface of the adjacent third semiconductor pattern SP3.

[0034] In one embodiment, the first source / drain pattern SD1 comprises a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. In this case, the first source / drain pattern SD1 applies compressive stress to the first channel pattern CH1. The second source / drain pattern SD2 is formed of or comprises the same semiconductor material (e.g., Si) as the substrate 100.

[0035] In one embodiment, a first gate electrode GE1 is disposed extending in a first direction D1 and intersecting with a first active pattern AP1 and a second active pattern AP2. The first gate electrode GE1 extends from a first PMOSFET region PR1 to a first NMOSFET region NR1. The first gate electrode GE1 is vertically stacked with a first channel pattern CH1 and a second channel pattern CH2.

[0036] In an embodiment, the first gate electrode GE1 includes a first portion PO1 disposed between the substrate 100 and the first semiconductor pattern SP1, a second portion PO2 disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 disposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 disposed on the third semiconductor pattern SP3.

[0037] Return to reference Figure 2C In this embodiment, the first gate electrode GE1 surrounds the top surface TS, bottom surface BS, and opposite side surface SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. That is, the transistor in the peripheral region PER according to this embodiment is a three-dimensional field-effect transistor, such as a multi-bridge channel field-effect transistor (MBCFET) or a gate-all-around FET (GAAFET), where the gate electrode is three-dimensionally surrounded by the channel pattern.

[0038] Return to reference Figure 1 and Figures 2A to 2DIn one embodiment, a pair of gate spacers GS are disposed on opposite side surfaces of the first gate electrode GE1. The gate spacers GS extend along the first gate electrode GE1 or in a first direction D1. The gate spacers GS have a top surface that is higher than the top surface of the first gate electrode GE1. The top surface of the gate spacers GS is coplanar with the top surface of the first interlayer insulating layer 110, which will be described below. The gate spacers GS are formed of or include at least one of SiCN, SiCON, and SiN. In another embodiment, the gate spacers GS have a multilayer structure comprising at least two layers, each of which is made of SiCN, SiCON, or SiN.

[0039] In an embodiment, a gate cap pattern GP is disposed on a first gate electrode GE1. The gate cap pattern GP extends along the first gate electrode GE1 in a first direction D1. The gate cap pattern GP is formed of or includes a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. For example, the gate cap pattern GP is formed of or includes at least one of SiON, SiCN, SiCON, and SiN.

[0040] In an embodiment, a first gate insulating layer GI1 is disposed between a first gate electrode GE1 and a first channel pattern CH1, and between a first gate electrode GE1 and a second channel pattern CH2. The first gate insulating layer GI1 directly surrounds the top surface TS, bottom surface BS, and opposite side surface SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 (e.g., see...). Figure 2C The first gate insulating layer GI1 extends along the bottom surface of the first gate electrode GE1 thereon. The first gate insulating layer GI1 covers the top surface of the device isolation layer ST located below the first gate electrode GE1.

[0041] In an embodiment, the first gate insulating layer GI1 includes a high-k dielectric layer HK that directly covers the top surface, bottom surface, and opposite side surface of each of the first channel pattern CH1 and the second channel pattern CH2. The first gate insulating layer GI1 also includes an insulating layer IL on the high-k dielectric layer HK. The first gate electrode GE1 and the first gate insulating layer GI1 fill the space between vertically adjacent first semiconductor patterns SP1, second semiconductor patterns SP2, and third semiconductor patterns SP3.

[0042] In an embodiment, the high-k dielectric layer HK is thicker than the insulating layer IL. The insulating layer IL comprises a silicon oxide layer or a silicon oxynitride layer. The high-k dielectric layer HK is formed of or comprises a high-k dielectric material whose dielectric constant is higher than that of silicon oxide. For example, the high-k dielectric material includes at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0043] In another embodiment, the semiconductor device includes a negative capacitance (NC) FET that uses a negative capacitor. For example, the first gate insulating layer GI1 includes a ferroelectric layer and a paraelectric layer.

[0044] In this embodiment, the ferroelectric layer has a negative capacitance, and the paraelectric layer has a positive capacitance. When two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance is less than the capacitance of each individual capacitor. In contrast, when at least one of the capacitors connected in series has a negative capacitance, the total capacitance of the capacitors connected in series is positive and can be greater than the absolute value of each individual capacitor.

[0045] In an embodiment, when a ferroelectric layer with negative capacitance and a paraelectric layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric layers increases. Due to this increase in total capacitance, the transistor including the ferroelectric layer exhibits a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0046] In the embodiments, the ferroelectric layer is formed of or includes at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, hafnium zirconium oxide is hafnium oxide doped with zirconium (Zr). Optionally, hafnium zirconium oxide is one of a compound composed of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0047] In embodiments, the ferroelectric layer further includes dopants. For example, the dopants include at least one selected from aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant in the ferroelectric layer varies depending on the ferroelectric material in the ferroelectric layer.

[0048] In an embodiment, when the ferroelectric layer comprises hafnium oxide, the dopant in the ferroelectric layer comprises at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0049] In the embodiments, when the dopant is aluminum (Al), the aluminum content in the ferroelectric layer is in the range of 3 at% to 8 at% (atomic percentage). Here, the aluminum dopant content is the ratio of the number of aluminum atoms to the total number of hafnium atoms and aluminum atoms.

[0050] When the dopant is silicon (Si), the silicon content in the ferroelectric layer ranges from 2 at% to 10 at%. When the dopant is yttrium (Y), the yttrium content in the ferroelectric layer ranges from 2 at% to 10 at%. When the dopant is gadolinium (Gd), the gadolinium content in the ferroelectric layer ranges from 1 at% to 7 at%. When the dopant is zirconium (Zr), the zirconium content in the ferroelectric layer ranges from 50 at% to 80 at%.

[0051] In embodiments, the paraelectric layer is formed of or includes at least one of, for example, silicon oxide and a high-k metal oxide. Metal oxides that can be used as the paraelectric layer include at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide, but embodiments of the inventive concept are not limited to these examples.

[0052] In this embodiment, the ferroelectric layer and the paraelectric layer comprise the same material. The ferroelectric layer is ferroelectric by definition, but the paraelectric layer is not ferroelectric. For example, when both the ferroelectric and paraelectric layers contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer is different from the crystal structure of the hafnium oxide in the paraelectric layer.

[0053] In the embodiments, the ferroelectric layer is ferroelectric only when its thickness is within a specific range. In the embodiments, the thickness of the ferroelectric layer is in the range of 0.5 nm to 10 nm, but the embodiments of the inventive concept are not limited to this range. Since the critical thickness associated with ferroelectricity varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer also varies depending on the type of ferroelectric material.

[0054] For example, in one embodiment, the first gate insulating layer GI1 includes a single ferroelectric layer. For example, in another embodiment, the first gate insulating layer GI1 includes a plurality of ferroelectric layers spaced apart from each other. The first gate insulating layer GI1 has a multilayer structure in which a plurality of ferroelectric layers and a plurality of paraelectric layers are alternately stacked.

[0055] In one embodiment, the first gate electrode GE1 includes a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern is disposed on a first gate insulating layer GI1 adjacent to a first channel pattern CH1 and a second channel pattern CH2. The first metal pattern includes work function metal that can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be realized.

[0056] In an embodiment, the first metal pattern includes a metal nitride layer. For example, the first metal pattern includes at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) or nitrogen (N). In an embodiment, the first metal pattern also includes carbon (C). The first metal pattern may include multiple stacked active power metal layers.

[0057] In an embodiment, the second metal pattern comprises a metal whose resistance is lower than that of the first metal pattern. For example, the second metal pattern comprises at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0058] Return to reference Figure 2B In this embodiment, an internal spacer IP is disposed on the first NMOSFET region NR1. The internal spacer IP is respectively positioned between a first portion PO1, a second portion PO2, and a third portion PO3 of the first gate electrode GE1 and the second source / drain pattern SD2. The internal spacer IP directly contacts the second source / drain pattern SD2. Each of the first portion PO1, the second portion PO2, and the third portion PO3 of the first gate electrode GE1 is spaced apart from the second source / drain pattern SD2 by the internal spacer IP.

[0059] In embodiments, the internal spacer IP is formed of or comprises at least one low-k dielectric material. Low-k dielectric materials include silicon oxide or dielectric materials with a dielectric constant lower than that of silicon oxide. For example, low-k dielectric materials include silicon oxide, fluorine- or carbon-doped silicon oxide, porous silicon oxide, or organic polymer dielectric materials.

[0060] In one embodiment, a first interlayer insulating layer 110 is disposed on a substrate 100. The first interlayer insulating layer 110 covers a gate spacer GS and a first source / drain pattern SD1 and a second source / drain pattern SD2. The first interlayer insulating layer 110 has a top surface that is substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 covering the gate cap pattern GP is disposed on the first interlayer insulating layer 110. In one embodiment, at least one of the first interlayer insulating layer 110 and the second interlayer insulating layer 120 includes a silicon oxide layer.

[0061] In this embodiment, active contacts AC are provided that penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and are electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC are respectively disposed on both sides of the first gate electrode GE1. When viewed in a plan view, the active contacts AC have a strip pattern extending in the first direction D1.

[0062] In an embodiment, the active contact AC includes a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The conductive pattern FM is formed of or includes at least one metal such as aluminum, copper, tungsten, molybdenum, or cobalt. The barrier pattern BM covers the side and bottom surfaces of the conductive pattern FM. In an embodiment, the barrier pattern BM includes a metal layer and a metal nitride layer. The metal layer is formed of or includes at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer is formed of or includes at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0063] In this embodiment, the active contact AC is a self-aligned contact. For example, the active contact AC is formed using a self-aligned process of the gate cap pattern GP and the gate spacer GS. For example, the active contact AC covers at least a portion of the side surface of the gate spacer GS. Additionally, the active contact AC covers a portion of the top surface of the gate cap pattern GP.

[0064] In this embodiment, a silicide pattern SC is positioned between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC is electrically connected to either the source / drain pattern SD1 or SD2 via the silicide pattern SC. The silicide pattern SC is formed of or includes at least one metallic silicide material such as titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0065] In one embodiment, a first gate contact GC1 is disposed on the first gate electrode GE1 and penetrates the second interlayer insulating layer 120 and the gate cap pattern GP. Similar to the active contact AC, the first gate contact GC1 includes a conductive pattern FM and a blocking pattern BM surrounding the conductive pattern FM. The first gate contact GC1 has a longitudinal axis parallel to a first direction D1. That is, the first gate contact GC1 extends along the first gate electrode GE1 and in the first direction D1. For example, the first gate contact GC1 may be disposed on a first PMOSFET region PR1 or a first NMOSFET region NR1. The first gate contact GC1 may be vertically stacked with a first channel pattern CH1 or a second channel pattern CH2.

[0066] In this embodiment, a dielectric layer DL is disposed between the first gate contact GC1 and the first gate electrode GE1. Specifically, the dielectric layer DL is disposed between the first gate contact GC1 and the fourth portion PO4 of the first gate electrode GE1. The first gate contact GC1 is spaced apart from the first gate electrode GE1 by the dielectric layer DL. The dielectric layer DL is located between the bottom surface of the first gate contact GC1 and the top surface of the first gate electrode GE1, and extends in the first direction D1. For example, the dielectric layer DL covers the bottom and side surfaces of the first gate contact GC1. Specifically, the dielectric layer DL covers the bottom and side surfaces of the blocking pattern BM of the first gate contact GC1.

[0067] In embodiments, the dielectric layer DL is formed of or comprises a high-k dielectric material whose dielectric constant is higher than that of silicon oxide. For example, the dielectric layer DL is formed of or comprises at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and zinc lead niobate, or comprises at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and zinc lead niobate.

[0068] For three-dimensional field-effect transistors, it can be difficult to increase the thickness of the gate insulating layer. According to an embodiment of the inventive concept, since the dielectric layer DL is disposed between the first gate contact GC1 and the first gate electrode GE1, the voltage applied between the first gate electrode GE1 and the substrate 100 can be reduced. In other words, reliability problems associated with high-power transistors formed on the peripheral region PER can be prevented. As a result, the electrical and reliability characteristics of the semiconductor device can be improved.

[0069] In this embodiment, the first width W1 is the minimum width of the first gate electrode GE1 in the second direction D2, and the second width W2 is the maximum width of the dielectric layer DL in the second direction D2. For example, the second width W2 is greater than the first width W1.

[0070] In an embodiment, the third width W3 is the width of the channel patterns CH1 and / or CH2 in the first direction D1, and the fourth width W4 is the width of the first gate contact GC1 in the first direction D1. For example, the fourth width W4 is greater than the third width W3. In an embodiment, to reduce or maintain the voltage applied to the transistor, the widths of the first gate contact GC1 and the dielectric layer DL can be adjusted proportionally to the width of the channel patterns. The thickness of the dielectric layer DL can be adjusted to apply a desired voltage to the transistor.

[0071] In one embodiment, a third interlayer insulating layer 130 is disposed on the second interlayer insulating layer 120. A first metal layer M1 is formed in the third interlayer insulating layer 130. The first metal layer M1 includes a first interconnect IL1 and a first via VI1. The first via VI1 is formed below the first interconnect IL1. The first interconnect IL1 extends in a first direction D1. Each first interconnect IL1 has a linear or stripe pattern extending in a second direction D2.

[0072] In one embodiment, a first via VI1 is formed below the first interconnect IL1 of the first metal layer M1. The first via VI1 is positioned between the active contact AC and the first interconnect IL1. The first via VI1 is also positioned between the first gate contact GC1 and the first interconnect IL1.

[0073] In this embodiment, the first interconnect IL1 and the underlying first via VI1 are formed by a separate process. In other words, each of the first interconnect IL1 and the first via VI1 is formed by a single damascene process. The semiconductor device according to this embodiment can be fabricated using a process smaller than 20nm (sub-20nm).

[0074] In one embodiment, a fourth interlayer insulating layer 140 is disposed on the third interlayer insulating layer 130. A second metal layer M2 is formed in the fourth interlayer insulating layer 140. The second metal layer M2 includes second interconnects IL2. Each second interconnect IL2 is a linear or stripe pattern extending in a first direction D1. For example, the second interconnects IL2 extend parallel to each other in the first direction D1.

[0075] In one embodiment, the second metal layer M2 further includes a second via VI2. The second via VI2 is formed below the second interconnect IL2. The second via VI2 is located between the first interconnect IL1 and the second interconnect IL2.

[0076] In one embodiment, the second interconnect IL2 and the underlying second via VI2 are formed using the same process, and in this case, constitute a single object. For example, the second interconnect IL2 and the second via VI2 of the second metal layer M2 are formed together using a dual damascene process.

[0077] In the embodiments, the first interconnect line IL1 of the first metal layer M1 and the second interconnect line IL2 of the second metal layer M2 can be formed of the same conductive material or different conductive materials, or include the same conductive material or different conductive materials. For example, the first interconnect line IL1 and the second interconnect line IL2 can be formed of at least one metal such as copper (Cu), ruthenium (Ru), cobalt (Co), tungsten (W), aluminum (Al) and / or molybdenum (Mo), or include at least one metal such as copper (Cu), ruthenium (Ru), cobalt (Co), tungsten (W), aluminum (Al) and / or molybdenum (Mo).

[0078] In one embodiment, additional metal layers may also be stacked on the fourth interlayer insulating layer 140. Each of the stacked metal layers includes wiring.

[0079] In the following text, reference will be made to Figure 1 as well as Figures 2E to 2H A more detailed description of the transistors in the logic cell region (LGC) is provided. For brevity, references may be omitted in the following description. Figure 1 as well as Figures 2A to 2D A description of the characteristics of the transistors in the peripheral region PER.

[0080] In this embodiment, the logic cell region LGC includes a second PMOSFET region PR2 and a second NMOSFET region NR2. The second PMOSFET region PR2 and the second NMOSFET region NR2 are separated by a second trench TR2 formed in the upper part of the substrate 100. A third active pattern AP3 and a fourth active pattern AP4 are separated by a first trench TR1 formed in the upper part of the substrate 100. The third active pattern AP3 and the fourth active pattern AP4 are respectively disposed on the second PMOSFET region PR2 and the second NMOSFET region NR2.

[0081] In an embodiment, the third active pattern AP3 includes a third channel pattern CH3 formed thereon, and the fourth active pattern AP4 includes a fourth channel pattern CH4 formed thereon. Each of the third channel pattern CH3 and the fourth channel pattern CH4 includes a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are stacked sequentially.

[0082] In this embodiment, the third source / drain pattern SD3 is disposed above the third active pattern AP3. The fourth source / drain pattern SD4 is disposed above the fourth active pattern AP4. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the third channel pattern CH3 are disposed between a pair of third source / drain patterns SD3. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the fourth channel pattern CH4 are disposed between a pair of fourth source / drain patterns SD4.

[0083] In an embodiment, each of the third source / drain patterns SD3 is an epitaxial pattern including an impurity of a first conductivity type (e.g., p-type). Each of the fourth source / drain patterns SD4 is an epitaxial pattern including an impurity of a second conductivity type (e.g., n-type).

[0084] In this embodiment, a second gate electrode GE2 is disposed extending in the first direction D1 and intersecting the third channel pattern CH3 and the fourth channel pattern CH4. The second gate electrode GE2 extends from the second PMOSFET region PR2 to the second NMOSFET region NR2. The second gate electrode GE2 is vertically stacked with the third channel pattern CH3 and the fourth channel pattern CH4. A pair of gate spacers GS are disposed on opposite side surfaces of the second gate electrode GE2. A gate cap pattern GP is disposed on the second gate electrode GE2.

[0085] In an embodiment, the second gate electrode GE2 includes a first portion PO1 disposed between the substrate 100 and the first semiconductor pattern SP1, a second portion PO2 disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 disposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 disposed on the third semiconductor pattern SP3.

[0086] Return to reference Figure 2G In this embodiment, the second gate electrode GE2 surrounds the top surface TS, bottom surface BS, and opposite side surface SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. That is, the transistor in the logic cell region LGC according to this embodiment is a three-dimensional field-effect transistor (such as an MBCFET or GAAFET) with the gate electrode three-dimensionally surrounding the channel pattern.

[0087] Return to reference Figure 1 and Figures 2E to 2HIn one embodiment, a second gate insulating layer GI2 is disposed between the second gate electrode GE2 and the third channel pattern CH3, and between the second gate electrode GE2 and the fourth channel pattern CH4. The second gate insulating layer GI2 includes a high-k dielectric layer HK that directly covers the top surface, bottom surface, and opposite side surface of each of the third channel pattern CH3 and the fourth channel pattern CH4. The second gate insulating layer GI2 also includes an insulating layer IL disposed on the high-k dielectric layer HK. The second gate electrode GE2 and the second gate insulating layer GI2 fill the space between vertically adjacent first semiconductor patterns SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3.

[0088] In this embodiment, the internal spacer IP is disposed on the second NMOSFET region NR2. The internal spacer IP is respectively positioned between the first portion PO1, the second portion PO2, and the third portion PO3 of the second gate electrode GE2 and the fourth source / drain pattern SD4. However, the internal spacer IP is omitted from the second PMOSFET region PR2.

[0089] In this embodiment, a first interlayer insulating layer 110 and a second interlayer insulating layer 120 are disposed on a substrate 100. An active contact AC penetrates the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and is electrically connected to a third source / drain pattern SD3 and a fourth source / drain pattern SD4, respectively.

[0090] In this embodiment, a second gate contact GC2 is provided that penetrates the second interlayer insulating layer 120 and the gate cap pattern GP and is electrically connected to the second gate electrode GE2. That is, the dielectric layer DL is omitted from the logic cell region LGC. The second gate contact GC2 is disposed on the device isolation layer ST between the second PMOSFET region PR2 and the second NMOSFET region NR2. When viewed in a plan view, the second gate contact GC2 is a strip pattern extending in the second direction D2. Similar to the active contact AC, the second gate contact GC2 includes a conductive pattern FM and a blocking pattern BM surrounding the conductive pattern FM.

[0091] In this embodiment, a first metal layer M1 and a second metal layer M2 are disposed on the second interlayer insulating layer 120. The active contact AC, the first metal layer M1, and the second metal layer M2 are connected to a reference. Figure 1 as well as Figures 2A to 2D The active contact AC, the first metal layer M1, and the second metal layer M2 described have substantially the same characteristics.

[0092] Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13This is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the inventive concept. Figure 4A , Figure 6A , Figure 8A , Figure 10A , Figure 12A and Figure 14A They are along Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken by line A-A'. Figure 4B , Figure 6B , Figure 8B , Figure 10B , Figure 12B and Figure 14B They are along Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 The sectional view taken by line B-B'. Figure 4C , Figure 8C , Figure 10C , Figure 12C and Figure 14C They are along Figure 3 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken by line C-C'. Figure 4D , Figure 8D , Figure 10D , Figure 12D and Figure 14D They are along Figure 3 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken by line D-D'. Figure 8E , Figure 10E , Figure 12E and Figure 14E They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken from line E-E'. Figure 8F , Figure 10F and Figure 12F They are along Figure 7 , Figure 9 and Figure 11 The sectional view taken by line F-F'.

[0093] Reference Figure 3 as well as Figures 4A to 4DIn this embodiment, a substrate 100 is provided, comprising a peripheral region (PER) and a logic cell region (LGC). A semiconductor layer ACL and a sacrificial layer SAL are formed and alternately stacked on the substrate 100. The semiconductor layer ACL is formed of or comprises one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layer SAL is formed of or comprises another of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the semiconductor layer ACL is formed of or comprises silicon (Si), and the sacrificial layer SAL is formed of or comprises silicon-germanium (SiGe).

[0094] In one embodiment, a first patterning process is performed on the substrate 100 to form a first trench TR1 that separates the first active patterns AP1 to the fourth active patterns AP4. During the first patterning process, the semiconductor layer ACL and the sacrificial layer SAL are patterned. In other words, each of the first active patterns AP1 to the fourth active patterns AP4 includes a semiconductor layer ACL and a sacrificial layer SAL.

[0095] In one embodiment, a second patterning process is performed on the substrate 100 to form a second trench TR2 that separates the first PMOSFET region PR1, the first NMOSFET region NR1, the second PMOSFET region PR2, and the second NMOSFET region NR2. The second trench TR2 is narrower and deeper than the first trench TR1. However, in this embodiment, the second patterning process for forming the second trench TR2 is omitted.

[0096] In this embodiment, a first PMOSFET region PR1 and a first NMOSFET region NR1 are formed in the peripheral region PER. A first active pattern AP1 and a second active pattern AP2 are formed on the first PMOSFET region PR1 and the first NMOSFET region NR1, respectively. A second PMOSFET region PR2 and a second NMOSFET region NR2 are formed in the logic cell region LGC. A third active pattern AP3 and a fourth active pattern AP4 are formed on the second PMOSFET region PR2 and the second NMOSFET region NR2, respectively.

[0097] In one embodiment, a device isolation layer ST is formed on a substrate 100 and fills a first trench TR1 and a second trench TR2. The device isolation layer ST is formed of or includes at least one insulating material such as silicon oxide. The device isolation layer ST is recessed to expose the upper portions of the first active patterns AP1 to the fourth active patterns AP4. For example, the upper portions of the first active patterns AP1 and the second active patterns AP2 protrude vertically above the device isolation layer ST.

[0098] Reference Figure 5 , Figure 6A and Figure 6B In this embodiment, a sacrificial pattern PP is formed on the peripheral region PER and intersects with the first active pattern AP1 and the second active pattern AP2. A sacrificial pattern PP is formed on the logic cell region LGC and intersects with the third active pattern AP3 and the fourth active pattern AP4. Each sacrificial pattern PP has a line or strip shape extending in a first direction D1.

[0099] In detail, in an embodiment, the step of forming the sacrificial pattern PP includes: forming a sacrificial layer on a substrate 100; forming a hard mask pattern MP on the sacrificial layer; and using the hard mask pattern MP as an etch mask to pattern the sacrificial layer. The sacrificial layer is formed of or comprises polysilicon.

[0100] According to embodiments of the inventive concept, the patterning process for forming a sacrificial patterned polypropylene (PP) includes a photolithography process using extreme ultraviolet (EUV) light. In embodiments, the EUV light has a wavelength ranging from 4 nm to 124 nm, and specifically from 4 nm to 20 nm, and can be, for example, ultraviolet light with a wavelength of 13.5 nm. The EUV light has an energy ranging from 6.21 eV to 124 eV, and specifically from 90 eV to 95 eV.

[0101] In an embodiment, the photolithography process using EUV light includes performing an exposure process that irradiates a photoresist layer with EUV light and performing a development process. For example, the photoresist layer is an organic photoresist layer comprising an organic polymer (such as polyhydroxystyrene). The organic photoresist layer also includes a photosensitive compound that can react with EUV light. The organic photoresist layer also contains a material that absorbs EUV, such as an organometallic material, an iodine-containing material, or a fluorine-containing material. In another example, the photoresist layer is an inorganic photoresist layer comprising an inorganic material (such as tin oxide).

[0102] In this embodiment, the photoresist layer is relatively thin. A photoresist pattern is formed by developing the photoresist layer, which has already been exposed to EUV light. When viewed in a planar view, the photoresist pattern can have a linear shape extending in a particular direction, an island shape, a sawtooth shape, a honeycomb shape, or a circular shape, but embodiments of the inventive concept are not limited to these examples.

[0103] In one embodiment, a hard mask pattern MP is formed by patterning at least one mask layer disposed beneath the photoresist pattern using a photoresist pattern as an etch mask. Subsequently, a target layer (i.e., a sacrificial film) is patterned using the hard mask pattern MP as an etch mask to form a desired pattern (i.e., a sacrificial pattern PP) on the wafer.

[0104] In the comparative example, multiple patterning (MPT) techniques using two or more photomasks are required to form fine-pitch patterns on the wafer. In contrast, when performing an EUV lithography process according to an embodiment of the inventive concept, only one photomask is used to form the sacrificial pattern PP with fine pitch.

[0105] For example, when a sacrificial pattern PP is formed using the EUV lithography process according to this embodiment, the minimum spacing between the sacrificial pattern PPs is less than 45 nm. In other words, since the EUV lithography process is performed to form the sacrificial pattern PPs, the sacrificial pattern PPs can be formed precisely and finely without using multiple patterning techniques.

[0106] In this embodiment, EUV lithography is used in the patterning process that forms not only the sacrificial pattern PP but also the first active pattern AP1 to the fourth active pattern AP4 described above. However, the embodiments of the inventive concept are not limited to this example.

[0107] In an embodiment, a pair of gate spacers GS are formed on opposite side surfaces of each sacrificial pattern PP. The step of forming the gate spacers GS includes conformally forming a gate spacer layer on the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer is formed of at least one of SiCN, SiCON, and SiN, or includes at least one of SiCN, SiCON, and SiN. Optionally, in an embodiment, the gate spacer layer is a multilayer structure including at least two of SiCN, SiCON, and SiN.

[0108] Reference Figure 7 and Figures 8A to 8F In this embodiment, first source / drain patterns SD1 to fourth source / drain patterns SD4 are formed on first active patterns AP1 to fourth active patterns AP4, respectively. For example, the first source / drain pattern SD1 is formed in the upper part of the first active pattern AP1. A pair of first source / drain patterns SD1 are formed on both sides of the sacrificial pattern PP. Specifically, the first recessed region RS1 is formed by etching the upper part of the first active pattern AP1 using a hard mask pattern MP and a gate spacer GS as an etching mask. During the etching of the upper part of the first active pattern AP1, the device isolation layer ST between the first active patterns AP1 is partially recessed (e.g., see...). Figure 8C ).

[0109] In this embodiment, a first source / drain pattern SD1 is formed by performing a selective epitaxial growth process using the inner surface of the first recessed region RS1 of the first active pattern AP1 as a seed layer. As a result of forming the first source / drain patterns SD1, a first channel pattern CH1 comprising a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 is formed between each pair of first source / drain patterns SD1. The selective epitaxial growth process includes, for example, chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The first source / drain patterns SD1 comprise a semiconductor material (such as SiGe) having a lattice constant greater than that of the substrate 100. Each first source / drain pattern SD1 is a multilayer structure comprising multiple semiconductor layers.

[0110] For example, in one embodiment, the first source / drain pattern SD1 is in-situ doped during a selective epitaxial growth process. In another embodiment, after the formation of the first source / drain pattern SD1, impurities are implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 is doped to have a first conductivity type, such as p-type.

[0111] In this embodiment, a second source / drain pattern SD2 is formed in the upper part of the second active pattern AP2. A pair of second source / drain patterns SD2 are formed on both sides of the sacrificial pattern PP. As a result of forming the second source / drain patterns SD2, a second channel pattern CH2 including a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 is formed between the pair of second source / drain patterns SD2.

[0112] In detail, in an embodiment, a second recessed region RS2 is formed by etching the upper portion of a second active pattern AP2 using a hard mask pattern MP and a gate spacer GS as an etching mask. Subsequently, a second source / drain pattern SD2 is formed in the second recessed region RS2 by performing a selective epitaxial growth process that uses the inner surface of the second recessed region RS2 as a seed layer. In an embodiment, the second source / drain pattern SD2 is formed of or comprises the same semiconductor material (such as Si) as the substrate 100. The second source / drain pattern SD2 is doped to have a second conductivity type, such as n-type.

[0113] In this embodiment, a third source / drain pattern SD3 is formed in the upper part of the third active pattern AP3, and the process for forming the third source / drain pattern SD3 is substantially the same as the process for forming the first source / drain pattern SD1. In this embodiment, the first source / drain pattern SD1 and the third source / drain pattern SD3 are formed simultaneously. As a result of forming the third source / drain pattern SD3, a third channel pattern CH3, including a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3, is formed between a pair of third source / drain patterns SD3.

[0114] In this embodiment, a fourth source / drain pattern SD4 is formed in the upper part of the fourth active pattern AP4, and the process for forming the fourth source / drain pattern SD4 is substantially the same as the process for forming the second source / drain pattern SD2 described above. In this embodiment, the second source / drain pattern SD2 and the fourth source / drain pattern SD4 are formed simultaneously. As a result of forming the fourth source / drain pattern SD4, a fourth channel pattern CH4, including a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3, is formed between a pair of fourth source / drain patterns SD4.

[0115] Reference Figure 9 as well as Figures 10A to 10F In one embodiment, a first interlayer insulating layer 110 is formed covering the first source / drain patterns SD1 to the fourth source / drain patterns SD4, the hard mask pattern MP, and the gate spacer GS. In another embodiment, the first interlayer insulating layer 110 is formed of or includes silicon oxide.

[0116] In one embodiment, the first interlayer insulating layer 110 is planarized to expose the top surface of the sacrificial pattern PP. The planarization of the first interlayer insulating layer 110 is performed using an etch-back or chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask pattern MP is removed. As a result, the first interlayer insulating layer 110 has a top surface that is substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0117] In this embodiment, the sacrificial pattern PP is selectively removed. Because the sacrificial pattern PP is removed, a first empty space ET1 is formed, exposing the first active patterns AP1 to the fourth active patterns AP4 (e.g., see...). Figure 10C and Figure 10F ).

[0118] In this embodiment, the sacrificial layer SAL, which is disposed on the peripheral region PER and exposed through the first empty space ET1, is selectively removed. For details, refer back to the reference. Figure 10CThe sacrificial layer SAL is selectively removed by an etching process. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 are not removed by this etching process. As a result of removing the sacrificial layer SAL, a second empty space ET2 is formed. The second empty space ET2 is formed between adjacent patterns of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0119] In this embodiment, the sacrificial layer SAL, which is disposed on the logic cell region LGC and exposed through the first empty space ET1, is selectively removed. For details, refer back to the reference. Figure 10F The sacrificial layer SAL is selectively removed by an etching process. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 are not removed by this etching process. As a result of removing the sacrificial layer SAL, a second empty space ET2 is formed. The second empty space ET2 is formed between adjacent patterns of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0120] Return to reference Figure 10B and Figure 10E In this embodiment, an internal spacer IP is formed in the second empty space ET2 on the first NMOSFET region NR1 and the second empty space ET2 on the second NMOSFET region NR2. The internal spacer IP partially fills the second empty space ET2. The internal spacer IP is in contact with the second source / drain pattern SD2 and the fourth source / drain pattern SD4.

[0121] Reference Figure 11 as well as Figures 12A to 12F In this embodiment, a first gate insulating layer GI1 is formed in a first empty space ET1 and a second empty space ET2 on the peripheral region PER. A second gate insulating layer GI2 is formed in the first empty space ET1 and the second empty space ET2 on the logic cell region LGC. Each of the first gate insulating layer GI1 and the second gate insulating layer GI2 surrounds a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3.

[0122] In detail, in this embodiment, an insulating layer IL is formed in the first empty space ET1 and the second empty space ET2. Subsequently, a high-k dielectric layer HK is formed in the first empty space ET1 and the second empty space ET2. The high-k dielectric layer HK is formed conformally. The high-k dielectric layer HK covers the insulating layer IL. The insulating layer IL and the high-k dielectric layer HK located on the peripheral region PER constitute a first gate insulating layer GI1. The insulating layer IL and the high-k dielectric layer HK located on the logic cell region LGC constitute a second gate insulating layer GI2.

[0123] In this embodiment, a first gate electrode GE1 is formed in a first empty space ET1 and a second empty space ET2 on the peripheral region PER. A second gate electrode GE2 is formed in the first empty space ET1 and the second empty space ET2 on the logic cell region LGC. The first gate electrode GE1 includes a first portion PO1, a second portion PO2, and a third portion PO3 filling the second empty space ET2, and a fourth portion PO4 filling the first empty space ET1. The second gate electrode GE2 includes a first portion PO1, a second portion PO2, and a third portion PO3 filling the second empty space ET2, and a fourth portion PO4 filling the first empty space ET1. A gate cap pattern GP is formed on each of the first gate electrode GE1 and the second gate electrode GE2.

[0124] Reference Figure 13 as well as Figures 14A to 14E In one embodiment, a second interlayer insulating layer 120 is formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 is formed of or includes silicon oxide. An active contact AC is formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and to be electrically connected to the first source / drain patterns SD1 to the fourth source / drain patterns SD4. A silicide pattern SC is formed between the active contact AC and each of the first source / drain patterns SD1 to the fourth source / drain patterns SD4.

[0125] In one embodiment, a first mask layer MA1 is formed on the logic cell region LGC. The first mask layer MA1 covers the logic cell region LGC, but exposes the peripheral region PER.

[0126] In this embodiment, a contact hole HO is formed on the peripheral region PER, penetrating the second interlayer insulating layer 120 and the gate cap pattern GP. A dielectric layer DL is formed in the contact hole HO. The dielectric layer DL is formed conformally. The dielectric layer DL extends along the bottom surface and inner surface of the contact hole HO. In this embodiment, the dielectric layer DL is formed using either atomic layer deposition (ALD) or physical vapor deposition (PVD) processes. Subsequently, a first gate contact GC1 is formed to fill the remaining space of the contact hole HO.

[0127] Return to reference Figure 1 as well as Figures 2A to 2H In this embodiment, the first mask layer MA1 is removed, and then a second mask layer is formed on the peripheral region PER. The second mask layer covers the peripheral region PER but exposes the logic cell region LGC.

[0128] In one embodiment, a second gate contact GC2 is formed on the logic cell region LGC and the second gate contact GC2 penetrates the second interlayer insulating layer 120 and the gate cover pattern GP.

[0129] In this embodiment, the second mask layer is removed, and then a third interlayer insulating layer 130 is formed on the second interlayer insulating layer 120. A first metal layer M1 is formed in the third interlayer insulating layer 130. The step of forming the first metal layer M1 includes forming a first interconnect IL1 and a first via VI1. A fourth interlayer insulating layer 140 is formed on the first metal layer M1. A second metal layer M2 is formed in the fourth interlayer insulating layer 140. The step of forming the second metal layer M2 includes forming a second interconnect IL2 and a second via VI2.

[0130] According to an embodiment of the inventive concept, at least one of interconnect lines IL1 and IL2 in the first metal layer M1 and the second metal layer M2 is formed by an EUV lithography process. The EUV lithography process used to form the interconnect line (i.e., the BEOL process) is substantially the same as the EUV lithography process used to form the sacrificial pattern PP. For example, when the first interconnect line IL1 is formed by the EUV lithography process according to this embodiment, the minimum spacing between the first interconnect lines IL1 can be less than 45 nm.

[0131] Figure 15A , Figure 15B and Figure 15C These are respectively the edges of a semiconductor device used to illustrate an embodiment according to the inventive concept. Figure 1 The sectional views are taken along lines A-A', B-B', and C-C'. In the following description, previously referred to... Figure 1 as well as Figures 2A to 2H The described elements may be identified by the same reference numerals without repeating their descriptions.

[0132] Reference Figure 15A , Figure 15B and Figure 15C In this embodiment, a dielectric layer DL is disposed between the bottom surface of the first gate contact GC1 and the top surface of the first gate electrode GE1, and extends in the first direction D1. The dielectric layer DL does not cover the side surface of the first gate contact GC1. The side surface of the first gate contact GC1 is exposed through the dielectric layer DL. That is, the dielectric layer DL does not extend on the side surface of the first gate contact GC1. The side surface of the first gate contact GC1 contacts the second interlayer insulating layer 120, the gate cap pattern GP, ​​and the gate spacer GS.

[0133] Figure 16A , Figure 16B and Figure 16C These are respectively the edges of a semiconductor device used to illustrate an embodiment according to the inventive concept. Figure 1 The sectional views are taken along lines A-A', B-B', and C-C'. In the following description, previously referred to... Figure 1 and Figures 2A to 2HThe described elements may be identified by the same reference numerals without repeating their descriptions.

[0134] Reference Figure 16A , Figure 16B and Figure 16C In one embodiment, a dielectric layer DL is disposed between the bottom surface of the first gate contact GC1 and the top surface of the first gate electrode GE1, and extends in a first direction D1. The dielectric layer DL includes a protrusion PT. The protrusion PT is a portion of the dielectric layer DL that protrudes in a direction perpendicular to the top surface of the substrate 100 (i.e., in a third direction D3). The protrusion PT extends along a portion of the side surface of the first gate contact GC1. The protrusion PT exposes at least a portion of the side surface of the first gate contact GC1. Therefore, the exposed portion of the side surface of the first gate contact GC1 contacts the second interlayer insulating layer 120, the gate cap pattern GP, ​​and the gate spacer GS.

[0135] Figure 17 It is along Figure 1 The cross-sectional view of a semiconductor device according to an embodiment of the inventive concept is shown by line C-C'. In the following description, prior reference is made to... Figure 1 as well as Figures 2A to 2H The described elements may be identified by the same reference numerals without repeating their descriptions.

[0136] Reference Figure 17 In one embodiment, a first dielectric layer DL1 is disposed between a first gate contact GC1 and a first gate electrode GE1. The first dielectric layer DL1 is disposed between the bottom surface of the first gate contact GC1 and the top surface of the first gate electrode GE1, and extends in a first direction D1. The first dielectric layer DL1 has a reference [missing information]. Figure 1 as well as Figures 2A to 2H The dielectric layer DL described has essentially the same characteristics.

[0137] In one embodiment, a second dielectric layer DL2 is disposed between the first via VI1 and the first gate contact GC1. The first gate contact GC1 is spaced apart from the first via VI1 by the second dielectric layer DL2. In one embodiment, the second dielectric layer DL2 covers the bottom and side surfaces of the first via VI1. In another embodiment, the second dielectric layer DL2 does not extend to the side surface of the first via VI1, as shown in the reference. Figure 15A , Figure 15B and Figure 15C As described. Alternatively, in another embodiment, the second dielectric layer DL2 includes a reference. Figure 16A , Figure 16B and Figure 16C The highlighted part of the description is PT.

[0138] In an embodiment, the second dielectric layer DL2 is formed of or comprises a high-k dielectric material whose dielectric constant is higher than that of silicon oxide. For example, the second dielectric layer DL2 is formed of or comprises the same material as the first dielectric layer DL1.

[0139] In this embodiment, since the second dielectric layer DL2 is disposed between the first via VI1 and the first gate contact GC1, the voltage applied between the first gate electrode GE1 and the substrate 100 can be reduced. Therefore, reliability issues in high-power transistors formed on the peripheral region PER can be prevented. As a result, the electrical and reliability characteristics of the semiconductor device can be improved.

[0140] Figure 18 This is a plan view of a semiconductor device according to an embodiment of the inventive concept. Figure 19 It is along Figure 18 A sectional view taken along line A-A'. In the following description, previously referred to... Figure 1 as well as Figures 2A to 2H The described elements may be identified by the same reference numerals without repeating their descriptions.

[0141] Reference Figure 18 and Figure 19 In this embodiment, the first gate contact GC1 extends from the first PMOSFET region PR1 to the first NMOSFET region NR1. The first gate contact GC1 intersects with the device isolation layer ST between the first active pattern AP1 and the second active pattern AP2. The dielectric layer DL also extends from the first PMOSFET region PR1 to the first NMOSFET region NR1.

[0142] In one embodiment, the widths of the first gate contact GC1 and the dielectric layer DL can be adjusted to reduce or maintain the voltage applied to the transistor.

[0143] Figure 20 This is a plan view of a semiconductor device according to an embodiment of the inventive concept. Figure 21 It is along Figure 20 A sectional view taken along line A-A'. In the following description, previously referred to... Figure 1 and Figures 2A to 2H The described elements may be identified by the same reference numerals without repeating their descriptions.

[0144] Reference Figure 20 and Figure 21In one embodiment, a first gate contact GC1 is disposed on a device isolation layer ST between a first active pattern AP1 and a second active pattern AP2. The first gate contact GC1 is horizontally offset from the first channel pattern CH1 and the second channel pattern CH2 in a first direction D1. This results in a third width W3 (e.g., see...). Figure 2C The fourth width W4 is the width of the channel patterns CH1 and / or CH2 in the first direction D1. The fourth width W4 is the width of the first gate contact GC1 in the first direction D1. In an embodiment, the fourth width W4 is greater than the third width W3.

[0145] According to embodiments of the inventive concept, a semiconductor device includes a dielectric layer disposed on a peripheral region and positioned between a gate electrode and a gate contact. Therefore, for three-dimensional field-effect transistors, while increasing the thickness of the gate insulating layer may be difficult, the voltage applied between the gate electrode and the substrate can be reduced. As a result, the electrical characteristics and reliability of the semiconductor device can be improved.

[0146] Although embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: The base, including the surrounding area; The first active pattern is set in the outer area; The first source / drain pattern is set on the first active pattern; A first channel pattern is formed on a first active pattern and connected to a first source / drain pattern, wherein the first channel pattern comprises semiconductor patterns stacked and spaced apart from each other. A first gate electrode extends in a first direction and intersects with a first channel pattern; A gate insulating layer is disposed between the first gate electrode and the first channel pattern; A first gate contact is disposed on a first gate electrode and extends in a first direction; and A first dielectric layer is disposed between the first gate electrode and the first gate contact. The first dielectric layer is disposed between the bottom surface of the first gate contact and the top surface of the first gate electrode, such that the first gate contact is spaced apart from the first gate electrode by the first dielectric layer, and the first dielectric layer extends in a first direction.

2. The semiconductor device according to claim 1, wherein, The maximum width of the first dielectric layer in the second direction intersecting the first direction is greater than the minimum width of the first gate electrode in the second direction.

3. The semiconductor device according to claim 1, wherein, The first dielectric layer covers the bottom and side surfaces of the first gate contact.

4. The semiconductor device according to claim 1, wherein, The first dielectric layer includes a protruding portion protruding in a direction perpendicular to the top surface of the substrate, and The protruding portion extends along a portion of the side surface of the first gate contact.

5. The semiconductor device according to claim 1, further comprising: A first metal layer is disposed on a first gate electrode, wherein the first metal layer includes interconnects and vias between the interconnects and the first gate contact; and The second dielectric layer is placed between the first gate contact and the via.

6. The semiconductor device according to claim 1, wherein, The width of the first gate contact in the first direction is greater than the width of the first channel pattern in the first direction.

7. The semiconductor device according to claim 1, further comprising: The second active pattern is disposed on the peripheral area and spaced apart from the first active pattern in the first direction; The second source / drain pattern is set on the second active pattern; as well as The second channel pattern is formed on the second active pattern and connected to the second source / drain pattern. The second channel pattern comprises semiconductor patterns that are stacked and spaced apart from each other. The first gate electrode extends across the second channel pattern.

8. The semiconductor device according to claim 7, wherein, The first gate contact extends across the first channel pattern and the second channel pattern.

9. The semiconductor device of claim 7, further comprising a device isolation layer separating the first active pattern and the second active pattern. in, The first gate contact is disposed on the device isolation layer between the first active pattern and the second active pattern.

10. The semiconductor device according to claim 1, wherein, The substrate also includes a logic cell region, and The semiconductor device further includes: The third and fourth active patterns are disposed on the logic cell region and spaced apart from each other in the first direction; The third source / drain pattern and the fourth source / drain pattern are respectively set on the third active pattern and the fourth active pattern; A third channel pattern and a fourth channel pattern are formed on the third active pattern and the fourth active pattern, respectively, and are connected to the third source / drain pattern and the fourth source / drain pattern, respectively. Each of the third channel pattern and the fourth channel pattern includes semiconductor patterns that are stacked and spaced apart from each other. The second gate electrode extends in a first direction and intersects the third and fourth channel patterns; and The second gate contact is electrically connected to the second gate electrode.

11. A semiconductor device, the semiconductor device comprising: The base includes the peripheral region and the logical unit region; The first active pattern and the second active pattern are respectively set on the peripheral area and the logic unit area; The first source / drain pattern and the second source / drain pattern are respectively disposed on the first active pattern and the second active pattern; A first channel pattern and a second channel pattern are formed on a first active pattern and a second active pattern, respectively, and are respectively connected to a first source / drain pattern and a second source / drain pattern, wherein each of the first channel pattern and the second channel pattern includes semiconductor patterns stacked on top of each other and spaced apart. The first gate electrode and the second gate electrode extend in a first direction and intersect the first channel pattern and the second channel pattern, respectively; A first gate contact is disposed on a first gate electrode; The second gate contact is electrically connected to the second gate electrode; and A dielectric layer is located between the first gate contact and the first gate electrode. The dielectric layer is disposed between the bottom surface of the first gate contact and the top surface of the first gate electrode, such that the first gate contact is separated from the first gate electrode by the dielectric layer. Wherein, the width of the first gate contact in the first direction is greater than the width of the first channel pattern in the first direction.

12. The semiconductor device according to claim 11, in, The first gate contact extends in the first direction, and The dielectric layer extends in the first direction.

13. The semiconductor device according to claim 11, wherein, The dielectric layer covers the bottom and side surfaces of the first gate contact.

14. The semiconductor device according to claim 11, wherein, The first channel pattern is vertically stacked with the first gate contact.

15. The semiconductor device of claim 11, further comprising: The third active pattern is disposed on the peripheral area and spaced apart from the first active pattern in the first direction; The third source / drain pattern is set on the third active pattern; as well as The third channel pattern is formed on the third active pattern and connected to the third source / drain pattern. The first gate electrode extends across the third channel pattern, and The first gate contact extends across the first channel pattern and the third channel pattern.

16. A semiconductor device, the semiconductor device comprising: The base includes the peripheral region and the logical unit region; The first active pattern and the second active pattern are disposed on the outer region, spaced apart from each other in a first direction, and extend in a second direction that intersects the first direction; A device isolation layer is disposed on the substrate, and the device isolation layer separates the first active pattern and the second active pattern; The first source / drain pattern and the second source / drain pattern are respectively disposed on the first active pattern and the second active pattern; A first channel pattern and a second channel pattern are formed on a first active pattern and a second active pattern, respectively, and are respectively connected to a first source / drain pattern and a second source / drain pattern. Each of the first channel pattern and the second channel pattern includes semiconductor patterns stacked and spaced apart from each other. The semiconductor patterns include a first semiconductor pattern at the lowest level, a second semiconductor pattern on the first semiconductor pattern, and a third semiconductor pattern on the second semiconductor pattern. A first gate electrode extends in a first direction and intersects a first channel pattern and a second channel pattern. The first gate electrode includes a first portion between a substrate and a first semiconductor pattern, a second portion between the first semiconductor pattern and a second semiconductor pattern, a third portion between the second semiconductor pattern and a third semiconductor pattern, and a fourth portion on the third semiconductor pattern. A first gate insulating layer is disposed between the first gate electrode and the first channel pattern and between the first gate electrode and the second channel pattern. The first gate insulating layer includes a high-k dielectric layer and an insulating layer on the high-k dielectric layer. A pair of gate spacers are respectively disposed on both sides of the first gate electrode; A gate cover pattern is disposed on the first gate electrode; The first interlayer insulating layer is disposed on the gate cover pattern; An active contact that penetrates the first interlayer insulation layer and is electrically connected to at least one of the first source / drain pattern and the second source / drain pattern; A first gate contact is disposed on a first gate electrode, wherein the first gate contact penetrates the first interlayer insulating layer and the gate cover pattern; A first dielectric layer is disposed between the first gate contact and the first gate electrode; A second interlayer insulation layer is disposed on the first interlayer insulation layer; and A first metal layer is formed in the second interlayer insulating layer and on the first gate contact, wherein the first metal layer is electrically connected to the active contact. Wherein, the first gate contact extends in the first direction, and The first dielectric layer is disposed between the bottom surface of the first gate contact and the top surface of the first gate electrode, such that the first gate contact is spaced apart from the first gate electrode by the first dielectric layer, and the first dielectric layer extends in a first direction.

17. The semiconductor device according to claim 16, wherein, The maximum width of the first dielectric layer in the second direction intersecting the first direction is greater than the minimum width of the first gate electrode in the second direction.

18. The semiconductor device according to claim 16, wherein, The width of the first gate contact in the first direction is greater than the width of the first channel pattern in the first direction.

19. The semiconductor device according to claim 16, wherein, The first dielectric layer covers the bottom and side surfaces of the first gate contact.

20. The semiconductor device of claim 16, further comprising: The third active pattern and the fourth active pattern are disposed on the logic cell region, wherein the third active pattern and the fourth active pattern are spaced apart from each other in a first direction, extend in a second direction intersecting the first direction, and are separated by a device isolation layer. The third source / drain pattern and the fourth source / drain pattern are respectively set on the third active pattern and the fourth active pattern; The third channel pattern and the fourth channel pattern are formed on the third active pattern and the fourth active pattern, respectively, and are connected to the third source / drain pattern and the fourth source / drain pattern, respectively, wherein each of the third channel pattern and the fourth channel pattern includes semiconductor patterns stacked on top of each other and spaced apart. The second gate electrode extends in the first direction and intersects with the third and fourth channel patterns; A second gate insulating layer is disposed between the second gate electrode and the third channel pattern and between the second gate electrode and the fourth channel pattern; and The second gate contact penetrates the first interlayer insulating layer and the gate cap pattern, and is electrically connected to the second gate electrode.

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