Nanometer-structured fet semiconductor devices and methods of forming the same

Abstract

The present disclosure relates to nanostructured FET semiconductor devices and methods of forming the same. Embodiments include nanostructured devices and methods of forming nanostructured devices including a processing step that extends sidewall spacer material after deposition to close seams in the sidewall spacer material. The processing step includes an oxidation anneal and a thermal anneal to extend the sidewall spacer material and crosslink open seams to form closed seams, reduce k-value, and reduce density.

Description

Technical Field

[0001] This disclosure generally relates to nanostructured FET semiconductor devices and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a first nanostructure; a second nanostructure on the first nanostructure; a source / drain region adjacent to the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; and a first internal spacer inserted between the first nanostructure and the second nanostructure, the first internal spacer being inserted between the gate structure and the source / drain region, the first internal spacer being oxidized on a first side, and the first side of the first internal spacer being in contact with the source / drain region.

[0005] According to another embodiment of this disclosure, a transistor is provided, comprising: a first nanostructure on a semiconductor substrate, the first nanostructure including a first end; a second nanostructure on the first nanostructure, the second nanostructure including a second end; a spacer inserted between the first end and the second end; a gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric having an interface with a first side of the spacer; and a source / drain region adjacent to the first end and the second end, the source / drain region having an interface with a second side of the spacer, the second side of the spacer being opposite to the first side, wherein the first side of the spacer has a first recessed profile, wherein the second side of the spacer has a second recessed profile, wherein the second recessed profile is less recessed than the first recessed profile.

[0006] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: etching a first recess adjacent to a first nanostructure and a second nanostructure, the first nanostructure being located on top of the second nanostructure; etching a sidewall of the first nanostructure through the first recess to form a sidewall recess of the first nanostructure; forming a first sidewall spacer in the sidewall recess, the first sidewall spacer having a horizontal seam between an upper portion and a lower portion; performing an oxidation annealing, the oxidation annealing injecting oxygen into the horizontal seam; and performing a dry annealing, the dry annealing causing crosslinking between the upper portion and the lower portion, the size of the horizontal seam being reduced by the crosslinking. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nano-FET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A, Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 24C , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B and Figure 26C This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0010] Figure 27A , Figure 27B and Figure 27C This is a cross-sectional view of a nanostructured FET according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0013] The embodiments are described below in the specific context of dies including nanostructured FETs. However, various embodiments can be applied to dies including alternatives to or in combination with nanostructured FETs (e.g., fin field-effect transistors (FinFETs), planar transistors, etc.).

[0014] Embodiments of this disclosure advantageously perform a process on the sidewall spacers of a nanostructured FET to reduce or eliminate seams that may form in the spacers and to reduce or eliminate dishing of the sidewall spacers. In the formation of a nanostructured FET, sidewall spacers can be used between the source / drain epitaxial regions and the gate structure. After forming recesses for the source / drain epitaxial regions, the nanostructure is laterally etched to create sidewall recesses in the nanostructure. This etching may produce recesses in the sidewall recesses of the nanostructure. Spacers are then deposited in the sidewall recesses. In some cases, seams may appear between the top and bottom of the spacers during spacer deposition due to the dishing of the sidewall recesses. Embodiments advantageously process the spacers to reduce or eliminate seams and to reduce or eliminate dishing of the sidewall spacers. As a result, the C-value of the transistor is improved. eff Furthermore, it improved AC performance.

[0015] Figure 1 An example of a nanostructured FET (e.g., nanowire FET, nanosheet FET (NSFET), etc.) according to some embodiments is shown in a three-dimensional view. The nanostructured FET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) on fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as the channel region of the nanostructured FET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, which may protrude above the isolation regions 68 between adjacent isolation regions 68. Although the isolation regions 68 are shown / described as being separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fin 66 is shown as being a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0016] A gate dielectric layer 100 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0017] Figure 1The reference cross sections used in the following figures are further illustrated. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to, for example, the direction of current flow between the epitaxial source / drain regions 92 of the nanostructure FET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fin 66 of the nanostructure FET, and in, for example, the direction of current flow between the epitaxial source / drain regions 92 of the nanostructure FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nanostructure FET. For clarity, the following figures refer to these reference cross sections.

[0018] Some embodiments discussed herein are discussed in the context of nanostructured FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices (e.g., planar FETs) or in FinFETs.

[0019] Figures 2 to 26C This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A and Figure 27A It shows Figure 1 The reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 10C , Figure 11B , Figure 11C , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 15 , Figure 16 , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B and Figure 27B It shows Figure 1 The reference section B-B' is shown. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 17A , Figure 18A , Figure 18C , Figure 19C , Figure 24C , Figure 25C , Figure 26C and Figure 27C It shows Figure 1 The reference section C-C' is shown. Figure 27A , Figure 27B and Figure 27C This is a cross-sectional view of a nanostructured FET according to some embodiments.

[0020] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0021] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type nanostructure FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0022] Further in Figure 2In this process, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nanostructured FET in a p-type region 50P. Alternatively, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of a nanostructured FET in an n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanostructured FET in an n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanostructured FET in a p-type region 50P.

[0023] In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form the channel region of the nanostructured FET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form the channel region of the nanostructured FET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously. Figure 27A , Figure 27B and Figure 27C The structure resulting from such an embodiment is shown, wherein, for example, the channel regions in both the p-type region 50P and the n-type region 50N comprise silicon.

[0024] For illustrative purposes, the multilayer stack 64 is shown as comprising three layers each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanostructure FETs, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanostructure FETs, such as silicon, silicon carbon, etc. For illustrative purposes, the multilayer stack 64 is shown as having a bottom semiconductor layer suitable for p-type nanostructure FETs. In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for n-type nanostructure FETs.

[0025] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity relative to each other. Thus, in the n-type region 50N, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanostructure FET. Similarly, in the p-type region 50P, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanostructure FET.

[0026] Now for reference Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51 and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55.

[0027] The fin 66 and nanostructure 55 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fin 66 and nanostructure 55, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0028] For illustrative purposes, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be larger or thinner than the width of the fin 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is shown to always have a consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal.

[0029] exist Figure 4 In the nanostructure 55, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fin 66, and nanostructure 55. A filler material, such as that described above, can then be formed on the liner.

[0030] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof may be employed. This planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the top surface of the nanostructure 55 and the insulating material are flush.

[0031] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type regions 50N and p-type regions 50P protrude between adjacent STI regions 68. Furthermore, the top surface of the STI regions 68 can have a flat surface (as shown), a convex surface, a concave surface (e.g., recessed), or a combination thereof. The top surface of the STI regions 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI regions 68 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 66 and nanostructures 55). For example, it can be removed using an oxide employing, for example, diluted hydrofluoric acid (dHF).

[0032] The above about Figures 2 to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include alternating semiconductor materials as described above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and / or subsequent implantation, but in-situ doping and implantation doping may be used together.

[0033] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N, or may be formed in a different order.

[0034] Further in Figure 4In this process, suitable wells (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, different implantation steps for n-type regions 50N and p-type regions 50P can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0035] After or before implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist can be removed, for example, by an acceptable ashing process.

[0036] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0037] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material, and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0038] Figures 6A to 18C Various additional steps in manufacturing the embodiment device are shown. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13A , Figure 13C , Figure 14A , Figure 15 and Figure 18C The characteristics of either the n-type region 50N or the p-type region 50P are shown. Figure 6A and Figure 6B In this process, acceptable photolithography and etching techniques can be used to pattern the mask layer 74 (see [link]). Figure 5A mask 78 is formed. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to separate each dummy gate 76 from the adjacent dummy gate 76 entities. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66.

[0039] exist Figure 7A and Figure 7B In, respectively in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and on the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation, or deposited by CVD, ALD, etc. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0040] Implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed after the formation of the first spacer layer 80 and before the formation of the second spacer layer 82. In embodiments with different device types, similar to the above... Figure 4 The implantation discussed earlier can involve forming a mask, such as a photoresist, on the n-type region 50N while exposing the p-type region 50P. An impurity of an appropriate type (e.g., p-type) can then be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm3 The impurity concentration is within a certain range. Annealing can be used to repair injection damage and reactivate the injected impurities.

[0041] exist Figure 8A and Figure 8B In this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used for self-alignment of the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can be used as an etch stop layer when patterning the second spacer layer 82, and such that the second spacer layer 82 can be used as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 serves as an etch stop layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, as shown below. Figure 8A As shown. Subsequently, the second spacer 83 serves as a mask during the etching of the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as... Figure 8A As shown.

[0042] like Figure 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0043] Note that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0044] exist Figure 9A and Figure 9B In some embodiments, a first recess 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54, and into the substrate 50. Figure 9A As shown, the top surface of the STI region 68 may be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; and so on. The first recess 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using anisotropic etching processes such as RIE, NBE, etc. The first spacer 81, the second spacer 83, and the mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50 during the etching process for forming the first recess 86. Each layer of the nanostructure 55 and / or the fin 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first recess 86 after it has reached a desired depth.

[0045] exist Figure 10A , Figure 10B and Figure 10C In the process, the portion of the sidewall of the layer of nanostructure 55 formed of a first semiconductor material (e.g., first nanostructure 52) exposed by the first recess 86 is etched to form a sidewall recess 88 in the n-type region 50N, and the portion of the sidewall of the layer of nanostructure 55 formed of a second semiconductor material (e.g., second nanostructure 54) exposed by the first recess 86 is etched to form a sidewall recess 88 in the p-type region 50P. Although in Figure 10B The sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight, but these sidewalls can be convex or concave, such as Figure 10CAs shown. Isotropic etching processes, such as wet etching, can be used to etch the sidewalls. A mask (not shown) can be used to protect the p-type region 50P while an etchant selective for the first semiconductor material is used to etch the first nanostructure 52, such that in the n-type region 50N, the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52. Similarly, a mask (not shown) can be used to protect the n-type region 50N while an etchant selective for the second semiconductor material is used to etch the second nanostructure 54, such that in the p-type region 50P, the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54. In embodiments in which the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 in the n-type region 50N can be etched using a dry etching process employing tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., and the sidewalls of the second nanostructure 54 in the p-type region 50P can be etched using a wet or dry etching process employing hydrogen fluoride, another fluorine-based etchant, etc.

[0046] Figure 10C The following are illustrations based on some embodiments. Figure 10BEnlarged views of the regions marked F10CN and F10CP. Both the first nanostructure 52 and the second nanostructure 54 are etched in the process of forming the sidewall recess 88, but in the n-type region 50N, the first nanostructure 52 is etched more aggressively than the second nanostructure 54 to form the sidewall recess 88. The p-type region 50P has a similar result, except that the second nanostructure 54 is etched more aggressively than the first nanostructure 52, thus forming the sidewall recess 88 in the p-type region 50P. The width 54w of the second nanostructure 54 and the width 52w of the first nanostructure can be between about 5 nm and 30 nm. In the n-type region 50N, the lateral recess 88r is measured according to the lateral extent of the width 54w of the second nanostructure 54. In the p-type region 50P, the lateral recess 88r is measured according to the lateral extent of the width 52w of the first nanostructure 52. In some embodiments, the lateral recess 88r can be between 1 nm and about 15 nm, or between 5% and 35% of the width 54w. Etching may also cause concavity or depression in the sidewall recess 88. The extent of the depression can be characterized by a depression value 88d, which is the distance between the lateral extent of the first nanostructure 52 in the n-type region 50N (or the second nanostructure 54 in the p-type region 50P) and the deepest point of the sidewall recess 88. In some embodiments, the depression value 88d of the sidewall recess 88 can be between 0.5 nm and about 15 nm, or between about 10% and 50% of the lateral recess 88r. Note that the depression value 88d corresponds to the reverse depression value of a spacer that is subsequently formed sharing the same interface. The maximum height 88h of the sidewall recess 88 can be between 1 nm and 10 nm, for example, between 2 nm and 8 nm, or between 0% and 20% greater than the thickness of one of the first nanostructures 52 in the n-type region 50N (or the second nanostructure 54 in the p-type region 50P). After the first recess 86 and the sidewall recess 88 are formed, the aspect ratio of the first recess 86 can be as high as about 30:1, that is, its depth can be as high as about 30 times its width, but a larger aspect ratio is also possible and anticipated.

[0047] exist Figure 11A , Figure 11B and Figure 11C In the middle, an internal spacer layer 90s is formed in the sidewall recess 88. The internal spacer layer 90s can be formed by depositing the internal spacer layer 90s in... Figure 10A , Figure 10B and Figure 10CThe structure shown is formed on top of this. In a subsequent step, the internal spacer layer 90s will be etched to form the first internal spacer 90. The resulting first internal spacer 90 will serve as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by the corresponding gate structures.

[0048] The internal spacer layer 90s can be deposited using a conformal deposition process such as CVD or ALD. The conformity of this deposition can be between approximately 50% and 99%. The internal spacer layer 90s can comprise materials such as silicon nitride, silicon carbonitride, or silicon oxynitride, but any suitable material can be used. In some embodiments, the internal spacer layer 90s is a low-k spacer layer, which can use materials such as SiH x Cl y R z (R=CH3,NCH3), SiH x Cl y SiH x (R1) y Cl x (R2) z (R1=CH, R2=NCH3), C x H y N x / O y / H z Precursors such as these are deposited and deposited at temperatures between approximately 200°C and approximately 600°C.

[0049] During deposition, the inner spacer layer 90s may include the following elemental composition: C with a molecular weight of 5-15%, N with a molecular weight of 10-30%, O with a molecular weight of 10-55%, and Si with a molecular weight of 30-45%. The inner spacer layer 90s may be a low-k film with a k-value of approximately 3.0 to 6.0. Depending on the composition, the density may be approximately 1 to 3 g / cm³. 3 The values ​​vary between these values. For example, in some embodiments, such as when the material is silicon oxycarbonate, the internal spacer layer 90s may have a k value between about 4.9 and 5.4 during deposition, and may have a g / cm³ content between 2.5 and 2.7 g / cm³. 3 The density between.

[0050] exist Figure 11C In some embodiments, it is shown that Figure 11B An enlarged view of the area labeled F11CN is shown, and it also illustrates... Figure 11B A magnified view of the area marked F11CP. Figure 11CA detailed view of the internal spacer layer 90s after the deposition process is shown.

[0051] like Figure 11C As shown, in some embodiments, the deposition process of the first internal spacer 90 results in the formation of a transverse or horizontal seam 89 or a beak-shaped opening between the upper portion 90u of the internal spacer layer 90s and the lower portion 90l of the internal spacer layer 90s, and has a seam end corresponding to the side portion 90i of the internal spacer layer 90s. The upper portion 90u of the internal spacer layer 90s is produced by conformally depositing the material of the internal spacer layer 90s on the bottom of the exposed second nanostructure 54. The lower portion 90l of the internal spacer layer 90s is produced by conformally depositing the material of the internal spacer layer 90s on the top of the exposed second nanostructure 54. And the side portion 90i of the internal spacer layer 90s is produced by conformally depositing the material of the internal spacer layer 90s on the first nanostructure 52 in the sidewall recess 88. The height 90h of the internal spacer layer 90s between the second nanostructures 54 in the n-type region 50N and between the first nanostructures in the p-type region 50P corresponds to Figure 10C The height is 88h. For example... Figure 11C As shown, the lateral seam 89 has a bird's beak-shaped opening. The lateral thickness 90lt1 of the inner spacer layer 90s can be between 2nm and 30nm, and the pre-processing recess 90d1 can be between 25% and 75% of the lateral thickness 90lt1, for example, between about 1nm and 23nm. Extreme recesses and lateral seams 89 will reduce the effectiveness of the first inner spacer 90, resulting in poor transistor performance during formation. eff Performance degradation. Since the source / drain regions can penetrate into the lateral seam 89 during formation, this performance degradation will reduce the effectiveness of the first internal spacer 90. In some cases, the lateral seam 89 may also cause a short circuit between the subsequently formed source / drain regions and the subsequently formed metal gate.

[0052] In some embodiments, it is possible to Figure 11A , Figure 11B and Figure 11C The illustrated structure undergoes a processing step to reduce the recess and the transverse seam 89. In other embodiments, the internal spacer layer 90s may be etched first to form the first internal spacer 90, followed by this processing step to reduce the recess and the transverse seam 89. In embodiments where the internal spacer layer 90s is not etched before this processing step, Figure 12A , Figure 12B and Figure 12C The etching process shown can be performed after this processing step.

[0053] Figure 12A , Figure 12B and Figure 12C An anisotropic etching process is illustrated for removing portions of the internal spacer layer 90s to form the first internal spacer 90. In some embodiments, such as Figure 12B As shown, the outer wall of the first internal spacer 90 can be recessed from the sidewall of the second nanostructure 54 and / or the first nanostructure 52, respectively (depending on whether it is in the p-type region 50P or the n-type region 50N). The resulting first internal spacer 90 can form a beak-shaped opening in which conformal deposition is performed following the contour of the sidewall recess 88.

[0054] The internal spacer layer 90s can be etched using an anisotropic etching process such as RIE, NBE, etc. The first internal spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes for forming the gate structure) from affecting the subsequently formed source / drain regions (e.g., epitaxial source / drain regions 92, hereinafter referred to as...). Figures 18A-18C (To be discussed) damage.

[0055] exist Figure 12C In some embodiments, it is shown that Figure 12B An enlarged view of the area labeled F12CN is shown, and it also illustrates... Figure 12B A magnified view of the area marked F12CP. Figure 12C A detailed view of the first internal spacer 90 after the etching process is shown.

[0056] like Figure 12C As shown, in some embodiments, after etching the inner spacer layer 90s to form the first inner spacer 90, a horizontal seam 89 or a beak-shaped opening is formed between the upper portion 90u of the first inner spacer 90 and the lower portion 90l retained in each first inner spacer 90. The total lateral thickness 90lt2 of the first inner spacer 90 is between 1 and 15 nm, and the pre-processed recess 90d2 can be between 25% and 75% of the lateral thickness 90lt2, for example, between about 1 nm and 12 nm. The height 90h of the first inner spacer 90 between the second nanostructures 54 in the n-type region 50N and between the first nanostructures in the p-type region 50P corresponds to Figure 10C The altitude is 88h.

[0057] Figures 13A-13D The processing technique is shown for closing the transverse seam 89, thereby closing the beak-shaped opening and reducing the recess associated with the inner spacer layer 90s or the first inner spacer 90 (depending on whether the first inner spacer 90 has been formed by the inner spacer layer 90s). Figures 13A-13D The process shown can be used for Figure 11A , Figure 11B and Figure 11C The structure shown is executed (i.e., before the formation of the first internal spacer 90), or may be... Figure 12A , Figure 12B and Figure 12C The structure shown is executed (i.e., after etching to form the first internal spacer 90). For simplicity, refer to... Figures 13A to 13D Reference will be made only to the first internal spacer 90, but it should be understood that... Figures 13A to 13D The described process also applies to the internal spacer layer 90s embodiment. Figure 13A It shows Figure 11C The box marked F13A, or Figure 12C A magnified view of the box labeled F13A, depending on whether the above regarding... Figure 12A , Figure 12B and Figure 12C The etching described. Figure 13A Also includes for Figures 13A-13D The key content. In Figure 13A In the process prior to the seam closure process, after anisotropically etching the first internal spacer 90, various compounds including amine, hydroxyl, and methyl groups can be observed on the surface of the first internal spacer 90. These compounds may be artifacts of the deposition process used to form the first internal spacer 90 or of subsequent etching processes used to remove excess material from the formation of the first internal spacer 90 in the first recess 86. These compounds may include Si-OH, Si-CH3, and Si-NH2.

[0058] Brief reference Figure 14A and Figure 14B This shows the inner spacer layer 90s or the first inner spacer 90. In Figure 14A One configuration of these compounds is shown in the figure, and in Figure 14B Another configuration of these compounds is shown. Some embodiments may include only... Figure 14A The configuration in some embodiments may only include Figure 14B The configuration in the text, and some embodiments may include the formation of these two compounds. For example... Figure 14A and Figure 14B As shown, silicon at the surface of the internal spacer layer 90s or the first internal spacer 90 can be bonded to complexes including Si, C, and O, as well as functional groups including CH3, NH2, or OH functional groups via hydrogen bonds through hydrogen atoms.

[0059] return Figure 13BOxidative annealing is performed. This oxidative annealing provides severe oxidation of the first internal spacer 90 at a temperature between about 200°C and about 600°C, a duration between about 0.1 hours and 12 hours, and a pressure between about 0.5 atm and 5 atm. The atmosphere may use vapor H2O (vapor / wet annealing), CO2, O*-related oxidizing agents (e.g., O2 and O3), another oxidizing agent, or a combination thereof. This oxidative annealing removes residual amine groups by converting amine groups to hydroxyl groups (Si-NH2→Si-OH). This oxidative annealing also provides oxygen to the transverse joint 89, thereby causing expansion of the first internal spacer 90 and reduction of the transverse joint 89.

[0060] exist Figure 13C During oxidation annealing, as the oxygen percentage increases and the nitrogen percentage decreases, the first internal spacer 90 expands and the transverse seam 89 decreases, making the first internal spacer 90 less dense and larger in volume. As the transverse seam 89 shrinks, the hydroxyl groups on the upper portion 90u and the lower portion 90l of the first internal spacer 90 can combine to form Si-O-Si bonds (2Si-OH → Si-O-Si + H2O). After oxidation annealing, the treatment chamber is degassed.

[0061] exist Figure 13D Dry annealing is performed. This dry annealing can be performed at a higher temperature than oxidative annealing (e.g., between about 500°C and about 800°C), a pressure of about 0.01 atm to about 2 atm, and a duration of about 0.1 hours to 6 hours. This dry annealing can be performed in an environment containing H2, NH3, N2, Ar, (one or more) other inert gases, and combinations thereof. This dry annealing will cause another expansion of the first internal spacer 90, compressing the transverse joint 89 to close. Simultaneously, when the transverse joint 89 closes, the dry annealing causes the hydroxyl groups at the upper portion 90u of the first internal spacer 90 to crosslink with the hydroxyl groups at the lower portion 90l of the first internal spacer 90, forming Si-O-Si bonds and reducing polarization (2Si-OH → Si-O-Si + H2O). This dry annealing will also remove moisture byproducts (H2O) from the crosslinking process, as well as moisture byproducts that may be present in oxidative annealing (e.g., if steam is used in oxidative annealing).

[0062] Repeat as needed Figures 13A-13DThe process is used to achieve joint closure and crosslinking of the upper part 90u and the lower part 90l of the first internal spacer 90. It should be noted that even if the joint is closed by this process to form a closed joint 91, inspection of the first internal spacer 90 may reveal that a joint was previously present, for example, by observing small gaps in the closed joint 91 or by observing the products of the joint closure process, such as residues of Si-CH3, Si-OH, Si-NH2, etc.

[0063] exist Figure 15 In some embodiments, it is shown that in the already executed Figures 13A-13D After the de-seaming process Figure 11B Enlarged view of the regions marked F11CN and F11CP. Figure 13D and Figure 15 The magnified portion of the region marked F13D is consistent. Figure 15 A detailed view of the inner spacer layer 90s in the n-type region 50N and p-type region 50P after the seam removal process is shown.

[0064] Figure 15 The diagram shows that the depression 90d3 of the internal spacer layer 90s after the seam removal process is smaller than the depression 90d1 of the internal spacer layer 90s before the seam removal process. In some embodiments, the depression 90d3 can be between 10% and 50% of the depression 90d1, for example, between 0 nm and 5 nm. In some embodiments, the depression of the internal spacer layer 90s is completely removed (or will be completely removed during the formation of the first internal spacer 90). The seam removal process can also reduce the k-value of the material of the internal spacer layer 90s to a value less than the nominal k-value of the deposited material. For example, the k-value of the deposited silicon carbonitride can be between 4.9 and 5.4, while the k-value of the seam-removed internal spacer layer 90s after seam removal can be between 4.5 and 5.1, which means a reduction of about 5% to 10%. The decrease in the k-value is due to the oxidation of the inner spacer layer 90s during heavy oxidation annealing, particularly due to the decrease in the nitrogen percentage (and increase in oxygen) and the decrease in the density of the inner spacer layer 90s. Furthermore, the size of the inner spacer layer 90s can increase by about 5% to about 20%, and the density of the inner spacer layer 90s can decrease by about 5% to 15%. For example, the density of the deposited silicon carbonitride can be from 2.5 to 2.7 g / cm³. 3 Between. After the seam removal process, the density of silicon dioxide can be reduced to approximately 2.2 to 2.4 g / cm³. 3 Between. The resulting transverse thickness of the internal spacer layer 90s (e.g., Figure 11A , Figure 11B and Figure 11CThe total lateral thickness 90lt1) can be extended to a lateral thickness 90lt3 of approximately 2nm to 35nm (e.g., 5nm to 25nm).

[0065] Following the seam removal process, in some embodiments, the inner spacer layer 90s may have a uniform composition. After processing, the inner spacer layer 90s may include an elemental composition in which the molecular weight of C is 0-10%, the molecular weight of N is 0-20%, the molecular weight of O is 30-60%, and the molecular weight of Si is 25-40%. In some embodiments, the inner spacer layer 90s may exhibit an oxidation depth of approximately 0 nm to 8 nm, depending on the duration of the high-oxidation annealing. In some embodiments, the oxidation may be uniform for the oxidized portion of the inner spacer layer 90s, while in other embodiments, the oxidation may have an oxygen concentration gradient present in the inner spacer layer 90s, which decreases laterally from the outer surface of the inner spacer layer 90s toward the inner surface of the inner spacer layer 90s (at the side 90i). In such embodiments, the material composition of the inner spacer layer 90s at the interface with the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P may remain unchanged compared to the deposited material composition. In other words, the high-level oxidation annealing is controlled so that the first nanostructure 52 and the second nanostructure 54 are not oxidized. In a subsequent process, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed and replaced with a replacement metal gate, which will then have an interface with the internal spacer layer 90s (e.g., at the side 90i).

[0066] exist Figure 16 In the example, according to some embodiments, it is shown that the execution has been performed. Figures 13A-13D After the seam removal process Figure 12B Enlarged views of the areas labeled F12CN and F12CP. These views are consistent with the embodiment in which the first internal spacer 90 is formed prior to the seam removal process. Figure 13D and Figure 16 The magnified portion of the region marked F13D is consistent. Figure 16 A detailed view of the first internal spacer 90 in the n-type region 50N and p-type region 50P after the seam removal process is shown.

[0067] Figure 16The diagram shows that the recess 90d4 of the first internal spacer 90 after the seam removal process is smaller than the recess 90d2 of the first internal spacer 90 before the seam removal process. In some embodiments, the recess 90d4 can be between 10% and 50% of the recess 90d2, for example, between 0 nm and 5 nm. In some embodiments, the recess 90d4 of the first internal spacer 90 is completely removed. The seam removal process can also reduce the k-value of the material of the first internal spacer 90 to a k-value smaller than the nominal k-value of the deposited material, for example, as described above with respect to the internal spacer layer 90s. Furthermore, the size of the first internal spacer 90 can be increased by about 5% to about 20%, and the density of the first internal spacer 90 can be reduced by about 5% to 15%. The resulting lateral thickness of the first internal spacer 90 (e.g., Figure 12A , Figure 12B and Figure 12C The total lateral thickness 90lt2) can be extended to a lateral thickness 90lt4 of approximately 1nm to 18nm (e.g., 5nm to 15nm).

[0068] Following the seam removal process, in some embodiments, the first internal spacer 90 may have a uniform composition. After processing, the first internal spacer 90 may include an elemental composition in which the molecular weight of C is 0-10%, the molecular weight of N is 0-20%, the molecular weight of O is 30-60%, and the molecular weight of Si is 25-40%. In some embodiments, the first internal spacer 90 may exhibit an oxidation depth of about 0 nm to 8 nm, depending on the duration of the high-oxidation annealing. In some embodiments, the oxidation may be uniform for the oxidized portion of the first internal spacer 90, while in other embodiments, the oxidation may have an oxygen concentration gradient present in the first internal spacer 90, which decreases laterally from the outer surface of the first internal spacer 90 toward the inner surface of the first internal spacer 90 (at side 90i). In such embodiments, the material composition of the first internal spacer 90 at the interface (at side 90i) of the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P may remain unchanged compared to the deposited material composition. In other words, the high-level oxidation annealing is controlled such that the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are not oxidized. In a subsequent process, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed and replaced with a replacement metal gate, which will then have an interface with the first internal spacer 90 (e.g., at side 90i).

[0069] Figure 17A and Figure 17B It shows the Figure 15The structure shown undergoes an anisotropic etching process to remove portions of the internal spacer layer 90s to form the first internal spacer 90. In some embodiments, such as Figure 17B As shown, the outer wall of the first internal spacer 90 can be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively (depending on whether it is in the p-type region 50P or the n-type region 50N). The resulting first internal spacer 90 can have a reduced or eliminated recessed profile, similar to the above description. Figure 16 As stated above.

[0070] The internal spacer layer 90s can be etched using an anisotropic etching process such as RIE, NBE, etc. The first internal spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes for forming the gate structure) from affecting the subsequently formed source / drain regions (e.g., epitaxial source / drain regions 92, hereinafter referred to as...). Figures 18A-18C (To be discussed) damage.

[0071] In some embodiments, any remaining recesses in the inner spacer layer 90s may be removed when etching the spacer layer 90s to form the first inner spacer 90. In such embodiments, the deepest portion of the remaining recesses (see Figure 15 The recess 90d3 can be exposed to anisotropic etching used to form the first internal spacer 90, thereby eliminating the recess in the first internal spacer 90. Eliminating the recess in the first internal spacer 90 advantageously provides better separation between the subsequently formed source / drain regions and the subsequently formed replacement gate structure.

[0072] exist Figures 18A-18C In this embodiment, an epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Figure 18B As shown, epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76 by an appropriate lateral distance, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the subsequently formed gate of the resulting nanostructure FET.

[0073] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by masking the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which tensile strain is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon-phosphorus, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have a facet.

[0074] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanostructure FET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can comprise a material on which compressive strain is applied, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface protruding from the corresponding surface of the nanostructure 55 and can have a facet.

[0075] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain region can be approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0076] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanostructure FET to merge, such as... Figure 18A As shown. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as... Figure 18C As shown. In Figure 18A and Figure 18C In the illustrated embodiment, a first spacer 81 may be formed on the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructure 55 to further prevent epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0077] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments in which the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on top of the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on top of the second semiconductor material layer 92B.

[0078] exist Figures 19A-19C In, respectively in Figure 6A , Figure 18B and Figure 18A The first interlayer dielectric (ILD) 96 is deposited on the structure shown. Figure 7A-18C The process will not change. Figure 6A (See the cross-section shown). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and first spacer 81. CESL 94 may include a dielectric material having an etch rate different from that of the first ILD 96 described above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0079] exist Figures 20A-20B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. This planarization process may also remove the mask 78 on the dummy gate 76, as well as a portion of the first spacer 81 along the sidewall of the mask 78. After this planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0080] exist Figure 21A and Figure 21B In one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed to form the second recess 98. A portion of the dummy gate dielectric 71 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, this etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or overlays a portion of the nanostructure 55 that serves as a channel region in the subsequently completed nanostructure FET. The portion of the nanostructure 55 serving as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer as the dummy gate 76 is etched. The dummy gate dielectric 71 can then be removed after the removal of the dummy gate 76.

[0081] exist Figure 22A and Figure 22B In this embodiment, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, extending the second recess 98. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, the first nanostructure 52 in the n-type region 50N can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0082] The second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the second nanostructure 54, while the first nanostructure 52, substrate 50, and STI region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 comprises, for example, SiGe and the first nanostructure 52 comprises, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, etc., can be used to remove the second nanostructure 54 in the p-type region 50P.

[0083] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 from both the n-type region 50N and the p-type region 50P, or by removing the second nanostructure 54 from both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanostructure FET and the p-type nanostructure FET can have the same material composition, such as silicon, silicon germanium, etc. Figure 27A , Figure 27B and Figure 27C A structure resulting from such an embodiment is shown, wherein the channel region in both the p-type region 50P and the n-type region 50N is provided by a second nanostructure 54 and includes, for example, silicon.

[0084] After the removal of the first nanostructure 52 and / or the second nanostructure 54, the first internal spacer 90 is retained. Due to the reduction and / or elimination of lateral seams, the first internal spacer 90 allows C... eff This increases and decreases the chance of a short circuit between the source / drain region 92 and the subsequently formed metal gate.

[0085] exist Figure 23A and Figure 23B In this process, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the first nanostructure 52, along the first internal spacer 90. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68.

[0086] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer situated on top of the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0087] Gate electrodes 102 are deposited on the gate dielectric layer 100 and fill the remainder of the second recess 98. Gate electrodes 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although in Figure 23A and Figure 23B A single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0088] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0089] After filling the second recess 98, a planarization process such as CMP can be performed to remove material from the gate electrode 102 and excess portions of the gate dielectric layer 100 above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus form the replacement gate structure of the resulting nanostructured FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the “gate structure”.

[0090] exist Figures 24A-24C In this process, the gate structure (including the gate dielectric layer 100 and the corresponding upper gate electrode 102) is recessed, such that a recess is formed directly above the gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the recess, and then a planarization process is performed to remove excess dielectric material extending above the first ILD 96. The gate contacts subsequently formed (e.g., referred to below) Figures 26A-26C The gate contact 114 discussed here passes through the gate mask 104 and contacts the top surface of the recessed gate electrode 102.

[0091] like Figures 24A-24C As further shown, the second ILD 106 is deposited on top of the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0092] exist Figures 25A-25CIn this process, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a third recess 108, which exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and it can then be etched through the CESL 94 using a third etching process. A mask (e.g., photoresist) can be formed on the second ILD 106 and patterned thereon to mask portions of the second ILD 106 relative to the first and second etching processes. In some embodiments, the etching process may over-etch, so the third recess 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third recess 108 may be flush with (e.g., at the same level, or at the same distance from the substrate) or below (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figure 25B The third recess 108 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross section. However, in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of short-circuiting subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed as follows: first, a metal (not shown) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 to form a silicide region or germanide region is deposited over the exposed portion of the epitaxial source / drain region 92, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, is deposited, and then a thermal annealing process is performed to form the silicide region 110. Then, unreacted portions of the deposited metal are removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicide and germanide). In an embodiment, the silicide region 110 comprises TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0093] Next, in Figures 26A-26CIn the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive filler material, and are electrically coupled to underlying conductive features (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer for contacts 112 and 114 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive filler material for contacts 112 and 114 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0094] Figures 27A-27C A cross-sectional view of a device according to some alternative embodiments is shown. Figure 27A It shows Figure 1 The reference section A-A' is shown. Figure 27B It shows Figure 1 The reference section B-B' is shown. Figure 27C It shows Figure 1 The reference section C-C' is shown. Figures 27A-27C In the figures, the same reference numerals indicate that they are connected by the same reference numerals. Figures 26A-26C The same components are formed using the same process and structure. However, in Figures 27A-27C In this configuration, the channel regions in the n-type region 50N and the p-type region 50P comprise the same material. For example, a second nanostructure 54 comprising silicon provides the channel region for both the p-type nanostructure FET in the p-type region 50P and the n-type nanostructure FET in the n-type region 50N. Figures 27A-27C The structure can be formed as follows: an internal sidewall spacer is formed on the first nanostructure 52 of both the p-type region 50P and the n-type region 50N; the internal sidewall spacer is subjected to... Figures 13A to 13D The process involves: a seam-closing process; simultaneous removal of the first nanostructure 52 from both the p-type region 50P and the n-type region 50N; deposition of a gate dielectric layer 100 and a gate electrode 102P (e.g., a gate electrode suitable for a p-type nanostructure FET) around the second nanostructure 54 in the p-type region 50P; and deposition of a gate dielectric layer 100 and a gate electrode 102N (e.g., a gate electrode suitable for an n-type nanostructure FET) around the second nanostructure 54 in the n-type region 50N. In such an embodiment, as described above, the material of the epitaxial source / drain region 92 in the n-type region 50N can be different from that in the p-type region 50P.

[0095] The embodiments can achieve several advantages. For example, lateral seams caused by the conformal deposition process of the spacer layers can be resolved by the expansion and crosslinking resulting from oxidation annealing and dry annealing. This reduces the chance of short circuits, lowers the k-value, and provides better transistor C. eff Performance. The embodiments also inject oxygen into the spacer layer and provide oxidation of the spacer layer to increase its volume and reduce its density. The embodiments also advantageously remove various compounds, including amines and methyl groups, from the spacer layer by conversion to hydroxyl groups, providing better crosslinking ability and more effective insulating properties. The material composition of the spacer layer changes from its deposited state to include different component decompositions, which increases oxygen and reduces carbon and nitrogen. The embodiments also reduce the recess profile of the spacer layer, thereby effectively increasing the lateral thickness of the spacer layer.

[0096] One embodiment is a device including a first nanostructure. The device also includes a second nanostructure on top of the first nanostructure. The device further includes a source / drain region adjacent to the first nanostructure. The device also includes a gate structure surrounding the first and second nanostructures. The device further includes a first internal spacer inserted between the first and second nanostructures, the first internal spacer being inserted between the gate structure and the source / drain region, the first internal spacer being oxidized on a first side that contacts the source / drain region. In one embodiment, the oxidation has a lateral depth between 0 nm and 8 nm. In one embodiment, the oxidation has a concentration gradient that decreases laterally from the first side of the first internal spacer towards a deeper portion of the first internal spacer. In one embodiment, the material composition of the first internal spacer, by molecular weight, includes: 0-10% C, 0-20% N, 30-60% O, and 25-40% Si. In one embodiment, the material composition of the first internal spacer adjacent to the gate structure, based on molecular weight, comprises: 5-15% C, 10-30% N, 10-55% O, and 30-45% Si. In one embodiment, the second side of the first internal spacer has a first curved sidewall adjacent to the gate structure, wherein the first side of the first internal spacer has a second curved sidewall opposite to the first side, and wherein the second curved sidewall is flatter than the first curved sidewall. In one embodiment, the first internal spacer has a width between 5 nm and 15 nm. In one embodiment, the first internal spacer has a uniform material composition.

[0097] Another embodiment is a transistor including a first nanostructure on a semiconductor substrate, the first nanostructure including a first end. The transistor also includes a second nanostructure on the first nanostructure, the second nanostructure including a second end. The transistor further includes a spacer inserted between the first end and the second end. The transistor also includes a gate dielectric surrounding the first and second nanostructures, the gate dielectric having an interface with a first side of the spacer. The transistor also includes a source / drain region adjacent to the first and second ends, the source / drain region having an interface with a second side of the spacer opposite to the first side, wherein the first side of the spacer has a first recessed profile, and the second side of the spacer has a second recessed profile, wherein the second recessed profile is less recessed than the first recessed profile. In one embodiment, the first recessed profile is between 0.5 nm and 15 nm, and the second recessed profile is between 0 nm and 5 nm. In one embodiment, the spacer has a first oxide concentration disposed on the second side of the spacer. In one embodiment, the lateral depth of the first oxide concentration from the second side of the spacer is greater than 0 nm and less than about 8 nm. In one embodiment, the first oxidation concentration has a concentration gradient that decreases from the second side of the spacer toward the first side of the spacer.

[0098] Another embodiment is a method comprising etching a first recess adjacent to a first nanostructure and a second nanostructure, the first nanostructure being situated on top of the second nanostructure. The method further comprises etching sidewalls of the first nanostructure through the first recess to form sidewall recesses of the first nanostructure. The method further comprises forming a first sidewall spacer in the sidewall recess, the first sidewall spacer having a horizontal seam between an upper and a lower portion. The method further comprises performing an oxidation annealing that injects oxygen into the horizontal seam. The method further comprises performing a dry annealing that causes crosslinking between the upper and lower portions, the size of the horizontal seam being reduced by the crosslinking. In one embodiment, after oxidation annealing and dry annealing, the k-value of the first sidewall spacer is reduced by 5% to 10%. In one embodiment, oxidation annealing and dry annealing increase the volume of the first sidewall spacer by 5% to 20%. In one embodiment, the method further includes: depositing a source / drain region in a first recess; etching an opening over a first nanostructure and a second nanostructure; etching to expand the opening to remove the first nanostructure; and depositing a gate structure in the opening and around the second nanostructure, with a first sidewall spacer disposed between the gate structure and the source / drain region. In one embodiment, oxidation annealing is performed in an atmosphere comprising H2O, CO2, O2, O3, O-related oxidizing agents, or combinations thereof, at a temperature between 200°C and 600°C. In one embodiment, dry annealing is performed at a temperature between 500°C and 800°C. In one embodiment, oxidation annealing and dry annealing reduce the density of the first sidewall spacer by 5% to 15%.

[0099] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0100] Example 1 is a semiconductor device comprising: a first nanostructure; a second nanostructure on the first nanostructure; a source / drain region adjacent to the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; and a first internal spacer inserted between the first nanostructure and the second nanostructure, the first internal spacer being inserted between the gate structure and the source / drain region, the first internal spacer being oxidized on a first side, the first side of the first internal spacer being in contact with the source / drain region.

[0101] Example 2 is the device described in Example 1, wherein the oxidation has a lateral depth between 0 nm and 8 nm.

[0102] Example 3 is the device described in Example 1, wherein the oxidation has a concentration gradient that decreases laterally from a first side of the first internal spacer toward a deeper part of the first internal spacer.

[0103] Example 4 is the device described in Example 1, wherein the material composition of the first internal spacer, based on molecular weight, comprises: 0-10% C, 0-20% N, 30-60% O, and 25-40% Si.

[0104] Example 5 is the device described in Example 4, wherein the material composition of the first internal spacer immediately adjacent to the gate structure, based on molecular weight, comprises: 5-15% C, 10-30% N, 10-55% O, and 30-45% Si.

[0105] Example 6 is the device described in Example 1, wherein the second side of the first internal spacer has a first curved sidewall adjacent to the gate structure, wherein the first side of the first internal spacer has a second curved sidewall opposite to the first side, wherein the second curved sidewall is flatter than the first curved sidewall.

[0106] Example 7 is the device described in Example 1, wherein the first internal spacer has a width between 5 nm and 15 nm.

[0107] Example 8 is the device described in Example 1, wherein the first internal spacer has a uniform material composition.

[0108] Example 9 is a transistor comprising: a first nanostructure on a semiconductor substrate, the first nanostructure including a first end; a second nanostructure on the first nanostructure, the second nanostructure including a second end; a spacer inserted between the first end and the second end; a gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric having an interface with a first side of the spacer; and a source / drain region adjacent to the first end and the second end, the source / drain region having an interface with a second side of the spacer opposite to the first side, wherein the first side of the spacer has a first recessed profile, wherein the second side of the spacer has a second recessed profile, wherein the second recessed profile is less recessed than the first recessed profile.

[0109] Example 10 is the transistor described in Example 9, wherein the first recess profile is between 0.5 nm and 15 nm, and wherein the second recess profile is between 0 nm and 5 nm.

[0110] Example 11 is the transistor described in Example 9, wherein the spacer has a first oxidation concentration disposed on a second side of the spacer.

[0111] Example 12 is the transistor described in Example 11, wherein the first oxide concentration has a lateral depth from the second side of the spacer that is greater than 0 nm and less than about 8 nm.

[0112] Example 13 is the transistor described in Example 12, wherein the first oxidation concentration has a concentration gradient that decreases from the second side of the spacer toward the first side of the spacer.

[0113] Example 14 is a method of forming a semiconductor device, comprising: etching a first recess adjacent to a first nanostructure and a second nanostructure, the first nanostructure being situated on top of the second nanostructure; etching a sidewall of the first nanostructure through the first recess to form a sidewall recess of the first nanostructure; forming a first sidewall spacer in the sidewall recess, the first sidewall spacer having a horizontal seam between an upper portion and a lower portion; performing an oxidation annealing that injects oxygen into the horizontal seam; and performing a dry annealing that causes crosslinking between the upper portion and the lower portion, the size of the horizontal seam being reduced by the crosslinking.

[0114] Example 15 is the method described in Example 14, wherein, after the oxidation annealing and the dry annealing, the k value of the first sidewall spacer is reduced by 5% to 10%.

[0115] Example 16 is the method of Example 14, wherein the oxidation annealing and the dry annealing increase the volume of the first sidewall spacer by 5% to 20%.

[0116] Example 17 is the method of Example 14, further comprising: depositing a source / drain region in the first recess; etching an opening over the first nanostructure and the second nanostructure; etching to expand the opening to remove the first nanostructure; and depositing a gate structure in the opening and around the second nanostructure, the first sidewall spacer being disposed between the gate structure and the source / drain region.

[0117] Example 18 is the method described in Example 14, wherein the oxidative annealing is performed in an atmosphere comprising H2O, CO2, O2, O3, O-related oxidizing agents, or combinations thereof, at a temperature between 200°C and 600°C.

[0118] Example 19 is the method described in Example 14, wherein the dry annealing is performed at a temperature between 500°C and 800°C.

[0119] Example 20 is the method described in Example 14, wherein the oxidation annealing and the dry annealing reduce the density of the first sidewall spacer by 5% to 15%.

Claims

1. A semiconductor device, comprising: First nanostructure; The second nanostructure is built on top of the first nanostructure; The source / drain region is adjacent to the first nanostructure. A gate structure surrounding the first nanostructure and the second nanostructure; as well as A first internal spacer is inserted between the first nanostructure and the second nanostructure. The first internal spacer is inserted between the gate structure and the source / drain region. The first internal spacer is oxidized on a first side. The first side of the first internal spacer is in contact with the source / drain region. The first internal spacer includes a closed seam horizontal to the first nanostructure.

2. The device according to claim 1, wherein, The oxidation has a lateral depth between 0 nm and 8 nm.

3. The device according to claim 1, wherein, The oxidation has a concentration gradient that decreases laterally from a first side of the first internal spacer toward a deeper part of the first internal spacer.

4. The device according to claim 1, wherein, The material composition of the first internal spacer, based on molecular weight, includes: 0-10% C, 0-20% N, 30-60% O, and 25-40% Si.

5. The device according to claim 4, wherein, The material composition of the first internal spacer adjacent to the gate structure, based on molecular weight, includes: 5-15% C, 10-30% N, 10-55% O, and 30-45% Si.

6. The device according to claim 1, wherein, The second side of the first internal spacer has a first curved sidewall adjacent to the gate structure, wherein the first side of the first internal spacer has a second curved sidewall opposite to the first side, wherein the second curved sidewall is flatter than the first curved sidewall.

7. The device according to claim 1, wherein, The first internal spacer has a width between 5 nm and 15 nm.

8. The device according to claim 1, wherein, The first internal spacer has a uniform material composition.

9. A transistor, comprising: A first nanostructure is disposed on a semiconductor substrate, the first nanostructure including a first end; A second nanostructure is built on top of the first nanostructure, and the second nanostructure includes a second end; A spacer is inserted between the first end and the second end; A gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric having an interface with a first side of the spacer; as well as A source / drain region, adjacent to the first end and the second end, the source / drain region having an interface with a second side of the spacer, the second side of the spacer being opposite to the first side, wherein the first side of the spacer has a first recessed profile, wherein the second side of the spacer has a second recessed profile, wherein the second recessed profile is less recessed than the first recessed profile.

10. The transistor according to claim 9, wherein, The first concave profile is between 0.5 nm and 15 nm, and the second concave profile is between 0 nm and 5 nm.

11. The transistor according to claim 9, wherein, The spacer has a first oxidation concentration disposed on a second side of the spacer.

12. The transistor of claim 11, wherein, The first oxidation concentration has a lateral depth from the second side of the spacer that is greater than 0 nm and less than 8 nm.

13. The transistor of claim 12, wherein, The first oxidation concentration has a concentration gradient that decreases from the second side of the spacer toward the first side of the spacer.

14. A method of forming a semiconductor device, comprising: A first recess is etched adjacent to the first nanostructure and the second nanostructure, with the first nanostructure located on top of the second nanostructure. Etch the sidewall of the first nanostructure through the first recess to form the sidewall recess of the first nanostructure; A first sidewall spacer is formed in the sidewall recess, and the first sidewall spacer has a horizontal joint between the upper and lower parts; An oxidation annealing process is performed, during which oxygen is injected into the horizontal joint. as well as Dry annealing is performed, which causes crosslinking between the upper and lower parts, and the size of the horizontal joint is reduced by the crosslinking.

15. The method according to claim 14, wherein, After the oxidation annealing and the dry annealing, the k value of the first sidewall spacer decreases by 5% to 10%.

16. The method of claim 14, wherein, The oxidation annealing and the dry annealing increase the volume of the first sidewall spacer by 5% to 20%.

17. The method of claim 14, further comprising: Deposit the source / drain region in the first recess; Openings are etched onto the first nanostructure and the second nanostructure; Etching is performed to expand the opening in order to remove the first nanostructure; as well as A gate structure is deposited in the opening and around the second nanostructure, with the first sidewall spacer disposed between the gate structure and the source / drain region.

18. The method according to claim 14, wherein, The oxidative annealing is performed in an atmosphere containing H2O, CO2, O2, O3, O-related oxidizing agents, or combinations thereof, at a temperature between 200°C and 600°C.

19. The method of claim 14, wherein, The dry annealing is performed at a temperature between 500°C and 800°C.

20. The method of claim 14, wherein, The oxidation annealing and the dry annealing reduce the density of the first sidewall spacer by 5% to 15%.

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