Microelectronic devices and related electronic systems and methods including hierarchical stacking

Abstract

This application relates to microelectronic devices comprising hierarchical stacking, and related electronic systems and methods. One microelectronic device includes: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in a hierarchy, the stacked structure being divided into block structures separated from each other by slot structures; a memory cell string extending vertically through the block structures of the stacked structure, each memory cell string individually including a channel material extending vertically through the stacked structure; an additional stacked structure vertically overlying the stacked structure and comprising a vertical sequence of additional conductive and insulating structures arranged in an additional hierarchy; a first pillar extending through the additional stacked structure and vertically overlying the memory cell strings, each of the first pillars being horizontally offset from the center of a corresponding memory cell string; a second pillar extending through the additional stacked structure and vertically overlying the memory cell strings; and an additional slot structure comprising a dielectric material extending through at least a portion of the additional stacked structure and subdividing each of the block structures into sub-block structures, the additional slot structure being horizontally adjacent to the first pillar. Related microelectronic devices, electronic systems, and methods are also described.

Description

[0001] Priority Claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application Serial No. 17 / 127,971, filed on December 18, 2020, entitled "Microelectronic Devices Including Tiered Stacks Including Conductive Structures Isolated by Slot Structures, and Related Electronic Systems and Methods". Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to microelectronic devices and related electronic systems, and methods of forming microelectronic devices. Background Technology

[0004] A persistent goal of the microelectronics industry is to increase the memory density of memory devices (e.g., the number of memory cells per memory die), such as non-volatile memory devices (e.g., NAND flash memory devices). One approach to increasing memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array comprises vertical strings of memory extending through openings in a stack of layers of conductive structures (e.g., word lines) and dielectric material at each junction of the vertical memory strings and the conductive structures. Compared to structures with a conventional planar (e.g., two-dimensional) transistor arrangement, this configuration allows for the placement of a greater number of switching devices (e.g., transistors) within a unit die area (i.e., the length and width of the active surface consumed) by constructing the array upwards (e.g., longitudinally, vertically) on the die.

[0005] A conventional vertical memory array includes electrical connections between conductive structures and access lines (e.g., word lines), allowing memory cells in the vertical memory array to be uniquely selected for write, read, or erase operations. One method of forming this electrical connection involves forming at least one so-called "staircase" (or "step") structure at the edge (e.g., horizontal end) of a hierarchy of conductive structures. The staircase structure includes individual "steps" providing contact areas for the conductive structures, on which conductive contact structures can be positioned to provide electrical access to the conductive structures.

[0006] With advancements in vertical memory array technology, additional memory density is provided by forming vertical memory arrays to include stacked additional levels of conductive structures and thus associated additional staircase structures and / or additional steps in individual staircase structures. As the number of conductive structure levels increases, the processing conditions for aligning contacts with the various components of the microelectronic device become increasingly difficult. Furthermore, other techniques for increasing memory density have reduced the spacing between adjacent vertical memory strings. However, reducing the spacing between adjacent vertical memory strings may increase the difficulty of forming various isolation structures between vertical memory strings. Summary of the Invention

[0007] In some embodiments, a microelectronic device includes: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in a hierarchy, the stacked structure being divided into block structures separated from each other by slot structures; a memory cell string extending vertically through the block structures of the stacked structure, the memory cell string individually including a channel material extending vertically through the stacked structure; an additional stacked structure vertically overlying the stacked structure and comprising a vertical sequence of additional conductive and insulating structures arranged in additional hierarchies; a first pillar extending through the additional stacked structure and vertically overlying the memory cell strings, each of the first pillars being horizontally offset from the center of a corresponding memory cell string; a second pillar extending through the additional stacked structure and vertically overlying the memory cell strings; and an additional slot structure comprising a dielectric material extending through at least a portion of the additional stacked structure and subdividing each of the block structures into sub-block structures, the additional slot structure being horizontally adjacent to the first pillar.

[0008] In other embodiments, a method of forming a microelectronic device includes: forming a first stacked structure comprising alternating layers of insulating structures and other insulating structures; forming a string of memory cells comprising a channel material extending through the first stacked structure; forming a second stacked structure comprising alternating layers of additional insulating structures and other additional insulating structures above the first stacked structure; forming first pillars extending through the second stacked structure and above some of the memory cells, the center of each of the first pillars being offset from the center of the corresponding memory cells string; forming second pillars extending through the stacked structure and above the others of the memory cells string, the center of each of the second pillars being substantially horizontally aligned with the center of the corresponding memory cells string; and forming a slot structure between adjacent first pillars, the slot structure having a non-linear shape.

[0009] In another embodiment, a microelectronic device includes: a memory cell string extending through a first stacked structure comprising alternating conductive and insulating structures, the memory cell string including at least a dielectric material and a channel material extending vertically through the first stacked structure; a second stacked structure vertically overlying the first stacked structure; a first pillar extending through the second stacked structure and vertically overlying the first of the memory cell strings, the first pillar being horizontally offset from the center of the first of the memory cell strings; and a second pillar extending through the second stacked structure and vertically overlying the second of the memory cell strings, the second pillar being horizontally aligned with the center of the second of the memory cell strings.

[0010] In an additional embodiment, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure. The at least one microelectronic device structure includes: a memory cell string extending through a stacked structure comprising alternating layers of insulating and conductive structures; a pillar within an additional stacked structure comprising alternating layers of additional insulating and conductive structures; a channel region extending through the stacked structure and the memory cell string, the channel region having a greater thickness between the stacked structure and the additional stacked structure compared to other portions of the channel region; and a slot structure extending at least partially through the stacked structure, the slot structures individually exhibiting a non-linear shape. Attached Figure Description

[0011] Figures 1A to 1P This is a simplified cross-sectional view illustrating a method for forming a microelectronic device structure according to embodiments of the present disclosure. Figure 1A , Figure 1C , Figure 1D , Figures 1F to 1J , Figure 1L , Figure 1M , Figure 10 and Figure 1P ) and top view ( Figure 1B , Figure 1E , Figure 1K and Figure 1N );

[0012] Figure 2 This is a partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure;

[0013] Figure 3 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0014] Figure 4This is a block diagram of a processor-based system according to embodiments of the present disclosure. Detailed Implementation

[0015] The description contained herein is not intended to be an actual view of any particular system, microelectronic structure, microelectronic device, or its integrated circuit, but merely an idealized representation used to describe the embodiments herein. Common elements and features between the figures may retain the same numerical designations, except that, for ease of description below, reference numerals begin with the figure number on which the element is introduced or most fully described.

[0016] The following description provides specific details, such as material type, material thickness, and processing conditions, to provide a thorough description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the description provided herein does not form a complete process flow for manufacturing microelectronic device structures or microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices) or complete microelectronic devices. The structures described below do not form complete microelectronic devices. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form complete microelectronic devices from structures can be performed using conventional techniques.

[0017] The materials described herein can be formed using conventional techniques, including (but not limited to) spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, those skilled in the art can choose the appropriate technique for depositing or growing the material. Material removal can be achieved using any suitable technique, including (but not limited to) etching, abrasive planarization (e.g., chemical mechanical planarization), or other known techniques, unless the context otherwise indicates.

[0018] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of at least one structure and at least one device that facilitates the operation of one or more structures and devices in a predetermined manner.

[0019] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to the principal plane of a substrate (e.g., base material, base structure, base construction, etc.) in which one or more structures and / or features are formed, and are not necessarily defined by the Earth’s gravitational field. A “lateral” or “horizontal” direction is generally parallel to the principal plane of the substrate, while a “longitudinal” or “vertical” direction is generally perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by a surface of the substrate that has a relatively large area compared to the other surfaces of the substrate.

[0020] As used herein, the term "generally" with respect to a given parameter, property, or condition means, and includes, to the extent that a person skilled in the art would understand, that the given parameter, property, or condition is satisfied with a certain degree of variance, such as within acceptable tolerances. By way of example, depending on the specific parameter, property, or condition that is generally satisfied, the parameter, property, or condition may be satisfied with at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0021] As used herein, “about” or “approximately” with respect to a numerical value for a particular parameter includes the numerical value and a degree of deviation from the numerical value within acceptable tolerances for the particular parameter, as would be understood by one of ordinary skill in the art. For example, “about” or “approximately” with respect to a numerical value may include additional values ​​in the range of 90.0% to 110.0% of the numerical value, such as in the range of 95.0% to 105.0%, in the range of 97.5% to 102.5%, in the range of 99.0% to 101.0%, in the range of 99.5% to 100.5%, or in the range of 99.9% to 100.1%.

[0022] As used herein, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “top,” “front,” “rear,” “left,” “right,” and similar terms may be used to describe the relationship of one element or feature to another, as illustrated in the diagrams. Unless otherwise stated, spatial relative terms are intended to encompass different orientations of material other than those depicted in the diagrams. For example, if the material in the diagram were inverted, an element described as “below,” “under,” “lower,” or “on the bottom” of another element or feature would then be oriented “above” or “top” of that other element or feature. Thus, depending on the context in which the term is used, the term “below” can encompass both above and below orientations, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0023] As used herein, features described as “adjacent” to each other (e.g., area, material, structure, device) mean and include the feature of the closest (e.g., nearest) disclosed identity (or multiple identities) to each other. Additional features (e.g., additional area, additional material, additional structure, additional device) that do not match the disclosed identity (or multiple identities) of an “adjacent” feature may be positioned between “adjacent” features. In other words, “adjacent” features may be directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be indirectly adjacent to each other such that at least one feature of an identity different from the identity associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other mean and include the feature of the disclosed identity (or multiple identities) positioned as the closest (e.g., vertically nearest) to each other. Furthermore, features described as “horizontally adjacent” to each other mean and include the feature of the disclosed identity (or multiple identities) located as the closest (e.g., horizontally nearest) to each other.

[0024] As used herein, the term "memory device" means and includes, but is not limited to, microelectronic devices that exhibit memory functionality but are not limited to memory functionality. In other words, and only by way of example, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices with combinational logic and memory, and graphics processing units (GPUs) incorporated into memory.

[0025] As used herein, “conductive material” means and includes conductive materials such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (MO), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (CO), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), and aluminum (Al)); alloys (e.g., Co-based alloys). The term "conductive structure" refers to and includes structures formed from conductive materials and containing conductive materials. This includes Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel.

[0026] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x Ny)) and at least one dielectric carbonitride material (e.g., silicon carbonitride (SiO) x C z N y Formulas containing one or more of the terms "x", "y", and "z" used in this article (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiOx C z N y The term "insulating material" indicates a material in which each atom of another element (e.g., Si, Al, Hf, Nb, Ti) contains an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of any additional element (if any). Since the formula represents relative atomic ratios rather than strict chemical structures, insulating materials may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if any) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds composed of elements that cannot be expressed by a ratio of well-defined natural numbers and violate the law of definite proportions. Additionally, "insulating structure" means and includes structures formed of and containing insulating materials.

[0027] According to embodiments described herein, a microelectronic device includes a stacked structure comprising alternating conductive and insulating structures arranged in layers, each layer including both conductive and insulating structures. Strings of memory cells extend through the stacked structure and may include, for example, channel material extending through the stacked structure as a portion of a pillar structure. The strings of memory cells may be arranged in rows and columns. Memory cells of a string of memory cells may be located at intersections between conductive structures and pillar-like structures (containing channel material), with adjacent memory cells of each string separated from each other by one of the insulating structures. In some embodiments, strings may include strings horizontally (e.g., laterally) aligned with each other and at least other strings horizontally offset from each other.

[0028] Another stacked structure may be vertically superimposed on the stacked structure and may include additional conductive and insulating structures disposed within the layers. The microelectronic device may be separated into one or more block structures via slots filled with dielectric material. Each of the block structures may be separated into one or more sub-block structures via additional slots extending through at least a portion of the other stacked structures. Pillars extend through the other stacked structures and are vertically superimposed on the memory cell string. Pillars may contain channel material electrically coupled to the channel material of the memory cell string. Pillars adjacent to (e.g., near their location) the additional slots may be horizontally offset from the center of the underlying memory cell string in a direction away from the additional slots. Therefore, the center of a pillar adjacent to (e.g., near) the additional slots may be horizontally farther from the horizontal boundary of the additional slot than from the center of the underlying memory cell string. Pillars spaced from the additional slots by other pillars may be substantially concentric with the underlying memory cell string. Therefore, the pillars may comprise a first group of pillars horizontally offset from the center of the directly underlying memory cell string and a second group of pillars aligned with (e.g., concentric with) the directly underlying memory cell string or horizontally offset from the center of the underlying memory cell string to a lesser extent than the pillars of the first group of pillars. Forming pillars adjacent to (e.g., near) the additional slot so that they are horizontally offset from the center of the underlying memory cell string can facilitate an increased width of the additional slot, which can promote improved uniformity in the formation of the additional conductive structure.

[0029] Microelectronic devices can be formed by forming pillars comprising channel material extending through a stacked structure and forming other stacked structures above the stacked structure. The stacked structure may include hierarchies comprising alternating insulating structures and other insulating structures. Other stacked structures may include hierarchies comprising alternating additional insulating structures and additional other insulating structures. Pillars comprising channel material may be formed above each of the pillars in the stacked structure and are electrically connected to the channel material. Slot structures may be formed through the stacked structure and other stacked structures to divide the microelectronic device into one or more block structures. Other insulating structures may be removed through the slot structure and replaced with conductive structures to form a memory cell string. Additional other insulating structures may be simultaneously removed through the slot structure and replaced with additional conductive structures to form a select gate structure. Additional slot structures may be formed through at least a portion of the other stacked structures to form one or more sub-block structures in each block structure. The additional slot structures may have a non-linear shape, comprising one or more arcuate surfaces with a braided pattern defining the columns of pillars of the other stacked structures. Pillars directly adjacent to (e.g., adjacent to) the additional slot structures may be horizontally offset from the underlying memory cell string in a direction away from the additional slot structures. In some embodiments, the distance between pillars in adjacent columns of a second pillar separated by one of the additional slots may be greater than the distance between adjacent pillars not separated by the additional slot structure. Increasing the distance between pillars adjacent to (e.g., near) the additional slot structure can facilitate the formation of an additional slot structure with a larger horizontal dimension, which can facilitate the formation of improved additional conductive structures and the formation of select gate structures (e.g., select gate drain (SGD) structures) exhibiting improved properties (e.g., reduced threshold voltage).

[0030] Figures 1A to 1P A method for forming a microelectronic device structure according to embodiments of the present disclosure is described. Figure 1A This is a simplified partial cross-sectional view of a microelectronic device structure 100 according to an embodiment of the present disclosure. Figure 1B yes Figure 1A Top view of the microelectronic device structure 100. Figure 1A The cross section along Figure 1B The section line AA is cut off. The microelectronic device structure 100 may include a stack structure 101, which includes a vertical (e.g., in the Z direction) alternating sequence of insulating structures 104 and other insulating structures 106 arranged in layers 102. Each layer 102 may individually include a layer of insulating structures 104 that are directly vertically adjacent (e.g., adjacent) to (the layer of other insulating structures 106). The insulating structures 104 of the stack structure 101 may also be referred to herein as “insulating material”, and the other insulating structures 106 of the stack structure 101 may also be referred to herein as “other insulating material”.

[0031] In some embodiments, the number (e.g., quantity) of the layers 102 of the stacked structure 101 may range from 32 layers 102 to 256 layers 102. In some embodiments, the stacked structure 101 comprises 128 layers 102. However, this disclosure is not so limited, and the stacked structure 101 may comprise a different number of layers 102. Additionally, in some embodiments, the stacked structure 101 includes a first layer structure vertically overlying the source structure 103 and including layers 102 of insulating structures 104 and other insulating structures 106, and a second layer structure above the first layer structure, the second layer structure including layers 102 of insulating structures 104 and other insulating structures 106. In some such embodiments, the first layer structure may be separated from the second layer structure by interlayer regions. For example, the stacked structure 101 may include a dual-layer 3D NAND device (e.g., a 3D NAND flash memory device). In some embodiments, the stacked structure 101 may be referred to herein as a layer structure or a first layer structure.

[0032] The layers of the insulating structure 104 may be formed of and contain at least one dielectric material, such as oxide materials (e.g., one or more of silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), and aluminum oxide (Al2O3). In some embodiments, the insulating structure 104 is formed of and contains silicon dioxide.

[0033] The layers of other insulating structures 106 may be formed and comprised of an insulating material different from that of insulating structure 104 and exhibiting etch selectivity with respect to insulating structure 104. In some embodiments, other insulating structures 106 are formed and comprised of a nitride material (e.g., silicon nitride (Si3N4)) or an oxide nitride material (e.g., silicon oxynitride). In some embodiments, other insulating structures 106 comprise silicon nitride.

[0034] Stacked structure 101 may be formed above source structure 103 (e.g., source plate). Source structure 103 may be formed and comprised of a semiconductor material, for example, doped with one or more P-type conductive materials (e.g., polysilicon doped with at least one P-type dopant, such as one or more of boron, aluminum, and gallium) or one or more N-type conductive materials (e.g., polysilicon doped with at least one N-type dopant, such as one or more of arsenic, phosphorus, antimony, and bismuth). Although Figure 1AThe present disclosure is not limited to including a stacked structure 101 directly above (e.g., on) the source structure 103. In other embodiments, the stacked structure 101 is overlaid on a layered structure comprising an insulating structure 104 and other insulating structures 106, the layered structure being separated from the stacked structure 101 by at least one dielectric material.

[0035] Dielectric material 108 may be located above the uppermost layer in layer 102. Dielectric material 108 may be formed of and comprise an electrically insulating material, such as (for example) one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), and silicon dioxide. In some embodiments, dielectric material 108 comprises the same material composition as insulating structure 104. In some embodiments, dielectric material 108 comprises silicon dioxide.

[0036] The thickness T1 of the dielectric material 108 (e.g., in the Z direction) can range from about 40 nanometers (nm) to about 80 nm, for example from about 40 nm to about 60 nm, or from about 60 nm to about 80 nm. In some embodiments, the thickness T1 is about 60 nm. However, this disclosure is not so limited, and the thickness T1 may differ from the thickness described above.

[0037] The pillars 110 of the material (e.g., cell pillars) may extend vertically (e.g., in the Z direction) through the stack structure 101. As will be described herein, the material of the pillars 110 may form memory cells (e.g., memory cell strings). Each pillar 110 may individually include an insulating material 112, a channel material 114 horizontally adjacent to the insulating material 112, a tunnel dielectric material (also referred to as "tunneling dielectric") 116 horizontally adjacent to the channel material 114, a memory material 118 horizontally adjacent to the tunnel dielectric material 116, and a dielectric barrier material (also referred to as "charge barrier material") 120 horizontally adjacent to the memory material 118. The dielectric barrier material 120 may be horizontally adjacent to one of the other insulating structures 106 of one of the layers 102 of the stack structure 101. The channel material 114 can be horizontally inserted between the insulating material 112 and the tunnel dielectric material 116; the tunnel dielectric material 116 can be horizontally inserted between the channel material 114 and the memory material 118; the memory material 118 can be horizontally inserted between the tunnel dielectric material 116 and the dielectric barrier material 120; and the dielectric barrier material 120 can be horizontally inserted between the memory material 118 and the layer of another insulating structure 106.

[0038] The insulating material 112 may be formed of and comprise an electrically insulating material, such as (for example) phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), nitrogen oxides (e.g., silicon oxynitride), dielectric carbonitride materials (e.g., silicon carbonitride (SiCN)), dielectric carboxyl nitride materials (e.g., carboxyl silicon nitride (SiOCN)) or combinations thereof. In some embodiments, the insulating material 112 comprises silicon dioxide.

[0039] The channel material 114 may be formed from and comprise one or more of semiconductor materials (at least one elemental semiconductor material, such as polycrystalline silicon; at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, GaAs, InP, GaP, GaN, other semiconductor materials) and oxide semiconductor materials. In some embodiments, the channel material 114 comprises amorphous silicon or polycrystalline silicon. In some embodiments, the channel material 114 comprises a doped semiconductor material.

[0040] The tunnel dielectric material 116 may be formed of and comprise a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions, for example, by hot carrier injection or by charge transfer induced by Fowler-Nordheim tunneling. By way of non-limiting example, the tunnel dielectric material 116 may be formed of and comprise one or more of silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In some embodiments, the tunnel dielectric material 116 comprises silicon dioxide. In other embodiments, the tunnel dielectric material 116 comprises silicon oxynitride.

[0041] The memory material 118 may include a charge-trapping material or a conductive material. The memory material 118 may be formed from and contain one or more of the following: silicon nitride, silicon oxynitride, polycrystalline silicon (doped polycrystalline silicon), conductive materials (tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and their alloys, or metal silicides, such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof), semiconducting polycrystalline silicon, or amorphous semiconductor materials containing at least one elemental semiconductor element or at least one compound semiconductor material, conductive nanoparticles (e.g., ruthenium nanoparticles), and metal dots. In some embodiments, the memory material 118 includes silicon nitride.

[0042] The dielectric barrier material 120 may be formed of and comprise a dielectric material, such as one or more of oxides (e.g., silicon dioxide), nitrides (silicon nitride), and oxynitrides (silicon oxynitride), or another material. In some embodiments, the dielectric barrier material 120 comprises silicon oxynitride.

[0043] In some embodiments, the tunnel dielectric 116, memory material 118, and dielectric barrier material 120 together may include a structure configured to trap charge, such as (for example) an oxide-nitride-oxide (ONO) structure. In some such embodiments, the tunnel dielectric 116 comprises silicon dioxide, the memory material 118 comprises silicon nitride, and the dielectric barrier material 120 comprises silicon dioxide.

[0044] refer to Figure 1B Some of the pillars 110 may be aligned with each other (e.g., in the Y direction), and others of the pillars 110 may be offset from each other (e.g., in the Y direction). The pillars 110 may be arranged in a so-called woven pattern (e.g., a hexagonal close-packed arrangement), which can facilitate an increased density of the pillars 110 (and the resulting strings of memory cells) in the stacked structure 101. The pillars 110 may be arranged as rows 107 extending in a first horizontal (e.g., lateral) direction (e.g., in the X direction) and columns 109 extending in a second horizontal direction (e.g., in the Y direction). In some embodiments, the pillars 110 in columns 109 may be laterally offset from the pillars 110 in adjacent (e.g., adjacent) columns 109 (e.g., in each of the X and Y directions). Additionally, the pillars 110 in every other column 109 may be horizontally aligned (e.g., in the Y direction). Similarly, the pillars 110 in rows 107 may be horizontally offset from the pillars 110 in adjacent (e.g., adjacent) rows 107 (e.g., in each of the X and Y directions). Additionally, the pillars 110 of every other row 107 can be horizontally aligned (e.g., in the X direction).

[0045] Continue to refer to Figure 1A and Figure 1B The dimension D1 (e.g., diameter) of the support 110 may be in the range of about 100 nm to about 150 nm, for example, from about 100 nm to about 110 nm, from about 110 nm to about 120 nm, from about 120 nm to about 130 nm, from about 130 nm to about 140 nm, or from about 140 nm to about 150 nm. In some embodiments, the dimension D1 is about 120 nm. However, this disclosure is not so limited, and the dimension D1 may differ from the dimension described.

[0046] refer to Figure 1CAfter the pillar 110 is formed, a portion of the pillar 110 may be removed to make the pillar 110 recessed relative to the uppermost surface of the dielectric material 108. In some embodiments, a portion of the insulating material and the channel material 114 may be vertically recessed (e.g., in the Z direction) lower than other components of the pillar 110 (e.g., tunnel dielectric material 116, memory material 118, dielectric barrier material 120). In some embodiments, removing a portion of the pillar 110 may form rounded portions 121 (also referred to as “rounded corners”) of at least some of the remaining portions of the pillar 110. The rounded portions 121 may have an arcuate shape. In some embodiments, a portion of the dielectric barrier material 120 may be retained, leaving the rounded portions 121 of the dielectric barrier material 120. As will be described herein, the rounded portions 121 may facilitate the formation of a channel region (e.g., channel material 130) presenting the corresponding rounded portion. Figure 1G )).

[0047] In some embodiments, conductive material 122 may be formed within the groove to form a so-called “conductive plug structure”. Conductive material 122 may be formed of and comprise polysilicon or another material, formulated to exhibit etch selectivity with respect to one or more of the material of dielectric material 108 and, in some embodiments, the material of pillar 110. In some embodiments, conductive material 122 is formed of and comprises polysilicon. In some embodiments, conductive material 122 is electrically connected to (e.g., electrically communicated with) channel material 114. In some embodiments, conductive material 122 comprises doped polysilicon. In some embodiments, conductive material 122 is doped with one or more n-type dopants, such as (for example) phosphorus. In some embodiments, conductive material 122 is lightly doped (e.g., with about 1 × 10⁻⁶). 18 atoms / cm 3 (concentration).

[0048] After the conductive material 122 is formed, the microelectronic device structure 100 may be exposed to a chemical mechanical planarization (CMP) process to remove the conductive material from the outer surface of the groove (e.g., on the upper surface of the dielectric material 108). In some embodiments, the conductive material 122 is exposed to an oxidation process to form a rounded portion 121 at its vertical (e.g., in the Z direction) portion. In other embodiments, the upper portion of the conductive material 122 includes an acute angle, and the conductive material 122 includes a rounded portion 121 at its vertical lower (e.g., in the Z direction) portion.

[0049] Common Reference Figure 1D and Figure 1EAfter the conductive material 122 is formed, another stacked structure 105 (e.g., an upper stacked structure, a selected gate-drain (SGD) stacked structure) may be formed on top of the stacked structure 101 (which may also be referred to herein as a "second layer structure"). Figure 1D It is along Figure 1E The simplified cross-sectional view of the microelectronic device structure 100 is taken by the section line DD. Figure 1E This indicates that it corresponds to Figure 1B A top view of a portion of the microelectronic device structure 100 at the location of box E. Figure 1E In the diagram, pillar 110 is shown in dashed lines to indicate that it is located below the upper surface of the microelectronic device structure 100.

[0050] refer to Figure 1D Another stacked structure 105 may include alternating layers of additional insulating structures 104 and other additional insulating structures 106 formed above the etch stop material 125. The alternating layers of insulating structures 104 and other insulating structures 106 may be arranged in layers 124. The dielectric material 108 between stacked structure 101 and another stacked structure 105 may be referred to as an interlayer region 111. Another stacked structure 105 may include a topmost insulating structure 129 having a greater thickness in the vertical direction (e.g., in the Z direction) than the other insulating structures 104 of the other stacked structure 105.

[0051] The etch stop material 125 may be formed of and comprise a material that exhibits etch selectivity with respect to insulating structure 104 and other insulating structures 106. In some embodiments, the etch stop material 125 comprises a carbon-containing material (e.g., silicon carbonitride (SiCN)). In some such embodiments, the etch stop material 125 may promote an improved electric field through a channel region adjacent to the etch stop material 125 during use and operation of the microelectronic device structure 100. In some embodiments, the microelectronic device structure 100 may not include the etch stop material 125 between the stacked structure 101 and another stacked structure 105. In some such embodiments, a dielectric material 108 may be interposed between the stacked structure 101 and another stacked structure 105.

[0052] The thickness T2 of the etch stop material 125 can be in the range of about 10 nm to about 30 nm, for example, from about 10 nm to about 20 nm, or from about 20 nm to about 30 nm. In some embodiments, the thickness T2 is about 20 nm. However, this disclosure is not so limited, and the thickness T2 may differ from the thickness described.

[0053] After forming another stacked structure 105, a first opening 126 and a second opening 127 (collectively referred to as openings 126, 127) can be formed through the other stacked structure 105 to the conductive material 122. In some embodiments, the first opening 126 is offset from the pillar 110 (e.g., not concentric), and the second opening 127 is aligned with the pillar 110 (e.g., concentric). In other embodiments, the second opening 127 is horizontally offset from the center of the underlying pillar 110, but to a lesser extent than the first opening 126. In some such embodiments, the second opening 127 is not substantially concentric with the center of the underlying pillar 110, but the center of the second opening 127 may be located closer to the center of the underlying pillar 110 than the center of the first opening 126 is located to the center of the underlying pillar 110. As will be described herein, the first opening 126 may be adjacent to (e.g., located adjacent to) a slot structure that separates the block structure of the microelectronic device structure 100 into one or more sub-block structures.

[0054] The size D2 (e.g., diameter) of the lower portion of openings 126, 127 may be in the range of about 40 nm to about 70 nm, such as from about 40 nm to about 50 nm, from about 50 nm to about 60 nm, or from about 60 nm to about 70 nm. In some embodiments, the size D2 may be in the range of about 50 nm to about 60 nm, such as about 55 nm.

[0055] The size D3 (e.g., diameter) of the upper portion of openings 126, 127 can range from about 50 nm to about 80 nm, for example, from about 50 nm to about 60 nm, from about 60 nm to about 70 nm, or from about 70 nm to about 80 nm. In some embodiments, size D3 is from about 55 nm to about 65 nm, for example, about 60 nm. In some embodiments, size D3 is larger than size D2, and the sidewalls of openings 126, 127 are tapered (e.g., angled) relative to the main surface of source structure 103. In some embodiments, the size D1 of pillar 110 is approximately twice the size D3.

[0056] refer to Figure 1E In some embodiments, the first opening 126 is arranged in a column 109 (e.g., extending in the Y direction), and the second opening 127 is arranged horizontally adjacent to the column 109 of the first opening 126. In some such embodiments, the first opening 126 may be horizontally aligned with other first openings 126 in the same column 109 (e.g., in the X direction), and the second opening 127 may be horizontally aligned with other second openings 127 in the same column 109 (e.g., in the X direction).

[0057] After forming the first opening 126 and the second opening 127, a first pad material 128 may be formed over the surfaces (e.g., sidewalls) of the first opening 126 and the second opening 127. A second pad material 131 may be formed over and in contact with the first pad material 128. The first pad material 128 may be formed of and contain an insulating material, such as one or more of the materials described above with reference to insulating material 112. In some embodiments, the first pad material 128 comprises silicon dioxide. In some embodiments, the second pad material 131 is formed of and contains polycrystalline silicon. In some embodiments, after forming the first pad material 128 and the second pad material 131, the second pad material 131 may be exposed to stamping etching to expose a portion of the conductive material 122.

[0058] Continue to refer to Figure 1E The pitch P between horizontally adjacent (e.g., in the Y direction, i.e., along the direction in which they form the slot structure) pillars 110 (and openings 126, 127) can be in the range of about 120 nm to about 180 nm, for example, from about 120 nm to about 140 nm, from about 140 nm to about 160 nm, or from about 160 nm to about 180 nm. In some embodiments, the pitch P is from about 140 nm to about 150 nm or from about 150 nm to about 160 nm. However, this disclosure is not so limited, and the pitch P may differ from the pitch described.

[0059] Continue to refer to Figure 1E After removing the horizontal extensions of the second pad material 131 and the first pad material 128, the vertically lower (e.g., in the Z direction) portion of the first pad material 128 may be exposed to the etchant to form an additional rounded portion 121. Since the upper portion of the first pad material 128 is covered by the second pad material 131, it may not be substantially exposed to the etchant.

[0060] refer to Figure 1F After removing the vertical lower portion of the first pad material 128, a portion of the second pad material 131 and the conductive material 122 can be removed.

[0061] Now for reference Figure 1GThe channel material 130 may be formed on the side above the first pad material 128 and electrically communicated with the channel material 114 via the conductive material 122. The channel material 130 may include one or more of the materials of the channel material 114 as described above. In some embodiments, the channel material 130 may include the same material composition as the channel material 114. In some embodiments, the channel material 130 may be continuous with the channel material 114. Since the channel material 130 may include the same material composition as the channel material 114 and the channel material 130 is electrically communicated with the channel material 114 via the conductive material 122, the channel material 114, the conductive material 122, and the channel material 130 may be collectively referred to as the channel region as used herein.

[0062] In some embodiments, the channel material 130 may not have acute angles and may include rounded corners 132. The rounded corners 132 of the channel material 130 may have an arc shape and may also be referred to herein as "arc" corners.

[0063] The fillet 132 may be formed, for example, by rounding the portion 121 of the insulating material 112 and the dielectric barrier material 120. Therefore, some of the fillets 132 may correspond to the respective interfaces between the channel material 130 and each of the insulating material 112 and the dielectric barrier material 120. In some such embodiments, the interface between the channel material 114 and the insulating material 112 may include the fillet 132. Additionally, the interface between the channel material 130 and the dielectric barrier material 120 may include the fillet 132. Furthermore, the exposed portion of the channel material 130 may include the fillet 132.

[0064] The rounded corner 132 shape can promote improved electrical performance of devices (e.g., memory cells) associated with channel materials 114 and 130. For example, during use and operation of the microelectronic device structure 100, the rounded corner 132 can significantly reduce or prevent charge accumulation at regions (e.g., corners) of the channel material 130. Additionally, the rounded corner 132 can promote improved electric fields induced through the channel materials 114 and 130.

[0065] Continue to refer to Figure 1G In some embodiments, the thickness T3 of the channel material 114 may be approximately the same as the thickness T4 of the channel material 130. In other embodiments, the thickness T3 of the channel material 114 is less than the thickness T4 of the channel material 130. In still other embodiments, the thickness T3 of the channel material 114 is greater than the thickness T4 of the channel material 130. In some embodiments, the thickness of the channel region (including the channel material 114, the channel material 130, and the conductive material 122) between the stacked structure 101 and the additional stacked structure 105 (e.g., near the interlayer region 111) may be greater than the thickness at other locations.

[0066] Thickness T3 and thickness T4 may each be individually in the range of about 5 nm to about 15 nm, for example, from about 5 nm to about 10 nm, or from about 10 nm to about 20 nm. Thickness T4 may be in the range of about 10 nm to about 30 nm, for example, from about 10 nm to about 20 nm, or from about 20 nm to about 30 nm.

[0067] refer to Figure 1H After the channel material 130 is formed, an insulating material 134 may be formed in the remaining portions of the openings 126, 127 between the channel materials 130 to form a first upper support structure 135 and a second upper support structure 137 from the respective first opening 126 and second opening 127. The insulating material 134 may be vertically overlaid (e.g., in the Z direction) on the channel material 130, for example, on the horizontal extension of the channel material 130 above the conductive material 122.

[0068] The first upper support structure 135 may be horizontally offset from the center of the vertically oriented (e.g., in the Z direction) support 110 (e.g., in the X direction and in the Y direction). The second upper support structure 137 may be horizontally aligned with the center of the vertically oriented (e.g., in the Z direction) support 110 (e.g., in each of the X and Y directions). In some embodiments, the second upper support structure 137 may be horizontally offset from the center of the vertically oriented support 110, but to a lesser extent than the horizontal offset of the first upper support structure 135 from the vertically oriented support 110.

[0069] The insulating material 134 may be formed from and comprise one or more of the materials described above with reference to insulating material 112. In some embodiments, the insulating material 134 comprises substantially the same material composition as insulating material 112. In some embodiments, the insulating material 134 comprises silicon dioxide. In some embodiments, the microelectronic device structure 100 is exposed to a planarization process, such as a CMP process, after the insulating material 134 is formed.

[0070] Now for reference Figure 1I After the insulating material 134 is formed, at least a portion of the insulating material 134 may be recessed from the upper support structures 135, 137 to form a groove. The groove may be filled with additional channel material to form a horizontal extension 136 of the channel material 130. The additional channel material may include the same material composition as the channel material 130.

[0071] The thickness (e.g., in the Z direction) T5 of the horizontal extension 136 of the channel material 130 may be in the range of about 30 nm to about 50 nm, for example, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm. However, this disclosure is not so limited, and the thickness T6 may differ from the thickness described.

[0072] Common Reference Figure 1J and Figure 1K After forming the horizontal extension 136 of the channel material 130, a slot 133 can be formed through another stacked structure 105 and stacked structure 101. Figure 1J It is along Figure 1K The simplified partial cross-sectional view of the microelectronic device structure 100 is taken by section line JJ. The slot 133 may be referred to herein as a "replacement gate" slot. In some embodiments, the slot 133 exposes at least a portion of the source structure 103.

[0073] refer to Figure 1K The microelectronic device structure 100 may include slots 133 that are horizontally spaced from each other (e.g., in the X direction) by a plurality of columns 109 of pillars 110 and upper pillar structures 135, 137. The microelectronic device structure 100 may be divided into block structures 140 between horizontally adjacent (e.g., in the X direction) slots 133. Although Figure 1K Only one block structure 140 is described, but it will be understood that the microelectronic device structure 100 may contain several block structures 140. As will be described herein, the block structure 140 may be divided into one or more sub-block structures.

[0074] Return to reference Figure 1J After the slot 133 is formed, as part of a so-called "replace gate" or "gate final" process, other insulating structures 106 of the stacked structure 101 can be removed through the slot 133. By way of non-limiting examples, other insulating structures 106 can be removed by exposing them to a wet etchant comprising one or more of phosphoric acid, sulfuric acid, hydrochloric acid, nitric acid, or another material. In some embodiments, other insulating structures 106 are removed by exposing them to a so-called "wet nitride band" comprising a wet etchant containing phosphoric acid. In some embodiments, other insulating structures 106 of the stacked structure 101 and another stacked structure 105 can be removed simultaneously through the slot 133.

[0075] refer to Figure 1L After removing other insulation structures 106 ( Figure 1JSubsequently, conductive structure 142 may be formed between adjacent insulating structures 104 at locations corresponding to other insulating materials 106 to form a stacked structure 101 comprising alternating layers 144 of insulating structures 104 and conductive structures 142, and another stacked structure 105 comprising alternating layers 144 of insulating structures 104 and additional conductive structures 145 (which may include the same material composition as conductive structures 142). For clarity, the insulating structure 104 of the other stacked structure 105 may be referred to herein as additional insulating structure 104. The conductive structure 142 of the stacked structure 101 may be used as a local word line structure (e.g., a local or word line board). The additional conductive structure 145 of the other stacked structure 105 may be used as a select gate structure, such as a select gate drain (SGD) structure.

[0076] The conductive structure 142 and the additional conductive structure 145 may each be individually formed of and comprise a conductive material, such as at least one conductive material, for example (e.g.) tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, metallic materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and iridium oxide (IrO). x ), Ruthenium oxide (RuO) x Materials including at least one of the following: conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.), polycrystalline silicon, other conductive materials, or combinations thereof. In some embodiments, conductive structure 142 and additional conductive structure 145 include tungsten.

[0077] In some embodiments, the conductive structure 142 may include a conductive pad material surrounding the conductive structure 142, for example, between the conductive structure 142 and the insulating structure 104. Additionally, an additional conductive structure 145 may include a conductive pad material surrounding the additional conductive structure 145, for example, between the additional conductive structure 145 and the insulating structure 104. The conductive pad material may include, for example, a seed material, from which the conductive structure 142 and the additional conductive structure 145 may be formed. The conductive pad material may be formed of and comprise, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, the conductive pad material includes titanium nitride.

[0078] The formation of conductive structure 142 can form a string 160 of memory cells 162. The memory cells 162 of the string 160 can be located at the intersection of the pillars 110 and conductive structure 142, and can individually include a portion of one of the pillars 110 and a portion of one of the conductive structures 142. Vertically adjacent memory cells 162 of the string 160 can be separated from each other by one of the layers of insulating structure 104.

[0079] After forming conductive structure 142 and additional conductive structures, slot 133 may be filled with dielectric material 146. Dielectric material 146 may extend through another stacked structure 105 and stacked structure 101. Therefore, dielectric material 146 can physically separate adjacent (e.g., neighboring) block structures 140 of the microelectronic device structure 100. Figure 1K ).

[0080] The dielectric material 146 may include one or more of the materials described above with reference to the insulating material 112. In some embodiments, the dielectric material 146 comprises substantially the same material composition as the insulating material 112. In some embodiments, the dielectric material 146 comprises silicon dioxide.

[0081] Now for joint reference Figure 1M and Figure 1N After the slot 133 is filled with dielectric material 146, an additional slot 148 can be formed through the alternating layers 144 of the insulating structure 104 and the additional conductive structure 145 of another stacked structure 105. In some embodiments, the additional slot 148 is formed by sequentially removing the layers 144 of the insulating structure 104 and the additional conductive structure 145. Figure 1M It was cut along the section line MM. Figure 1N A simplified cross-sectional view of the microelectronic device structure 100.

[0082] In some embodiments, the additional slot 148 terminates in the lowest of the layers 144 of another stacked structure 105. In some such embodiments, the additional conductive structure 145 of the lowest layer 144 of the other stacked structure 105 may be substantially continuous within the block structure 140 and may be continuous, for example, with the conductive structure 142 of the stacked structure 101. By comparison, the additional slot 148 may divide the additional conductive structure 145 of the layers 144 of the other stacked structure 105 (excluding the lowest layer 144) into distinct portions such that the additional conductive structure 145 is not substantially continuous within the block structure 140. Instead, such additional conductive structure 145 may be divided by the additional slot 148.

[0083] In some embodiments, the lowermost additional conductive structure 145 may include a so-called "dummy" word line structure. During use and operation of the microelectronic device structure 100, a voltage may be applied to the lowermost additional conductive structure 145, which may facilitate improved current flow through the channel material 130 horizontally adjacent to the lowermost additional conductive structure 145 and through the interlayer region 111. Successive lowermost additional conductive structures 145 may facilitate voltage application near substantially all of the first upper pillar structures 135 and second upper pillar structures 137 within the block structure 140. Additionally, in some embodiments, the uppermost conductive structure 142 of the stacked structure 101 may include a dummy word line structure. Similarly, applying a voltage to the uppermost conductive structure 142 may facilitate improved current flow through the channel material 130 adjacent to the interlayer region 111.

[0084] Continue to refer to Figure 1M and Figure 1N The additional slot 148 may extend vertically over at least a portion of each of the struts 110 adjacent to the additional slot 148 (e.g., in the Z direction). The additional slot 148 may be sized and shaped to facilitate electrical isolation of the additional conductive structure 145 and may be physically spaced from the upper strut structures 135, 137.

[0085] The additional slot 148 may present a so-called "woven" pattern, wherein the additional slot 148 is not defined by a generally straight line (e.g., extending in the Y direction). Instead, the additional slot 148 may be configured to extend between adjacent columns of the pillars 110 and the upper pillar structure 135, and may present a shape that at least partially conforms to the layout (e.g., shape) of the string 160 of the memory cells 162 and the first upper pillar structure 135. For example, the additional slot 148 may include peak regions 165 (e.g., raised regions) extending in a direction away from the horizontally adjacent (e.g., in the X direction) pillars 110 and upper pillar structure 137, and may include corresponding valley regions 167 (e.g., recessed regions) horizontally adjacent (e.g., in the X direction) to the peak regions 165.

[0086] Additional slots 148 may be located between first upper pillar structures 135, which are horizontally offset (e.g., non-concentric) from corresponding strings 160 of memory cells 162 directly below the first upper pillar structure 135 (e.g., formed from the first opening 126 (FIG. 1)). By forming the first upper pillar structure 135 adjacent to (e.g., near) the additional slots 148, the additional slots 148 can be formed to have a larger horizontal dimension without being positioned too close or removing portions of the upper pillar structure 135. Furthermore, the weave pattern of the additional slots 148 and the horizontal offset of the first upper pillar structure 135 facilitate the formation of block structures 140 with relatively small horizontal dimensions between slots 133 compared to conventional microelectronic devices. For example, in conventional microelectronic devices, additional slots may be formed through some (e.g., columns) of the upper pillar structure, thereby reducing the total number of upper pillar structures that can fit within a given horizontal dimension between adjacent slots.

[0087] The dimension D4 (e.g., diameter) of the upper portion of the additional slot 148 may range from about 20 nm to about 50 nm, for example from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm. In some embodiments, the dimension D4 is about 35 nm. However, this disclosure is not so limited and the dimension D4 may differ from the dimension described. In some embodiments, the dimension D4 is substantially uniform across the width of the additional slot 148 (e.g., in the X direction). Therefore, even if the additional slot 148 presents a woven shape with an arcuate surface, the dimension D4 may be substantially uniform.

[0088] refer to Figure 1N In some embodiments, the size D4 of the additional slot 148 may be greater than the distance between horizontally adjacent strings 160 of the memory cell 162. In some embodiments, the additional slot 148 vertically overlaps the underlying string 160 of the memory cell 162 and is located within the horizontal boundary of the underlying string 160 of the memory cell 162.

[0089] The dimension D5 (e.g., diameter) of the lower portion of the additional slot 148 may range from about 10 nm to about 40 nm, for example from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, or from about 30 nm to about 40 nm. In some embodiments, the dimension D5 is about 25 nm. However, this disclosure is not so limited and the dimension D5 may differ from the dimension described.

[0090] The dimension D6 (e.g., distance) between the horizontal edge of the additional slot 148 and the nearest horizontal edge of the first upper support structure 135 can be in the range of about 15 nm to about 55 nm, for example, from about 15 nm to about 25 nm, from about 25 nm to about 35 nm, from about 35 nm to about 45 nm, or from about 45 nm to about 55 nm. In some embodiments, the dimension D6 is in the range of about 40 nm to about 45 nm. However, this disclosure is not so limited and the dimension D6 may differ from the dimension described.

[0091] refer to Figure 1N The additional slot 148 can divide the block structure 140 into sub-block structures 150, each defined within the horizontal boundary between adjacent additional slots 148.

[0092] Now for reference Figure 10 After the additional slot 148 is formed, the additional slot 148 may be filled with dielectric material 152. Dielectric material 152 may include one or more of the materials of dielectric material 146 as described above. In some embodiments, dielectric material 152 comprises substantially the same material composition as dielectric material 146. In some embodiments, dielectric material 152 comprises silicon dioxide.

[0093] After the dielectric material 152 is formed within the additional slot 148, the dielectric material 152 located outside the additional slot 148 can be removed, for example by exposing the microelectronic device structure 100 to a CMP process. An etch stop material 154 can be formed over the microelectronic device structure 100. The etch stop material 154 may include one or more of the materials described above with reference to etch stop material 125. In some embodiments, the etch stop material 154 comprises substantially the same material composition as etch stop material 125. In some embodiments, the etch stop material 154 comprises a carbon-containing material (e.g., silicon carbonitride (SiCN)).

[0094] Continue to refer to Figure 10 An opening 156 can be formed through the etch stop material 154 to expose the upper portion of the upper support structure 135, such as at least the upper surface of the horizontal extension portion 136 of the channel material 130.

[0095] Now for reference Figure 1P After the opening 156 is formed, a conductive contact 158 ​​may be formed on and electrically connected to the channel material 130. The conductive contact 158 ​​may be electrically coupled to an access line (e.g., a bit line) configured for selective coupling to a string 160 of a memory cell 162.

[0096] The conductive contact 158 ​​may include a conductive material, such as one or more of the materials described above with reference to the conductive structure 142. In some embodiments, the conductive contact 158 ​​includes a material composition substantially the same as that of the conductive structure 142. In some embodiments, the conductive contact 158 ​​includes tungsten.

[0097] As described above, the horizontal offset of the additional slot 148 and the first upper pillar structure 135 can facilitate improved operation of the microelectronic device structure 100. For example, the select gate structure formed from the additional conductive structure 145 can exhibit improved threshold voltage properties compared to conventional microelectronic devices. Furthermore, since the additional conductive structure 145 is formed through the slot 133 (rather than through the additional slot 148), the additional conductive structure 145 can be formed to exhibit improved electrical properties compared to the additional conductive structure 145 in conventional microelectronic device structures. Moreover, since the additional slot 148 is formed through another stacked structure 105 including the additional conductive structure 145 and other insulating structures 104 (rather than through a stacked structure including polysilicon or another sacrificial material, as in conventional microelectronic device structures), the additional conductive structure 145 can exhibit fewer voids (e.g., tungsten voids) compared to conventional microelectronic device structures, resulting in improved conductivity (and lower resistance).

[0098] although Figures 1A to 1P The present disclosure is not limited to memory cells 162 which have been described and illustrated as having a specific structure and configuration. In some embodiments, memory cells 162 may include so-called “MONOS” (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, memory cells 162 may include so-called “TANOS” (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells or so-called “BETANOS” (band / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In other embodiments, memory cells 162 may include so-called “floating gate” memory cells which include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally positioned between the central structure of string 160 and conductive structure 142.

[0099] In some embodiments, electrically connecting the channel material 114 to the channel material 130 via the conductive material 122 can promote improved performance of the microelectronic device structure 100. For example, the conductive material 122 can enhance the current flow between the channel material 114 and the channel material 130 because current can flow along several paths through the conductive material 122 between the channel material 114 and the channel material 130 (due to the size and shape of the conductive material 122). Additionally, the dopant concentration within the conductive material 122 can be controlled to promote improved current flow between the channel material 114 and the channel material 130.

[0100] Figure 2 This illustration shows a partial cross-sectional perspective view of a portion of a microelectronic device 201 (e.g., a memory device, such as a dual-layer 3D NAND flash memory device) including a microelectronic device structure 200. The microelectronic device structure 200 may be substantially similar to that in the previous references. Figure 1P The microelectronic device structure 100 described follows the processing stage. (As in...) Figure 2 As shown, the microelectronic device structure 200 may include a staircase structure 220, which defines a way to connect access lines 206 to conductive layers 205 (e.g., conductive layers, conductive plates, such as conductive structure 142). Figure 1P The contact area of ​​the microelectronic device structure 200 may include memory cells 203 (e.g., memory cell 162) coupled in series with each other. Figure 1P The vertical string 207 (e.g., string 160) Figure 1P Vertical string 207 may extend vertically (e.g., in the Z direction) and orthogonally to conductive lines and layers 205, such as data lines 202 and source layers 204 (e.g., source structure 103). Figure 1P Conductive layer 205, access line 206, first select gate 208 (e.g., upper select gate, drain select gate (SGD), for example another stacked structure 105) Figure 1P Additional conductive structure 145 ( Figure 1N ), select line 209 and second select gate 210 (e.g., lower select gate, source select gate (SGS)). Select gate 208 may be horizontally divided (e.g., in the Y direction) into multiple blocks 232 (e.g., block structure 140). Figure 1N They are horizontally separated from each other by slot 230 (e.g., in the Y direction) (e.g., formed in replacement gate slot 133). Figure 1M , Figure 1N Dielectric material 146 () inside Figure 1M , Figure 1N ) and additional slot 148 ( Figure 1P Dielectric material 152 ( Figure 1PAs described above with reference to the microelectronic device structure 100, relative to the first upper pillar structure 135 ( Figure 1P ) and conductive contacts 158 ( Figure 1P The size, shape, and orientation of the additional slot 148 can facilitate the formation of a first selective gate 208 that exhibits relatively improved properties.

[0101] Vertical conductive contacts 211 can electrically couple components to each other, as shown. For example, select line 209 can be electrically coupled to first select gate 208, and access line 206 can be electrically coupled to conductive layer 205. Microelectronic device 201 may also include a control unit 212 below the memory array, which may contain control logic configured to control various operations of other features of microelectronic device 201 (e.g., string 207 of memory cells 203). By way of non-limiting example, control unit 212 may include a charge pump (e.g., V... CCP Charge pump, V NEGWL One or more of the following (e.g., each): charge pump, DVC2 charge pump, delay-locked loop (DLL) circuit system (e.g., ring oscillator), V dd Regulators, drivers (e.g., string drivers), decoders (e.g., local layer decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry systems (e.g., column repair circuitry systems, row repair circuitry systems), I / O devices (e.g., local I / O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh / wear leveling devices, and other chip / layer control circuitry systems. For example, control unit 212 may be electrically coupled to data line 202, source layer 204, access line 206, first select gate 208, and second select gate 210. In some embodiments, control unit 212 includes a CMOS (complementary metal-oxide-semiconductor) circuitry system. In such embodiments, control unit 212 may be characterized to have an "array-below-the-array CMOS" ("CuA") configuration.

[0102] The first select gate 208 may extend horizontally in a first direction (e.g., in the X direction) and may be coupled at a first end (e.g., the upper end) of the vertical string 207 to a corresponding first group of vertical strings 207 of the memory cell 203. The second select gate 210 may be formed in a generally planar configuration and may be coupled at a second opposite end (e.g., the lower end) of the vertical string 207 of the memory cell 203 to the vertical string 207.

[0103] Data lines 202 (e.g., bit lines) may extend horizontally in a second direction (e.g., in the Y direction), which forms an angle (e.g., perpendicular) with the first select gate 208 along its first direction of extension. Data lines 202 may be coupled at a first end (e.g., the upper end) of a vertical string 207 to a corresponding second group of vertical strings 207. The first group of vertical strings 207 coupled to the corresponding first select gate 208 may share a specific vertical string 207 with the second group of vertical strings 207 coupled to the corresponding data lines 202. Therefore, a specific vertical string 207 can be selected at the intersection of a specific first select gate 208 and a specific data line 202. Thus, the first select gate 208 can be used to select a memory cell 203 in a string 207 of memory cells 203.

[0104] Conductive layer 205 (e.g., word line board, e.g., conductive structure 142) Figure 1P The conductive layers 205 can extend in the corresponding horizontal plane. The conductive layers 205 can be stacked vertically such that each conductive layer 205 is coupled to all vertical strings 207 of the memory cells 203, and the vertical strings 207 of the memory cells 203 extend vertically through the stack of conductive layers 205. The conductive layers 205 can be coupled to or can form the control gate of the memory cell 203 coupled to the conductive layer 205. Each conductive layer 205 can be coupled to a specific memory cell 203 within a particular vertical string 207 of the memory cell 203.

[0105] The first select gate 208 and the second select gate 210 are operable to select a specific vertical string 207 of memory cells 203 between a specific data line 202 and the source layer 204. Therefore, a specific memory cell 203 can be selected and electrically coupled to the data line 202 by operating (e.g., by selecting) the appropriate first select gate 208, second select gate 210, and conductive layer 205 coupled to the specific memory cell 203.

[0106] The staircase structure 220 can be configured to provide an electrical connection between the access line 206 and the step 205 via a vertical conductive contact 211. In other words, a specific step of the step 205 can be selected via the access line 206 electrically connected to the corresponding vertical conductive contact 211, which is electrically connected to the specific step 205.

[0107] Data line 202 can be connected via conductive contact structure 234 (e.g., conductive contact ( Figure 1P Electrically coupled to vertical string 207.

[0108] Therefore, according to some embodiments of this disclosure, a microelectronic device includes a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in a hierarchy, the stacked structure being divided into block structures separated from each other by slot structures; a memory cell string extending vertically through the block structures of the stacked structure, each memory cell string individually including a channel material extending vertically through the stacked structure; an additional stacked structure vertically overlying the stacked structure and comprising a vertical sequence of additional conductive and insulating structures arranged in an additional hierarchy; a first pillar extending through the additional stacked structure and vertically overlying the memory cell strings, each of the first pillars being horizontally offset from the center of a corresponding memory cell string; a second pillar extending through the additional stacked structure and vertically overlying the memory cell strings; and an additional slot structure comprising a dielectric material extending through at least a portion of the additional stacked structure and subdividing each of the block structures into sub-block structures, the additional slot structure being horizontally adjacent to the first pillar.

[0109] Therefore, according to an additional embodiment of this disclosure, a microelectronic device includes: a memory cell string extending through a first stacked structure comprising alternating conductive and insulating structures, the memory cell string including at least a dielectric material and a channel material extending vertically through the first stacked structure; a second stacked structure vertically covering the first stacked structure; a first pillar extending through the second stacked structure and vertically covering the first of the memory cell strings, the first pillar being horizontally offset from the center of the first of the memory cell strings; and a second pillar extending through the second stacked structure and vertically covering the second of the memory cell strings, the second pillar being horizontally aligned with the center of the second of the memory cell strings.

[0110] Therefore, according to a further embodiment of the present disclosure, a method of forming a microelectronic device includes: forming a first stacked structure comprising alternating layers of insulating structures and other insulating structures; forming a string of memory cells comprising a channel material extending through the first stacked structure; forming a second stacked structure comprising alternating layers of additional insulating structures and other additional insulating structures above the first stacked structure; forming first pillars extending through the second stacked structure and above some of the memory cells, the center of each of the first pillars being offset from the center of the corresponding memory cells string; forming second pillars extending through the stacked structure and above the others of the memory cells string, the center of each of the second pillars being substantially horizontally aligned with the center of the corresponding memory cells string; and forming a slot structure between adjacent first pillars, the slot structure having a non-linear shape.

[0111] Microelectronic devices including microelectronic devices (e.g., microelectronic device 201) and microelectronic device structures including additional slots 148 presenting a woven pattern (e.g., microelectronic device structures 100, 200) can be used in embodiments of the electronic systems disclosed herein. For example, Figure 3 This is a block diagram of an electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer, such as (for example) or Tablet computers, e-books, navigation devices, etc. Electronic system 303 includes at least one memory device 305. Memory device 305 may include, for example, the microelectronic device architecture previously described herein (e.g., microelectronic device architectures 100, 200) or previously referenced... Figures 1A to 1P and Figure 2 An embodiment of the described microelectronic device (e.g., microelectronic device 201) includes an additional slot 148 and a first upper support structure 135 and a second upper support structure 137.

[0112] The electronic system 303 may further include at least one electronic signal processor device 307 (generally referred to as a “microprocessor”). The electronic signal processor device 307 may optionally be included in embodiments of the microelectronic device or microelectronic device architecture previously described herein (e.g., previously referenced...). Figures 1A to 1P and Figure 2 The described microelectronic device 201 or one or more of the microelectronic device structures 100, 200. Electronic system 303 may further include one or more input devices 309 for inputting information into electronic system 303 by a user, such as (for example) a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 303 may further include one or more output devices 311 for outputting information to a user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 309 and output device 311 may include a single touchscreen device, which can be used both to input information into electronic system 303 and to output visual information to a user. Input device 309 and output device 311 may be in electrical communication with one or more of memory device 305 and electronic signal processor device 307.

[0113] refer to Figure 4The description describes a processor-based system 400. The processor-based system 400 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 201 or microelectronic device structures 100, 200). The processor-based system 400 may be any of various types, such as a computer, pager, cellular phone, personal organizer, control circuitry, or other electronic device. The processor-based system 400 may include one or more processors 402, such as microprocessors, to control system functions and request processing within the processor-based system 400. The processor 402 and other sub-components of the processor-based system 400 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 201 or microelectronic device structures 100, 200).

[0114] Processor-based system 400 may include a power supply 404 operatively communicatively with processor 402. For example, if processor-based system 400 is a portable system, then power supply 404 may include one or more of a fuel cell, power harvesting device, permanent battery, replaceable battery, and rechargeable battery. Power supply 404 may also include an AC adapter; thus, for example, processor-based system 400 may be plugged into a wall socket. For example, power supply 404 may also include a DC adapter, allowing processor-based system 400 to be plugged into a vehicle cigarette lighter or vehicle power port.

[0115] Depending on the functions performed by the processor-based system 400, various other devices may be coupled to the processor 402. For example, a user interface 406 may be coupled to the processor 402. The user interface 406 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 408 may also be coupled to the processor 402. The display 408 may include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projector, an audio display, or combinations thereof. Furthermore, an RF subsystem / baseband processor 410 may also be coupled to the processor 402. The RF subsystem / baseband processor 410 may include antennas coupled to an RF receiver and an RF transmitter (not shown). One or more communication ports 412 may also be coupled to the processor 402. For example, communication port 412 may be adapted to couple to one or more peripheral devices 414, such as modems, printers, computers, scanners or cameras, or to a network, such as a local area network, a remote area network, an intranet or the Internet.

[0116] Processor 402 can control processor-based system 400 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 402 to store various programs and facilitate their execution. For example, processor 402 may be coupled to system memory 416, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), race memory, and other known memory types. System memory 416 may include volatile memory, non-volatile memory, or combinations thereof. System memory 416 is typically large enough to store dynamically loaded application programs and data. In some embodiments, system memory 416 may include semiconductor devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 201 and microelectronic device structures 100, 200), or combinations thereof.

[0117] Processor 402 may also be coupled to non-volatile memory 418, which does not imply that system memory 416 is necessarily volatile. Non-volatile memory 418 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used with system memory 416. The size of non-volatile memory 418 is typically chosen to be just large enough to store any necessary operating system, applications, and fixed data. Alternatively, for example, non-volatile memory 418 may include high-capacity memory such as disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory. Non-volatile memory 418 may include microelectronic devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 201 and microelectronic device structures 100, 200), or combinations thereof.

[0118] Therefore, according to embodiments of this disclosure, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: a memory cell string extending through a stacked structure comprising alternating layers of insulating and conductive structures; a pillar within an additional stacked structure comprising alternating layers of additional insulating and conductive structures; a channel region extending through the stacked structure and the memory cell string, the channel region having a greater thickness between the stacked structure and the additional stacked structure compared to other portions of the channel region; and a slot structure extending at least partially through the stacked structure, the slot structure individually exhibiting a non-linear shape.

[0119] Additional non-limiting example embodiments of this disclosure are described below.

[0120] Example 1: A microelectronic device includes a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in a hierarchy, the stacked structure being divided into block structures separated from each other by slot structures; a memory cell string extending vertically through the block structures of the stacked structure, each memory cell string individually including a channel material extending vertically through the stacked structure; an additional stacked structure vertically overlying the stacked structure and comprising a vertical sequence of additional conductive and insulating structures arranged in an additional hierarchy; a first pillar extending through the additional stacked structure and vertically overlying the memory cell strings, each of the first pillars being horizontally offset from the center of a corresponding memory cell string; a second pillar extending through the additional stacked structure and vertically overlying the memory cell strings; and an additional slot structure comprising a dielectric material extending through at least a portion of the additional stacked structure and subdividing each of the block structures into sub-block structures, the additional slot structure being horizontally adjacent to the first pillar.

[0121] Example 2: The microelectronic device according to Example 1, wherein at least a portion of each of the additional slot structures is located within the horizontal boundary of the memory cell string that is vertically oriented under the first pillar.

[0122] Example 3: A microelectronic device according to Example 1 or Example 2, wherein two or more of the additional slot structures that are horizontally adjacent to each other are spaced apart by at least one column of the first pillar and at least one column of the second pillar.

[0123] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the additional slot structure is spaced apart from the second pillar at least by the first pillar.

[0124] Example 5: A microelectronic device according to any one of Examples 1 to 4, further comprising another channel material that extends vertically through the additional stack structure and is electrically connected to the channel material.

[0125] Example 6: The microelectronic device according to Example 5, wherein the channel material is electrically coupled to the additional channel material through a conductive material.

[0126] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein the channel material includes an arcuate surface.

[0127] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein the additional slot structure separates the column of the first pillar.

[0128] Example 9: A microelectronic device according to any one of Examples 1 to 8, wherein the horizontal distance between two or more of the first pillars that are horizontally adjacent to each other is greater than the horizontal distance between two or more of the second pillars that are horizontally adjacent to each other.

[0129] Example 10: A microelectronic device according to any one of Examples 1 to 9, wherein the horizontal distance between one of the first pillars and one of the second pillars adjacent to the first pillar is less than the horizontal distance between the first pillar and an additional second pillar adjacent to the second pillar.

[0130] Example 11: A microelectronic device according to any one of Examples 1 to 10, wherein each of the block structures includes two columns of the first pillar and two columns of the second pillar between two or more additional slot structures that are horizontally adjacent to each other.

[0131] Example 12: A method of forming a microelectronic device, the method comprising: forming a first stacked structure including alternating layers of insulating structures and other insulating structures; forming a string of memory cells including a channel material extending through the first stacked structure; forming a second stacked structure including alternating layers of additional insulating structures and other additional insulating structures above the first stacked structure; forming first pillars extending through the second stacked structure and above some of the memory cells, the center of each of the first pillars being offset from the center of the corresponding memory cells string; forming second pillars extending through the stacked structure and above the others of the memory cells string, the center of each of the second pillars being substantially horizontally aligned with the center of the corresponding memory cells string; and forming a slot structure between adjacent first pillars, the slot structure having a non-linear shape.

[0132] Example 13: The method according to Example 12 further includes forming an additional channel material through the first pillar, the additional channel material being electrically connected to the channel material of the memory cell string to form a channel region containing the channel material and the additional channel material.

[0133] Example 14: The method according to Example 13, wherein forming the channel region includes forming a conductive material, the conductive material including doped polysilicon electrically connected to the additional channel material.

[0134] Example 15: The method according to any one of Examples 12 to 14, wherein forming the slot structure includes forming a slot structure having a generally uniform horizontal width, and the sides of the slot structure including arcuate surfaces.

[0135] Example 16: The method according to any of Examples 12 to 15, wherein forming the insertion slot structure includes forming at least a portion of the insertion slot structure to vertically overlay at least a portion of some of the memory cell strings.

[0136] Example 17: The method according to any of Examples 12 to 16, wherein forming the slot structure includes forming the slot structure to be separated from the second pillar at least by the first pillar.

[0137] Example 18: The method according to any of Examples 12 to 17, wherein forming the second pillar includes forming one of the second pillars between one of the first pillars and an additional one of the second pillars, the distance between the one of the second pillars and the one of the first pillars being less than the distance between the one of the second pillars and the additional one of the second pillars.

[0138] Example 19: A microelectronic device comprising: a memory cell string extending through a first stacked structure including alternating conductive and insulating structures, the memory cell string including at least a dielectric material and a channel material extending vertically through the first stacked structure; a second stacked structure vertically covering the first stacked structure; a first pillar extending through the second stacked structure and vertically covering the first of the memory cell strings, the first pillar being horizontally offset from the center of the first of the memory cell strings; and a second pillar extending through the second stacked structure and vertically covering the second of the memory cell strings, the second pillar being horizontally aligned with the center of the second of the memory cell strings.

[0139] Example 20: The microelectronic device according to Example 19 further includes a slot structure horizontally adjacent to the first pillar.

[0140] Example 21: The microelectronic device according to Example 20, wherein the slot structure includes an arcuate shape.

[0141] Example 22: The microelectronic device according to Example 20 or Example 21, wherein the slot structure is spaced from the second pillar by at least the horizontal dimension of the first pillar.

[0142] Example 23: A microelectronic device according to any of Examples 20 to 22, wherein the slot structure extends between the first pillar and a third pillar vertically overlying a third in the memory cell string, the third pillar being horizontally offset from the center of the third in the memory cell string.

[0143] Example 24: A microelectronic device according to any one of Examples 20 to 23, wherein the slot structure includes a horizontal dimension greater than the horizontal distance between the first and the second in the memory cell string.

[0144] Example 25: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure including: a memory cell string extending through a stacked structure comprising alternating layers of insulating and conductive structures; a pillar within an additional stacked structure comprising alternating layers of additional insulating and conductive structures; a channel region extending through the stacked structure and the memory cell string, the channel region having a greater thickness between the stacked structure and the additional stacked structure compared to other portions of the channel region; and a slot structure extending at least partially through the stacked structure, the slot structure individually exhibiting a non-linear shape.

[0145] Although certain illustrative embodiments have been described in conjunction with drawings, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. Rather, many additions, deletions, and modifications, such as those claimed below and including legal equivalents, may be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure. Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being covered within the scope of this disclosure.

Claims

1. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in a hierarchy, the stacked structure being divided into block structures separated from each other by slot structures; A string of memory cells extending vertically through the block structure of the stacked structure, each string of memory cells individually including channel material extending vertically through the stacked structure; An additional stacked structure, which is vertically superimposed on the stacked structure and includes a vertical sequence of additional conductive and insulating structures arranged in an additional layer; A first pillar extends through the additional stacking structure and vertically covers the memory cell string, each of the first pillars being horizontally offset from the center of the corresponding memory cell string. The second pillar extends through the additional stacked structure and vertically covers the memory cell string; and An additional slot structure includes a dielectric material extending through at least a portion of the additional stack structure and subdividing each of the block structures into sub-block structures. The additional slot structure is horizontally adjacent to the first pillar, and the horizontal distance between one of the first pillars and one of the second pillars horizontally adjacent to the first pillar is less than the horizontal distance between the first pillar and an additional second pillar adjacent to the first pillar.

2. The microelectronic device of claim 1, wherein at least a portion of each of the additional slot structures lies within the horizontal boundary of the memory cell string that lies vertically beneath the first pillar.

3. The microelectronic device of claim 1, wherein two or more of the additional slot structures that are horizontally adjacent to each other are spaced apart by at least one column of the first pillar and at least one column of the second pillar.

4. The microelectronic device of claim 1, wherein the additional slot structure is spaced apart from the second pillar at least by the first pillar.

5. The microelectronic device of claim 1, further comprising another channel material extending vertically through the additional stack structure and in electrical communication with the channel material.

6. The microelectronic device of claim 5, wherein the channel material is electrically coupled to the other channel material via a conductive material.

7. The microelectronic device of claim 1, wherein the channel material comprises an arcuate surface.

8. The microelectronic device of claim 1, wherein the additional slot structure separates the column of the first pillar.

9. The microelectronic device of claim 1, wherein the horizontal distance between two or more of the first pillars that are horizontally adjacent to each other is greater than the horizontal distance between two or more of the second pillars that are horizontally adjacent to each other.

10. The microelectronic device of claim 1, wherein each of the block structures comprises two columns of the first pillar and two columns of the second pillar between two or more additional slot structures that are horizontally adjacent to each other.

11. A method of forming a microelectronic device, the method comprising: Forming a first stacked structure comprising alternating layers of insulating structures and other insulating structures; Forming a memory cell string comprising at least a dielectric material and a channel material extending vertically through the first stacked structure; A second stacked structure is formed, the second stacked structure comprising alternating layers of additional insulating structures and other additional insulating structures vertically overlaid on the first stacked structure; Forming a first pillar extending through the second stacking structure and vertically covering the first memory cell string in the memory cell string, the center of each of the first pillars being offset from the center of the corresponding memory cell string; A second pillar is formed that extends through the second stack structure and vertically over the second memory cell string in the memory cell string, the center of each of the second pillars being substantially horizontally aligned with the center of the corresponding memory cell string; A slot structure is formed that is horizontally adjacent to the first pillar, the slot structure having a horizontal dimension greater than the horizontal distance between one of the first memory cell strings and one of the second memory cell strings; as well as The slot structure is used to replace the other insulating structures and additional insulating structures to form corresponding conductive structures and additional conductive structures.

12. The method of claim 11, further comprising forming an additional channel material through the first post, the additional channel material being electrically connected to the channel material of the memory cell string to form a channel region comprising the channel material and the additional channel material.

13. The method of claim 12, wherein forming the channel region comprises forming a conductive material, the conductive material comprising doped polysilicon electrically connecting the channel material to the additional channel material.

14. The method of claim 11, wherein forming the slot structure comprises forming a slot structure having a substantially uniform horizontal width, the sides of the slot structure comprising arcuate surfaces.

15. The method of claim 11, wherein forming the slot structure includes forming at least a portion of the slot structure to vertically overlay at least a portion of some of the memory cell strings.

16. The method of claim 11, wherein forming the slot structure includes forming the slot structure to be separated from the second pillar at least by the first pillar.

17. The method of claim 11, wherein forming the second pillar comprises forming one of the second pillars between one of the first pillars and an additional one of the second pillars, the distance between said one of the second pillars and said one of the first pillars being less than the distance between said one of the second pillars and said additional one of the second pillars.

18. A microelectronic device comprising: A memory cell string extending through a first stacked structure comprising alternating conductive and insulating layers, the memory cell string comprising at least a dielectric material and a channel material extending vertically through the first stacked structure; The second stacked structure is vertically superimposed on the first stacked structure; A first pillar extends through the second stacked structure and vertically covers the first memory cell string in the memory cell string, the center of the first pillar being horizontally offset from the center of the first memory cell string in the memory cell string. A second pillar extends through the second stacked structure and vertically covers the second memory cell string in the memory cell string, the center of the second pillar being horizontally aligned with the center of the second memory cell string in the memory cell string; and A slot structure horizontally adjacent to the first pillar, the slot structure having a horizontal dimension greater than the horizontal distance between the first memory cell string and the second memory cell string in the memory cell string.

19. The microelectronic device of claim 18, wherein the slot structure comprises an arcuate shape.

20. The microelectronic device of claim 18, wherein the slot structure is spaced from the second pillar by at least the horizontal dimension of the first pillar.

21. The microelectronic device of claim 18, wherein the slot structure extends between the first pillar and a third pillar vertically overlying a third memory cell string in the memory cell string, the third pillar being horizontally offset from the center of the third memory cell string in the memory cell string.

22. An electronic system comprising: Input device; Output device; A processor device, which is grounded to the input device and the output device; and A memory device, grounded to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: A string of memory cells extends through a first stacked structure comprising alternating layers of insulating and conductive structures; A second stacked structure is vertically superimposed on the first stacked structure, which includes alternating layers of additional insulating and additional conductive structures; A first pillar extends through the second stack structure and vertically covers the first one in the memory cell string, the center of the first pillar being horizontally offset from the center of the first one in the memory cell string; A second pillar extends through the second stack structure and vertically covers the second one in the memory cell string, with the center of the second pillar horizontally aligned with the center of the second one in the memory cell string. A channel region extending through the first stack structure and the memory cell string, having a greater thickness between the first and second stack structures compared to other portions of the channel region; and A slot structure horizontally adjacent to the first pillar, the slot structure having a horizontal dimension greater than the horizontal distance between the first and the second in the memory cell string.

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