A semiconductor device

Abstract

The application discloses a semiconductor device, which comprises an array device and a plurality of rows of source lead-out contacts arranged along a first direction and leading out a source layer. The array device comprises a plurality of channel structures and a plurality of rows of gate line slits extending along the first direction, and two adjacent rows of the gate line slits have a first interval, and two adjacent rows of the source lead-out contacts have a second interval. The second interval is equal to the first interval, so that the position of each source lead-out contact in a memory block is fixed, and the distance between the channel structure around each source lead-out contact and the source lead-out contact is fixed, so that the voltage drop between the channel structure and the source lead-out contact can be prevented from being too large, the voltage drop can be controlled within a smaller range, and the device performance is improved.

Description

Technical Field

[0001] This invention relates generally to electronic devices, and more specifically to a semiconductor device. Background Technology

[0002] In the novel 3D NAND structure, a first silicon substrate is first formed, and multiple array devices, including multiple NAND strings, are formed on the front side of the substrate. An array interconnect layer is then formed on the multiple NAND strings. Simultaneously, a second silicon substrate is formed, and peripheral devices are formed on the second silicon substrate. A peripheral interconnect layer is formed on the peripheral devices. Then, the array devices are inverted, and the array interconnect layer and the peripheral interconnect layer are aligned and combined. Next, the first silicon substrate is removed, and a source layer is formed on the array devices. An N-well pick-up layer (NPU) is formed on the source layer to connect the source terminals. The NPU is then connected to an Al metal layer (connected to external circuitry) to form a diode structure, thereby electrically connecting the array devices to external circuitry for signal transmission.

[0003] The current signal flows from the NAND string to the source layer, and then through the NPU to the external circuit. However, in the existing technology, the voltage drop between the NAND string and the NPU fluctuates too much, which affects the device performance. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device that avoids excessive voltage drop fluctuations between the channel structure and the source lead-out contacts, thereby improving device performance.

[0005] This invention provides a semiconductor device, comprising: An array device includes multiple rows of gate line slots extending in a first direction, multiple channel structures located between two adjacent rows of gate line slots and having a channel layer, and a source layer connected to the channel layer of the multiple channel structures. Multiple source leads are connected to the source layer and arranged in multiple rows along the first direction; There is a first spacing between the gaps of two adjacent rows of gate lines, and a second spacing between two adjacent rows of source lead-out contacts, wherein the second spacing is equal to the first spacing.

[0006] More preferably, the semiconductor device further includes a metal interconnect layer covering the plurality of source lead-out contacts.

[0007] More preferably, the projection of each of the source lead-out contacts in the longitudinal direction is located between the projections of the gaps in the longitudinal direction of the adjacent two rows of gate lines.

[0008] More preferably, the projection of each of the source lead-out contacts in the longitudinal direction is located in the middle of the projection of the gap between two adjacent rows of gate lines in the longitudinal direction.

[0009] More preferably, each of the source lead-out contacts and the gate wire gaps have overlapping portions in their longitudinal projections.

[0010] More preferably, the source lead-out contact is elongated, and the length direction of the source lead-out contact is consistent with the first direction.

[0011] More preferably, the source lead-out contact is elongated, and the width direction of the source lead-out contact is consistent with the first direction.

[0012] More preferably, the source lead-out contacts of different rows are aligned in a second direction, which is perpendicular to the first direction.

[0013] Further preferably, the source lead-out contacts of different rows are staggered in the first direction.

[0014] More preferably, the source lead-out contacts in the same row are evenly spaced along the first direction.

[0015] More preferably, the metal interconnect layer includes a plurality of first traces that extend continuously and are parallel, and a plurality of second traces that connect two adjacent first traces and are perpendicular to the first traces.

[0016] More preferably, the plurality of first traces cover the plurality of source lead-out contacts and extend continuously along the length direction of the source lead-out contacts.

[0017] More preferably, the plurality of second traces cover the plurality of source lead-out contacts, and each of the first traces covers one row of the gate line gaps and extends continuously along the gate line gaps.

[0018] More preferably, the area between two adjacent first traces is a second trace area, and the second traces in two adjacent second trace areas are staggered.

[0019] More preferably, the shape of the source lead-out contact includes a circle or a square.

[0020] More preferably, the gate line slots include at least two rows of first gate line slots and at least one row of second gate line slots located between two adjacent rows of first gate line slots, the first gate line slots dividing the array device into multiple memory blocks, the second gate line slots dividing the memory blocks into multiple finger memory blocks, and the first spacing being the width of the finger memory block.

[0021] More preferably, the plurality of channel structures and the plurality of source lead-out contacts are located on both sides of the source layer in the longitudinal direction.

[0022] The beneficial effects of this invention are as follows: This invention provides a semiconductor device, including an array device and multiple rows of source lead-out contacts arranged along a first direction to lead out the source layer. The array device includes multiple channel structures and multiple rows of gate line slots extending along the first direction. Adjacent rows of gate line slots have a first spacing, and adjacent rows of source lead-out contacts have a second spacing. The second spacing is equal to the first spacing, fixing the position of each source lead-out contact within the memory block. Therefore, the distance from the channel structure surrounding each source lead-out contact to that source lead-out contact is fixed, thereby avoiding excessive voltage drop fluctuations between the channel structure and the source lead-out contacts. This allows the voltage drop to be controlled within a smaller range, improving device performance. Attached Figure Description

[0023] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0024] Figure 1 This is a top view of the semiconductor device provided in the first embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of the semiconductor device provided in the first embodiment of the present invention at A-A1. Figure 3 This is a top view schematic diagram of the semiconductor device provided in the second embodiment of the present invention; Figure 4 This is a top view of a semiconductor device provided in a modified embodiment of the second embodiment of the present invention; Figure 5 This is a top view schematic diagram of a semiconductor device with a metal interconnect layer provided in the second embodiment of the present invention; Figure 6 This is a top view of the semiconductor device provided in the third embodiment of the present invention; Figure 7 This is a top view schematic diagram of a semiconductor device with a metal interconnect layer provided in the third embodiment of the present invention; Figure 8 This is a top view of a semiconductor device provided in a modified embodiment of the third embodiment of the present invention; Figure 9 This is a top view schematic diagram of a semiconductor device with a metal interconnect layer provided in a modified embodiment of the third embodiment of the present invention; Figure 10 This is a top view of the semiconductor device provided in the fourth embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0027] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0028] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0029] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends vertically relative to the substrate. This document uses Cartesian coordinates to represent directions, with the substrate as the reference. The term "first direction" refers to the direction parallel to the substrate, denoted by "X"; the term "longitudinal direction" refers to the direction perpendicular to the substrate and also perpendicular to the X direction, denoted by "Z"; and the term "second direction" refers to the direction perpendicular to both X and Z, that is, parallel to the substrate and perpendicular to the X direction, denoted by "Y".

[0030] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0031] Please see Figure 1 , Figure 1 This is a top view schematic diagram of a semiconductor device provided in the first embodiment of the present invention. The semiconductor device 100 includes an array device, which includes multiple rows of gate line slots 10 extending in a first direction (X), channel structures 11 located between the rows of gate line slots 10, and source layers (not shown) electrically connected to the multiple channel structures 11. The semiconductor device 100 also includes multiple source lead-out contacts 12, which are electrically connected to the source layer and arranged in multiple rows along the first direction (X). It should be noted that the main purpose of the top view schematic diagram of this embodiment is to show the positional distribution of the source lead-out contacts 12. Figure 1 The source layer is not shown in the figure. It is understood that the source layer is located between the channel structure 11 and the source lead-out contacts 12; that is, the channel structure 11 and the plurality of source lead-out contacts 12 are located on opposite sides of the source layer in the longitudinal direction, and the structure of this source layer will be shown in the cross-sectional view below. The semiconductor device 100 also includes a metal interconnect layer (not shown) covering the source lead-out contacts 12 to electrically connect the source lead-out contacts 12 to the metal interconnect layer, thereby enabling electrical connection between the channel structure and external circuitry through the metal interconnect layer.

[0032] In this embodiment, the gate line slot 10 includes at least two rows of first gate line slots 101 and at least one row of second gate line slots 102 located between two adjacent rows of first gate line slots 101. The first gate line slots 101 divide the array device into multiple memory blocks, and the second gate line slots 102 divide the memory blocks into multiple pointer memory blocks G1. The first gate line slots 101 extend continuously in a first direction (X), while the second gate line slots 102 are discontinuous along a second direction (Y), i.e., they are multiple segments of second gate line slots spaced apart.

[0033] In this configuration, source lead-out contacts 12 in the same row are evenly spaced along the first direction (X), while source lead-out contacts 12 in different rows are aligned in the second direction (Y). Adjacent rows of gate line gaps 10 have a first spacing P1 in the second direction (Y) perpendicular to the first direction (X), where the first spacing P1 is actually the width of the memory block G1 in the second direction (Y). Adjacent rows of source lead-out contacts 12 have a second spacing P2 in the second direction (Y).

[0034] Please also refer to Figure 2 , Figure 2 This is a cross-sectional view of the semiconductor device provided in the first embodiment of the present invention along line A-A1. The semiconductor device 100 includes, in the longitudinal direction (Z), a substrate 110, a peripheral interconnect layer 120 on the substrate 110, an array interconnect layer 103 on the peripheral interconnect layer 120, an array device 104 on the array interconnect layer 103, source lead-out contacts 12 on the array device 104, and a metal interconnect layer 105 on the source lead-out contacts 12. The array device 104 includes a stack 1041, a channel structure 11 extending through the stack 1041 in the longitudinal direction (Z), a gate line slot (not shown) extending through the stack 1041 in the longitudinal direction (Z), and a source layer 1042 on the stack 1041 electrically connected to the channel structure 11. Specifically, the source layer 1042 is connected to the channel layer 111 of the channel structure 11. In this embodiment, the metal interconnect layer 105 can be an AL trace, the source layer 1042 can be N-type doped polysilicon, and the stack 1041 is formed by alternating stacks of interlayer insulating layers and interlayer gate layers. The source lead-out contact 12 has a hole-like structure, such as a circle or a square.

[0035] Understandably, current flows from the channel structure 11 to the source layer 1042 and then to the source lead-out contact 12. The distance between the channel structure 11 and the source lead-out contact 12 affects the voltage drop. Since the length of the channel structure 11 and the thickness of the source layer 1042 are constant, the distance from different channel structures 11 to the source lead-out contact 12 is determined by the distance between the channel structure 11 and the source lead-out contact 12 in the XY plane. Figure 1 In this process, the distribution of the source lead-out contact 12 is particularly important.

[0036] like Figure 1 As shown, the first spacing P1 of the memory block G1 and the second spacing P2 of the source lead-out contact 22 are perfectly matched, that is, P1=P2. Therefore, the position of each source lead-out contact 12 in a memory block G1 is the same, so the voltage drop distribution around all source lead-out contacts 12 is the same.

[0037] Furthermore, if the source lead-out contacts 12 and the pointer memory block G1 are projected along the longitudinal direction (Z) onto an XY plane, each row of source lead-out contacts 12 (arranged along the first direction (X)) is located in the middle position of the pointer memory block G1, that is, the source lead-out contacts 12 are located in the middle position of the pointer memory block G1 in the second direction (Y). Therefore, the channel structures 11 around the source lead-out contacts 12 are symmetrically distributed. Since the voltage drop increases with distance, the voltage drop from each source lead-out contact 12 to the surrounding channel structures 11 increases uniformly. More specifically, in a finger memory block G1, the distances from the first row of channel structures 11 and the ninth row of channel structures 11 to the source lead-out contact 12 are the same (same voltage drop), and the distances from the second row of channel structures 11 and the eighth row of channel structures 11 to the source lead-out contact 12 are the same (same voltage drop). Therefore, in each finger memory block G1, the voltage drop also varies uniformly, thereby improving the uniformity of device performance.

[0038] In the semiconductor device 100 provided in the first embodiment of the present invention, the first spacing P1 of the gate line gap 10 is equal to the second spacing P2 of the source lead-out contacts 12, so that the source lead-out contacts 12 with the aperture structure are uniformly distributed in the memory block. The position of each source lead-out contact 12 in the memory block G1 is fixed, so that the voltage drop change around each source lead-out contact 12 is the same, which can make the voltage drop between the source lead-out contact 12 and the channel structure 11 more stable, keep the voltage drop within a small range, and improve device performance. Furthermore, the source lead-out contacts 12 are located in the middle of the memory block G1, so that the channel structure 11 around them is symmetrically distributed, thereby making the voltage drop change uniform, which can improve the uniformity of device performance.

[0039] Please see Figure 3 , Figure 3 This is a top view schematic diagram of a semiconductor device provided in the second embodiment of the present invention. The semiconductor device 200 includes multiple gate line slots 20 extending in a first direction (X) (including a first gate line slot 201 and a second gate line slot 202), a channel structure 21 located between the multiple gate line slots 20, a source layer electrically connected to the channel structure 21, multiple source lead-out contacts 22 located on the source layer, and a metal interconnect layer covering the multiple source lead-out contacts 22. Adjacent rows of gate line slots 20 have a first spacing P3 in the second direction (Y), and adjacent rows of source lead-out contacts 22 have a second spacing P4 in the second direction (Y), and the second spacing P4 is equal to the first spacing P3.

[0040] Preferably, the source lead-out contact 22 is located between the two rows of gate line gaps 20 and is located in the middle of the finger memory block G2 in the second direction (Y). That is, the distance from the source lead-out contact 22 to the upper and lower rows of gate line gaps 20 is equal. Therefore, the channel structure 21 around each source lead-out contact 22 is symmetrically distributed, so that the voltage drop between each source lead-out contact 22 and the surrounding channel structure 21 is uniformly distributed, and the voltage drop in each finger memory block G2 is also uniformly varied, thereby improving the uniformity of the device.

[0041] Preferably, the source lead-out contact 22 is elongated, as can be referred to Figure 2 In the cross-sectional view shown, compared to semiconductor device 100, the source lead-out contact 22 in the semiconductor device 200 of the second embodiment has an increased contact area with the source layer in the first direction (X), thus reducing the voltage drop caused by the resistor and capacitor. Simultaneously, because the source lead-out contact 22 has increased in size in the first direction (X), it is easier to align with the source lead-out contact 22 during subsequent fabrication of the metal interconnect layer, and the effective process window for fabricating the source lead-out contact 22 and the metal interconnect layer is also increased.

[0042] In the second embodiment, the length direction of the source lead-out contact 22 is consistent with the first direction (X), and its width direction is consistent with the second direction (Y). The source lead-out contacts 22 in the same row are evenly distributed along the first direction (X), and the source lead-out contacts 22 in different rows are aligned in the second direction (Y). This ensures that the source lead-out contacts 22 are evenly distributed throughout the memory block, keeping the voltage drop within a small range.

[0043] Please see Figure 4 , Figure 4 This is a top view schematic diagram of a semiconductor device provided in a modified embodiment of the second embodiment of the present invention. The difference between the semiconductor device 200 in this modified embodiment and the second embodiment is that the source leads 22 in different rows are not aligned one-to-one in the second direction (Y). Specifically, the source leads 22 in the second row are staggered relative to the source leads 22 in the first direction (X). Preferably, one source lead 22 in the second row is located exactly in the middle of two adjacent source leads 22 in the first row. Figure 4 As shown, if two adjacent source leads 22 in the first row have an axis of symmetry, then the left and right sides of one source lead 22 in the second row are symmetrical about the axis of symmetry. Therefore, this staggered arrangement of source leads 22 is also uniformly distributed within a memory block, thus avoiding excessive voltage drop fluctuations caused by some channel structures 21 being too far from the source leads 22. Furthermore, the source leads 22 are located in the middle of the finger memory block G2, ensuring a uniform voltage drop across each finger memory block G2, which improves the uniformity of device performance.

[0044] Please combine Figure 5 , Figure 5 This is a top view schematic diagram of a semiconductor device with a metal interconnect layer provided in the second embodiment of the present invention. The semiconductor device 200 further includes a metal interconnect layer 23 covering multiple source lead-out contacts 22. The metal interconnect layer 23 includes multiple continuously extending and parallel first traces 231, and multiple second traces 232 connecting two adjacent first traces 231 and perpendicular to the first traces 231. Therefore, all the metal traces are connected together, and even if one of the first traces 231 breaks at some point, signals can still be transmitted to the broken first trace 231 through the other first traces 231 and second traces 232, improving security.

[0045] In the second embodiment, multiple first traces 231 cover the multiple source lead-out contacts 22 and extend continuously along the length direction of the source lead-out contacts 22. The area between two adjacent first traces 231 is a second trace area, and the second traces 232 in two adjacent second trace areas are staggered. Specifically, the second traces 232 in the second row are located in the middle of the second traces 232 in the first row, so that the metal traces are evenly distributed in the memory block.

[0046] In the semiconductor device 200 provided by the second embodiment and its variations of the present invention, the first spacing P3 between the two rows of gate line gaps 20 is equal to the second spacing P4 between the two rows of source lead-out contacts 22, and the source lead-out contacts 22 are located in the middle of the finger memory block G2, so that the channel structure 21 around each source lead-out contact 22 is symmetrically distributed, thereby the voltage drop around each source lead-out contact 22 varies uniformly, and the voltage drop in each finger memory block G1 also varies uniformly, thereby increasing the uniformity of device performance. In addition, the source lead-out contacts 22 are elongated, which increases the contact area with the source layer in the first direction (X) compared to the semiconductor device 100. Since the contact area is larger, the effective process window can be increased, and the metal interconnect layer 23 and the source lead-out contacts 22 are easier to align, and the voltage drop caused by resistors and capacitors can also be reduced.

[0047] Please see Figure 6 , Figure 6This is a top view schematic diagram of the semiconductor device provided in the third embodiment of the present invention. The semiconductor device 300 includes gate line gaps 30 (including a first gate line gap 301 and a second gate line gap 302), a channel structure 31, a source layer, source lead-out contacts 32, and a metal interconnect layer. The difference between the semiconductor device 300 and the semiconductor device 200 lies in the orientation of the source lead-out contacts 32 within the memory block G3. The length direction of the source lead-out contacts 32 is aligned with the second direction (Y), and its width direction is aligned with the first direction (X). Furthermore, source lead-out contacts 32 in different rows are aligned in the second direction (Y).

[0048] Please see Figure 7 , Figure 7 This is a top view schematic diagram of a semiconductor device with a metal interconnect layer according to a third embodiment of the present invention. For ease of understanding, this semiconductor device 300 uses the same structural reference numerals as the semiconductor device 300 in the third embodiment. The semiconductor device 300 also includes a metal interconnect layer 33 covering a plurality of source lead-out contacts 32. This metal interconnect layer 33 and… Figure 5 The pattern of the intermediate metal interconnect layer 23 is similar, including multiple continuously extending and parallel first traces 331, and multiple second traces 332 connecting two adjacent first traces 331 and perpendicular to the first traces 331. The multiple first traces 331 cover the multiple source lead-out contacts 32 and extend continuously along the length direction of the source lead-out contacts 32. The second traces 332 in adjacent second trace regions are staggered in the second direction (Y).

[0049] Please see Figure 8 , Figure 8 This is a top view schematic diagram of a semiconductor device provided in a variation of the third embodiment of the present invention. For ease of understanding, this semiconductor device 400 uses the same structural reference numerals as the semiconductor device 300 in the third embodiment. The difference between this semiconductor device 400 and the semiconductor device 300 in the third embodiment is that the source lead-out contacts 32 in different rows are staggered in the first direction (X). Preferably, the source lead-out contacts 32 in one row are located exactly in the middle of the source lead-out contacts 32 in the adjacent row, and the source lead-out contacts 32 in the alternate rows are aligned in the second direction (Y), thereby making the source lead-out contacts 32 uniformly distributed in the memory block, thereby controlling the voltage drop within a small range.

[0050] In the third embodiment and its variations, the distance from the channel structure 31 to the source lead-out contact 32 is symmetrical, so the voltage drop varies uniformly, which is beneficial to increasing the uniformity of device performance.

[0051] Please see Figure 9 , Figure 9This is a top view schematic diagram of a semiconductor device with a metal interconnect layer provided in a variation of the third embodiment of the present invention. For ease of understanding, this semiconductor device 400 uses the same structural reference numerals as the semiconductor device 300 in the third embodiment. In the variation of the third embodiment, the metal interconnect layer 33 includes a plurality of continuously extending and parallel first traces 331, and a plurality of second traces 332 connecting two adjacent first traces 331 and perpendicular to the first traces 331. Figure 5 The second embodiment and Figure 7 As can be seen from the third embodiment, the continuously extending first trace 331 is all along the length direction of the source lead-out contact 32. And... Figure 9 In a variation of the third embodiment, continuous first traces 331 extend along the gate line slots 30, with each first trace 331 covering one row of gate line slots 30. Adjacent rows of first traces 331 connect the two ends of the source lead-out contacts 32. Second traces 332 exactly cover the source lead-out contacts 32, and the number of second traces 332 is the same as the number and position of the source lead-out contacts 32, except that the length and width of the second traces 332 are larger than those of the source lead-out contacts 32.

[0052] The semiconductor devices 300 and 400 provided in the third embodiment and its variations of the present invention differ from those in the second embodiment only in the orientation of the source lead-out contact 32, and have the same beneficial effects as the second embodiment, which will not be described in detail here.

[0053] Please see Figure 10 , Figure 10 This is a top view schematic diagram of the semiconductor device provided in the fourth embodiment of the present invention. For ease of understanding, the structural reference numerals in this semiconductor device 500 continue to use the structural reference numerals in the second embodiment 200. The difference between this semiconductor device 500 and semiconductor device 200 is that the source lead-out contact 22 is located directly above the gate line slot 20, or in other words, the source lead-out contact 22 and the gate line slot 20 are located at the same position in the second direction (Y). Specifically, when the source lead-out contact 22 and the gate line slot 20 are projected along the longitudinal direction (Z) onto an XY plane, the source lead-out contact 22 and the gate line slot 20 have overlapping portions.

[0054] In the fourth embodiment, the pattern of the metal interconnect layer is the same as that of the metal interconnect layer 23 in the second embodiment. Figure 5 The pattern of the metal interconnect layer 23 is moved a certain distance in the second direction (Y) so that the metal interconnect layer 23 is moved to a position that coincides with the gate line gap 20, and the metal interconnect layer of the semiconductor device 500 in the fourth embodiment can be obtained.

[0055] In the semiconductor device 500 provided in the fourth embodiment of the present invention, the first spacing P1 between the two rows of gate line gaps 20 is equal to the second spacing P2 between the two rows of source lead-out contacts 22, and the source lead-out contacts 22 are located directly above the gate line gaps 20. Therefore, the channel structures 21 around the source lead-out contacts 22 are symmetrically distributed with uniformly varying distances, resulting in a uniformly varying voltage drop from the channel structures 21 to the source lead-out contacts 22. The voltage drop in each memory block G2 is also uniformly varied, thereby increasing the uniformity of device performance. In addition, since the contact area between the source lead-out contacts 22 and the source layer is increased, the resistance and capacitance are reduced, thus reducing the voltage drop. At the same time, the effective process window is increased, making it easier to align the metal interconnect layer with the source lead-out contacts 22 when forming the metal interconnect layer, so that the metal interconnect layer can completely cover the source lead-out contacts 22.

[0056] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include: An array device includes multiple channel structures and a source layer connected to the multiple channel structures; Multiple rows of gate line slots extending along a first direction parallel to the source layer; Multiple source lead-out contacts are connected to the source layer and are located on both sides of the multiple channel structures, respectively; the multiple source lead-out contacts include a first source lead-out contact and a second source lead-out contact; the orthographic projection of the surface of the first source lead-out contact in contact with the source layer is located between the orthographic projections of two adjacent rows of gate line gaps on the source layer, and the first source lead-out contact overlaps with the multiple channel structures; The orthographic projection of the surface of the second source lead-out contact that contacts the source layer on the source layer is located between the orthographic projections of the two adjacent rows of gate line slots on the source layer.

2. The semiconductor device according to claim 1, characterized in that, The plurality of source leads are arranged in a row along the first direction, and the source leads in the same row are distributed at equal intervals along the first direction.

3. The semiconductor device according to claim 1, characterized in that, The plurality of source leads are arranged in a row along the first direction, and the plurality of source leads are arranged in multiple rows along a second direction perpendicular to the first direction, and there is a second spacing between adjacent rows of source leads.

4. The semiconductor device according to claim 3, characterized in that, There is a first spacing between the gaps of two adjacent rows of grid lines, and the first spacing is equal to the second spacing.

5. The semiconductor device according to claim 3 or 4, characterized in that, The source lead-out contacts of different rows are staggered in the first direction.

6. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the surface of each source lead-out contact that contacts the source layer on the source layer is located at the exact midpoint of the orthographic projection of the gaps between two adjacent rows of gate lines on the source layer.

7. The semiconductor device according to claim 1, characterized in that, The source lead-out contact is elongated, and the length direction of the source lead-out contact is consistent with the first direction parallel to the source layer.

8. The semiconductor device according to claim 1, characterized in that, The source lead-out contact is elongated, and the width direction of the source lead-out contact is consistent with the first direction parallel to the source layer.

9. The semiconductor device according to claim 7 or 8, characterized in that, The source lead-out contacts are aligned in a second direction, which is perpendicular to the first direction and parallel to the source layer.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a metal interconnect layer covering the plurality of source lead-out contacts.

11. The semiconductor device according to claim 10, characterized in that, The metal interconnect layer includes a plurality of first traces that extend continuously and are parallel to each other, and a plurality of second traces that connect two adjacent first traces and are perpendicular to the first traces.

12. The semiconductor device according to claim 11, characterized in that, The multiple first traces cover the multiple source lead-out contacts and extend continuously along the length direction of the source lead-out contacts.

13. The semiconductor device according to claim 11, characterized in that, The plurality of second traces cover the plurality of source lead-out contacts, and each of the first traces covers one row of the gate line gaps and extends continuously along the gate line gaps.

14. The semiconductor device according to claim 11, characterized in that, The area between two adjacent first routing lines is the second routing area, and the second routing lines in two adjacent second routing areas are staggered.

15. The semiconductor device according to claim 1, characterized in that, The source lead-out contact is circular or square in shape.

16. The semiconductor device according to claim 4, characterized in that, The gate line slots include at least two rows of first gate line slots and at least one row of second gate line slots located between two adjacent rows of first gate line slots. The first gate line slots divide the array device into multiple memory blocks, and the second gate line slots divide the memory blocks into multiple finger memory blocks. The first spacing is the width of the finger memory block.

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