Three-dimensional storage devices and their manufacturing methods

Abstract

This invention provides a three-dimensional memory device and a method for manufacturing the same. The method includes: providing a substrate on which a stacked structure is formed, the stacked structure including alternating layers of polysilicon and insulating layers; forming a channel hole through the stacked structure along the thickness direction of the substrate, the inner wall of the channel hole including a first interface and a second interface; forming metal silicides on both radial sides of the channel hole using the polysilicon layers; removing the metal silicides to form a groove, and forming a barrier layer on the surface of the groove and on the first interface; depositing a charge trapping layer on the barrier layer to fill the groove, and forming an opening corresponding to the groove on the surface of the charge trapping layer; forming a mask in the opening to remove excess charge trapping layer through the mask, and forming unit charge trapping layers spaced apart from each other along the thickness direction. Because the unit charge trapping layers are spaced apart along the thickness direction, electrons can be prevented from drifting or diffusing along the axial direction of the channel hole.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a three-dimensional storage device and its manufacturing method. Background Technology

[0002] As the demand for memory capacity continues to increase, and given that two-dimensional memory devices are nearing their practical expansion limits, the industry has proposed 3D NAND memory to further improve storage capacity and reduce the cost per bit. Current designs for 3D NAND memory use a concentric circle structure. Typically, a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer are sequentially filled inside the channel vias, and finally, a dielectric layer is filled inside the concentric circles, thus forming a continuous charge trapping memory from top to bottom.

[0003] However, in existing 3D NAND memories, some electrons in the charge trapping layer are lost during data retention due to axial drift or diffusion along the channel aperture, and this loss becomes more significant over time or as the channel length shortens, leading to reduced reliability of 3D memory devices. Summary of the Invention

[0004] This invention provides a three-dimensional storage device and its manufacturing method, aiming to solve the problem of electron loss due to axial drift or diffusion along the channel hole in the three-dimensional storage device, thereby improving the reliability of the three-dimensional storage device.

[0005] In a first aspect, the present invention provides a method for manufacturing a three-dimensional memory device, comprising: providing a substrate on which a stacked structure is formed, the stacked structure comprising alternating layers of polysilicon and insulating layers; forming a channel hole through the stacked structure along the thickness direction of the substrate, the inner wall of the channel hole comprising a first interface and a second interface intersecting the channel hole with the insulating layer and the polysilicon layer respectively; forming metal silicides on both radial sides of the channel hole using the polysilicon layers; removing the metal silicides to form grooves on both radial sides at the second interface, and forming a barrier layer on the surface of the grooves and on the first interface; depositing a charge trapping layer on the surface of the barrier layer to fill the grooves, and forming an opening corresponding to the grooves on the surface of the charge trapping layer; forming a mask in the openings to remove excess charge trapping layers outside the grooves through the mask, and forming unit charge trapping layers spaced apart from each other along the thickness direction; removing the mask, and sequentially forming a tunneling layer, a channel layer, and a dielectric layer filling the channel hole on the surfaces of the barrier layer and the unit charge trapping layers.

[0006] The step of forming metal silicides on both radial sides of the channel hole using the polysilicon layer includes: forming a metal layer on the inner wall of the channel hole; annealing the metal layer and the polysilicon layer to form the metal silicide; and removing the unreacted remaining metal layer on the inner wall of the channel hole.

[0007] The step of forming a mask in the opening to remove excess charge trapping layers outside the groove using the mask as a mask, and forming unit charge trapping layers spaced apart from each other along the thickness direction, includes: depositing a sacrificial layer filling the opening on the charge trapping layer; etching back the sacrificial layer to remove excess sacrificial layers outside the opening, retaining the remaining sacrificial layer inside the opening as the mask; and using the mask as a mask to remove excess charge trapping layers outside the groove to form the unit charge trapping layers.

[0008] The method further includes, after forming a channel hole through the stacked structure along the thickness direction of the substrate, forming an epitaxial layer at the bottom of the channel hole and forming a supplementary insulating layer on the epitaxial layer.

[0009] The step of forming a barrier layer on the surface of the groove and the first interface includes: depositing a silicon nitride layer on the surface of the groove and the first interface; and oxidizing the silicon nitride layer to form the barrier layer.

[0010] The metal layer is made of one or more of cobalt, titanium, and nickel.

[0011] The material of the mask includes polycrystalline silicon.

[0012] In a second aspect, the present invention also provides a three-dimensional memory device, comprising: a substrate; a stacked structure located on the substrate, the stacked structure including alternately stacked polysilicon gate layers and insulating layers; a channel hole penetrating the stacked structure along the thickness direction of the substrate, the inner wall of the channel hole including a first interface and a second interface intersecting the channel hole with the insulating layer and the polysilicon gate layer respectively, the stacked structure having a groove at the second interface; a barrier layer located on the surface of the groove and on the first interface; a unit charge trapping layer located on the surface of the barrier layer, filling the groove and spaced apart from each other in the thickness direction; a tunneling layer located on the surface of the barrier layer and the unit charge trapping layer; a channel layer located on the surface of the tunneling layer; and a dielectric layer located on the surface of the channel layer and filling the channel hole.

[0013] The three-dimensional storage device further includes: an epitaxial layer located at the bottom of the channel hole and a supplementary insulating layer located on the epitaxial layer.

[0014] The thickness of the polycrystalline silicon gate layer is greater than 16.5 nm.

[0015] The difference between the thickness of the polysilicon gate layer and the thickness of the unit charge trapping layer is twice the thickness of the barrier layer.

[0016] In the three-dimensional storage device and its manufacturing method provided by the present invention, a metal silicide is formed using a polysilicon layer, and the metal silicide is removed to form a groove capable of accommodating a unit charge trapping layer. Since the corresponding groove is separated in the thickness direction, the adjacent two unit charge trapping layers are also separated in the thickness direction, thereby preventing electrons in the charge trapping layer from drifting or diffusing along the axial direction of the channel hole, thus improving the data retention capability of the three-dimensional storage device and improving the reliability of the three-dimensional storage device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of the three-dimensional storage device manufacturing method provided in an embodiment of the present invention;

[0019] Figures 2A-2M This is a cross-sectional structural diagram of the three-dimensional storage device provided in the embodiments of the present invention at each stage of the manufacturing method.

[0020] Figure 3 This is a flowchart illustrating step S13 provided in an embodiment of the present invention;

[0021] Figure 4 This is a flowchart illustrating step S16 provided in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0026] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0027] Please see Figure 1 , Figure 1 This is a schematic flowchart of the manufacturing method of the three-dimensional storage device provided in the embodiment of the present invention, as shown below. Figure 1 As shown, the manufacturing method may specifically include the following steps:

[0028] Step S11: Provide a substrate on which a stacked structure is formed, the stacked structure comprising alternating layers of polysilicon and insulating layers.

[0029] The cross-sectional structure diagram of the three-dimensional storage device after step S11 is shown below. Figure 2A As shown.

[0030] Specifically, the substrate 10 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). In the stacked structure 20, the insulating layer 21 can be made of silicon oxide or other high-k dielectric layers. The formation process of the insulating layer 21 on the substrate 10 is preferably chemical vapor deposition (CVD). Further, when the insulating layer 21 is silicon oxide, a tetraethyl orthosilicate (TEOS) / ozone (O3) system can be used in the CVD process to precipitate and form the corresponding silicon oxide film. The polycrystalline silicon layer 22 can be formed on the insulating layer 21 using atomic layer deposition (ALD) or CVD processes. The thickness of the polycrystalline silicon layer 22 deposited in the z-direction is greater than 16.5 nm. In this embodiment of the invention, the polysilicon layer 22 does not need to be replaced with a metal gate in subsequent processes and can be directly used as the gate in the three-dimensional memory device. Therefore, the process steps for forming the gate in the three-dimensional memory device can be reduced. At the same time, since it is not necessary to replace the polysilicon layer with a metal gate layer, the porosity defects caused by the replacement process are avoided, thereby improving the structural stability of the three-dimensional memory device. Furthermore, since there are more defects at the metal-insulator interface, it is easy to form more surface energy levels between the two, affecting the device characteristics. In contrast, the Si-SiO2 interface has fewer defects. Relatively speaking, choosing a polysilicon layer as the gate layer can further improve the characteristics of the three-dimensional memory device. In addition, in semiconductor manufacturing processes, gate materials need to be deposited at high temperatures to improve device performance. When polysilicon is used as the gate layer, since the melting point of polysilicon is higher than that of most metals, it will not affect the upper limit of the temperature range that can be used in the process.

[0031] Step S12: Form a channel hole through the stacked structure along the thickness direction of the substrate. The inner wall of the channel hole includes a first interface and a second interface where the channel hole intersects with the insulating layer and the polysilicon layer, respectively.

[0032] The cross-sectional structure diagram of the three-dimensional storage device after step S12 is shown below. Figure 2B As shown.

[0033] Specifically, such as Figure 2B As shown, the thickness direction of the substrate 10 is... Figure 2BThe z-direction. In this embodiment, the channel hole 30 can be formed by photolithography. For example, a photoresist layer can be first covered on the stacked structure 20, and then a mask defining the position of the channel hole 30 can be used for exposure. Then, a corresponding etching process can be used to etch the stacked structure 20 to form the channel hole 30. The inner wall 300 of the channel hole 30 includes a first interface 301 where the channel hole 30 intersects with the insulating layer 21 and a second interface 302 where the channel hole 30 intersects with the polysilicon layer 22.

[0034] After step S12, the following process steps may also be included: forming an epitaxial layer at the bottom of the channel hole; forming a supplementary insulating layer on the epitaxial layer.

[0035] Specifically, such as Figure 2B As shown, during the etching of the stacked structure 20, the channel via 30 can be selectively extended to the substrate 10 and a portion of the substrate 10 can be etched to form a trench 101 on the substrate 10. The trench 101 is located at the bottom of the channel via 30. Then, as... Figure 2C As shown, an epitaxial layer 11 and a supplementary insulating layer 12 are sequentially formed on the surface of the substrate 10 exposed by the trench 101 using a selective epitaxial growth (SEG) process. The supplementary insulating layer 12 can be formed by directly oxidizing the epitaxial layer 11.

[0036] Step S13: Use the polysilicon layer to form metal silicides on both sides of the channel hole in the radial direction.

[0037] This metal silicide can be formed by reacting a metal with polycrystalline silicon through an annealing process, specifically, as shown in... Figure 3 As shown, step S13 may specifically include:

[0038] Step S131: Form a metal layer on the inner wall of the channel hole.

[0039] The cross-sectional structure diagram of the three-dimensional storage device after step S131 is shown below. Figure 2D As shown. In this embodiment, a metal layer 40 can be deposited on the inner wall 300 of the channel hole 30 by an ALD (Atomic Layer Deposition) process. The material of the metal layer 40 includes, but is not limited to, one or more combinations of cobalt, titanium and nickel, and the metal layer 40 can be further divided into a partial metal layer covering the first interface 301 and a partial metal layer covering the second interface 302.

[0040] Step S132: Anneal the metal layer and the polysilicon layer to form the metal silicide.

[0041] The cross-sectional structure diagram of the three-dimensional storage device after step S132 is shown below. Figure 2E As shown, after step S132 is completed, a portion of the metal layer on the second interface 302 reacts with the polycrystalline silicon layer 22 to form a layer as shown in the figure. Figure 2E The metal silicide 42 shown is distributed on both sides of the channel hole 30 in the radial direction, that is, the metal silicide 42 is distributed along... Figure 2E The x-direction is distributed on both sides of the channel hole 30.

[0042] Step S133: Remove the unreacted residual metal layer on the inner wall of the channel hole.

[0043] The cross-sectional structure diagram of the three-dimensional storage device after step S132 is shown below. Figure 2F As shown. In this embodiment, the formation process of the metal silicide 42 is a self-aligned silicide process, that is, the metal silicide 42 is formed by using a metal layer 40 (such as cobalt / titanium / nickel) and a polycrystalline silicon layer 22 in direct contact, and the metal layer 40 does not react with the insulating layer 21 (such as silicon oxide) under a certain annealing process, thereby achieving self-alignment.

[0044] It should be further explained that, considering that forming metal silicide 42 through a single rapid thermal annealing (RTA) process requires excessively high process temperatures, silicon will diffuse along the grain boundaries of the metal silicide formed during the reaction, leading to overgrowth of metal silicide at the interface of the insulating layer 21. This results in the formation of metal silicide on the insulating layer 21 as well, thus preventing self-alignment. Therefore, in this embodiment, the annealing process includes two consecutive rapid thermal annealing (RTA) processes. The reaction temperature of the first RTA is set to 450–650°C, and the reaction temperature of the second RTA is set to greater than 750°C. Through these two RTA processes, metal silicide 42 is formed only at the second interface 302, achieving self-alignment.

[0045] In this embodiment, the unreacted residual metal layer 40' can be removed by a wet etching process. Specifically, a highly selective etching solution (a mixture of NH4OH / H2O2 / H2O or H2SO4 / H2O2) can be used to etch the residual metal layer 40'.

[0046] Step S14: Remove the metal silicide to form grooves on both radial sides at the second interface, and form a barrier layer on the surface of the grooves and the first interface.

[0047] In this embodiment, a wet etching process can be used to remove the metal silicide 42. Specifically, a mixed reagent of nitric acid, hydrochloric acid, and hydrofluoric acid can be used to etch and remove the metal silicide 42, thereby forming a structure as shown in the figure. Figure 2G The groove 32 shown is followed by the formation of a barrier layer 50 on the surface of the groove 32 and the first interface 301. Specifically, the barrier layer 50 can be formed by first depositing a silicon nitride layer on the surface of the groove 32 and the first interface 301 using an ALD process, and then oxidizing the silicon nitride layer to form the barrier layer 50 using a thermal oxidation process. A cross-sectional view of the three-dimensional memory device after step S14 is shown below. Figure 2H As shown.

[0048] Step S15: Deposit a charge trapping layer on the surface of the barrier layer to fill the groove, and form an opening on the surface of the charge trapping layer corresponding to the groove.

[0049] The cross-sectional structure diagram of the three-dimensional storage device after step S15 is shown below. Figure 2I As shown.

[0050] Specifically, a charge trapping layer 60 can be formed on the surface of the barrier layer 50 using an ALD process to fill the area. Figure 2H The groove 32 shown is filled with a charge trapping layer 60 made of silicon nitride. It should be further explained that the process of filling the groove 32 is actually a process of the charge trapping layers 60 fusing together within the groove 32. Due to the ALD process and the geometric effects of the groove 32, after filling the groove 32, an opening 36 corresponding to the groove 32 spontaneously forms on the surface of the charge trapping layer 60. The position of this opening 36 continuously shifts from within the groove 32 along the x-direction outwards during the ALD process, thus allowing the desired effect to be achieved by controlling the timing of the ALD process. Figure 2I The opening 36 shown is completely outside the groove 32. In other embodiments of the invention, the timing of the ALD process can be controlled so that part or all of the opening 36 is inside the groove 32.

[0051] Step S16: A mask body is formed in the opening to remove excess charge trapping layers outside the groove through the mask body, and unit charge trapping layers spaced apart from each other along the thickness direction are formed.

[0052] In this embodiment, by removing the excess charge trapping layer outside the groove 32, the adjacent two unit charge trapping layers 61 are separated in the z direction, thereby preventing electrons in the unit charge trapping layer 61 from drifting or diffusing in the z direction, thus improving the data retention capability of the three-dimensional storage device and improving the reliability of the three-dimensional storage device.

[0053] Please see Figure 4 Specifically, step S16 may include:

[0054] Step S161: Deposit a sacrificial layer that fills the opening on the charge trapping layer.

[0055] The cross-sectional structure diagram of the three-dimensional storage device after step S161 is shown below. Figure 2J As shown. In this embodiment, the material of the sacrificial layer 70 can be selected as polycrystalline silicon, and it can be deposited on the charge trapping layer 60 using an ALD process to form a layer that fills the opening 36 (in). Figure 2I The sacrificial layer 70 (as shown in the diagram) is relatively thicker at the opening 36.

[0056] Step S162: Etch back the sacrificial layer to remove excess sacrificial layer outside the opening, and retain the remaining sacrificial layer inside the opening as the mask.

[0057] The cross-sectional structure diagram of the three-dimensional storage device after step S161 is shown below. Figure 2K As shown. In this embodiment, when the material of the sacrificial layer 70 can be selected as polycrystalline silicon, the sacrificial layer 70 can be etched back and forth with a tetramethylammonium hydroxide (TMAH) solution. Under the same process conditions, since the sacrificial layer 70 located at the opening 36 is thicker, when the excess sacrificial layer outside the opening 36 is removed, the remaining sacrificial layer inside the opening 36 serves as a mask 71.

[0058] Step S163: Using the mask as a mask, remove the excess charge trapping layer outside the groove to form the unit charge trapping layer.

[0059] The cross-sectional structure diagram of the three-dimensional storage device after step S163 is shown below. Figure 2L As shown, the position of the mask 71 is defined according to the position of the opening 36. In this embodiment, since the opening 36 can be made to appear as shown by controlling the ALD process time in step S15, Figure 2I As shown, it is completely outside the groove 32, therefore, as Figure 2K As shown, the mask 71 can be formed outside the groove 32. In other embodiments of the invention, the mask 71 can be formed inside the groove 32 when the timing of the ALD process is controlled such that the opening 36 is located inside the groove 32.

[0060] In this embodiment, since the sacrificial layer 70 is made of polycrystalline silicon and the charge trapping layer 60 is made of silicon nitride, the groove 32 can be etched using a selective etching solution such as phosphoric acid solution. Figure 2GThe excess charge trapping layer (as shown in the diagram) is used to form the unit charge trapping layer 61. Since the phosphoric acid solution does not react with the polycrystalline silicon material, the mask 71 can protect the unit charge trapping layer in the groove 32. The unit charge trapping layer 61 has a thickness of 11-15 nm along the z-direction and a width of 5-9 nm along the x-direction.

[0061] Step S17: Remove the mask and sequentially form a tunneling layer, a channel layer, and a dielectric layer filling the channel holes on the surfaces of the blocking layer and the unit charge trapping layer.

[0062] The cross-sectional structure diagram of the three-dimensional storage device after step S17 is shown below. Figure 2M As shown.

[0063] Specifically, when the material of the sacrificial layer 70 is selected as polycrystalline silicon, the mask 71 ( Figure 2K The material (as shown in the diagram) is also polycrystalline silicon. Therefore, the mask 71 can be selectively removed using a TMAH solution. Then, a tunneling layer 80 and a channel layer 90 are sequentially formed on the surfaces of the barrier layer 50 and the unit charge trapping layer 61 using an ALD or CVD process. Next, a dielectric layer 31 is selectively filled into the channel hole 30 using a CVD or ALD process. Finally, a planarization process is used to make the film layer within the channel hole 30 flush with the stacked structure 20. In this embodiment, the material of the tunneling layer 80 is silicon oxide, and the thickness of the tunneling layer 80 is selected to be 5–9 nm. The material of the channel layer 90 is polycrystalline silicon, and the thickness of the channel layer 90 is selected to be 7–11 nm. The material of the dielectric layer 31 is an insulating material, such as silicon oxide.

[0064] like Figure 2M As shown, this embodiment of the invention also provides a three-dimensional storage device 100, which can be formed by the above-described manufacturing method. Therefore, the formation process of this three-dimensional storage device 100 can be referred to... Figures 2A to 2M .like Figure 2M As shown, the three-dimensional memory device 100 includes a substrate 10, a stacked structure 20, a channel hole, a barrier layer 50, a unit charge trapping layer 61, a tunneling layer 80, a channel layer 90, and a dielectric layer 31. Since the channel hole is filled with a material such as the dielectric layer 31, the channel hole... Figure 2M Not shown in the image; please refer to the image for its specific shape. Figure 2G .

[0065] like Figure 2M As shown, the stacked structure 20 includes alternating layers of polysilicon gate layer 22 and insulating layer 21. (As...) Figure 2GAs shown, the channel hole 30 penetrates the stacked structure 20 along the thickness direction (z-direction) of the substrate 10. The inner wall 300 of the channel hole 30 includes a first interface 301 and a second interface 302' where the channel hole 30 intersects with the insulating layer 21 and the polysilicon gate layer 22, respectively. The stacked structure 20 has a groove 32 at the second interface 302'. A barrier layer 50 is located on the surface of the groove 32 and on the first interface 301. A unit charge trapping layer 61 is located on the surface of the barrier layer 50, fills the groove 32, and is spaced apart from each other in the z-direction. A tunneling layer 80 is located on the surfaces of the barrier layer 50 and the unit charge trapping layer 61. A channel layer 90 is located on the surface of the tunneling layer 80. A dielectric layer 31 is located on the surface of the channel layer 90 and fills the channel hole 30.

[0066] Specifically, the substrate 10 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). In the stacked structure 20, the insulating layer 21 can be made of silicon oxide or other high-k dielectric layers, and the polysilicon gate layer 22 has a thickness greater than 16.5 nm. The tunneling layer 80 is made of silicon oxide and has a thickness of 5–9 nm; the channel layer 90 is made of polysilicon and has a thickness of 7–11 nm. The thicknesses of the tunneling layer 80 and the channel layer 90 refer to their radial thickness along the channel via 30. The dielectric layer 31 is made of an insulating material, such as silicon oxide. The unit charge trapping layer 61 is made of silicon nitride and has a thickness of 11–15 nm and a width of 5–9 nm, which is the radial width along the channel via 30.

[0067] It should be further explained that, due to the numerous defects at the metal-insulator interface, many surface energy levels can easily form between the two, affecting device characteristics. In contrast, the Si-SiO2 interface has fewer defects. Therefore, choosing a polysilicon gate layer 22 can further improve the characteristics of the three-dimensional memory device. Furthermore, in semiconductor manufacturing processes, gate materials need to be deposited at high temperatures to improve device performance. When polysilicon is used as the gate layer, its higher melting point than most metals will not affect the upper temperature limit of the process.

[0068] The difference between the thickness of the polysilicon gate layer 22 and the thickness of the unit charge trapping layer 61 is twice the thickness of the barrier layer 50. For example, the thickness of the polysilicon gate layer 22 can be 20 nm, the thickness of the unit charge trapping layer 61 can be 13 nm, and the thickness of the barrier layer 50 is 3.5 nm.

[0069] The three-dimensional storage device 100 also includes an epitaxial layer 11 located at the bottom of the channel hole and a supplementary insulating layer located on the epitaxial layer. Figure 2C(As shown in the image).

[0070] In the three-dimensional storage device 100 provided by the present invention, two adjacent unit charge trapping layers 61 are separated in the z direction, thereby preventing electrons in the charge trapping layer from drifting or diffusing in the z direction, thereby improving the data retention capability of the three-dimensional storage device and improving the reliability of the three-dimensional storage device.

[0071] In the three-dimensional memory device and its manufacturing method provided by the present invention, by directly using a polysilicon layer as the gate layer, there is no need to replace the polysilicon layer with a metal gate layer, thus avoiding the porosity defects caused by the replacement process. Then, a metal silicide is formed using the polysilicon layer, and the metal silicide is removed to form a groove that can accommodate the unit charge trapping layer. Since the corresponding groove is separated in the thickness direction, the adjacent two unit charge trapping layers are also separated in the thickness direction, thereby preventing electrons in the charge trapping layer from drifting or diffusing along the axial direction of the channel hole, thereby improving the data retention capability of the three-dimensional memory device and improving the reliability of the three-dimensional memory device.

[0072] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.

[0073] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a three-dimensional storage device, characterized in that, include: A substrate is provided on which a stacked structure is formed, the stacked structure comprising alternating layers of polysilicon and insulating layers; A channel hole is formed along the thickness direction of the substrate, penetrating the stacked structure. The inner wall of the channel hole includes a first interface and a second interface where the channel hole intersects with the insulating layer and the polysilicon layer, respectively. A metal layer is formed on the inner wall of the channel hole; Anneal the metal layer and the polysilicon layer to form the metal silicide; Remove the unreacted residual metal layer on the inner wall of the channel hole to form metal silicides located on both radial sides of the channel hole; The metal silicide is removed to form grooves on both radial sides at the second interface, and a barrier layer is formed on the surface of the grooves and on the first interface. A charge trapping layer is deposited on the surface of the barrier layer to fill the groove, and an opening corresponding to the groove is formed on the surface of the charge trapping layer; A mask is formed in the opening to remove excess charge trapping layers outside the groove through the mask, and unit charge trapping layers spaced apart from each other along the thickness direction are formed. The mask is removed, and a tunneling layer, a channel layer, and a dielectric layer filling the channel holes are sequentially formed on the surfaces of the blocking layer and the unit charge trapping layer.

2. The method for manufacturing a three-dimensional storage device according to claim 1, characterized in that, The step of forming a mask body in the opening to remove excess charge trapping layers outside the groove through the mask body as a mask, and forming unit charge trapping layers spaced apart from each other along the thickness direction, includes: A sacrificial layer is deposited on the charge trapping layer to fill the opening; The sacrificial layer is etched back to remove excess sacrificial layer outside the opening, while the remaining sacrificial layer inside the opening is retained as the mask. Using the mask as a mask, excess charge trapping layer outside the groove is removed to form the unit charge trapping layer.

3. The method for manufacturing a three-dimensional storage device according to claim 1, characterized in that, After forming a channel hole through the stacked structure along the thickness direction of the substrate, the method further includes: An epitaxial layer is formed at the bottom of the channel hole; A supplementary insulating layer is formed on the epitaxial layer.

4. The method for manufacturing a three-dimensional storage device according to claim 1, characterized in that, The formation of a barrier layer on the surface of the groove and the first interface includes: A silicon nitride layer is deposited on the surface of the groove and the first interface; The silicon nitride layer is oxidized to form the barrier layer.

5. The method for manufacturing a three-dimensional storage device according to claim 1, characterized in that, The material of the metal layer includes one or more of cobalt, titanium, and nickel.

6. The method for manufacturing a three-dimensional storage device according to claim 1, characterized in that, The material of the mask includes polycrystalline silicon.

7. A three-dimensional storage device, characterized in that, include: Substrate; A stacked structure located on the substrate, the stacked structure comprising alternating layers of polysilicon gate layers and insulating layers; A channel hole extends through the stacked structure along the thickness direction of the substrate. The inner wall of the channel hole includes a first interface and a second interface where the channel hole intersects with the insulating layer and the polysilicon gate layer, respectively. The stacked structure has a groove at the second interface. A barrier layer located on the surface of the groove and on the first interface; Unit charge trapping layers located on the surface of the barrier layer, filling the grooves and spaced apart from each other in the thickness direction; A tunneling layer located on the surface of the barrier layer and the unit charge trapping layer; The channel layer located on the surface of the tunneling layer; A dielectric layer located on the surface of the channel layer and filling the channel holes.

8. The three-dimensional storage device according to claim 7, characterized in that, The three-dimensional storage device further includes: An epitaxial layer located at the bottom of the channel hole and a supplementary insulating layer located on the epitaxial layer.

9. The three-dimensional storage device according to claim 7, characterized in that, The thickness of the polysilicon gate layer is greater than 16.5 nm.

10. The three-dimensional storage device according to claim 7, characterized in that, The difference between the thickness of the polysilicon gate layer and the thickness of the unit charge trapping layer is twice the thickness of the barrier layer.

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