Array substrate, digital x-ray detector comprising same, and manufacturing method thereof

Abstract

An array substrate, a digital X-ray detector containing the array, and a method for manufacturing the same substrate are disclosed. Instead of using separate masking processes, the lower electrode of a PIN diode and a second protective layer covering the PIN diode are formed using the same mask and the same masking process, thereby reducing the number of masking processes and improving process efficiency. Furthermore, the lower electrode of the PIN diode is patterned, and then the second protective film covering the PIN diode is patterned, allowing for both pre-patterning and post-patterning to be performed using a single masking process, thereby reducing the increase in defects due to foreign matter or contaminants.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing an array substrate for a digital X-ray detector that can reduce the number of masking steps to improve process efficiency and reduce the degradation of thin-film transistors, an array substrate for a digital X-ray detector manufactured by the method, and a digital X-ray detector comprising the array substrate. Background Technology

[0002] Because X-rays have short wavelengths, they can easily pass through objects. The transmittance of X-rays depends on the internal density of the object. Therefore, the internal structure of an object can be observed by detecting the transmittance of X-rays as they pass through it.

[0003] One X-ray-based examination method used in the medical field is film printing. However, in film printing, images are taken and then printed to view the results. Therefore, viewing the results takes a long time. In particular, storing and protecting the printed film presents many difficulties in film printing.

[0004] Recently, digital X-ray detectors (DXD) using thin-film transistors have been developed and are widely used in the medical field.

[0005] Digital X-ray detectors detect the transmittance of X-rays through an object and display the object's internal state on a monitor based on the transmittance.

[0006] Therefore, digital X-ray detectors can display the internal structure of an object without using separate film and printing paper. Furthermore, DXD has the advantage of allowing real-time viewing of the results immediately after X-ray imaging. Summary of the Invention

[0007] Digital X-ray detectors are formed by stacking various elements such as thin-film transistors and PIN diodes, along with various protective layers made of organic or inorganic materials, in a predetermined pattern.

[0008] Specifically, each layer can be formed by depositing materials such as metals, organic materials, and inorganic materials, and by performing a patterned mask process using a photolithography process with a mask having a predetermined pattern.

[0009] Since digital X-ray detectors are formed by stacking layers with various patterns on top of each other, multiple masking processes using multiple masks with different patterns should be included.

[0010] In this case, the number of masking processes should correspond to the number of masks. Therefore, as the number of masks to be used increases, the number of masking processes to be performed should increase accordingly.

[0011] As the number of masking processes increases in this way, process time and process cost increase, and therefore process efficiency decreases.

[0012] Specifically, when a subsequent process is not performed immediately after the completion of the current single process, the increased waiting time increases the likelihood of foreign objects or stains appearing on the workpiece, leading to an increase in defects.

[0013] In addition, large amounts of hydrogen (H) may be generated during the deposition of materials such as metals, organic materials and inorganic materials.

[0014] When the generated hydrogen is retained in the thin-film transistor (specifically, the active layer made of oxide semiconductor material), a negative shift of the thin-film transistor may occur, leading to a problem of deterioration in electrical characteristics.

[0015] Specifically, regarding digital X-ray detectors, a large amount of hydrogen is generated during the process of forming PIN diodes (especially PIN layers).

[0016] Therefore, after forming the PIN layer of the PIN diode, it is necessary to effectively remove excess hydrogen from the thin-film transistor to the outside.

[0017] Therefore, the inventors of this disclosure have invented a method for manufacturing an array substrate for a digital X-ray detector that can reduce the number of masking steps to improve process efficiency and reduce the degradation of thin-film transistors, an array substrate for a digital X-ray detector manufactured by this method, and a digital X-ray detector comprising the array substrate.

[0018] An objective of one embodiment of this disclosure is to provide a method for manufacturing an array substrate for a digital X-ray detector that can improve process efficiency by reducing the number of masking steps, an array substrate for a digital X-ray detector manufactured by the method, and a digital X-ray detector comprising the array substrate.

[0019] The object of one embodiment of this disclosure is to provide a method for manufacturing an array substrate for a digital X-ray detector that can reduce process wait time, thereby reducing the increase in defects due to foreign matter or contamination, an array substrate for a digital X-ray detector manufactured by the method, and a digital X-ray detector comprising the array substrate.

[0020] An objective of one embodiment of this disclosure is to provide a method for manufacturing an array substrate for a digital X-ray detector that enables uniform panel characteristics to be achieved while performing multiple masking processes, an array substrate for a digital X-ray detector manufactured by this method, and a digital X-ray detector comprising the array substrate.

[0021] An objective of one embodiment of this disclosure is to provide a method for manufacturing an array substrate for a digital X-ray detector that can improve device performance by reducing device degradation due to hydrogen contained in thin-film transistors, an array substrate for a digital X-ray detector manufactured by the method, and a digital X-ray detector comprising the array substrate.

[0022] The purposes of this disclosure are not limited to those described above. Other purposes and advantages of this disclosure not mentioned above may be understood from the following description and may be more clearly understood from embodiments of this disclosure. Furthermore, it will be readily understood that the purposes and advantages of this disclosure may be achieved by the features disclosed in the claims and combinations thereof.

[0023] A method for manufacturing an array substrate for a digital X-ray detector according to an embodiment of the present disclosure may include: providing a substrate having an active region; forming a thin-film transistor on the substrate in the active region; forming a first protective layer on the substrate to cover the thin-film transistor; forming a lower electrode film on the first protective layer; forming a PIN (P-type / I-type / N-type semiconductor) layer and an upper electrode on the lower electrode film in the active region; forming a second protective film on the lower electrode film to cover the PIN layer and the upper electrode; and patterning the second protective film to form a second protective layer, and patterning the lower electrode film to form a lower electrode in the active region.

[0024] In this regard, the same masking process is used to pattern the second protective film and the lower electrode film.

[0025] Alternatively, the lower electrode film can be patterned after the second protective film has been patterned. In this regard, the second protective film is patterned using dry etching, and the lower electrode film is patterned using wet etching.

[0026] An array substrate for a digital X-ray detector according to an embodiment of the present disclosure may include: a substrate having an active region and a pad region; a thin-film transistor disposed on the substrate and in the active region; a first protective layer covering the thin-film transistor and disposed in the active region and the pad region; a PIN diode electrically connected to the thin-film transistor and disposed on the first protective layer and in the active region; and a second protective layer covering the PIN diode and disposed in the active region and the pad region.

[0027] In this respect, the second protective layer does not come into contact with the first protective layer.

[0028] Furthermore, a PIN diode includes a lower electrode, a PIN layer, and a upper electrode. The second protective layer does not cover the sides of the lower electrode.

[0029] In this way, the second protective film and the lower electrode film are patterned using the same masking process. After the PIN layer is formed, the second protective film is patterned to form dehydrogenation paths, thereby improving process efficiency and effectively removing hydrogen from the thin-film transistor.

[0030] According to one embodiment of this disclosure, the lower electrode of the PIN diode and the second protective layer covering the PIN diode are not formed using separate masking processes, but are formed using the same mask and the same masking process, thereby reducing the number of masking processes and thus improving process efficiency.

[0031] Furthermore, according to one embodiment of this disclosure, the lower electrode of the PIN diode is patterned, and then the second protective film covering the PIN diode is patterned, such that the front-end patterning and the back-end patterning are performed using a single mask process, thereby reducing the increase in defects due to foreign matter or stains.

[0032] Furthermore, according to one embodiment of this disclosure, the lower electrode of the PIN diode and the second protective layer covering the PIN diode can be patterned using the same mask, thereby ensuring uniform panel characteristics while performing multiple masking processes.

[0033] Furthermore, according to one embodiment of this disclosure, a PIN layer is formed for a PIN diode, and then a second protective layer covering the PIN diode is patterned such that the PIN diode and the pad area are protected while the thin-film transistor is not covered. This allows for ensuring that the dehydrogenation path (along which hydrogen is removed from the thin-film transistor) is a wider area, thereby reducing hydrogen-induced degradation of the thin-film transistor.

[0034] In addition to the effects described above, the specific effects of this disclosure will be described together with the following detailed description for carrying out this disclosure. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a digital X-ray detector.

[0036] Figure 2 This is a plan view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a digital X-ray detector including the array substrate, according to an embodiment of the present disclosure.

[0037] Figure 3 This is a cross-sectional view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a digital X-ray detector including the array substrate, according to an embodiment of the present disclosure.

[0038] Figures 4A to 4EThis is a process plan view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a method for manufacturing a digital X-ray detector including the array substrate, according to an embodiment of the present disclosure.

[0039] Figures 5A to 5E This is a process cross-sectional view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a method for manufacturing a digital X-ray detector including the array substrate, according to an embodiment of the present disclosure.

[0040] Figure 6 This is a plan view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a digital X-ray detector including the array substrate, according to another embodiment of the present disclosure.

[0041] Figure 7 This is a cross-sectional view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a digital X-ray detector including the array substrate, according to another embodiment of the present disclosure.

[0042] Figure 8 yes Figure 7 A magnified cross-sectional view of a portion of the area.

[0043] Figures 9A to 9E This is a process plan view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a method for manufacturing a digital X-ray detector including the array substrate, according to another embodiment of the present disclosure.

[0044] Figures 10A to 10E This is a process cross-sectional view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a method for manufacturing a digital X-ray detector including the array substrate, according to another embodiment of the present disclosure.

[0045] Figure 11 It is an image in a dark state when stains are generated on the array substrate used for a digital X-ray detector and the digital X-ray detector containing the array substrate. Detailed Implementation

[0046] For simplicity and clarity, the elements in the accompanying drawings are not necessarily drawn to scale. The same reference numerals in different drawings denote the same or similar elements, thus performing similar functions. Furthermore, descriptions and details of known steps and elements have been omitted to simplify the description. In addition, numerous specific details are set forth in the following detailed description of this disclosure to provide a comprehensive understanding of the disclosure. However, it should be understood that this disclosure can be practiced without these specific details. In other instances, known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure various aspects of this disclosure. Examples of various embodiments are further illustrated and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. Rather, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of this disclosure as defined by the appended claims. The shapes, dimensions, ratios, angles, and quantities disclosed in the drawings used to describe embodiments of this disclosure are exemplary, and this disclosure is not limited thereto. In this document, the same reference numerals denote the same elements. Furthermore, descriptions and details of known steps and elements have been omitted to simplify the description. In addition, numerous specific details are set forth in the following detailed description of this disclosure to provide a comprehensive understanding of the disclosure. However, it should be understood that this disclosure can be practiced without these specific details. In other instances, known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure various aspects of this disclosure.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to also include the plural forms unless the context clearly indicates otherwise. It should be further understood that when the terms “comprising” and “including” are used in this specification, they indicate the presence of the stated features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When a statement such as “at least one” precedes a series of elements, it may modify the entire series of elements as a whole, but not individual elements within that series. When “C to D” is mentioned, it means C (including C) to D (including D), unless otherwise stated. It should be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or part described below may be referred to as the second element, component, region, layer, or part.

[0048] Furthermore, it should be understood that when a first element or layer is referred to as existing "on" or "below" a second element or layer, the first element may be directly disposed on or below the second element, or indirectly disposed on or below the second element if a third element or layer is disposed between the first element or layer and the second element or layer. It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to, or coupled to another element or layer, or one or more intermediate elements or layers may exist. Furthermore, it should be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may exist. Moreover, as used herein, when a layer, film, region, plate, etc., is disposed "on" or "on top" of another layer, film, region, plate, etc., the former may directly contact the latter, or another layer, film, region, plate, etc., may be disposed between the former and the latter. As used herein, when a layer, membrane, region, plate, etc., is directly disposed "on" or "on top" of another layer, membrane, region, plate, etc., the former directly contacts the latter, and no other layer, membrane, region, plate, etc., is disposed between the former and the latter. Furthermore, as used herein, when a layer, membrane, region, plate, etc., is disposed "below" or "underneath" another layer, membrane, region, plate, etc., the former may directly contact the latter, or another layer, membrane, region, plate, etc., may be disposed between the former and the latter. As used herein, when a layer, membrane, region, plate, etc., is directly disposed "below" or "underneath" another layer, membrane, region, plate, etc., the former directly contacts the latter, and no other layer, membrane, region, plate, etc., is disposed between the former and the latter.

[0049] Unless otherwise defined, all terms used herein (including technical or scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It should be further understood that terms (e.g., those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted as having an idealized or overly formalized meaning unless expressly defined herein.

[0050] In one example, when an embodiment can be implemented differently, the functions or operations detailed in a particular block may occur in a different order than those detailed in the flowchart. For example, two consecutive blocks may actually be executed simultaneously. Depending on the associated functions or operations, blocks may be executed in reverse order. In descriptions of temporal relationships, such as the temporal precedence between two events described as "after," "following," "before," etc., unless "directly after," "directly following," or "directly before" is specified, another event may occur between the two events. Features of various embodiments of this disclosure may be combined partially or completely with each other and may be technically related or interoperable with each other. These embodiments may be implemented independently of each other and may be implemented together in an associated relationship. For ease of explanation, spatially related terms such as "below," "under," "lower," "below," "on," "upper" and "higher" may be used herein to describe the relationship between one element or feature as shown in the drawings and another element or feature. It should be understood that, in addition to the orientations shown in the drawings, spatially related terms are intended to encompass different orientations of means in use or operation. For example, when the device in the accompanying drawings is flipped, the orientation of an element described as "below," "under," or "below" other elements or features will be "above" other elements or features. Therefore, the example terms "below" and "below" can encompass both above and below orientations. The device can be oriented in other ways, such as by rotating 90 degrees or in other directions, and the spatially related descriptions used herein should be interpreted accordingly. "X-axis orientation," "Y-axis orientation," and "Z-axis orientation" should not be interpreted merely as having a geometric relationship where the X-axis, Y-axis, and Z-axis orientations are perpendicular to each other. "X-axis orientation," "Y-axis orientation," and "Z-axis orientation" can be interpreted as having a broader orientation within the scope of how the components described herein can functionally operate.

[0051] Hereinafter, with reference to the accompanying drawings, a method for manufacturing an array substrate for a digital X-ray detector according to some embodiments of the present disclosure, which can reduce the number of masking steps to improve process efficiency and reduce the degradation of thin-film transistors, the array substrate for a digital X-ray detector manufactured by the method, and a digital X-ray detector comprising the array substrate will be described.

[0052] Figure 1 This is a schematic block diagram of a digital X-ray detector. The digital X-ray detector may include a thin-film transistor array 110, a gate driver 120, a bias power supply 130, a readout circuit 140, and a timing controller 150.

[0053] The thin-film transistor array 110 includes multiple cell regions defined by multiple gate lines GL arranged in a first direction and multiple data lines DL arranged in a second direction orthogonal to the first direction.

[0054] The cell regions are arranged in a matrix. A photosensitive pixel P can be formed in each cell region. The thin-film transistor array 110 detects X-rays emitted from the X-ray source, converts the detected X-rays into an electrical signal, and outputs the electrical signal.

[0055] Each photosensitive pixel includes: a PIN diode that converts light from the visible light region converted from X-rays by a scintillator into an electrical signal and outputs the electrical signal; and a thin-film transistor (TFT) that transmits the detection signal output from the PIN diode to the readout circuit 140. One end of the PIN diode can be connected to the TFT, and the other end can be connected to the bias line BL.

[0056] The gate of the thin-film transistor (TFT) can be connected to the gate line GL, which transmits the scan signal. The source and drain of the TFT can be connected to the PIN diode and the data line DL, which transmits the detection signal output from the PIN diode, respectively. The bias lines BL can extend parallel to the data lines DL.

[0057] The gate driver 120 can sequentially apply a gate signal to the thin-film transistor of the photosensitive pixel via the gate line GL. The thin-film transistor of the photosensitive pixel can be turned on in response to a gate signal having a gate on-voltage level.

[0058] The bias power supply 130 can apply a driving voltage to the photosensitive pixel through the bias line BL. The bias power supply 130 can selectively apply a reverse bias or a forward bias to the PIN diode.

[0059] The readout circuit 140 can read the detection signal transmitted from the thin-film transistor that is turned on in response to the gate signal of the gate driver. That is, the detection signal output from the PIN diode can be input to the readout circuit 140 through the thin-film transistor and the data line DL.

[0060] The readout circuit 140 can read out the detection signals output from each photosensitive pixel during the shift readout period for reading out the shifted image and the X-ray readout period for reading out the detection signals after X-ray exposure.

[0061] The readout circuit 140 may include a signal detector and a multiplexer. The signal detector includes multiple amplifier circuits corresponding to data lines DL. Each amplifier circuit may include an amplifier, a capacitor, and a reset element.

[0062] The timing controller 150 can generate an initial signal and a clock signal, and supply the initial signal and clock signal to the gate driver 120 to control the operation of the gate driver 120. In addition, the timing controller 150 can generate a readout control signal and a readout clock signal, and supply the readout control signal and the readout clock signal to the readout circuit 140 to control the operation of the readout circuit 140.

[0063] Figure 2 This is a plan view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a digital X-ray detector including the array substrate, according to an embodiment of the present disclosure.

[0064] Figure 3 This is a cross-sectional view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a digital X-ray detector including the array substrate, according to an embodiment of the present disclosure. Figures 4A to 4E This is a process plan view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a method for manufacturing a digital X-ray detector including the array substrate, according to an embodiment of the present disclosure. Figures 5A to 5E This is a process cross-sectional view of an array substrate for a digital X-ray detector corresponding to a single pixel region, and a method for manufacturing a digital X-ray detector including the array substrate, according to an embodiment of the present disclosure.

[0065] In the following, an array substrate for a digital X-ray detector, a digital X-ray detector comprising the array substrate, and a method for manufacturing the same, according to an embodiment of the present disclosure, will be described in detail with reference to the accompanying drawings.

[0066] In the following text, the method for forming patterns in each layer can employ a mask process using photolithography, which includes deposition, photoresist coating (PR) application, exposure, development, etching, and photoresist stripping (PR stripping) processes conventionally performed by those skilled in the art. Therefore, detailed descriptions of each process are omitted.

[0067] For example, for deposition processes, sputtering can be used for metallic materials, while plasma-enhanced chemical vapor deposition (PECVD) can be used for semiconductors or insulating films.

[0068] Furthermore, for the etching process, dry etching and wet etching can be selectively used based on the material. Techniques performed by those skilled in the art can be applied to the etching process.

[0069] like Figure 4A and Figure 5A As shown, in the digital X-ray detector and the array substrate 10 for the digital X-ray detector, thin film transistors 220 are formed in the active region AA of the substrate 210.

[0070] The array substrate 10 for a digital X-ray detector includes a base substrate 210.

[0071] The substrate 210 can be implemented as a glass substrate. However, this disclosure is not limited thereto. When the array substrate 10 is applied to a flexible digital X-ray detector, the substrate 210 can be made of a polyimide material with flexible properties.

[0072] The substrate 210 includes an active region AA and a pad region PDA.

[0073] The active region AA includes a PIN diode region PINA with a PIN diode 240 and a thin film transistor region TFTA with a thin film transistor 220.

[0074] The pad area includes a readout pad area and a gate pad area. The readout pad area includes a readout pad area connected to the readout circuit 140 to read signals to the readout circuit 140. The gate pad area includes a gate pad area that receives scan signals from the gate driver 120.

[0075] The components contained in the active region AA will be described first below.

[0076] Multiple gate lines GL and multiple data lines DL are formed on the substrate 210 and intersect each other in a perpendicular manner.

[0077] Multiple cell regions are defined at the intersections of multiple gate lines GL and multiple data lines DL. Each cell region can correspond to a pixel P. Therefore, multiple pixel regions can be defined. The region corresponding to each of the gate lines GL and data lines DL can be defined as the boundary region between pixel regions.

[0078] Each thin-film transistor 220 and each PIN diode 240 can belong to a single pixel. Therefore, multiple thin-film transistors 220 and multiple PIN diodes 240 can be formed in an array substrate having multiple pixel regions.

[0079] In the following description, the thin-film transistor 220 and PIN diode 240 corresponding to a single pixel are used as a basis, and therefore, unless otherwise stated, they are applied equally to adjacent pixels.

[0080] A thin-film transistor 220, comprising a first electrode 223a, a second electrode 223b, a gate 225, and an active layer 221, is formed on a substrate 210.

[0081] A buffer layer 211 can be formed between the substrate 210 and the thin-film transistor 220. In this case, the buffer layer 211 can be made of a material such as a silicon oxide film (SiO2).x Or silicon nitride film SIN x It is composed of inorganic material membranes and can be implemented as multilayer buffer layers.

[0082] An active layer 221 is formed on a buffer layer 211. The active layer 221 can be made of an oxide semiconductor material such as IGZO (indium gallium zinc oxide), but is not limited thereto. The active layer 221 can be made of LTPS (low-temperature polycrystalline silicon) or amorphous silicon (a-Si).

[0083] A gate 225 may be formed on an active layer 221. A gate insulating layer 222 may be formed between the active layer 221 and the gate 225, so that the active layer 221 and the gate 225 can be insulated from each other.

[0084] Gate 225 may be formed on gate insulating layer 222 to correspond to the channel region of active layer 221.

[0085] The gate 225 can be made of one of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), and their alloys, and can be composed of a single layer or multiple layers.

[0086] Gate 225 can extend from gate line GL.

[0087] Furthermore, gate 225 can be integrated with gate line GL, allowing gate line GL to be used as gate 225. Therefore, gate line GL and gate 225 can form the same layer.

[0088] The gate insulating layer 222, made of inorganic material, can be formed to correspond to the gate 225 and can be formed to have an area equal to or greater than that of the gate 225 for effective insulation.

[0089] The gate 225 and the gate insulating layer 222 can be formed to correspond to the internal regions of the active layer 221. Therefore, the two opposite regions of the active layer 221 exposed when not covered by the gate 225 (i.e., the two opposite ends of the active layer 221 other than its channel region) can be used as the source region and the drain region, respectively.

[0090] The source region of the active layer 221 can be configured to be closer to the PIN diode 240 than its drain region. However, this disclosure is not limited thereto. The positions of the source and drain regions can be interchanged.

[0091] An interlayer insulating layer 226 made of inorganic material can be formed on the gate 225 to cover the substrate 210.

[0092] Interlayer insulating layer 226 can be formed on the entire surface of substrate 210, which includes active region AA and pad region PDA.

[0093] The first electrode 223a and the second electrode 223b can be formed on the interlayer insulating layer 226.

[0094] The first electrode 223a and the second electrode 223b can be formed to correspond to two opposite sides of the active layer 221, respectively, when the gate 225 is inserted between them.

[0095] Interlayer insulating layer contact holes 226h, corresponding to the source and drain regions of the active layer 221 respectively, can be formed in the interlayer insulating layer 226.

[0096] Therefore, the first electrode 223a and the second electrode 223b can be connected to the source region and drain region of the active layer 221 respectively via the interlayer insulating layer contact hole 226h.

[0097] Therefore, the first electrode 223a connected to the source region can be used as the source, and the second electrode 223b connected to the drain region can be used as the drain.

[0098] The first electrode 223a, the second electrode 223b, and the data line DL can be formed using the same patterning process and the same material, and can constitute the same layer.

[0099] In this case, the first electrode 223a can be configured to be spaced apart from the data line DL, while the second electrode 223b can extend from the data line DL or be formed in the data line DL.

[0100] The data cable DL can be made of one of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), and their alloys. This disclosure is not limited thereto.

[0101] The first protective layer 230 can be formed on the thin-film transistor 220 to cover the entire surface of the substrate 210 containing the active region AA and the pad region PDA.

[0102] The first protective layer 230 can be made of, for example, a silicon oxide film (SiO2). x Or silicon nitride film SIN x It is composed of an inorganic material film. This disclosure is not limited thereto. The first protective layer 230 can protect the underlying thin-film transistor 220, and in particular, the active layer 221.

[0103] The lower electrode film 241a for forming the lower electrode 241 of the PIN diode 240 can be deposited on the first protective layer 230 to cover the entire surface of the substrate 210 containing the active region AA and the pad region PDA. In this case, in order to electrically connect the first electrode 223a and the lower electrode film 241a to each other, the first protective layer contact hole 230h can be formed in the first protective layer 230 in a manner corresponding to the first electrode 223a.

[0104] Therefore, the lower electrode film 241a can be electrically connected to the first electrode 223a via the first protective layer contact hole 230h of the first protective layer 230.

[0105] Next, as Figure 4B and Figure 5B As shown, the lower electrode film 241a can be patterned using a mask with a predetermined pattern via a masking process, thereby forming the lower electrode 241.

[0106] In this case, wet etching can be used to pattern the lower electrode film 241a.

[0107] The lower electrode 241 can be used as a pixel electrode in the PIN diode 240. Depending on the characteristics of the PIN diode 240, the lower electrode 241 can be made of at least one material selected from opaque metals such as molybdenum (Mo) or transparent oxides such as ITO (indium tin oxide), IZO (indium zinc oxide), and ZnO (zinc oxide).

[0108] In this case, the lower electrode 241 can be formed in a pattern corresponding to each pixel region, and can be set in the pixel region.

[0109] Next, as Figure 4C and Figure 5C As shown, the PIN layer 243 and the upper electrode 245 of the PIN diode 240 can be formed on the lower electrode 241 and in each pixel region.

[0110] Specifically, the PIN film and the upper electrode film can be formed on the entire surface of the substrate 210 to cover the lower electrode 241. Then, the PIN film and the upper electrode film can be patterned using a masking process to form the PIN layer 243 and the upper electrode 245, respectively.

[0111] In this case, dry etching can be used to pattern the PIN film, and wet etching can be used to pattern the top electrode film.

[0112] The patterning order of the PIN film and the top electrode film is not particularly restricted.

[0113] Therefore, the PIN diode 240 may include a lower electrode 241 connected to the thin film transistor 220, a PIN layer 243 on the lower electrode 241, and an upper electrode 245 on the PIN layer 243.

[0114] The PIN layer 243 converts visible light, which is converted from X-rays by a scintillator, into electrical signals.

[0115] The PIN layer 243 can be formed by sequentially stacking an N-type semiconductor layer containing n-type impurities, an intrinsic semiconductor layer, and a P-type semiconductor layer containing p-type impurities on the lower electrode 241.

[0116] The intrinsic semiconductor layer can be relatively thicker than each of the N-type and P-type semiconductor layers. The PIN layer 243 can be formed to contain a material capable of converting visible light derived from X-rays by a scintillator into an electrical signal. For example, the PIN layer 243 can contain materials such as a-Se, HgI2, CdTe, PbO, PbI2, BiI3, GaAs, and Ge.

[0117] The upper electrode 245 may be made of at least one material selected from transparent oxides such as ITO (indium tin oxide), IZO (indium zinc oxide), and ZnO (zinc oxide), thereby improving the fill factor of the PIN diode 240.

[0118] Next, as Figure 4D and Figure 5D As shown, the second protective film 250a can be deposited on the entire surface of the substrate 210 containing the active region AA and the pad region PDA to cover the PIN diode 240.

[0119] The second protective film 250a can be made of materials such as silicon oxide film (SiO2). x Or silicon nitride film SIN x It is composed of inorganic material membranes. This disclosure is not limited thereto.

[0120] Next, as Figure 4E and Figure 5E As shown, the second protective layer 250 may include a second protective layer contact hole 250h corresponding to the upper electrode 245. For example, the second protective layer contact hole 250h can be formed by removing a portion of the second protective film 250a corresponding to the upper electrode 245. Figure 5E As shown, the second protective layer 250 can be formed by patterning the second protective film 250a.

[0121] In this case, the second protective film 250a can be patterned using dry etching.

[0122] Except for the second protective layer contact hole 250h, the second protective layer 250 can be formed on the entire surface of the substrate 210, so that components such as PIN diode 240 and thin film transistor 220 under the second protective layer 250 can be protected from external moisture or foreign matter.

[0123] refer to Figure 3 The planarization layer 260 can be formed on the second protective layer 250. The planarization layer 260 can be made of an organic material such as PAC (photopolymer acrylate). This disclosure is not limited thereto.

[0124] The planarization layer contact hole 260h can be formed in the planarization layer 260 in a manner corresponding to the second protective layer contact hole 250h.

[0125] The bias electrode 270 can be formed on the planarization layer 260. The bias electrode 270 can be connected to the upper electrode 245 of the PIN diode 240 via the planarization layer contact hole 260h and the second protective layer contact hole 250h, so that a bias voltage can be applied to the PIN diode 240.

[0126] The bias electrode 270 can branch from the bias line BL, which extends in a manner parallel to the data line DL.

[0127] The third protective layer 280 can be formed on the bias line BL. The third protective layer 280 can be made of a material such as a silicon oxide film (SiO2). x Or silicon nitride film SIN x It is composed of inorganic material membranes. This disclosure is not limited thereto.

[0128] On the third protective layer 280, the scintillator layer 290 can be formed to cover the PIN diode 240.

[0129] Specifically, the scintillator layer 290 can be disposed on the thin-film transistor 220 and the PIN diode 240, and located in the active region AA, so as to cover the thin-film transistor 220 and the PIN diode 240.

[0130] Since the scintillator layer 290 can be directly deposited on the array substrate 10 used for digital X-ray detectors, the bottom surface of the scintillator layer 290 should be planarized.

[0131] Therefore, an additional planarization layer made of organic materials such as PAC (photopolymer propylene) can be formed on the third protective layer 280.

[0132] Using an additional planarization layer to planarize the bottom surface of scintillator layer 290 can facilitate the formation of scintillator layer 290 via the deposition of scintillator material.

[0133] The scintillator layer 290 can be grown vertically to have multiple columnar crystal phases, allowing the multiple scintillator columnar crystals to be arranged side-by-side. This disclosure is not limited thereto. The scintillator can be made of materials such as cesium iodide (CsI) or thallium iodide (TlI). This disclosure is not limited thereto.

[0134] In one example, the pad region PDA includes a readout region containing readout pads and a gate pad region containing gate pads.

[0135] The readout pads in the PDA pad area will be described in detail below. The description of the readout pads can be applied in the same way to the gate pads. Some differences between them will be described separately.

[0136] The pads in the readout area of ​​the PDA include pad electrodes 323, pad connection electrodes 341, pad contact electrodes 370, and pad protection electrodes 380.

[0137] First, such as Figure 4A and Figure 5A As shown, the pad electrode 323 can be formed on the interlayer insulating layer 226 and in the pad region PDA.

[0138] The pad electrode 323 can be formed using the same patterning process as the patterning process used to form the first electrode 223a and the second electrode 223b. Therefore, the pad electrode 323 can have the same material as each of the first electrode 223a and the second electrode 223b. Furthermore, the pad electrode 323, the first electrode 223a, and the second electrode 223b can form the same layer.

[0139] However, in the gate pad region, before forming the pad electrode 323 using the same patterning process as that used to form the first electrode 223a and the second electrode 223b, a separate additional pad lower electrode can be formed using the same patterning process as that used to form the gate 225. The separate additional pad lower electrode and the gate 225 can be made of the same material and can form the same layer.

[0140] In this case, the lower electrode of the gate pad region can be formed under the interlayer insulating layer 226.

[0141] After the first protective layer 230 is formed on the pad electrode 323, the lower electrode film 241a can be formed on the first protective layer 230 to cover the entire surface of the active region AA and the pad region PDA.

[0142] In this configuration, the first protective layer contact hole 230h can be formed in the first protective layer 230 and in the pad region PDA in a manner corresponding to the pad electrode 323. Therefore, the lower electrode film 241a can be electrically connected to the pad electrode 323 via the first protective layer contact hole 230h.

[0143] Next, as Figures 4B to 4C as well as Figures 5B to 5C As shown, the lower electrode film 241a can be patterned to form a pad connection electrode 341 in the pad area PDA.

[0144] Therefore, the pad connection electrode 341 in the pad area PDA and the lower electrode 241 of the PIN diode 240 in the active area AA can form the same layer and can be made of the same material.

[0145] In this case, the portion of the pad connection electrode 341 corresponding to the first protective layer contact hole 230h can be patterned and removed to form the pad connection electrode contact hole 341h.

[0146] Next, as Figure 4D and Figure 5D As shown, the second protective film 250a can be formed on the pad connection electrode 341.

[0147] The second protective film 250a can be deposited on the entire surface of the substrate 210, which includes the active region AA and the pad region PDA.

[0148] Next, as Figure 4E and Figure 5E As shown, the second protective film 250a can be patterned to form second protective layer contact holes 250h corresponding to the first protective layer contact holes 230h and the pad connection electrode contact holes 341h in the pad region PDA. Therefore, the second protective layer 250 can be formed on the pad connection electrode 341.

[0149] The pad contact electrode 370 can be formed on the second protective layer 250 and in the pad area PDA.

[0150] The pad contact electrode 370 can be formed using the same patterning process as that used to form the bias electrode 270. Therefore, the pad contact electrode 370 and the bias electrode 270 can be made of the same material and can form the same layer.

[0151] The pad contact electrode 370 can be electrically connected to the lower pad electrode 323 via the first protective layer contact hole 230h, the pad connection electrode contact hole 341h, and the second protective layer contact hole 250h.

[0152] The pad protection electrode 380 may be additionally disposed on the pad contact electrode 370.

[0153] The pad protection electrode 380 can protect the pad contact electrode 370 to reduce its corrosion and can be made of ITO.

[0154] The operation of the digital X-ray detector according to this disclosure is as follows.

[0155] X-rays are irradiated by a digital X-ray detector. Scintillator layer 290 converts the X-rays into visible light. PIN layer 243 of PIN diode 240 converts the light in the visible region into electronic signals.

[0156] Specifically, when light in the visible region shines on the PIN layer 243, the I-type semiconductor layer is depleted by the P-type and N-type semiconductor layers, thereby generating an electric field therein. Then, holes and electrons generated by the light drift caused by the electric field are collected into the P-type and N-type semiconductor layers, respectively.

[0157] The PIN diode 240 converts light in the visible area into an electrical signal and transmits the signal to the thin-film transistor 220. The transmitted electrical signal is then displayed as an image signal via the data line DL connected to the thin-film transistor 220.

[0158] Figure 6 This is a plan view of an array substrate 10 for a digital X-ray detector corresponding to a single pixel region, and a digital X-ray detector 1 including the array substrate, according to another embodiment of the present disclosure. Figure 7 This is a cross-sectional view of an array substrate 10 for a digital X-ray detector corresponding to a single pixel region, and a digital X-ray detector 1 including the array substrate, according to another embodiment of the present disclosure.

[0159] Figures 9A to 9E This is a process plan view of an array substrate 10 for a digital X-ray detector corresponding to a single pixel region, and a method for manufacturing a digital X-ray detector including the array substrate, according to another embodiment of the present disclosure. Figures 10A to 10E This is a process cross-sectional view of an array substrate 10 for a digital X-ray detector corresponding to a single pixel region, and a method for manufacturing a digital X-ray detector including the array substrate, according to another embodiment of the present disclosure.

[0160] In the following, with reference to the accompanying drawings, an array substrate 10 for a digital X-ray detector and a digital X-ray detector and a method of manufacturing the same, according to another embodiment of the present disclosure, will be described in detail.

[0161] However, detailed descriptions of one embodiment of this disclosure, which is similarly applied as described above, should be omitted. The following description should focus on the differences between them.

[0162] The array substrate 10 for a digital X-ray detector and the digital X-ray detector and the method for manufacturing the same according to an embodiment of the present disclosure, as described above, can be referred to as the first embodiment. The array substrate 10 for a digital X-ray detector and the digital X-ray detector and the method for manufacturing the same according to another embodiment of the present disclosure, as described below, can be referred to as the second embodiment.

[0163] In the array substrate 10 for a digital X-ray detector and the digital X-ray detector and the method thereof according to the first embodiment of the present disclosure as described above, the lower electrode 241 of the PIN diode 240 and the second protective layer 250 covering the PIN diode 240 are formed using separate masking processes.

[0164] In this case, the masking process includes a deposition process and a patterning process using photolithography.

[0165] In other words, after forming the lower electrode 241 of the PIN diode 240 using a mask process with the lower electrode pattern, the PIN layer 243 and the upper electrode 245 of the PIN diode 240 are formed using a separate mask process. Next, a second protective layer 250 covering the PIN diode 240 is formed using a separate mask process.

[0166] In the first embodiment, the PIN diode 240 and the second protective layer 250 are formed using separate mask processes. Therefore, process efficiency may be reduced.

[0167] When multiple masking processes are performed sequentially, the following problem may occur due to equipment constraints or other process issues: after one masking process is completed, the next masking process may not proceed immediately, but may proceed after a predetermined waiting time.

[0168] In this situation, since the lower electrode 241 has already undergone a masking process and has been patterned, the underlying thin-film transistor 220 must remain exposed to the outside while waiting for the next process. Therefore, the likelihood of foreign matter or contaminants appearing on the array substrate increases during the waiting period.

[0169] Furthermore, during the formation of the lower electrode 241, the lower electrode film 241a is deposited on the entire surface of the substrate 210 and then patterned using a photolithography process. In this respect, the photolithography process may not be performed immediately after the deposition of the lower electrode film 241a. Therefore, contaminants may appear on the lower electrode film 241a during the waiting period.

[0170] Figure 11 The image shown is of the array substrate 10 and the digital X-ray detector in a dark state, after a photolithography process is performed following the deposition of the lower electrode film 241a in order to form the lower electrode 241 of the PIN diode 240 and after a predetermined time delay.

[0171] like Figure 11 As shown, when a photolithography process for the lower electrode 241 of the PIN diode 240 is performed after a predetermined time delay following the deposition of the lower electrode film 241a, a bright spot and a tilted stain are identified at the center of the array substrate 10 and the digital X-ray detector.

[0172] Furthermore, in the first embodiment, a masking process for the second protective layer 250 is performed after the masking process for the PIN layer 243 for the PIN diode 240. The second protective layer 250 is formed on the entire surface of the substrate 210, excluding the contact holes. Therefore, it may be difficult to ensure that a large amount of hydrogen generated during the formation process of the PIN layer 243 can be discharged to an external dehydrogenation path.

[0173] Therefore, compared with the first embodiment of the present disclosure as described above, the above-mentioned problems can be eliminated in the array substrate 10 for a digital X-ray detector and the digital X-ray detector and the manufacturing method thereof according to the second embodiment of the present disclosure.

[0174] Therefore, the array substrate 10 for a digital X-ray detector and the manufacturing method of the digital X-ray detector according to the second embodiment of the present disclosure may include: forming a thin film transistor 220 in an active region AA on a substrate 210; forming a first protective layer 230 on the substrate 210 to cover the thin film transistor 220; forming a lower electrode film 241a on the first protective layer 230; forming a PIN layer 243 and an upper electrode 245 in the active region AA on the lower electrode film 241a; forming a second protective film 250a on the lower electrode film 241a to cover the PIN layer 243 and the upper electrode 245; forming a second protective layer 250 by patterning the second protective film 250a; and forming a lower electrode 241 in the active region AA by patterning the lower electrode film 241a.

[0175] In this case, the second protective film 250a and the lower electrode film 241a are patterned using the same masking process.

[0176] like Figure 9A and Figure 10A As shown, a thin-film transistor 220 is formed in the active region AA and on the substrate 210.

[0177] The thin-film transistor 220 formed on the substrate 210 is formed to include an active layer 221, a first electrode 223a, a second electrode 223b and a gate 225.

[0178] The active layer 221 can be formed on the buffer layer 211 formed on the substrate 210.

[0179] A gate insulating layer 222 having a pattern corresponding to the gate 225 can be formed on the active layer 221. The gate 225 can be formed on the gate insulating layer 222.

[0180] An interlayer insulating layer 226 may be formed on the gate 225 and cover the entire surface of the substrate 210, which includes the active region AA and the pad region PDA, to cover the gate 225.

[0181] The first electrode 223a and the second electrode 223b can be formed on the interlayer insulating layer 226. In addition, the first electrode 223a and the second electrode 223b are electrically connected to the active layer 221 via the interlayer insulating layer contact hole 226h, respectively.

[0182] A first protective layer 230 is formed on the thin-film transistor 220 and on the substrate 210 to cover the thin-film transistor 220.

[0183] A first protective layer 230 is formed on the entire surface of a substrate 210 containing an active region AA and a pad region PDA.

[0184] The lower electrode film 241a can be deposited on the first protective layer 230.

[0185] The lower electrode film 241a is formed on the entire surface of the substrate 210, which includes the active region AA and the pad region PDA.

[0186] In one example, in the pad area PDA, pad electrodes 323 are formed on the substrate 210.

[0187] Specifically, the pad electrode 323 can be formed before the first protective layer 230 is formed. The pad electrode 323 can be formed between the interlayer insulating layer 226 and the first protective layer 230.

[0188] The pad electrode 323 in the pad area PDA can be formed using the same mask process as the first electrode 223a and the second electrode 223b of the thin film transistor 220 formed in the active area AA.

[0189] Therefore, the pad electrode 323 in the pad region PDA can be made of the same material as each of the first electrode 223a and the second electrode 223b of the thin-film transistor 220 in the active region AA. Furthermore, the pad electrode 323 in the pad region PDA and the first electrode 223a and the second electrode 223b of the thin-film transistor 220 disposed in the active region AA can form the same layer.

[0190] Next, as Figure 9B and Figure 10B As shown, the PIN layer 243 and the upper electrode 245 are formed in the active region AA and on the lower electrode film 241a.

[0191] After depositing the lower electrode film 241a, a PIN layer 243 and an upper electrode 245 are formed in the active region AA without performing a separate patterning process using photolithography.

[0192] The PIN layer 243 and the upper electrode 245 can be formed by performing a mask process that includes deposition and patterning processes.

[0193] For example, the PIN film and the upper electrode film can be deposited on the lower electrode film 241a to cover the entire surface of the substrate 210. Then, the PIN layer 243 and the upper electrode 245 can be formed by performing a patterning process using masks having patterns corresponding to the PIN layer 243 and the upper electrode 245, respectively.

[0194] Since the upper electrode film is formed on the PIN film, the patterning process of the upper electrode film can be performed before the patterning process of the PIN film.

[0195] The patterning process of the upper electrode film can be performed using a dry etching process, while the patterning process of the PIN film can be performed using a wet etching process.

[0196] Next, as Figure 9C and Figure 10C As shown, a second protective film 250a is formed on the lower electrode film 241a to cover the PIN layer 243 and the upper electrode 245.

[0197] A second protective film 250a is deposited to cover the entire surface of the substrate 210, which includes the active region AA and the pad region PDA.

[0198] Next, as Figure 9D and Figure 10D As shown, the second protective layer 250 is formed by patterning the second protective film 250a.

[0199] In addition, such as Figure 9E and Figure 10EAs shown, the lower electrode 241 can be formed by patterning the lower electrode film 241a disposed in the active region AA. Furthermore, the pad connection electrode 341 can be formed by patterning the lower electrode film 241a disposed in the pad region PDA.

[0200] In this case, the same masking process can be used to pattern the second protective film 250a and the lower electrode film 241a.

[0201] The second protective film 250a and the lower electrode film 241a can be patterned using a single, identical mask instead of separate masks. Therefore, patterning can be performed using a single, identical mask process.

[0202] Specifically, a second protective film 250a is formed on a lower electrode film 241a. Then, the second protective film 250a is first patterned using a mask with a predetermined pattern, and then the lower electrode film 241a is patterned using the same mask as in the patterning process of the second protective film 250a.

[0203] The second protective film 250a can be patterned using dry etching, and the lower electrode film 241a can be patterned using wet etching.

[0204] The second protective film 250a patterned in this manner can be formed as the second protective layer 250 in the active region AA and the pad region PDA. In addition, the patterned lower electrode film 241a can be used as the lower electrode 241 in the active region AA and as the pad connection electrode 341 in the pad region PDA.

[0205] Therefore, the lower electrode 241 in the active region AA and the pad connection electrode 341 in the pad region PDA are formed using the same mask process.

[0206] As described above, according to the second embodiment, the lower electrode 241 of the PIN diode 240 and the second protective layer 250 covering the PIN diode 240 can be formed using the same mask and the same mask process without using a separate mask process, thereby reducing the number of mask processes and thus improving process efficiency.

[0207] Furthermore, according to the second embodiment, a single masking process can be performed, allowing the second protective layer 250 to be formed by patterning the second protective film 250a covering the PIN diode 240, and then the lower electrode 241 to be formed by patterning the lower electrode film 241a. Therefore, problems arising from the manufacturing process can be eliminated.

[0208] Specifically, after the second protective film 250a protecting the lower electrode film 241a is patterned, the masking process does not need to be changed. Therefore, the lower electrode film 241a can be patterned in batches using the same masking process without waiting time. Thus, during the manufacturing process of the array substrate for the digital X-ray detector and the digital X-ray detector itself, the increase of foreign matter or contaminants that might otherwise exist on the array substrate can be reduced.

[0209] Furthermore, according to the second embodiment, after forming the PIN layer 243 of the PIN diode 240, the second protective layer 250 covering the PIN diode 240 can be patterned so that the PIN diode 240 is protected by the second protective layer 250, while the second protective layer 250 does not cover the thin film transistor 220.

[0210] In other words, when the number of patterns of the second protective layer 250 formed on the thin-film transistor 220 is minimized, the area not covered by the second protective layer 250 is increased, thus allowing hydrogen to be discharged through a wider discharge region. Therefore, the dehydrogenation path of the thin-film transistor 220 can be wider. In this way, a wider dehydrogenation path is ensured for the thin-film transistor 220, thereby reducing hydrogen-induced degradation of the thin-film transistor 220.

[0211] During the process of forming the PIN layer 243 of the PIN diode 240, a large amount of hydrogen may be generated. In this regard, when hydrogen flows into the underlying thin-film transistor 220, the characteristics of the device may deteriorate.

[0212] Specifically, oxide semiconductor-based thin-film transistors 220 with an active layer 221 made of oxide semiconductor are more susceptible to degradation due to hydrogen. Therefore, it is necessary to ensure a dehydrogenation path that can remove hydrogen introduced during the process of forming the PIN layer 243 to the outside.

[0213] According to the second embodiment, the second protective layer 250, which is formed to cover the PIN layer 243 after the PIN layer 243 is formed, is not formed to cover the entire surface of the substrate 210. Instead, the second protective layer 250 can be patterned in the active region AA to a pattern corresponding to the lower electrode 241, and the second protective layer 250 can be patterned in the pad region PDA to a pattern corresponding to the pad connection electrode 341, so that the second protective layer 250 is formed with a minimum number of patterns.

[0214] When the second protective layer 250 covers the entire surface of the substrate 210, a dehydrogenation path from the thin-film transistor 220 may not be guaranteed due to the second protective layer 250. However, as in the second embodiment, when the second protective layer 250 is formed with a minimum number of patterns, the areas where the second protective layer 250 is not formed can be used as dehydrogenation paths. Therefore, a large amount of hydrogen can be removed from the thin-film transistor 220 to the outside via a subsequent heat treatment process.

[0215] Furthermore, according to the second embodiment, the second protective layer 250 can be patterned to have the same pattern as the lower electrode 241. Therefore, compared with the structure in the first embodiment, the array substrate for the digital X-ray detector and the digital X-ray detector containing the array substrate can have constant and uniform panel characteristics.

[0216] Figure 8 yes Figure 7 An enlarged cross-sectional view of a portion of the region in which the second protective layer 250 and the lower electrode 241 are formed.

[0217] like Figure 8 As shown, the second protective layer 250 does not contact the first protective layer 230.

[0218] As described above, in the second embodiment, the lower electrode film 241a and the second protective film 250a on the lower electrode film 241a can be patterned using a single mask process with the same mask. Therefore, in the active region AA, the second protective layer 250 formed by patterning the second protective film 250a can be formed with a pattern corresponding to the pattern of the lower electrode 241 formed by patterning the lower electrode film 241a.

[0219] Similarly, in the pad area PDA, the second protective layer 250 formed by patterning the second protective film 250a can be formed as a pattern corresponding to the pattern of the pad connection electrode 341 formed by patterning the lower electrode film 241a.

[0220] Therefore, the second protective layer 250 may not be in contact with the first protective layer 230. The second protective layer 250 may be formed so as not to cover the side surface of the lower electrode 241.

[0221] In this case, the second protective layer 250 and the lower electrode 241, as well as the second protective layer 250 and the pad connection electrode 341, can be patterned using the same mask and the same mask process, but they do not have to have the exact same pattern.

[0222] For example, such as Figure 8As shown, the side of the lower electrode 241 can be tilted downwards and outwards. In addition, the top end 241e of the lower electrode 241 can be located inside the bottom end 250e of the second protective layer 250.

[0223] The second protective layer 250 can be patterned by dry etching the second protective film 250a. The patterning process of the second protective film 250a can also affect the lower electrode film 241a disposed below the second protective film 250a. Therefore, a portion of the lower electrode film 241a disposed below the second protective film 250a can be etched away during the dry etching process used to pattern the second protective film 250a.

[0224] In the subsequent wet etching of the lower electrode film 241a, the tip 241e of the lower electrode 241 can withstand the effects of dry etching of the second protective film 250a and wet etching of the lower electrode film 241a. Therefore, the side surface of the lower electrode 241 can be partially over-etched.

[0225] Therefore, the side of the lower electrode 241 can be tilted downward and outward. In addition, the top end 241e of the lower electrode 241 can be located inside the bottom end 250e of the second protective layer 250.

[0226] In the active region AA, a second protective layer 250 can be formed, and then a planarization layer 260 can be formed on it. Furthermore, as... Figure 7 As shown, the bias electrode 270 can be formed on the planarization layer 260.

[0227] The bias electrode 270 can be electrically connected to the upper electrode 245 of the PIN diode 240 via the contact hole 260h of the planarization layer 260 and the contact hole 250h of the second protective layer 250.

[0228] refer to Figure 7 The third protective layer 280 can be formed on the PIN diode 240, the planarization layer 260, and the bias electrode 270. Furthermore, the scintillator layer 290 can be disposed on the third protective layer 280 and in the active region AA.

[0229] In one example, in the pad area PDA, the pad contact electrode 370 can be formed on the second protective layer 250.

[0230] The pad contact electrode 370 in the pad area PDA can be formed using the same mask process as the bias electrode 270 in the active area AA. Therefore, the pad contact electrode 370 can be made of the same material as the bias electrode 270, and the pad contact electrode 370 and the bias electrode 270 can form the same layer.

[0231] The pad contact electrode 370 can be electrically connected to the bottom pad electrode 323 via the first protective layer contact hole 230h, the pad connection electrode contact hole, and the second protective layer contact hole 250h.

[0232] On the pad contact electrode 370 in the pad area PDA, a pad protection electrode 380 can be formed to cover the pad contact electrode 370.

[0233] The pad protection electrode 380 can be used to reduce corrosion of the pad contact electrode 370 that may occur when the pad contact electrode 370 is exposed to the outside. For this purpose, the pad protection electrode 380 may contain a material such as ITO. However, this disclosure is not limited thereto. The pad protection electrode 380 may be made of a corrosion-resistant metallic material.

[0234] In one example, in the gate pad region, before forming the pad electrode 323 using the same patterning process as forming the first electrode 223a and the second electrode 223b, a separate additional pad lower electrode can be formed using the same patterning process as forming the gate 225. The separate additional pad lower electrode and the gate 225 can be made of the same material and can form the same layer.

[0235] In this case, the lower electrode of the gate pad region PDA can be located below the interlayer insulating layer 226.

[0236] This disclosure may include the following aspects and their implementation methods.

[0237] The first aspect of this disclosure provides a method for manufacturing an array substrate for a digital X-ray detector, the method comprising: setting a substrate having an active region and a pad region; forming a thin-film transistor on the substrate in the active region; forming a first protective layer on the substrate to cover the thin-film transistor; forming a lower electrode film on the first protective layer; forming a PIN (P-type / I-type / N-type semiconductor) layer and an upper electrode on the lower electrode film in the active region; forming a second protective film on the lower electrode film to cover the PIN layer and the upper electrode; and patterning the second protective film to form a second protective layer, and patterning the lower electrode film to form a lower electrode in the active region, wherein the second protective film and the lower electrode film are patterned using the same masking process.

[0238] In one embodiment of the first aspect, each of the lower electrode film and the second protective film is formed to cover the entire surface of the substrate.

[0239] In one embodiment of the first aspect, the second protective film is patterned, and then the lower electrode film is patterned.

[0240] In one embodiment of the first aspect, the second protective film is patterned using dry etching, and the lower electrode film is patterned using wet etching.

[0241] In one embodiment of the first aspect, the method further includes: forming pad electrodes in a pad region on a substrate prior to forming a first protective layer.

[0242] In one embodiment of the first aspect, the thin-film transistor includes an active layer, a first electrode, a second electrode, and a gate, wherein the pad electrode, the first electrode, and the second electrode are formed using the same mask process.

[0243] In one embodiment of the first aspect, forming the lower electrode includes patterning the lower electrode film to form a pad connection electrode in the pad region.

[0244] In one embodiment of the first aspect, the lower electrode and the pad connection electrode are formed using the same mask process.

[0245] In one embodiment of the first aspect, the pad region includes a readout pad region.

[0246] In one embodiment of the first aspect, the method further includes: after forming the second protective layer and the lower electrode, forming a bias electrode and a pad contact electrode in the active region and the pad region, respectively, wherein the bias electrode and the pad contact electrode are formed using the same mask process.

[0247] In one embodiment of the first aspect, the method further includes forming a pad protection electrode covering the pad contact electrode in the pad region.

[0248] A second aspect of this disclosure provides a method for manufacturing a digital X-ray detector, the method comprising: setting an array substrate for the digital X-ray detector; and forming a scintillator layer on the array substrate to cover an active region of the array substrate, wherein setting the array substrate comprises: setting a base substrate having an active region and a pad region; forming a thin-film transistor in the active region and on the base substrate; forming a first protective layer on the base substrate to cover the thin-film transistor; forming a lower electrode film on the first protective layer; forming a PIN (P-type / I-type / N-type semiconductor) layer and an upper electrode in the active region and on the lower electrode film; forming a second protective film on the lower electrode film to cover the PIN layer and the upper electrode; and patterning the second protective film to form a second protective layer, and patterning the lower electrode film to form a lower electrode in the active region, wherein the second protective film and the lower electrode film are patterned using the same masking process.

[0249] A third aspect of this disclosure provides an array substrate for a digital X-ray detector, the array substrate comprising: a substrate having an active region and a pad region; a thin-film transistor disposed in the active region and on the substrate; a first protective layer covering the thin-film transistor and disposed in the active region and the pad region; a PIN diode electrically connected to the thin-film transistor and disposed in the active region and on the first protective layer; a second protective layer covering the PIN diode and disposed in the active region and the pad region; and a bias electrode electrically connected to the PIN diode and disposed in the second protective layer and in the active region, wherein the second protective layer does not contact the first protective layer.

[0250] In one embodiment of the third aspect, the PIN diode includes a lower electrode, a PIN layer, and an upper electrode, wherein the second protective layer does not cover the side of the lower electrode.

[0251] In one embodiment of the third aspect, the side of the lower electrode is inclined downward and outward, wherein the top of the lower electrode is located inside the bottom end of the second protective layer.

[0252] In one embodiment of the third aspect, the upper electrode is electrically connected to the bias electrode via a contact hole formed in the second protective layer.

[0253] In one embodiment of the third aspect, the thin-film transistor includes an active layer, a first electrode, a second electrode, and a gate, wherein the array substrate further includes: a pad electrode disposed in a pad region, wherein the pad electrode, the first electrode, and the second electrode constitute the same layer; a pad connection electrode disposed in the pad region, wherein the pad connection electrode and the lower electrode constitute the same layer; and a pad contact electrode disposed in the pad region, wherein the pad contact electrode and the bias electrode constitute the same layer.

[0254] In one embodiment of the third aspect, the array substrate further includes a pad protection electrode disposed in the pad region, wherein the pad protection electrode covers the pad contact electrode.

[0255] A fourth aspect of this disclosure provides a digital X-ray detector, comprising: an array substrate for the digital X-ray detector; and a scintillator layer disposed on the array substrate to cover an active region of the array substrate, wherein the array substrate for the digital X-ray detector comprises: a substrate having an active region and a pad region; a thin-film transistor disposed on the substrate and in the active region; a first protective layer covering the thin-film transistor and disposed in the active region and the pad region; a PIN diode electrically connected to the thin-film transistor and disposed on the first protective layer and in the active region; a second protective layer covering the PIN diode and disposed in the active region and the pad region; and a bias electrode electrically connected to the PIN diode and disposed on the second protective layer and in the active region, wherein the second protective layer does not contact the first protective layer.

[0256] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments. The present disclosure can be implemented in various modifications without departing from the spirit and concept of the present disclosure. Therefore, the embodiments disclosed herein are not intended to limit the spirit and concept of the present disclosure, but are for the purpose of describing the present disclosure. The scope of the spirit and concept of the present disclosure is not limited by the embodiments. Therefore, it should be understood that the embodiments described above are illustrative and non-limiting in all respects. The scope of protection of the present disclosure should be interpreted by the claims, and all spirit and concept within the scope of the present disclosure should be interpreted as being included within the scope of the present disclosure.

Claims

1. A method for manufacturing an array substrate for a digital X-ray detector, the method comprising: Set a substrate with an active area and a pad area; A thin-film transistor is formed on the substrate and in the active region; A first protective layer is formed on the substrate to cover the thin-film transistor; A lower electrode film is formed on the first protective layer; A PIN layer, i.e., a P-type / I-type / N-type semiconductor layer and an upper electrode, are formed on the lower electrode film and in the active region; A second protective film is formed on the lower electrode film to cover the PIN layer and the upper electrode; as well as The second protective film is patterned to form a second protective layer with contact holes, and the lower electrode film is patterned to form a lower electrode in the active region. The second protective film and the lower electrode film are patterned using the same masking process, and In this process, the second protective film is patterned using a mask with a predetermined pattern, and then the lower electrode film is patterned using the same mask as in the patterning process of the second protective film.

2. The method of claim 1, wherein, In the active region, the second protective layer is patterned into a pattern corresponding to the lower electrode.

3. The method of claim 1, wherein, Each of the lower electrode film and the second protective film is formed to cover the entire surface of the substrate.

4. The method according to claim 1, wherein, The second protective film is patterned using dry etching, and the lower electrode film is patterned using wet etching.

5. The method according to claim 1, wherein, The method further includes: forming pad electrodes on the substrate and in the pad region before forming the first protective layer.

6. The method according to claim 5, wherein, The thin-film transistor includes an active layer, a first electrode, a second electrode, and a gate. The pad electrode, the first electrode, and the second electrode are formed using the same mask process.

7. The method according to claim 5, wherein, Forming the lower electrode includes patterning the lower electrode film to form a pad connection electrode in the pad region.

8. The method according to claim 7, wherein, The lower electrode and the pad connection electrode are formed using the same mask process.

9. The method according to claim 7, wherein, In the pad area, the second protective layer is patterned into a pattern corresponding to the pad connection electrode.

10. The method according to claim 7, wherein, The method further includes: after forming the second protective layer and the lower electrode, forming a bias electrode and a pad contact electrode in the active region and the pad region, respectively. The bias electrode and the pad contact electrode are formed using the same mask process.

11. The method according to claim 10, wherein, The method further includes forming a pad protection electrode covering the pad contact electrode in the pad area.

12. A method for manufacturing a digital X-ray detector, the method comprising: An array substrate for the digital X-ray detector according to any one of claims 1-11 is provided; as well as A scintillator layer is formed on the array substrate to cover the active region of the array substrate.

13. An array substrate for a digital X-ray detector, the array substrate comprising: A substrate having an active region and a pad region; A thin-film transistor disposed in the active region and on the substrate; A first protective layer covers the thin-film transistor and is disposed in the active region and the pad region; A PIN diode, which is electrically connected to the thin-film transistor and is disposed in the active region and on the first protective layer; as well as A second protective layer covers the PIN diode and is disposed in the active region and the pad region. The second protective layer does not contact the first protective layer. The PIN diode includes a lower electrode, a PIN layer, and an upper electrode. The lower electrode has its sides tilted downwards and outwards, and The top end of the lower electrode is located inside the bottom end of the second protective layer.

14. The array substrate according to claim 13, in, The second protective layer does not cover the sides of the lower electrode.

15. The array substrate of claim 13, further comprising a bias electrode electrically connected to the PIN diode and disposed on the second protective layer and in the active region. in, The upper electrode is electrically connected to the bias electrode via a contact hole formed in the second protective layer.

16. The array substrate according to claim 15, wherein, The thin-film transistor includes an active layer, a first electrode, a second electrode, and a gate. The array substrate further includes: A pad electrode is disposed in the pad area, wherein the pad electrode, the first electrode, and the second electrode constitute the same layer; A pad-connecting electrode is disposed in the pad area, wherein the pad-connecting electrode and the lower electrode constitute the same layer; and A pad contact electrode is disposed in the pad area, wherein the pad contact electrode and the bias electrode form the same layer.

17. The array substrate according to claim 16, wherein, The array substrate further includes a pad protection electrode disposed in the pad region, wherein the pad protection electrode covers the pad contact electrode.

18. A digital X-ray detector, comprising: Array substrate for the digital X-ray detector according to any one of claims 13-17; as well as A scintillator layer is disposed on the array substrate to cover the active region of the array substrate.

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